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0091bb70a411305d3c45e7b4277f109106bee36d
SigGen/firmware/Debug/SigGen.list
Anton Mukhin 0091bb70a4 Initial commit
2022-10-29 02:38:03 +03:00

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SigGen.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000b8 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000036d8 080000b8 080000b8 000100b8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000000cc 08003790 08003790 00013790 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 0800385c 0800385c 0002000c 2**0
CONTENTS
4 .ARM 00000000 0800385c 0800385c 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 0800385c 0800385c 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 0800385c 0800385c 0001385c 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08003860 08003860 00013860 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08003864 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000002ac 2000000c 08003870 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000600 200002b8 08003870 000202b8 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 00010be3 00000000 00000000 00020034 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001d86 00000000 00000000 00030c17 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000e78 00000000 00000000 000329a0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00000dd0 00000000 00000000 00033818 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 000157b8 00000000 00000000 000345e8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00010710 00000000 00000000 00049da0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0008c8b8 00000000 00000000 0005a4b0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000050 00000000 00000000 000e6d68 2**0
CONTENTS, READONLY
20 .debug_frame 000034f0 00000000 00000000 000e6db8 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000b8 <__do_global_dtors_aux>:
80000b8: b510 push {r4, lr}
80000ba: 4c06 ldr r4, [pc, #24] ; (80000d4 <__do_global_dtors_aux+0x1c>)
80000bc: 7823 ldrb r3, [r4, #0]
80000be: 2b00 cmp r3, #0
80000c0: d107 bne.n 80000d2 <__do_global_dtors_aux+0x1a>
80000c2: 4b05 ldr r3, [pc, #20] ; (80000d8 <__do_global_dtors_aux+0x20>)
80000c4: 2b00 cmp r3, #0
80000c6: d002 beq.n 80000ce <__do_global_dtors_aux+0x16>
80000c8: 4804 ldr r0, [pc, #16] ; (80000dc <__do_global_dtors_aux+0x24>)
80000ca: e000 b.n 80000ce <__do_global_dtors_aux+0x16>
80000cc: bf00 nop
80000ce: 2301 movs r3, #1
80000d0: 7023 strb r3, [r4, #0]
80000d2: bd10 pop {r4, pc}
80000d4: 2000000c .word 0x2000000c
80000d8: 00000000 .word 0x00000000
80000dc: 08003778 .word 0x08003778
080000e0 <frame_dummy>:
80000e0: 4b04 ldr r3, [pc, #16] ; (80000f4 <frame_dummy+0x14>)
80000e2: b510 push {r4, lr}
80000e4: 2b00 cmp r3, #0
80000e6: d003 beq.n 80000f0 <frame_dummy+0x10>
80000e8: 4903 ldr r1, [pc, #12] ; (80000f8 <frame_dummy+0x18>)
80000ea: 4804 ldr r0, [pc, #16] ; (80000fc <frame_dummy+0x1c>)
80000ec: e000 b.n 80000f0 <frame_dummy+0x10>
80000ee: bf00 nop
80000f0: bd10 pop {r4, pc}
80000f2: 46c0 nop ; (mov r8, r8)
80000f4: 00000000 .word 0x00000000
80000f8: 20000010 .word 0x20000010
80000fc: 08003778 .word 0x08003778
08000100 <__udivsi3>:
8000100: 2200 movs r2, #0
8000102: 0843 lsrs r3, r0, #1
8000104: 428b cmp r3, r1
8000106: d374 bcc.n 80001f2 <__udivsi3+0xf2>
8000108: 0903 lsrs r3, r0, #4
800010a: 428b cmp r3, r1
800010c: d35f bcc.n 80001ce <__udivsi3+0xce>
800010e: 0a03 lsrs r3, r0, #8
8000110: 428b cmp r3, r1
8000112: d344 bcc.n 800019e <__udivsi3+0x9e>
8000114: 0b03 lsrs r3, r0, #12
8000116: 428b cmp r3, r1
8000118: d328 bcc.n 800016c <__udivsi3+0x6c>
800011a: 0c03 lsrs r3, r0, #16
800011c: 428b cmp r3, r1
800011e: d30d bcc.n 800013c <__udivsi3+0x3c>
8000120: 22ff movs r2, #255 ; 0xff
8000122: 0209 lsls r1, r1, #8
8000124: ba12 rev r2, r2
8000126: 0c03 lsrs r3, r0, #16
8000128: 428b cmp r3, r1
800012a: d302 bcc.n 8000132 <__udivsi3+0x32>
800012c: 1212 asrs r2, r2, #8
800012e: 0209 lsls r1, r1, #8
8000130: d065 beq.n 80001fe <__udivsi3+0xfe>
8000132: 0b03 lsrs r3, r0, #12
8000134: 428b cmp r3, r1
8000136: d319 bcc.n 800016c <__udivsi3+0x6c>
8000138: e000 b.n 800013c <__udivsi3+0x3c>
800013a: 0a09 lsrs r1, r1, #8
800013c: 0bc3 lsrs r3, r0, #15
800013e: 428b cmp r3, r1
8000140: d301 bcc.n 8000146 <__udivsi3+0x46>
8000142: 03cb lsls r3, r1, #15
8000144: 1ac0 subs r0, r0, r3
8000146: 4152 adcs r2, r2
8000148: 0b83 lsrs r3, r0, #14
800014a: 428b cmp r3, r1
800014c: d301 bcc.n 8000152 <__udivsi3+0x52>
800014e: 038b lsls r3, r1, #14
8000150: 1ac0 subs r0, r0, r3
8000152: 4152 adcs r2, r2
8000154: 0b43 lsrs r3, r0, #13
8000156: 428b cmp r3, r1
8000158: d301 bcc.n 800015e <__udivsi3+0x5e>
800015a: 034b lsls r3, r1, #13
800015c: 1ac0 subs r0, r0, r3
800015e: 4152 adcs r2, r2
8000160: 0b03 lsrs r3, r0, #12
8000162: 428b cmp r3, r1
8000164: d301 bcc.n 800016a <__udivsi3+0x6a>
8000166: 030b lsls r3, r1, #12
8000168: 1ac0 subs r0, r0, r3
800016a: 4152 adcs r2, r2
800016c: 0ac3 lsrs r3, r0, #11
800016e: 428b cmp r3, r1
8000170: d301 bcc.n 8000176 <__udivsi3+0x76>
8000172: 02cb lsls r3, r1, #11
8000174: 1ac0 subs r0, r0, r3
8000176: 4152 adcs r2, r2
8000178: 0a83 lsrs r3, r0, #10
800017a: 428b cmp r3, r1
800017c: d301 bcc.n 8000182 <__udivsi3+0x82>
800017e: 028b lsls r3, r1, #10
8000180: 1ac0 subs r0, r0, r3
8000182: 4152 adcs r2, r2
8000184: 0a43 lsrs r3, r0, #9
8000186: 428b cmp r3, r1
8000188: d301 bcc.n 800018e <__udivsi3+0x8e>
800018a: 024b lsls r3, r1, #9
800018c: 1ac0 subs r0, r0, r3
800018e: 4152 adcs r2, r2
8000190: 0a03 lsrs r3, r0, #8
8000192: 428b cmp r3, r1
8000194: d301 bcc.n 800019a <__udivsi3+0x9a>
8000196: 020b lsls r3, r1, #8
8000198: 1ac0 subs r0, r0, r3
800019a: 4152 adcs r2, r2
800019c: d2cd bcs.n 800013a <__udivsi3+0x3a>
800019e: 09c3 lsrs r3, r0, #7
80001a0: 428b cmp r3, r1
80001a2: d301 bcc.n 80001a8 <__udivsi3+0xa8>
80001a4: 01cb lsls r3, r1, #7
80001a6: 1ac0 subs r0, r0, r3
80001a8: 4152 adcs r2, r2
80001aa: 0983 lsrs r3, r0, #6
80001ac: 428b cmp r3, r1
80001ae: d301 bcc.n 80001b4 <__udivsi3+0xb4>
80001b0: 018b lsls r3, r1, #6
80001b2: 1ac0 subs r0, r0, r3
80001b4: 4152 adcs r2, r2
80001b6: 0943 lsrs r3, r0, #5
80001b8: 428b cmp r3, r1
80001ba: d301 bcc.n 80001c0 <__udivsi3+0xc0>
80001bc: 014b lsls r3, r1, #5
80001be: 1ac0 subs r0, r0, r3
80001c0: 4152 adcs r2, r2
80001c2: 0903 lsrs r3, r0, #4
80001c4: 428b cmp r3, r1
80001c6: d301 bcc.n 80001cc <__udivsi3+0xcc>
80001c8: 010b lsls r3, r1, #4
80001ca: 1ac0 subs r0, r0, r3
80001cc: 4152 adcs r2, r2
80001ce: 08c3 lsrs r3, r0, #3
80001d0: 428b cmp r3, r1
80001d2: d301 bcc.n 80001d8 <__udivsi3+0xd8>
80001d4: 00cb lsls r3, r1, #3
80001d6: 1ac0 subs r0, r0, r3
80001d8: 4152 adcs r2, r2
80001da: 0883 lsrs r3, r0, #2
80001dc: 428b cmp r3, r1
80001de: d301 bcc.n 80001e4 <__udivsi3+0xe4>
80001e0: 008b lsls r3, r1, #2
80001e2: 1ac0 subs r0, r0, r3
80001e4: 4152 adcs r2, r2
80001e6: 0843 lsrs r3, r0, #1
80001e8: 428b cmp r3, r1
80001ea: d301 bcc.n 80001f0 <__udivsi3+0xf0>
80001ec: 004b lsls r3, r1, #1
80001ee: 1ac0 subs r0, r0, r3
80001f0: 4152 adcs r2, r2
80001f2: 1a41 subs r1, r0, r1
80001f4: d200 bcs.n 80001f8 <__udivsi3+0xf8>
80001f6: 4601 mov r1, r0
80001f8: 4152 adcs r2, r2
80001fa: 4610 mov r0, r2
80001fc: 4770 bx lr
80001fe: e7ff b.n 8000200 <__udivsi3+0x100>
8000200: b501 push {r0, lr}
8000202: 2000 movs r0, #0
8000204: f000 f806 bl 8000214 <__aeabi_idiv0>
8000208: bd02 pop {r1, pc}
800020a: 46c0 nop ; (mov r8, r8)
0800020c <__aeabi_uidivmod>:
800020c: 2900 cmp r1, #0
800020e: d0f7 beq.n 8000200 <__udivsi3+0x100>
8000210: e776 b.n 8000100 <__udivsi3>
8000212: 4770 bx lr
08000214 <__aeabi_idiv0>:
8000214: 4770 bx lr
8000216: 46c0 nop ; (mov r8, r8)
08000218 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000218: b580 push {r7, lr}
800021a: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
800021c: f000 fe00 bl 8000e20 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000220: f000 f811 bl 8000246 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000224: f000 faca bl 80007bc <MX_GPIO_Init>
MX_SPI1_Init();
8000228: f000 f868 bl 80002fc <MX_SPI1_Init>
MX_SPI2_Init();
800022c: f000 f8a4 bl 8000378 <MX_SPI2_Init>
MX_TIM3_Init();
8000230: f000 f8e0 bl 80003f4 <MX_TIM3_Init>
MX_TIM6_Init();
8000234: f000 f942 bl 80004bc <MX_TIM6_Init>
MX_TIM16_Init();
8000238: f000 f97c bl 8000534 <MX_TIM16_Init>
MX_TIM17_Init();
800023c: f000 fa02 bl 8000644 <MX_TIM17_Init>
MX_USART3_UART_Init();
8000240: f000 fa88 bl 8000754 <MX_USART3_UART_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000244: e7fe b.n 8000244 <main+0x2c>
08000246 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000246: b590 push {r4, r7, lr}
8000248: b093 sub sp, #76 ; 0x4c
800024a: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800024c: 2414 movs r4, #20
800024e: 193b adds r3, r7, r4
8000250: 0018 movs r0, r3
8000252: 2334 movs r3, #52 ; 0x34
8000254: 001a movs r2, r3
8000256: 2100 movs r1, #0
8000258: f003 fa86 bl 8003768 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800025c: 1d3b adds r3, r7, #4
800025e: 0018 movs r0, r3
8000260: 2310 movs r3, #16
8000262: 001a movs r2, r3
8000264: 2100 movs r1, #0
8000266: f003 fa7f bl 8003768 <memset>
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
800026a: 2380 movs r3, #128 ; 0x80
800026c: 009b lsls r3, r3, #2
800026e: 0018 movs r0, r3
8000270: f001 f8bc bl 80013ec <HAL_PWREx_ControlVoltageScaling>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8000274: 193b adds r3, r7, r4
8000276: 2202 movs r2, #2
8000278: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
800027a: 193b adds r3, r7, r4
800027c: 2280 movs r2, #128 ; 0x80
800027e: 0052 lsls r2, r2, #1
8000280: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
8000282: 0021 movs r1, r4
8000284: 187b adds r3, r7, r1
8000286: 2200 movs r2, #0
8000288: 611a str r2, [r3, #16]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
800028a: 187b adds r3, r7, r1
800028c: 2240 movs r2, #64 ; 0x40
800028e: 615a str r2, [r3, #20]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000290: 187b adds r3, r7, r1
8000292: 2202 movs r2, #2
8000294: 61da str r2, [r3, #28]
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
8000296: 187b adds r3, r7, r1
8000298: 2202 movs r2, #2
800029a: 621a str r2, [r3, #32]
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
800029c: 187b adds r3, r7, r1
800029e: 2200 movs r2, #0
80002a0: 625a str r2, [r3, #36] ; 0x24
RCC_OscInitStruct.PLL.PLLN = 8;
80002a2: 187b adds r3, r7, r1
80002a4: 2208 movs r2, #8
80002a6: 629a str r2, [r3, #40] ; 0x28
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
80002a8: 187b adds r3, r7, r1
80002aa: 2280 movs r2, #128 ; 0x80
80002ac: 0292 lsls r2, r2, #10
80002ae: 62da str r2, [r3, #44] ; 0x2c
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
80002b0: 187b adds r3, r7, r1
80002b2: 2280 movs r2, #128 ; 0x80
80002b4: 0592 lsls r2, r2, #22
80002b6: 631a str r2, [r3, #48] ; 0x30
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80002b8: 187b adds r3, r7, r1
80002ba: 0018 movs r0, r3
80002bc: f001 f8e2 bl 8001484 <HAL_RCC_OscConfig>
80002c0: 1e03 subs r3, r0, #0
80002c2: d001 beq.n 80002c8 <SystemClock_Config+0x82>
{
Error_Handler();
80002c4: f000 fb44 bl 8000950 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80002c8: 1d3b adds r3, r7, #4
80002ca: 2207 movs r2, #7
80002cc: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80002ce: 1d3b adds r3, r7, #4
80002d0: 2202 movs r2, #2
80002d2: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80002d4: 1d3b adds r3, r7, #4
80002d6: 2200 movs r2, #0
80002d8: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80002da: 1d3b adds r3, r7, #4
80002dc: 2200 movs r2, #0
80002de: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
80002e0: 1d3b adds r3, r7, #4
80002e2: 2102 movs r1, #2
80002e4: 0018 movs r0, r3
80002e6: f001 fbdd bl 8001aa4 <HAL_RCC_ClockConfig>
80002ea: 1e03 subs r3, r0, #0
80002ec: d001 beq.n 80002f2 <SystemClock_Config+0xac>
{
Error_Handler();
80002ee: f000 fb2f bl 8000950 <Error_Handler>
}
}
80002f2: 46c0 nop ; (mov r8, r8)
80002f4: 46bd mov sp, r7
80002f6: b013 add sp, #76 ; 0x4c
80002f8: bd90 pop {r4, r7, pc}
...
080002fc <MX_SPI1_Init>:
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
80002fc: b580 push {r7, lr}
80002fe: af00 add r7, sp, #0
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
8000300: 4b1b ldr r3, [pc, #108] ; (8000370 <MX_SPI1_Init+0x74>)
8000302: 4a1c ldr r2, [pc, #112] ; (8000374 <MX_SPI1_Init+0x78>)
8000304: 601a str r2, [r3, #0]
hspi1.Init.Mode = SPI_MODE_MASTER;
8000306: 4b1a ldr r3, [pc, #104] ; (8000370 <MX_SPI1_Init+0x74>)
8000308: 2282 movs r2, #130 ; 0x82
800030a: 0052 lsls r2, r2, #1
800030c: 605a str r2, [r3, #4]
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
800030e: 4b18 ldr r3, [pc, #96] ; (8000370 <MX_SPI1_Init+0x74>)
8000310: 2200 movs r2, #0
8000312: 609a str r2, [r3, #8]
hspi1.Init.DataSize = SPI_DATASIZE_16BIT;
8000314: 4b16 ldr r3, [pc, #88] ; (8000370 <MX_SPI1_Init+0x74>)
8000316: 22f0 movs r2, #240 ; 0xf0
8000318: 0112 lsls r2, r2, #4
800031a: 60da str r2, [r3, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
800031c: 4b14 ldr r3, [pc, #80] ; (8000370 <MX_SPI1_Init+0x74>)
800031e: 2200 movs r2, #0
8000320: 611a str r2, [r3, #16]
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
8000322: 4b13 ldr r3, [pc, #76] ; (8000370 <MX_SPI1_Init+0x74>)
8000324: 2200 movs r2, #0
8000326: 615a str r2, [r3, #20]
hspi1.Init.NSS = SPI_NSS_SOFT;
8000328: 4b11 ldr r3, [pc, #68] ; (8000370 <MX_SPI1_Init+0x74>)
800032a: 2280 movs r2, #128 ; 0x80
800032c: 0092 lsls r2, r2, #2
800032e: 619a str r2, [r3, #24]
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8000330: 4b0f ldr r3, [pc, #60] ; (8000370 <MX_SPI1_Init+0x74>)
8000332: 2200 movs r2, #0
8000334: 61da str r2, [r3, #28]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
8000336: 4b0e ldr r3, [pc, #56] ; (8000370 <MX_SPI1_Init+0x74>)
8000338: 2200 movs r2, #0
800033a: 621a str r2, [r3, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
800033c: 4b0c ldr r3, [pc, #48] ; (8000370 <MX_SPI1_Init+0x74>)
800033e: 2200 movs r2, #0
8000340: 625a str r2, [r3, #36] ; 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8000342: 4b0b ldr r3, [pc, #44] ; (8000370 <MX_SPI1_Init+0x74>)
8000344: 2200 movs r2, #0
8000346: 629a str r2, [r3, #40] ; 0x28
hspi1.Init.CRCPolynomial = 7;
8000348: 4b09 ldr r3, [pc, #36] ; (8000370 <MX_SPI1_Init+0x74>)
800034a: 2207 movs r2, #7
800034c: 62da str r2, [r3, #44] ; 0x2c
hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
800034e: 4b08 ldr r3, [pc, #32] ; (8000370 <MX_SPI1_Init+0x74>)
8000350: 2200 movs r2, #0
8000352: 631a str r2, [r3, #48] ; 0x30
hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
8000354: 4b06 ldr r3, [pc, #24] ; (8000370 <MX_SPI1_Init+0x74>)
8000356: 2208 movs r2, #8
8000358: 635a str r2, [r3, #52] ; 0x34
if (HAL_SPI_Init(&hspi1) != HAL_OK)
800035a: 4b05 ldr r3, [pc, #20] ; (8000370 <MX_SPI1_Init+0x74>)
800035c: 0018 movs r0, r3
800035e: f001 fd49 bl 8001df4 <HAL_SPI_Init>
8000362: 1e03 subs r3, r0, #0
8000364: d001 beq.n 800036a <MX_SPI1_Init+0x6e>
{
Error_Handler();
8000366: f000 faf3 bl 8000950 <Error_Handler>
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
800036a: 46c0 nop ; (mov r8, r8)
800036c: 46bd mov sp, r7
800036e: bd80 pop {r7, pc}
8000370: 20000028 .word 0x20000028
8000374: 40013000 .word 0x40013000
08000378 <MX_SPI2_Init>:
* @brief SPI2 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI2_Init(void)
{
8000378: b580 push {r7, lr}
800037a: af00 add r7, sp, #0
/* USER CODE BEGIN SPI2_Init 1 */
/* USER CODE END SPI2_Init 1 */
/* SPI2 parameter configuration*/
hspi2.Instance = SPI2;
800037c: 4b1b ldr r3, [pc, #108] ; (80003ec <MX_SPI2_Init+0x74>)
800037e: 4a1c ldr r2, [pc, #112] ; (80003f0 <MX_SPI2_Init+0x78>)
8000380: 601a str r2, [r3, #0]
hspi2.Init.Mode = SPI_MODE_MASTER;
8000382: 4b1a ldr r3, [pc, #104] ; (80003ec <MX_SPI2_Init+0x74>)
8000384: 2282 movs r2, #130 ; 0x82
8000386: 0052 lsls r2, r2, #1
8000388: 605a str r2, [r3, #4]
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
800038a: 4b18 ldr r3, [pc, #96] ; (80003ec <MX_SPI2_Init+0x74>)
800038c: 2200 movs r2, #0
800038e: 609a str r2, [r3, #8]
hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
8000390: 4b16 ldr r3, [pc, #88] ; (80003ec <MX_SPI2_Init+0x74>)
8000392: 22e0 movs r2, #224 ; 0xe0
8000394: 00d2 lsls r2, r2, #3
8000396: 60da str r2, [r3, #12]
hspi2.Init.CLKPolarity = SPI_POLARITY_HIGH;
8000398: 4b14 ldr r3, [pc, #80] ; (80003ec <MX_SPI2_Init+0x74>)
800039a: 2202 movs r2, #2
800039c: 611a str r2, [r3, #16]
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
800039e: 4b13 ldr r3, [pc, #76] ; (80003ec <MX_SPI2_Init+0x74>)
80003a0: 2200 movs r2, #0
80003a2: 615a str r2, [r3, #20]
hspi2.Init.NSS = SPI_NSS_SOFT;
80003a4: 4b11 ldr r3, [pc, #68] ; (80003ec <MX_SPI2_Init+0x74>)
80003a6: 2280 movs r2, #128 ; 0x80
80003a8: 0092 lsls r2, r2, #2
80003aa: 619a str r2, [r3, #24]
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
80003ac: 4b0f ldr r3, [pc, #60] ; (80003ec <MX_SPI2_Init+0x74>)
80003ae: 2200 movs r2, #0
80003b0: 61da str r2, [r3, #28]
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
80003b2: 4b0e ldr r3, [pc, #56] ; (80003ec <MX_SPI2_Init+0x74>)
80003b4: 2200 movs r2, #0
80003b6: 621a str r2, [r3, #32]
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
80003b8: 4b0c ldr r3, [pc, #48] ; (80003ec <MX_SPI2_Init+0x74>)
80003ba: 2200 movs r2, #0
80003bc: 625a str r2, [r3, #36] ; 0x24
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80003be: 4b0b ldr r3, [pc, #44] ; (80003ec <MX_SPI2_Init+0x74>)
80003c0: 2200 movs r2, #0
80003c2: 629a str r2, [r3, #40] ; 0x28
hspi2.Init.CRCPolynomial = 7;
80003c4: 4b09 ldr r3, [pc, #36] ; (80003ec <MX_SPI2_Init+0x74>)
80003c6: 2207 movs r2, #7
80003c8: 62da str r2, [r3, #44] ; 0x2c
hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
80003ca: 4b08 ldr r3, [pc, #32] ; (80003ec <MX_SPI2_Init+0x74>)
80003cc: 2200 movs r2, #0
80003ce: 631a str r2, [r3, #48] ; 0x30
hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
80003d0: 4b06 ldr r3, [pc, #24] ; (80003ec <MX_SPI2_Init+0x74>)
80003d2: 2208 movs r2, #8
80003d4: 635a str r2, [r3, #52] ; 0x34
if (HAL_SPI_Init(&hspi2) != HAL_OK)
80003d6: 4b05 ldr r3, [pc, #20] ; (80003ec <MX_SPI2_Init+0x74>)
80003d8: 0018 movs r0, r3
80003da: f001 fd0b bl 8001df4 <HAL_SPI_Init>
80003de: 1e03 subs r3, r0, #0
80003e0: d001 beq.n 80003e6 <MX_SPI2_Init+0x6e>
{
Error_Handler();
80003e2: f000 fab5 bl 8000950 <Error_Handler>
}
/* USER CODE BEGIN SPI2_Init 2 */
/* USER CODE END SPI2_Init 2 */
}
80003e6: 46c0 nop ; (mov r8, r8)
80003e8: 46bd mov sp, r7
80003ea: bd80 pop {r7, pc}
80003ec: 2000008c .word 0x2000008c
80003f0: 40003800 .word 0x40003800
080003f4 <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
80003f4: b590 push {r4, r7, lr}
80003f6: b08d sub sp, #52 ; 0x34
80003f8: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_Encoder_InitTypeDef sConfig = {0};
80003fa: 240c movs r4, #12
80003fc: 193b adds r3, r7, r4
80003fe: 0018 movs r0, r3
8000400: 2324 movs r3, #36 ; 0x24
8000402: 001a movs r2, r3
8000404: 2100 movs r1, #0
8000406: f003 f9af bl 8003768 <memset>
TIM_MasterConfigTypeDef sMasterConfig = {0};
800040a: 003b movs r3, r7
800040c: 0018 movs r0, r3
800040e: 230c movs r3, #12
8000410: 001a movs r2, r3
8000412: 2100 movs r1, #0
8000414: f003 f9a8 bl 8003768 <memset>
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
8000418: 4b25 ldr r3, [pc, #148] ; (80004b0 <MX_TIM3_Init+0xbc>)
800041a: 4a26 ldr r2, [pc, #152] ; (80004b4 <MX_TIM3_Init+0xc0>)
800041c: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 0;
800041e: 4b24 ldr r3, [pc, #144] ; (80004b0 <MX_TIM3_Init+0xbc>)
8000420: 2200 movs r2, #0
8000422: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
8000424: 4b22 ldr r3, [pc, #136] ; (80004b0 <MX_TIM3_Init+0xbc>)
8000426: 2200 movs r2, #0
8000428: 609a str r2, [r3, #8]
htim3.Init.Period = 65535;
800042a: 4b21 ldr r3, [pc, #132] ; (80004b0 <MX_TIM3_Init+0xbc>)
800042c: 4a22 ldr r2, [pc, #136] ; (80004b8 <MX_TIM3_Init+0xc4>)
800042e: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000430: 4b1f ldr r3, [pc, #124] ; (80004b0 <MX_TIM3_Init+0xbc>)
8000432: 2200 movs r2, #0
8000434: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000436: 4b1e ldr r3, [pc, #120] ; (80004b0 <MX_TIM3_Init+0xbc>)
8000438: 2200 movs r2, #0
800043a: 619a str r2, [r3, #24]
sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
800043c: 0021 movs r1, r4
800043e: 187b adds r3, r7, r1
8000440: 2203 movs r2, #3
8000442: 601a str r2, [r3, #0]
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
8000444: 187b adds r3, r7, r1
8000446: 2200 movs r2, #0
8000448: 605a str r2, [r3, #4]
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
800044a: 187b adds r3, r7, r1
800044c: 2201 movs r2, #1
800044e: 609a str r2, [r3, #8]
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
8000450: 187b adds r3, r7, r1
8000452: 2200 movs r2, #0
8000454: 60da str r2, [r3, #12]
sConfig.IC1Filter = 0;
8000456: 187b adds r3, r7, r1
8000458: 2200 movs r2, #0
800045a: 611a str r2, [r3, #16]
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
800045c: 187b adds r3, r7, r1
800045e: 2200 movs r2, #0
8000460: 615a str r2, [r3, #20]
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
8000462: 187b adds r3, r7, r1
8000464: 2201 movs r2, #1
8000466: 619a str r2, [r3, #24]
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
8000468: 187b adds r3, r7, r1
800046a: 2200 movs r2, #0
800046c: 61da str r2, [r3, #28]
sConfig.IC2Filter = 0;
800046e: 187b adds r3, r7, r1
8000470: 2200 movs r2, #0
8000472: 621a str r2, [r3, #32]
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
8000474: 187a adds r2, r7, r1
8000476: 4b0e ldr r3, [pc, #56] ; (80004b0 <MX_TIM3_Init+0xbc>)
8000478: 0011 movs r1, r2
800047a: 0018 movs r0, r3
800047c: f001 fe2a bl 80020d4 <HAL_TIM_Encoder_Init>
8000480: 1e03 subs r3, r0, #0
8000482: d001 beq.n 8000488 <MX_TIM3_Init+0x94>
{
Error_Handler();
8000484: f000 fa64 bl 8000950 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000488: 003b movs r3, r7
800048a: 2200 movs r2, #0
800048c: 601a str r2, [r3, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800048e: 003b movs r3, r7
8000490: 2200 movs r2, #0
8000492: 609a str r2, [r3, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8000494: 003a movs r2, r7
8000496: 4b06 ldr r3, [pc, #24] ; (80004b0 <MX_TIM3_Init+0xbc>)
8000498: 0011 movs r1, r2
800049a: 0018 movs r0, r3
800049c: f002 fc56 bl 8002d4c <HAL_TIMEx_MasterConfigSynchronization>
80004a0: 1e03 subs r3, r0, #0
80004a2: d001 beq.n 80004a8 <MX_TIM3_Init+0xb4>
{
Error_Handler();
80004a4: f000 fa54 bl 8000950 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
}
80004a8: 46c0 nop ; (mov r8, r8)
80004aa: 46bd mov sp, r7
80004ac: b00d add sp, #52 ; 0x34
80004ae: bd90 pop {r4, r7, pc}
80004b0: 200000f0 .word 0x200000f0
80004b4: 40000400 .word 0x40000400
80004b8: 0000ffff .word 0x0000ffff
080004bc <MX_TIM6_Init>:
* @brief TIM6 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM6_Init(void)
{
80004bc: b580 push {r7, lr}
80004be: b084 sub sp, #16
80004c0: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_Init 0 */
/* USER CODE END TIM6_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
80004c2: 1d3b adds r3, r7, #4
80004c4: 0018 movs r0, r3
80004c6: 230c movs r3, #12
80004c8: 001a movs r2, r3
80004ca: 2100 movs r1, #0
80004cc: f003 f94c bl 8003768 <memset>
/* USER CODE BEGIN TIM6_Init 1 */
/* USER CODE END TIM6_Init 1 */
htim6.Instance = TIM6;
80004d0: 4b15 ldr r3, [pc, #84] ; (8000528 <MX_TIM6_Init+0x6c>)
80004d2: 4a16 ldr r2, [pc, #88] ; (800052c <MX_TIM6_Init+0x70>)
80004d4: 601a str r2, [r3, #0]
htim6.Init.Prescaler = 64-1;
80004d6: 4b14 ldr r3, [pc, #80] ; (8000528 <MX_TIM6_Init+0x6c>)
80004d8: 223f movs r2, #63 ; 0x3f
80004da: 605a str r2, [r3, #4]
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
80004dc: 4b12 ldr r3, [pc, #72] ; (8000528 <MX_TIM6_Init+0x6c>)
80004de: 2200 movs r2, #0
80004e0: 609a str r2, [r3, #8]
htim6.Init.Period = 10000;
80004e2: 4b11 ldr r3, [pc, #68] ; (8000528 <MX_TIM6_Init+0x6c>)
80004e4: 4a12 ldr r2, [pc, #72] ; (8000530 <MX_TIM6_Init+0x74>)
80004e6: 60da str r2, [r3, #12]
htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80004e8: 4b0f ldr r3, [pc, #60] ; (8000528 <MX_TIM6_Init+0x6c>)
80004ea: 2200 movs r2, #0
80004ec: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
80004ee: 4b0e ldr r3, [pc, #56] ; (8000528 <MX_TIM6_Init+0x6c>)
80004f0: 0018 movs r0, r3
80004f2: f001 fd37 bl 8001f64 <HAL_TIM_Base_Init>
80004f6: 1e03 subs r3, r0, #0
80004f8: d001 beq.n 80004fe <MX_TIM6_Init+0x42>
{
Error_Handler();
80004fa: f000 fa29 bl 8000950 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80004fe: 1d3b adds r3, r7, #4
8000500: 2200 movs r2, #0
8000502: 601a str r2, [r3, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000504: 1d3b adds r3, r7, #4
8000506: 2200 movs r2, #0
8000508: 609a str r2, [r3, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
800050a: 1d3a adds r2, r7, #4
800050c: 4b06 ldr r3, [pc, #24] ; (8000528 <MX_TIM6_Init+0x6c>)
800050e: 0011 movs r1, r2
8000510: 0018 movs r0, r3
8000512: f002 fc1b bl 8002d4c <HAL_TIMEx_MasterConfigSynchronization>
8000516: 1e03 subs r3, r0, #0
8000518: d001 beq.n 800051e <MX_TIM6_Init+0x62>
{
Error_Handler();
800051a: f000 fa19 bl 8000950 <Error_Handler>
}
/* USER CODE BEGIN TIM6_Init 2 */
/* USER CODE END TIM6_Init 2 */
}
800051e: 46c0 nop ; (mov r8, r8)
8000520: 46bd mov sp, r7
8000522: b004 add sp, #16
8000524: bd80 pop {r7, pc}
8000526: 46c0 nop ; (mov r8, r8)
8000528: 2000013c .word 0x2000013c
800052c: 40001000 .word 0x40001000
8000530: 00002710 .word 0x00002710
08000534 <MX_TIM16_Init>:
* @brief TIM16 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM16_Init(void)
{
8000534: b580 push {r7, lr}
8000536: b094 sub sp, #80 ; 0x50
8000538: af00 add r7, sp, #0
/* USER CODE BEGIN TIM16_Init 0 */
/* USER CODE END TIM16_Init 0 */
TIM_OC_InitTypeDef sConfigOC = {0};
800053a: 2334 movs r3, #52 ; 0x34
800053c: 18fb adds r3, r7, r3
800053e: 0018 movs r0, r3
8000540: 231c movs r3, #28
8000542: 001a movs r2, r3
8000544: 2100 movs r1, #0
8000546: f003 f90f bl 8003768 <memset>
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
800054a: 003b movs r3, r7
800054c: 0018 movs r0, r3
800054e: 2334 movs r3, #52 ; 0x34
8000550: 001a movs r2, r3
8000552: 2100 movs r1, #0
8000554: f003 f908 bl 8003768 <memset>
/* USER CODE BEGIN TIM16_Init 1 */
/* USER CODE END TIM16_Init 1 */
htim16.Instance = TIM16;
8000558: 4b37 ldr r3, [pc, #220] ; (8000638 <MX_TIM16_Init+0x104>)
800055a: 4a38 ldr r2, [pc, #224] ; (800063c <MX_TIM16_Init+0x108>)
800055c: 601a str r2, [r3, #0]
htim16.Init.Prescaler = 0;
800055e: 4b36 ldr r3, [pc, #216] ; (8000638 <MX_TIM16_Init+0x104>)
8000560: 2200 movs r2, #0
8000562: 605a str r2, [r3, #4]
htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
8000564: 4b34 ldr r3, [pc, #208] ; (8000638 <MX_TIM16_Init+0x104>)
8000566: 2200 movs r2, #0
8000568: 609a str r2, [r3, #8]
htim16.Init.Period = 65535;
800056a: 4b33 ldr r3, [pc, #204] ; (8000638 <MX_TIM16_Init+0x104>)
800056c: 4a34 ldr r2, [pc, #208] ; (8000640 <MX_TIM16_Init+0x10c>)
800056e: 60da str r2, [r3, #12]
htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000570: 4b31 ldr r3, [pc, #196] ; (8000638 <MX_TIM16_Init+0x104>)
8000572: 2200 movs r2, #0
8000574: 611a str r2, [r3, #16]
htim16.Init.RepetitionCounter = 0;
8000576: 4b30 ldr r3, [pc, #192] ; (8000638 <MX_TIM16_Init+0x104>)
8000578: 2200 movs r2, #0
800057a: 615a str r2, [r3, #20]
htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800057c: 4b2e ldr r3, [pc, #184] ; (8000638 <MX_TIM16_Init+0x104>)
800057e: 2200 movs r2, #0
8000580: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim16) != HAL_OK)
8000582: 4b2d ldr r3, [pc, #180] ; (8000638 <MX_TIM16_Init+0x104>)
8000584: 0018 movs r0, r3
8000586: f001 fced bl 8001f64 <HAL_TIM_Base_Init>
800058a: 1e03 subs r3, r0, #0
800058c: d001 beq.n 8000592 <MX_TIM16_Init+0x5e>
{
Error_Handler();
800058e: f000 f9df bl 8000950 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim16) != HAL_OK)
8000592: 4b29 ldr r3, [pc, #164] ; (8000638 <MX_TIM16_Init+0x104>)
8000594: 0018 movs r0, r3
8000596: f001 fd3d bl 8002014 <HAL_TIM_PWM_Init>
800059a: 1e03 subs r3, r0, #0
800059c: d001 beq.n 80005a2 <MX_TIM16_Init+0x6e>
{
Error_Handler();
800059e: f000 f9d7 bl 8000950 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
80005a2: 2134 movs r1, #52 ; 0x34
80005a4: 187b adds r3, r7, r1
80005a6: 2260 movs r2, #96 ; 0x60
80005a8: 601a str r2, [r3, #0]
sConfigOC.Pulse = 0;
80005aa: 187b adds r3, r7, r1
80005ac: 2200 movs r2, #0
80005ae: 605a str r2, [r3, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80005b0: 187b adds r3, r7, r1
80005b2: 2200 movs r2, #0
80005b4: 609a str r2, [r3, #8]
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
80005b6: 187b adds r3, r7, r1
80005b8: 2200 movs r2, #0
80005ba: 60da str r2, [r3, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
80005bc: 187b adds r3, r7, r1
80005be: 2200 movs r2, #0
80005c0: 611a str r2, [r3, #16]
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
80005c2: 187b adds r3, r7, r1
80005c4: 2200 movs r2, #0
80005c6: 615a str r2, [r3, #20]
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
80005c8: 187b adds r3, r7, r1
80005ca: 2200 movs r2, #0
80005cc: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_ConfigChannel(&htim16, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
80005ce: 1879 adds r1, r7, r1
80005d0: 4b19 ldr r3, [pc, #100] ; (8000638 <MX_TIM16_Init+0x104>)
80005d2: 2200 movs r2, #0
80005d4: 0018 movs r0, r3
80005d6: f001 ff57 bl 8002488 <HAL_TIM_PWM_ConfigChannel>
80005da: 1e03 subs r3, r0, #0
80005dc: d001 beq.n 80005e2 <MX_TIM16_Init+0xae>
{
Error_Handler();
80005de: f000 f9b7 bl 8000950 <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
80005e2: 003b movs r3, r7
80005e4: 2200 movs r2, #0
80005e6: 601a str r2, [r3, #0]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
80005e8: 003b movs r3, r7
80005ea: 2200 movs r2, #0
80005ec: 605a str r2, [r3, #4]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
80005ee: 003b movs r3, r7
80005f0: 2200 movs r2, #0
80005f2: 609a str r2, [r3, #8]
sBreakDeadTimeConfig.DeadTime = 0;
80005f4: 003b movs r3, r7
80005f6: 2200 movs r2, #0
80005f8: 60da str r2, [r3, #12]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
80005fa: 003b movs r3, r7
80005fc: 2200 movs r2, #0
80005fe: 611a str r2, [r3, #16]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8000600: 003b movs r3, r7
8000602: 2280 movs r2, #128 ; 0x80
8000604: 0192 lsls r2, r2, #6
8000606: 615a str r2, [r3, #20]
sBreakDeadTimeConfig.BreakFilter = 0;
8000608: 003b movs r3, r7
800060a: 2200 movs r2, #0
800060c: 619a str r2, [r3, #24]
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
800060e: 003b movs r3, r7
8000610: 2200 movs r2, #0
8000612: 631a str r2, [r3, #48] ; 0x30
if (HAL_TIMEx_ConfigBreakDeadTime(&htim16, &sBreakDeadTimeConfig) != HAL_OK)
8000614: 003a movs r2, r7
8000616: 4b08 ldr r3, [pc, #32] ; (8000638 <MX_TIM16_Init+0x104>)
8000618: 0011 movs r1, r2
800061a: 0018 movs r0, r3
800061c: f002 fbfe bl 8002e1c <HAL_TIMEx_ConfigBreakDeadTime>
8000620: 1e03 subs r3, r0, #0
8000622: d001 beq.n 8000628 <MX_TIM16_Init+0xf4>
{
Error_Handler();
8000624: f000 f994 bl 8000950 <Error_Handler>
}
/* USER CODE BEGIN TIM16_Init 2 */
/* USER CODE END TIM16_Init 2 */
HAL_TIM_MspPostInit(&htim16);
8000628: 4b03 ldr r3, [pc, #12] ; (8000638 <MX_TIM16_Init+0x104>)
800062a: 0018 movs r0, r3
800062c: f000 fae4 bl 8000bf8 <HAL_TIM_MspPostInit>
}
8000630: 46c0 nop ; (mov r8, r8)
8000632: 46bd mov sp, r7
8000634: b014 add sp, #80 ; 0x50
8000636: bd80 pop {r7, pc}
8000638: 20000188 .word 0x20000188
800063c: 40014400 .word 0x40014400
8000640: 0000ffff .word 0x0000ffff
08000644 <MX_TIM17_Init>:
* @brief TIM17 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM17_Init(void)
{
8000644: b580 push {r7, lr}
8000646: b094 sub sp, #80 ; 0x50
8000648: af00 add r7, sp, #0
/* USER CODE BEGIN TIM17_Init 0 */
/* USER CODE END TIM17_Init 0 */
TIM_OC_InitTypeDef sConfigOC = {0};
800064a: 2334 movs r3, #52 ; 0x34
800064c: 18fb adds r3, r7, r3
800064e: 0018 movs r0, r3
8000650: 231c movs r3, #28
8000652: 001a movs r2, r3
8000654: 2100 movs r1, #0
8000656: f003 f887 bl 8003768 <memset>
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
800065a: 003b movs r3, r7
800065c: 0018 movs r0, r3
800065e: 2334 movs r3, #52 ; 0x34
8000660: 001a movs r2, r3
8000662: 2100 movs r1, #0
8000664: f003 f880 bl 8003768 <memset>
/* USER CODE BEGIN TIM17_Init 1 */
/* USER CODE END TIM17_Init 1 */
htim17.Instance = TIM17;
8000668: 4b37 ldr r3, [pc, #220] ; (8000748 <MX_TIM17_Init+0x104>)
800066a: 4a38 ldr r2, [pc, #224] ; (800074c <MX_TIM17_Init+0x108>)
800066c: 601a str r2, [r3, #0]
htim17.Init.Prescaler = 0;
800066e: 4b36 ldr r3, [pc, #216] ; (8000748 <MX_TIM17_Init+0x104>)
8000670: 2200 movs r2, #0
8000672: 605a str r2, [r3, #4]
htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
8000674: 4b34 ldr r3, [pc, #208] ; (8000748 <MX_TIM17_Init+0x104>)
8000676: 2200 movs r2, #0
8000678: 609a str r2, [r3, #8]
htim17.Init.Period = 65535;
800067a: 4b33 ldr r3, [pc, #204] ; (8000748 <MX_TIM17_Init+0x104>)
800067c: 4a34 ldr r2, [pc, #208] ; (8000750 <MX_TIM17_Init+0x10c>)
800067e: 60da str r2, [r3, #12]
htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000680: 4b31 ldr r3, [pc, #196] ; (8000748 <MX_TIM17_Init+0x104>)
8000682: 2200 movs r2, #0
8000684: 611a str r2, [r3, #16]
htim17.Init.RepetitionCounter = 0;
8000686: 4b30 ldr r3, [pc, #192] ; (8000748 <MX_TIM17_Init+0x104>)
8000688: 2200 movs r2, #0
800068a: 615a str r2, [r3, #20]
htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800068c: 4b2e ldr r3, [pc, #184] ; (8000748 <MX_TIM17_Init+0x104>)
800068e: 2200 movs r2, #0
8000690: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim17) != HAL_OK)
8000692: 4b2d ldr r3, [pc, #180] ; (8000748 <MX_TIM17_Init+0x104>)
8000694: 0018 movs r0, r3
8000696: f001 fc65 bl 8001f64 <HAL_TIM_Base_Init>
800069a: 1e03 subs r3, r0, #0
800069c: d001 beq.n 80006a2 <MX_TIM17_Init+0x5e>
{
Error_Handler();
800069e: f000 f957 bl 8000950 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim17) != HAL_OK)
80006a2: 4b29 ldr r3, [pc, #164] ; (8000748 <MX_TIM17_Init+0x104>)
80006a4: 0018 movs r0, r3
80006a6: f001 fcb5 bl 8002014 <HAL_TIM_PWM_Init>
80006aa: 1e03 subs r3, r0, #0
80006ac: d001 beq.n 80006b2 <MX_TIM17_Init+0x6e>
{
Error_Handler();
80006ae: f000 f94f bl 8000950 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
80006b2: 2134 movs r1, #52 ; 0x34
80006b4: 187b adds r3, r7, r1
80006b6: 2260 movs r2, #96 ; 0x60
80006b8: 601a str r2, [r3, #0]
sConfigOC.Pulse = 0;
80006ba: 187b adds r3, r7, r1
80006bc: 2200 movs r2, #0
80006be: 605a str r2, [r3, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80006c0: 187b adds r3, r7, r1
80006c2: 2200 movs r2, #0
80006c4: 609a str r2, [r3, #8]
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
80006c6: 187b adds r3, r7, r1
80006c8: 2200 movs r2, #0
80006ca: 60da str r2, [r3, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
80006cc: 187b adds r3, r7, r1
80006ce: 2200 movs r2, #0
80006d0: 611a str r2, [r3, #16]
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
80006d2: 187b adds r3, r7, r1
80006d4: 2200 movs r2, #0
80006d6: 615a str r2, [r3, #20]
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
80006d8: 187b adds r3, r7, r1
80006da: 2200 movs r2, #0
80006dc: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_ConfigChannel(&htim17, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
80006de: 1879 adds r1, r7, r1
80006e0: 4b19 ldr r3, [pc, #100] ; (8000748 <MX_TIM17_Init+0x104>)
80006e2: 2200 movs r2, #0
80006e4: 0018 movs r0, r3
80006e6: f001 fecf bl 8002488 <HAL_TIM_PWM_ConfigChannel>
80006ea: 1e03 subs r3, r0, #0
80006ec: d001 beq.n 80006f2 <MX_TIM17_Init+0xae>
{
Error_Handler();
80006ee: f000 f92f bl 8000950 <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
80006f2: 003b movs r3, r7
80006f4: 2200 movs r2, #0
80006f6: 601a str r2, [r3, #0]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
80006f8: 003b movs r3, r7
80006fa: 2200 movs r2, #0
80006fc: 605a str r2, [r3, #4]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
80006fe: 003b movs r3, r7
8000700: 2200 movs r2, #0
8000702: 609a str r2, [r3, #8]
sBreakDeadTimeConfig.DeadTime = 0;
8000704: 003b movs r3, r7
8000706: 2200 movs r2, #0
8000708: 60da str r2, [r3, #12]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
800070a: 003b movs r3, r7
800070c: 2200 movs r2, #0
800070e: 611a str r2, [r3, #16]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8000710: 003b movs r3, r7
8000712: 2280 movs r2, #128 ; 0x80
8000714: 0192 lsls r2, r2, #6
8000716: 615a str r2, [r3, #20]
sBreakDeadTimeConfig.BreakFilter = 0;
8000718: 003b movs r3, r7
800071a: 2200 movs r2, #0
800071c: 619a str r2, [r3, #24]
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
800071e: 003b movs r3, r7
8000720: 2200 movs r2, #0
8000722: 631a str r2, [r3, #48] ; 0x30
if (HAL_TIMEx_ConfigBreakDeadTime(&htim17, &sBreakDeadTimeConfig) != HAL_OK)
8000724: 003a movs r2, r7
8000726: 4b08 ldr r3, [pc, #32] ; (8000748 <MX_TIM17_Init+0x104>)
8000728: 0011 movs r1, r2
800072a: 0018 movs r0, r3
800072c: f002 fb76 bl 8002e1c <HAL_TIMEx_ConfigBreakDeadTime>
8000730: 1e03 subs r3, r0, #0
8000732: d001 beq.n 8000738 <MX_TIM17_Init+0xf4>
{
Error_Handler();
8000734: f000 f90c bl 8000950 <Error_Handler>
}
/* USER CODE BEGIN TIM17_Init 2 */
/* USER CODE END TIM17_Init 2 */
HAL_TIM_MspPostInit(&htim17);
8000738: 4b03 ldr r3, [pc, #12] ; (8000748 <MX_TIM17_Init+0x104>)
800073a: 0018 movs r0, r3
800073c: f000 fa5c bl 8000bf8 <HAL_TIM_MspPostInit>
}
8000740: 46c0 nop ; (mov r8, r8)
8000742: 46bd mov sp, r7
8000744: b014 add sp, #80 ; 0x50
8000746: bd80 pop {r7, pc}
8000748: 200001d4 .word 0x200001d4
800074c: 40014800 .word 0x40014800
8000750: 0000ffff .word 0x0000ffff
08000754 <MX_USART3_UART_Init>:
* @brief USART3 Initialization Function
* @param None
* @retval None
*/
static void MX_USART3_UART_Init(void)
{
8000754: b580 push {r7, lr}
8000756: af00 add r7, sp, #0
/* USER CODE END USART3_Init 0 */
/* USER CODE BEGIN USART3_Init 1 */
/* USER CODE END USART3_Init 1 */
huart3.Instance = USART3;
8000758: 4b16 ldr r3, [pc, #88] ; (80007b4 <MX_USART3_UART_Init+0x60>)
800075a: 4a17 ldr r2, [pc, #92] ; (80007b8 <MX_USART3_UART_Init+0x64>)
800075c: 601a str r2, [r3, #0]
huart3.Init.BaudRate = 115200;
800075e: 4b15 ldr r3, [pc, #84] ; (80007b4 <MX_USART3_UART_Init+0x60>)
8000760: 22e1 movs r2, #225 ; 0xe1
8000762: 0252 lsls r2, r2, #9
8000764: 605a str r2, [r3, #4]
huart3.Init.WordLength = UART_WORDLENGTH_8B;
8000766: 4b13 ldr r3, [pc, #76] ; (80007b4 <MX_USART3_UART_Init+0x60>)
8000768: 2200 movs r2, #0
800076a: 609a str r2, [r3, #8]
huart3.Init.StopBits = UART_STOPBITS_1;
800076c: 4b11 ldr r3, [pc, #68] ; (80007b4 <MX_USART3_UART_Init+0x60>)
800076e: 2200 movs r2, #0
8000770: 60da str r2, [r3, #12]
huart3.Init.Parity = UART_PARITY_NONE;
8000772: 4b10 ldr r3, [pc, #64] ; (80007b4 <MX_USART3_UART_Init+0x60>)
8000774: 2200 movs r2, #0
8000776: 611a str r2, [r3, #16]
huart3.Init.Mode = UART_MODE_TX_RX;
8000778: 4b0e ldr r3, [pc, #56] ; (80007b4 <MX_USART3_UART_Init+0x60>)
800077a: 220c movs r2, #12
800077c: 615a str r2, [r3, #20]
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800077e: 4b0d ldr r3, [pc, #52] ; (80007b4 <MX_USART3_UART_Init+0x60>)
8000780: 2200 movs r2, #0
8000782: 619a str r2, [r3, #24]
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
8000784: 4b0b ldr r3, [pc, #44] ; (80007b4 <MX_USART3_UART_Init+0x60>)
8000786: 2200 movs r2, #0
8000788: 61da str r2, [r3, #28]
huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
800078a: 4b0a ldr r3, [pc, #40] ; (80007b4 <MX_USART3_UART_Init+0x60>)
800078c: 2200 movs r2, #0
800078e: 621a str r2, [r3, #32]
huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1;
8000790: 4b08 ldr r3, [pc, #32] ; (80007b4 <MX_USART3_UART_Init+0x60>)
8000792: 2200 movs r2, #0
8000794: 625a str r2, [r3, #36] ; 0x24
huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000796: 4b07 ldr r3, [pc, #28] ; (80007b4 <MX_USART3_UART_Init+0x60>)
8000798: 2200 movs r2, #0
800079a: 629a str r2, [r3, #40] ; 0x28
if (HAL_UART_Init(&huart3) != HAL_OK)
800079c: 4b05 ldr r3, [pc, #20] ; (80007b4 <MX_USART3_UART_Init+0x60>)
800079e: 0018 movs r0, r3
80007a0: f002 fbfa bl 8002f98 <HAL_UART_Init>
80007a4: 1e03 subs r3, r0, #0
80007a6: d001 beq.n 80007ac <MX_USART3_UART_Init+0x58>
{
Error_Handler();
80007a8: f000 f8d2 bl 8000950 <Error_Handler>
}
/* USER CODE BEGIN USART3_Init 2 */
/* USER CODE END USART3_Init 2 */
}
80007ac: 46c0 nop ; (mov r8, r8)
80007ae: 46bd mov sp, r7
80007b0: bd80 pop {r7, pc}
80007b2: 46c0 nop ; (mov r8, r8)
80007b4: 20000220 .word 0x20000220
80007b8: 40004800 .word 0x40004800
080007bc <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80007bc: b590 push {r4, r7, lr}
80007be: b08b sub sp, #44 ; 0x2c
80007c0: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80007c2: 2414 movs r4, #20
80007c4: 193b adds r3, r7, r4
80007c6: 0018 movs r0, r3
80007c8: 2314 movs r3, #20
80007ca: 001a movs r2, r3
80007cc: 2100 movs r1, #0
80007ce: f002 ffcb bl 8003768 <memset>
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
80007d2: 4b5a ldr r3, [pc, #360] ; (800093c <MX_GPIO_Init+0x180>)
80007d4: 6b5a ldr r2, [r3, #52] ; 0x34
80007d6: 4b59 ldr r3, [pc, #356] ; (800093c <MX_GPIO_Init+0x180>)
80007d8: 2104 movs r1, #4
80007da: 430a orrs r2, r1
80007dc: 635a str r2, [r3, #52] ; 0x34
80007de: 4b57 ldr r3, [pc, #348] ; (800093c <MX_GPIO_Init+0x180>)
80007e0: 6b5b ldr r3, [r3, #52] ; 0x34
80007e2: 2204 movs r2, #4
80007e4: 4013 ands r3, r2
80007e6: 613b str r3, [r7, #16]
80007e8: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80007ea: 4b54 ldr r3, [pc, #336] ; (800093c <MX_GPIO_Init+0x180>)
80007ec: 6b5a ldr r2, [r3, #52] ; 0x34
80007ee: 4b53 ldr r3, [pc, #332] ; (800093c <MX_GPIO_Init+0x180>)
80007f0: 2101 movs r1, #1
80007f2: 430a orrs r2, r1
80007f4: 635a str r2, [r3, #52] ; 0x34
80007f6: 4b51 ldr r3, [pc, #324] ; (800093c <MX_GPIO_Init+0x180>)
80007f8: 6b5b ldr r3, [r3, #52] ; 0x34
80007fa: 2201 movs r2, #1
80007fc: 4013 ands r3, r2
80007fe: 60fb str r3, [r7, #12]
8000800: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000802: 4b4e ldr r3, [pc, #312] ; (800093c <MX_GPIO_Init+0x180>)
8000804: 6b5a ldr r2, [r3, #52] ; 0x34
8000806: 4b4d ldr r3, [pc, #308] ; (800093c <MX_GPIO_Init+0x180>)
8000808: 2102 movs r1, #2
800080a: 430a orrs r2, r1
800080c: 635a str r2, [r3, #52] ; 0x34
800080e: 4b4b ldr r3, [pc, #300] ; (800093c <MX_GPIO_Init+0x180>)
8000810: 6b5b ldr r3, [r3, #52] ; 0x34
8000812: 2202 movs r2, #2
8000814: 4013 ands r3, r2
8000816: 60bb str r3, [r7, #8]
8000818: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOD_CLK_ENABLE();
800081a: 4b48 ldr r3, [pc, #288] ; (800093c <MX_GPIO_Init+0x180>)
800081c: 6b5a ldr r2, [r3, #52] ; 0x34
800081e: 4b47 ldr r3, [pc, #284] ; (800093c <MX_GPIO_Init+0x180>)
8000820: 2108 movs r1, #8
8000822: 430a orrs r2, r1
8000824: 635a str r2, [r3, #52] ; 0x34
8000826: 4b45 ldr r3, [pc, #276] ; (800093c <MX_GPIO_Init+0x180>)
8000828: 6b5b ldr r3, [r3, #52] ; 0x34
800082a: 2208 movs r2, #8
800082c: 4013 ands r3, r2
800082e: 607b str r3, [r7, #4]
8000830: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, GEN1_FSYNC_Pin|GEN2_FSYNC_Pin|TFT_RST_Pin, GPIO_PIN_RESET);
8000832: 230a movs r3, #10
8000834: 33ff adds r3, #255 ; 0xff
8000836: 0019 movs r1, r3
8000838: 23a0 movs r3, #160 ; 0xa0
800083a: 05db lsls r3, r3, #23
800083c: 2200 movs r2, #0
800083e: 0018 movs r0, r3
8000840: f000 fdb6 bl 80013b0 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, TFT_CS_Pin|TFT_DC_Pin, GPIO_PIN_RESET);
8000844: 23c0 movs r3, #192 ; 0xc0
8000846: 021b lsls r3, r3, #8
8000848: 483d ldr r0, [pc, #244] ; (8000940 <MX_GPIO_Init+0x184>)
800084a: 2200 movs r2, #0
800084c: 0019 movs r1, r3
800084e: f000 fdaf bl 80013b0 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, CH1_EN_Pin|CH2_EN_Pin|PWM1_EN_Pin|PWM2_EN_Pin, GPIO_PIN_RESET);
8000852: 4b3c ldr r3, [pc, #240] ; (8000944 <MX_GPIO_Init+0x188>)
8000854: 2200 movs r2, #0
8000856: 210f movs r1, #15
8000858: 0018 movs r0, r3
800085a: f000 fda9 bl 80013b0 <HAL_GPIO_WritePin>
/*Configure GPIO pins : BTN_KEYPAD_Pin BTN_KEYPADC12_Pin BTN_KEYPADC13_Pin BTN_KEYPADC14_Pin
BTN_KEYPADC15_Pin BTN_KEYPADC0_Pin BTN_KEYPADC1_Pin BTN_CH1_Pin
BTN_CH2_Pin BTN_PWM1_Pin BTN_PWM2_Pin BTN_KEYPADC6_Pin
BTN_KEYPADC7_Pin BTN_KEYPADC8_Pin BTN_KEYPADC9_Pin BTN_KEYPADC10_Pin */
GPIO_InitStruct.Pin = BTN_KEYPAD_Pin|BTN_KEYPADC12_Pin|BTN_KEYPADC13_Pin|BTN_KEYPADC14_Pin
800085e: 193b adds r3, r7, r4
8000860: 4a39 ldr r2, [pc, #228] ; (8000948 <MX_GPIO_Init+0x18c>)
8000862: 601a str r2, [r3, #0]
|BTN_KEYPADC15_Pin|BTN_KEYPADC0_Pin|BTN_KEYPADC1_Pin|BTN_CH1_Pin
|BTN_CH2_Pin|BTN_PWM1_Pin|BTN_PWM2_Pin|BTN_KEYPADC6_Pin
|BTN_KEYPADC7_Pin|BTN_KEYPADC8_Pin|BTN_KEYPADC9_Pin|BTN_KEYPADC10_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000864: 193b adds r3, r7, r4
8000866: 2200 movs r2, #0
8000868: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLUP;
800086a: 193b adds r3, r7, r4
800086c: 2201 movs r2, #1
800086e: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000870: 193b adds r3, r7, r4
8000872: 4a36 ldr r2, [pc, #216] ; (800094c <MX_GPIO_Init+0x190>)
8000874: 0019 movs r1, r3
8000876: 0010 movs r0, r2
8000878: f000 fc36 bl 80010e8 <HAL_GPIO_Init>
/*Configure GPIO pins : GEN1_FSYNC_Pin GEN2_FSYNC_Pin TFT_RST_Pin */
GPIO_InitStruct.Pin = GEN1_FSYNC_Pin|GEN2_FSYNC_Pin|TFT_RST_Pin;
800087c: 0021 movs r1, r4
800087e: 187b adds r3, r7, r1
8000880: 220a movs r2, #10
8000882: 32ff adds r2, #255 ; 0xff
8000884: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000886: 000c movs r4, r1
8000888: 193b adds r3, r7, r4
800088a: 2201 movs r2, #1
800088c: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800088e: 193b adds r3, r7, r4
8000890: 2200 movs r2, #0
8000892: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000894: 193b adds r3, r7, r4
8000896: 2200 movs r2, #0
8000898: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800089a: 193a adds r2, r7, r4
800089c: 23a0 movs r3, #160 ; 0xa0
800089e: 05db lsls r3, r3, #23
80008a0: 0011 movs r1, r2
80008a2: 0018 movs r0, r3
80008a4: f000 fc20 bl 80010e8 <HAL_GPIO_Init>
/*Configure GPIO pins : TFT_CS_Pin TFT_DC_Pin */
GPIO_InitStruct.Pin = TFT_CS_Pin|TFT_DC_Pin;
80008a8: 0021 movs r1, r4
80008aa: 187b adds r3, r7, r1
80008ac: 22c0 movs r2, #192 ; 0xc0
80008ae: 0212 lsls r2, r2, #8
80008b0: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80008b2: 000c movs r4, r1
80008b4: 193b adds r3, r7, r4
80008b6: 2201 movs r2, #1
80008b8: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80008ba: 193b adds r3, r7, r4
80008bc: 2200 movs r2, #0
80008be: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80008c0: 193b adds r3, r7, r4
80008c2: 2200 movs r2, #0
80008c4: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80008c6: 193b adds r3, r7, r4
80008c8: 4a1d ldr r2, [pc, #116] ; (8000940 <MX_GPIO_Init+0x184>)
80008ca: 0019 movs r1, r3
80008cc: 0010 movs r0, r2
80008ce: f000 fc0b bl 80010e8 <HAL_GPIO_Init>
/*Configure GPIO pins : CH1_EN_Pin CH2_EN_Pin PWM1_EN_Pin PWM2_EN_Pin */
GPIO_InitStruct.Pin = CH1_EN_Pin|CH2_EN_Pin|PWM1_EN_Pin|PWM2_EN_Pin;
80008d2: 193b adds r3, r7, r4
80008d4: 220f movs r2, #15
80008d6: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80008d8: 193b adds r3, r7, r4
80008da: 2201 movs r2, #1
80008dc: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80008de: 193b adds r3, r7, r4
80008e0: 2200 movs r2, #0
80008e2: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80008e4: 193b adds r3, r7, r4
80008e6: 2200 movs r2, #0
80008e8: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80008ea: 193b adds r3, r7, r4
80008ec: 4a15 ldr r2, [pc, #84] ; (8000944 <MX_GPIO_Init+0x188>)
80008ee: 0019 movs r1, r3
80008f0: 0010 movs r0, r2
80008f2: f000 fbf9 bl 80010e8 <HAL_GPIO_Init>
/*Configure GPIO pins : BTN_TFT1_Pin BTN_TFT2_Pin BTN_TFT3_Pin */
GPIO_InitStruct.Pin = BTN_TFT1_Pin|BTN_TFT2_Pin|BTN_TFT3_Pin;
80008f6: 193b adds r3, r7, r4
80008f8: 2270 movs r2, #112 ; 0x70
80008fa: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80008fc: 193b adds r3, r7, r4
80008fe: 2200 movs r2, #0
8000900: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000902: 193b adds r3, r7, r4
8000904: 2201 movs r2, #1
8000906: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000908: 193b adds r3, r7, r4
800090a: 4a0e ldr r2, [pc, #56] ; (8000944 <MX_GPIO_Init+0x188>)
800090c: 0019 movs r1, r3
800090e: 0010 movs r0, r2
8000910: f000 fbea bl 80010e8 <HAL_GPIO_Init>
/*Configure GPIO pins : ENC_BTN_Pin BTN_LEFT_Pin BTN_RIGHT_Pin */
GPIO_InitStruct.Pin = ENC_BTN_Pin|BTN_LEFT_Pin|BTN_RIGHT_Pin;
8000914: 0021 movs r1, r4
8000916: 187b adds r3, r7, r1
8000918: 22c8 movs r2, #200 ; 0xc8
800091a: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800091c: 187b adds r3, r7, r1
800091e: 2200 movs r2, #0
8000920: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000922: 187b adds r3, r7, r1
8000924: 2201 movs r2, #1
8000926: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000928: 187b adds r3, r7, r1
800092a: 4a05 ldr r2, [pc, #20] ; (8000940 <MX_GPIO_Init+0x184>)
800092c: 0019 movs r1, r3
800092e: 0010 movs r0, r2
8000930: f000 fbda bl 80010e8 <HAL_GPIO_Init>
}
8000934: 46c0 nop ; (mov r8, r8)
8000936: 46bd mov sp, r7
8000938: b00b add sp, #44 ; 0x2c
800093a: bd90 pop {r4, r7, pc}
800093c: 40021000 .word 0x40021000
8000940: 50000400 .word 0x50000400
8000944: 50000c00 .word 0x50000c00
8000948: 0000ffff .word 0x0000ffff
800094c: 50000800 .word 0x50000800
08000950 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000950: b580 push {r7, lr}
8000952: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000954: b672 cpsid i
}
8000956: 46c0 nop ; (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000958: e7fe b.n 8000958 <Error_Handler+0x8>
...
0800095c <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
800095c: b580 push {r7, lr}
800095e: b082 sub sp, #8
8000960: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000962: 4b0f ldr r3, [pc, #60] ; (80009a0 <HAL_MspInit+0x44>)
8000964: 6c1a ldr r2, [r3, #64] ; 0x40
8000966: 4b0e ldr r3, [pc, #56] ; (80009a0 <HAL_MspInit+0x44>)
8000968: 2101 movs r1, #1
800096a: 430a orrs r2, r1
800096c: 641a str r2, [r3, #64] ; 0x40
800096e: 4b0c ldr r3, [pc, #48] ; (80009a0 <HAL_MspInit+0x44>)
8000970: 6c1b ldr r3, [r3, #64] ; 0x40
8000972: 2201 movs r2, #1
8000974: 4013 ands r3, r2
8000976: 607b str r3, [r7, #4]
8000978: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800097a: 4b09 ldr r3, [pc, #36] ; (80009a0 <HAL_MspInit+0x44>)
800097c: 6bda ldr r2, [r3, #60] ; 0x3c
800097e: 4b08 ldr r3, [pc, #32] ; (80009a0 <HAL_MspInit+0x44>)
8000980: 2180 movs r1, #128 ; 0x80
8000982: 0549 lsls r1, r1, #21
8000984: 430a orrs r2, r1
8000986: 63da str r2, [r3, #60] ; 0x3c
8000988: 4b05 ldr r3, [pc, #20] ; (80009a0 <HAL_MspInit+0x44>)
800098a: 6bda ldr r2, [r3, #60] ; 0x3c
800098c: 2380 movs r3, #128 ; 0x80
800098e: 055b lsls r3, r3, #21
8000990: 4013 ands r3, r2
8000992: 603b str r3, [r7, #0]
8000994: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000996: 46c0 nop ; (mov r8, r8)
8000998: 46bd mov sp, r7
800099a: b002 add sp, #8
800099c: bd80 pop {r7, pc}
800099e: 46c0 nop ; (mov r8, r8)
80009a0: 40021000 .word 0x40021000
080009a4 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
80009a4: b590 push {r4, r7, lr}
80009a6: b08d sub sp, #52 ; 0x34
80009a8: af00 add r7, sp, #0
80009aa: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80009ac: 241c movs r4, #28
80009ae: 193b adds r3, r7, r4
80009b0: 0018 movs r0, r3
80009b2: 2314 movs r3, #20
80009b4: 001a movs r2, r3
80009b6: 2100 movs r1, #0
80009b8: f002 fed6 bl 8003768 <memset>
if(hspi->Instance==SPI1)
80009bc: 687b ldr r3, [r7, #4]
80009be: 681b ldr r3, [r3, #0]
80009c0: 4a37 ldr r2, [pc, #220] ; (8000aa0 <HAL_SPI_MspInit+0xfc>)
80009c2: 4293 cmp r3, r2
80009c4: d131 bne.n 8000a2a <HAL_SPI_MspInit+0x86>
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
80009c6: 4b37 ldr r3, [pc, #220] ; (8000aa4 <HAL_SPI_MspInit+0x100>)
80009c8: 6c1a ldr r2, [r3, #64] ; 0x40
80009ca: 4b36 ldr r3, [pc, #216] ; (8000aa4 <HAL_SPI_MspInit+0x100>)
80009cc: 2180 movs r1, #128 ; 0x80
80009ce: 0149 lsls r1, r1, #5
80009d0: 430a orrs r2, r1
80009d2: 641a str r2, [r3, #64] ; 0x40
80009d4: 4b33 ldr r3, [pc, #204] ; (8000aa4 <HAL_SPI_MspInit+0x100>)
80009d6: 6c1a ldr r2, [r3, #64] ; 0x40
80009d8: 2380 movs r3, #128 ; 0x80
80009da: 015b lsls r3, r3, #5
80009dc: 4013 ands r3, r2
80009de: 61bb str r3, [r7, #24]
80009e0: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOA_CLK_ENABLE();
80009e2: 4b30 ldr r3, [pc, #192] ; (8000aa4 <HAL_SPI_MspInit+0x100>)
80009e4: 6b5a ldr r2, [r3, #52] ; 0x34
80009e6: 4b2f ldr r3, [pc, #188] ; (8000aa4 <HAL_SPI_MspInit+0x100>)
80009e8: 2101 movs r1, #1
80009ea: 430a orrs r2, r1
80009ec: 635a str r2, [r3, #52] ; 0x34
80009ee: 4b2d ldr r3, [pc, #180] ; (8000aa4 <HAL_SPI_MspInit+0x100>)
80009f0: 6b5b ldr r3, [r3, #52] ; 0x34
80009f2: 2201 movs r2, #1
80009f4: 4013 ands r3, r2
80009f6: 617b str r3, [r7, #20]
80009f8: 697b ldr r3, [r7, #20]
/**SPI1 GPIO Configuration
PA1 ------> SPI1_SCK
PA2 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GEN_SCLK_Pin|GEN_SDATA_Pin;
80009fa: 0021 movs r1, r4
80009fc: 187b adds r3, r7, r1
80009fe: 2206 movs r2, #6
8000a00: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a02: 187b adds r3, r7, r1
8000a04: 2202 movs r2, #2
8000a06: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a08: 187b adds r3, r7, r1
8000a0a: 2200 movs r2, #0
8000a0c: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a0e: 187b adds r3, r7, r1
8000a10: 2200 movs r2, #0
8000a12: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF0_SPI1;
8000a14: 187b adds r3, r7, r1
8000a16: 2200 movs r2, #0
8000a18: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000a1a: 187a adds r2, r7, r1
8000a1c: 23a0 movs r3, #160 ; 0xa0
8000a1e: 05db lsls r3, r3, #23
8000a20: 0011 movs r1, r2
8000a22: 0018 movs r0, r3
8000a24: f000 fb60 bl 80010e8 <HAL_GPIO_Init>
/* USER CODE BEGIN SPI2_MspInit 1 */
/* USER CODE END SPI2_MspInit 1 */
}
}
8000a28: e035 b.n 8000a96 <HAL_SPI_MspInit+0xf2>
else if(hspi->Instance==SPI2)
8000a2a: 687b ldr r3, [r7, #4]
8000a2c: 681b ldr r3, [r3, #0]
8000a2e: 4a1e ldr r2, [pc, #120] ; (8000aa8 <HAL_SPI_MspInit+0x104>)
8000a30: 4293 cmp r3, r2
8000a32: d130 bne.n 8000a96 <HAL_SPI_MspInit+0xf2>
__HAL_RCC_SPI2_CLK_ENABLE();
8000a34: 4b1b ldr r3, [pc, #108] ; (8000aa4 <HAL_SPI_MspInit+0x100>)
8000a36: 6bda ldr r2, [r3, #60] ; 0x3c
8000a38: 4b1a ldr r3, [pc, #104] ; (8000aa4 <HAL_SPI_MspInit+0x100>)
8000a3a: 2180 movs r1, #128 ; 0x80
8000a3c: 01c9 lsls r1, r1, #7
8000a3e: 430a orrs r2, r1
8000a40: 63da str r2, [r3, #60] ; 0x3c
8000a42: 4b18 ldr r3, [pc, #96] ; (8000aa4 <HAL_SPI_MspInit+0x100>)
8000a44: 6bda ldr r2, [r3, #60] ; 0x3c
8000a46: 2380 movs r3, #128 ; 0x80
8000a48: 01db lsls r3, r3, #7
8000a4a: 4013 ands r3, r2
8000a4c: 613b str r3, [r7, #16]
8000a4e: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000a50: 4b14 ldr r3, [pc, #80] ; (8000aa4 <HAL_SPI_MspInit+0x100>)
8000a52: 6b5a ldr r2, [r3, #52] ; 0x34
8000a54: 4b13 ldr r3, [pc, #76] ; (8000aa4 <HAL_SPI_MspInit+0x100>)
8000a56: 2102 movs r1, #2
8000a58: 430a orrs r2, r1
8000a5a: 635a str r2, [r3, #52] ; 0x34
8000a5c: 4b11 ldr r3, [pc, #68] ; (8000aa4 <HAL_SPI_MspInit+0x100>)
8000a5e: 6b5b ldr r3, [r3, #52] ; 0x34
8000a60: 2202 movs r2, #2
8000a62: 4013 ands r3, r2
8000a64: 60fb str r3, [r7, #12]
8000a66: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = TFT_SDA_Pin|TFT_SCL_Pin;
8000a68: 211c movs r1, #28
8000a6a: 187b adds r3, r7, r1
8000a6c: 22a0 movs r2, #160 ; 0xa0
8000a6e: 0192 lsls r2, r2, #6
8000a70: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a72: 187b adds r3, r7, r1
8000a74: 2202 movs r2, #2
8000a76: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a78: 187b adds r3, r7, r1
8000a7a: 2200 movs r2, #0
8000a7c: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a7e: 187b adds r3, r7, r1
8000a80: 2200 movs r2, #0
8000a82: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF0_SPI2;
8000a84: 187b adds r3, r7, r1
8000a86: 2200 movs r2, #0
8000a88: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000a8a: 187b adds r3, r7, r1
8000a8c: 4a07 ldr r2, [pc, #28] ; (8000aac <HAL_SPI_MspInit+0x108>)
8000a8e: 0019 movs r1, r3
8000a90: 0010 movs r0, r2
8000a92: f000 fb29 bl 80010e8 <HAL_GPIO_Init>
}
8000a96: 46c0 nop ; (mov r8, r8)
8000a98: 46bd mov sp, r7
8000a9a: b00d add sp, #52 ; 0x34
8000a9c: bd90 pop {r4, r7, pc}
8000a9e: 46c0 nop ; (mov r8, r8)
8000aa0: 40013000 .word 0x40013000
8000aa4: 40021000 .word 0x40021000
8000aa8: 40003800 .word 0x40003800
8000aac: 50000400 .word 0x50000400
08000ab0 <HAL_TIM_Encoder_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_encoder: TIM_Encoder handle pointer
* @retval None
*/
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
{
8000ab0: b590 push {r4, r7, lr}
8000ab2: b08b sub sp, #44 ; 0x2c
8000ab4: af00 add r7, sp, #0
8000ab6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000ab8: 2414 movs r4, #20
8000aba: 193b adds r3, r7, r4
8000abc: 0018 movs r0, r3
8000abe: 2314 movs r3, #20
8000ac0: 001a movs r2, r3
8000ac2: 2100 movs r1, #0
8000ac4: f002 fe50 bl 8003768 <memset>
if(htim_encoder->Instance==TIM3)
8000ac8: 687b ldr r3, [r7, #4]
8000aca: 681b ldr r3, [r3, #0]
8000acc: 4a1e ldr r2, [pc, #120] ; (8000b48 <HAL_TIM_Encoder_MspInit+0x98>)
8000ace: 4293 cmp r3, r2
8000ad0: d135 bne.n 8000b3e <HAL_TIM_Encoder_MspInit+0x8e>
{
/* USER CODE BEGIN TIM3_MspInit 0 */
/* USER CODE END TIM3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
8000ad2: 4b1e ldr r3, [pc, #120] ; (8000b4c <HAL_TIM_Encoder_MspInit+0x9c>)
8000ad4: 6bda ldr r2, [r3, #60] ; 0x3c
8000ad6: 4b1d ldr r3, [pc, #116] ; (8000b4c <HAL_TIM_Encoder_MspInit+0x9c>)
8000ad8: 2102 movs r1, #2
8000ada: 430a orrs r2, r1
8000adc: 63da str r2, [r3, #60] ; 0x3c
8000ade: 4b1b ldr r3, [pc, #108] ; (8000b4c <HAL_TIM_Encoder_MspInit+0x9c>)
8000ae0: 6bdb ldr r3, [r3, #60] ; 0x3c
8000ae2: 2202 movs r2, #2
8000ae4: 4013 ands r3, r2
8000ae6: 613b str r3, [r7, #16]
8000ae8: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000aea: 4b18 ldr r3, [pc, #96] ; (8000b4c <HAL_TIM_Encoder_MspInit+0x9c>)
8000aec: 6b5a ldr r2, [r3, #52] ; 0x34
8000aee: 4b17 ldr r3, [pc, #92] ; (8000b4c <HAL_TIM_Encoder_MspInit+0x9c>)
8000af0: 2102 movs r1, #2
8000af2: 430a orrs r2, r1
8000af4: 635a str r2, [r3, #52] ; 0x34
8000af6: 4b15 ldr r3, [pc, #84] ; (8000b4c <HAL_TIM_Encoder_MspInit+0x9c>)
8000af8: 6b5b ldr r3, [r3, #52] ; 0x34
8000afa: 2202 movs r2, #2
8000afc: 4013 ands r3, r2
8000afe: 60fb str r3, [r7, #12]
8000b00: 68fb ldr r3, [r7, #12]
/**TIM3 GPIO Configuration
PB4 ------> TIM3_CH1
PB5 ------> TIM3_CH2
*/
GPIO_InitStruct.Pin = ENC_A_Pin|ENC_B_Pin;
8000b02: 0021 movs r1, r4
8000b04: 187b adds r3, r7, r1
8000b06: 2230 movs r2, #48 ; 0x30
8000b08: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000b0a: 187b adds r3, r7, r1
8000b0c: 2202 movs r2, #2
8000b0e: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000b10: 187b adds r3, r7, r1
8000b12: 2201 movs r2, #1
8000b14: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000b16: 187b adds r3, r7, r1
8000b18: 2200 movs r2, #0
8000b1a: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
8000b1c: 187b adds r3, r7, r1
8000b1e: 2201 movs r2, #1
8000b20: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000b22: 187b adds r3, r7, r1
8000b24: 4a0a ldr r2, [pc, #40] ; (8000b50 <HAL_TIM_Encoder_MspInit+0xa0>)
8000b26: 0019 movs r1, r3
8000b28: 0010 movs r0, r2
8000b2a: f000 fadd bl 80010e8 <HAL_GPIO_Init>
/* TIM3 interrupt Init */
HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
8000b2e: 2200 movs r2, #0
8000b30: 2100 movs r1, #0
8000b32: 2010 movs r0, #16
8000b34: f000 faa6 bl 8001084 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM3_IRQn);
8000b38: 2010 movs r0, #16
8000b3a: f000 fab8 bl 80010ae <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
8000b3e: 46c0 nop ; (mov r8, r8)
8000b40: 46bd mov sp, r7
8000b42: b00b add sp, #44 ; 0x2c
8000b44: bd90 pop {r4, r7, pc}
8000b46: 46c0 nop ; (mov r8, r8)
8000b48: 40000400 .word 0x40000400
8000b4c: 40021000 .word 0x40021000
8000b50: 50000400 .word 0x50000400
08000b54 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8000b54: b580 push {r7, lr}
8000b56: b086 sub sp, #24
8000b58: af00 add r7, sp, #0
8000b5a: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM6)
8000b5c: 687b ldr r3, [r7, #4]
8000b5e: 681b ldr r3, [r3, #0]
8000b60: 4a21 ldr r2, [pc, #132] ; (8000be8 <HAL_TIM_Base_MspInit+0x94>)
8000b62: 4293 cmp r3, r2
8000b64: d114 bne.n 8000b90 <HAL_TIM_Base_MspInit+0x3c>
{
/* USER CODE BEGIN TIM6_MspInit 0 */
/* USER CODE END TIM6_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM6_CLK_ENABLE();
8000b66: 4b21 ldr r3, [pc, #132] ; (8000bec <HAL_TIM_Base_MspInit+0x98>)
8000b68: 6bda ldr r2, [r3, #60] ; 0x3c
8000b6a: 4b20 ldr r3, [pc, #128] ; (8000bec <HAL_TIM_Base_MspInit+0x98>)
8000b6c: 2110 movs r1, #16
8000b6e: 430a orrs r2, r1
8000b70: 63da str r2, [r3, #60] ; 0x3c
8000b72: 4b1e ldr r3, [pc, #120] ; (8000bec <HAL_TIM_Base_MspInit+0x98>)
8000b74: 6bdb ldr r3, [r3, #60] ; 0x3c
8000b76: 2210 movs r2, #16
8000b78: 4013 ands r3, r2
8000b7a: 617b str r3, [r7, #20]
8000b7c: 697b ldr r3, [r7, #20]
/* TIM6 interrupt Init */
HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
8000b7e: 2200 movs r2, #0
8000b80: 2100 movs r1, #0
8000b82: 2011 movs r0, #17
8000b84: f000 fa7e bl 8001084 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM6_IRQn);
8000b88: 2011 movs r0, #17
8000b8a: f000 fa90 bl 80010ae <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM17_MspInit 1 */
/* USER CODE END TIM17_MspInit 1 */
}
}
8000b8e: e026 b.n 8000bde <HAL_TIM_Base_MspInit+0x8a>
else if(htim_base->Instance==TIM16)
8000b90: 687b ldr r3, [r7, #4]
8000b92: 681b ldr r3, [r3, #0]
8000b94: 4a16 ldr r2, [pc, #88] ; (8000bf0 <HAL_TIM_Base_MspInit+0x9c>)
8000b96: 4293 cmp r3, r2
8000b98: d10e bne.n 8000bb8 <HAL_TIM_Base_MspInit+0x64>
__HAL_RCC_TIM16_CLK_ENABLE();
8000b9a: 4b14 ldr r3, [pc, #80] ; (8000bec <HAL_TIM_Base_MspInit+0x98>)
8000b9c: 6c1a ldr r2, [r3, #64] ; 0x40
8000b9e: 4b13 ldr r3, [pc, #76] ; (8000bec <HAL_TIM_Base_MspInit+0x98>)
8000ba0: 2180 movs r1, #128 ; 0x80
8000ba2: 0289 lsls r1, r1, #10
8000ba4: 430a orrs r2, r1
8000ba6: 641a str r2, [r3, #64] ; 0x40
8000ba8: 4b10 ldr r3, [pc, #64] ; (8000bec <HAL_TIM_Base_MspInit+0x98>)
8000baa: 6c1a ldr r2, [r3, #64] ; 0x40
8000bac: 2380 movs r3, #128 ; 0x80
8000bae: 029b lsls r3, r3, #10
8000bb0: 4013 ands r3, r2
8000bb2: 613b str r3, [r7, #16]
8000bb4: 693b ldr r3, [r7, #16]
}
8000bb6: e012 b.n 8000bde <HAL_TIM_Base_MspInit+0x8a>
else if(htim_base->Instance==TIM17)
8000bb8: 687b ldr r3, [r7, #4]
8000bba: 681b ldr r3, [r3, #0]
8000bbc: 4a0d ldr r2, [pc, #52] ; (8000bf4 <HAL_TIM_Base_MspInit+0xa0>)
8000bbe: 4293 cmp r3, r2
8000bc0: d10d bne.n 8000bde <HAL_TIM_Base_MspInit+0x8a>
__HAL_RCC_TIM17_CLK_ENABLE();
8000bc2: 4b0a ldr r3, [pc, #40] ; (8000bec <HAL_TIM_Base_MspInit+0x98>)
8000bc4: 6c1a ldr r2, [r3, #64] ; 0x40
8000bc6: 4b09 ldr r3, [pc, #36] ; (8000bec <HAL_TIM_Base_MspInit+0x98>)
8000bc8: 2180 movs r1, #128 ; 0x80
8000bca: 02c9 lsls r1, r1, #11
8000bcc: 430a orrs r2, r1
8000bce: 641a str r2, [r3, #64] ; 0x40
8000bd0: 4b06 ldr r3, [pc, #24] ; (8000bec <HAL_TIM_Base_MspInit+0x98>)
8000bd2: 6c1a ldr r2, [r3, #64] ; 0x40
8000bd4: 2380 movs r3, #128 ; 0x80
8000bd6: 02db lsls r3, r3, #11
8000bd8: 4013 ands r3, r2
8000bda: 60fb str r3, [r7, #12]
8000bdc: 68fb ldr r3, [r7, #12]
}
8000bde: 46c0 nop ; (mov r8, r8)
8000be0: 46bd mov sp, r7
8000be2: b006 add sp, #24
8000be4: bd80 pop {r7, pc}
8000be6: 46c0 nop ; (mov r8, r8)
8000be8: 40001000 .word 0x40001000
8000bec: 40021000 .word 0x40021000
8000bf0: 40014400 .word 0x40014400
8000bf4: 40014800 .word 0x40014800
08000bf8 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8000bf8: b590 push {r4, r7, lr}
8000bfa: b08b sub sp, #44 ; 0x2c
8000bfc: af00 add r7, sp, #0
8000bfe: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000c00: 2414 movs r4, #20
8000c02: 193b adds r3, r7, r4
8000c04: 0018 movs r0, r3
8000c06: 2314 movs r3, #20
8000c08: 001a movs r2, r3
8000c0a: 2100 movs r1, #0
8000c0c: f002 fdac bl 8003768 <memset>
if(htim->Instance==TIM16)
8000c10: 687b ldr r3, [r7, #4]
8000c12: 681b ldr r3, [r3, #0]
8000c14: 4a29 ldr r2, [pc, #164] ; (8000cbc <HAL_TIM_MspPostInit+0xc4>)
8000c16: 4293 cmp r3, r2
8000c18: d123 bne.n 8000c62 <HAL_TIM_MspPostInit+0x6a>
{
/* USER CODE BEGIN TIM16_MspPostInit 0 */
/* USER CODE END TIM16_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000c1a: 4b29 ldr r3, [pc, #164] ; (8000cc0 <HAL_TIM_MspPostInit+0xc8>)
8000c1c: 6b5a ldr r2, [r3, #52] ; 0x34
8000c1e: 4b28 ldr r3, [pc, #160] ; (8000cc0 <HAL_TIM_MspPostInit+0xc8>)
8000c20: 2101 movs r1, #1
8000c22: 430a orrs r2, r1
8000c24: 635a str r2, [r3, #52] ; 0x34
8000c26: 4b26 ldr r3, [pc, #152] ; (8000cc0 <HAL_TIM_MspPostInit+0xc8>)
8000c28: 6b5b ldr r3, [r3, #52] ; 0x34
8000c2a: 2201 movs r2, #1
8000c2c: 4013 ands r3, r2
8000c2e: 613b str r3, [r7, #16]
8000c30: 693b ldr r3, [r7, #16]
/**TIM16 GPIO Configuration
PA6 ------> TIM16_CH1
*/
GPIO_InitStruct.Pin = PWM1_Pin;
8000c32: 0021 movs r1, r4
8000c34: 187b adds r3, r7, r1
8000c36: 2240 movs r2, #64 ; 0x40
8000c38: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c3a: 187b adds r3, r7, r1
8000c3c: 2202 movs r2, #2
8000c3e: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c40: 187b adds r3, r7, r1
8000c42: 2200 movs r2, #0
8000c44: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c46: 187b adds r3, r7, r1
8000c48: 2200 movs r2, #0
8000c4a: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF5_TIM16;
8000c4c: 187b adds r3, r7, r1
8000c4e: 2205 movs r2, #5
8000c50: 611a str r2, [r3, #16]
HAL_GPIO_Init(PWM1_GPIO_Port, &GPIO_InitStruct);
8000c52: 187a adds r2, r7, r1
8000c54: 23a0 movs r3, #160 ; 0xa0
8000c56: 05db lsls r3, r3, #23
8000c58: 0011 movs r1, r2
8000c5a: 0018 movs r0, r3
8000c5c: f000 fa44 bl 80010e8 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM17_MspPostInit 1 */
/* USER CODE END TIM17_MspPostInit 1 */
}
}
8000c60: e027 b.n 8000cb2 <HAL_TIM_MspPostInit+0xba>
else if(htim->Instance==TIM17)
8000c62: 687b ldr r3, [r7, #4]
8000c64: 681b ldr r3, [r3, #0]
8000c66: 4a17 ldr r2, [pc, #92] ; (8000cc4 <HAL_TIM_MspPostInit+0xcc>)
8000c68: 4293 cmp r3, r2
8000c6a: d122 bne.n 8000cb2 <HAL_TIM_MspPostInit+0xba>
__HAL_RCC_GPIOA_CLK_ENABLE();
8000c6c: 4b14 ldr r3, [pc, #80] ; (8000cc0 <HAL_TIM_MspPostInit+0xc8>)
8000c6e: 6b5a ldr r2, [r3, #52] ; 0x34
8000c70: 4b13 ldr r3, [pc, #76] ; (8000cc0 <HAL_TIM_MspPostInit+0xc8>)
8000c72: 2101 movs r1, #1
8000c74: 430a orrs r2, r1
8000c76: 635a str r2, [r3, #52] ; 0x34
8000c78: 4b11 ldr r3, [pc, #68] ; (8000cc0 <HAL_TIM_MspPostInit+0xc8>)
8000c7a: 6b5b ldr r3, [r3, #52] ; 0x34
8000c7c: 2201 movs r2, #1
8000c7e: 4013 ands r3, r2
8000c80: 60fb str r3, [r7, #12]
8000c82: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = PWM2_Pin;
8000c84: 2114 movs r1, #20
8000c86: 187b adds r3, r7, r1
8000c88: 2280 movs r2, #128 ; 0x80
8000c8a: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c8c: 187b adds r3, r7, r1
8000c8e: 2202 movs r2, #2
8000c90: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c92: 187b adds r3, r7, r1
8000c94: 2200 movs r2, #0
8000c96: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c98: 187b adds r3, r7, r1
8000c9a: 2200 movs r2, #0
8000c9c: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF5_TIM17;
8000c9e: 187b adds r3, r7, r1
8000ca0: 2205 movs r2, #5
8000ca2: 611a str r2, [r3, #16]
HAL_GPIO_Init(PWM2_GPIO_Port, &GPIO_InitStruct);
8000ca4: 187a adds r2, r7, r1
8000ca6: 23a0 movs r3, #160 ; 0xa0
8000ca8: 05db lsls r3, r3, #23
8000caa: 0011 movs r1, r2
8000cac: 0018 movs r0, r3
8000cae: f000 fa1b bl 80010e8 <HAL_GPIO_Init>
}
8000cb2: 46c0 nop ; (mov r8, r8)
8000cb4: 46bd mov sp, r7
8000cb6: b00b add sp, #44 ; 0x2c
8000cb8: bd90 pop {r4, r7, pc}
8000cba: 46c0 nop ; (mov r8, r8)
8000cbc: 40014400 .word 0x40014400
8000cc0: 40021000 .word 0x40021000
8000cc4: 40014800 .word 0x40014800
08000cc8 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8000cc8: b590 push {r4, r7, lr}
8000cca: b08b sub sp, #44 ; 0x2c
8000ccc: af00 add r7, sp, #0
8000cce: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000cd0: 2414 movs r4, #20
8000cd2: 193b adds r3, r7, r4
8000cd4: 0018 movs r0, r3
8000cd6: 2314 movs r3, #20
8000cd8: 001a movs r2, r3
8000cda: 2100 movs r1, #0
8000cdc: f002 fd44 bl 8003768 <memset>
if(huart->Instance==USART3)
8000ce0: 687b ldr r3, [r7, #4]
8000ce2: 681b ldr r3, [r3, #0]
8000ce4: 4a1b ldr r2, [pc, #108] ; (8000d54 <HAL_UART_MspInit+0x8c>)
8000ce6: 4293 cmp r3, r2
8000ce8: d130 bne.n 8000d4c <HAL_UART_MspInit+0x84>
{
/* USER CODE BEGIN USART3_MspInit 0 */
/* USER CODE END USART3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART3_CLK_ENABLE();
8000cea: 4b1b ldr r3, [pc, #108] ; (8000d58 <HAL_UART_MspInit+0x90>)
8000cec: 6bda ldr r2, [r3, #60] ; 0x3c
8000cee: 4b1a ldr r3, [pc, #104] ; (8000d58 <HAL_UART_MspInit+0x90>)
8000cf0: 2180 movs r1, #128 ; 0x80
8000cf2: 02c9 lsls r1, r1, #11
8000cf4: 430a orrs r2, r1
8000cf6: 63da str r2, [r3, #60] ; 0x3c
8000cf8: 4b17 ldr r3, [pc, #92] ; (8000d58 <HAL_UART_MspInit+0x90>)
8000cfa: 6bda ldr r2, [r3, #60] ; 0x3c
8000cfc: 2380 movs r3, #128 ; 0x80
8000cfe: 02db lsls r3, r3, #11
8000d00: 4013 ands r3, r2
8000d02: 613b str r3, [r7, #16]
8000d04: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000d06: 4b14 ldr r3, [pc, #80] ; (8000d58 <HAL_UART_MspInit+0x90>)
8000d08: 6b5a ldr r2, [r3, #52] ; 0x34
8000d0a: 4b13 ldr r3, [pc, #76] ; (8000d58 <HAL_UART_MspInit+0x90>)
8000d0c: 2108 movs r1, #8
8000d0e: 430a orrs r2, r1
8000d10: 635a str r2, [r3, #52] ; 0x34
8000d12: 4b11 ldr r3, [pc, #68] ; (8000d58 <HAL_UART_MspInit+0x90>)
8000d14: 6b5b ldr r3, [r3, #52] ; 0x34
8000d16: 2208 movs r2, #8
8000d18: 4013 ands r3, r2
8000d1a: 60fb str r3, [r7, #12]
8000d1c: 68fb ldr r3, [r7, #12]
/**USART3 GPIO Configuration
PD8 ------> USART3_TX
PD9 ------> USART3_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
8000d1e: 193b adds r3, r7, r4
8000d20: 22c0 movs r2, #192 ; 0xc0
8000d22: 0092 lsls r2, r2, #2
8000d24: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000d26: 0021 movs r1, r4
8000d28: 187b adds r3, r7, r1
8000d2a: 2202 movs r2, #2
8000d2c: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d2e: 187b adds r3, r7, r1
8000d30: 2200 movs r2, #0
8000d32: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000d34: 187b adds r3, r7, r1
8000d36: 2200 movs r2, #0
8000d38: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF0_USART3;
8000d3a: 187b adds r3, r7, r1
8000d3c: 2200 movs r2, #0
8000d3e: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000d40: 187b adds r3, r7, r1
8000d42: 4a06 ldr r2, [pc, #24] ; (8000d5c <HAL_UART_MspInit+0x94>)
8000d44: 0019 movs r1, r3
8000d46: 0010 movs r0, r2
8000d48: f000 f9ce bl 80010e8 <HAL_GPIO_Init>
/* USER CODE BEGIN USART3_MspInit 1 */
/* USER CODE END USART3_MspInit 1 */
}
}
8000d4c: 46c0 nop ; (mov r8, r8)
8000d4e: 46bd mov sp, r7
8000d50: b00b add sp, #44 ; 0x2c
8000d52: bd90 pop {r4, r7, pc}
8000d54: 40004800 .word 0x40004800
8000d58: 40021000 .word 0x40021000
8000d5c: 50000c00 .word 0x50000c00
08000d60 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000d60: b580 push {r7, lr}
8000d62: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000d64: e7fe b.n 8000d64 <NMI_Handler+0x4>
08000d66 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000d66: b580 push {r7, lr}
8000d68: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000d6a: e7fe b.n 8000d6a <HardFault_Handler+0x4>
08000d6c <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000d6c: b580 push {r7, lr}
8000d6e: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
8000d70: 46c0 nop ; (mov r8, r8)
8000d72: 46bd mov sp, r7
8000d74: bd80 pop {r7, pc}
08000d76 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000d76: b580 push {r7, lr}
8000d78: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000d7a: 46c0 nop ; (mov r8, r8)
8000d7c: 46bd mov sp, r7
8000d7e: bd80 pop {r7, pc}
08000d80 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000d80: b580 push {r7, lr}
8000d82: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000d84: f000 f8b6 bl 8000ef4 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000d88: 46c0 nop ; (mov r8, r8)
8000d8a: 46bd mov sp, r7
8000d8c: bd80 pop {r7, pc}
...
08000d90 <TIM3_IRQHandler>:
/**
* @brief This function handles TIM3 global interrupt.
*/
void TIM3_IRQHandler(void)
{
8000d90: b580 push {r7, lr}
8000d92: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_IRQn 0 */
/* USER CODE END TIM3_IRQn 0 */
HAL_TIM_IRQHandler(&htim3);
8000d94: 4b03 ldr r3, [pc, #12] ; (8000da4 <TIM3_IRQHandler+0x14>)
8000d96: 0018 movs r0, r3
8000d98: f001 fa44 bl 8002224 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM3_IRQn 1 */
/* USER CODE END TIM3_IRQn 1 */
}
8000d9c: 46c0 nop ; (mov r8, r8)
8000d9e: 46bd mov sp, r7
8000da0: bd80 pop {r7, pc}
8000da2: 46c0 nop ; (mov r8, r8)
8000da4: 200000f0 .word 0x200000f0
08000da8 <TIM6_IRQHandler>:
/**
* @brief This function handles TIM6 global interrupt.
*/
void TIM6_IRQHandler(void)
{
8000da8: b580 push {r7, lr}
8000daa: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_IRQn 0 */
/* USER CODE END TIM6_IRQn 0 */
HAL_TIM_IRQHandler(&htim6);
8000dac: 4b03 ldr r3, [pc, #12] ; (8000dbc <TIM6_IRQHandler+0x14>)
8000dae: 0018 movs r0, r3
8000db0: f001 fa38 bl 8002224 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM6_IRQn 1 */
/* USER CODE END TIM6_IRQn 1 */
}
8000db4: 46c0 nop ; (mov r8, r8)
8000db6: 46bd mov sp, r7
8000db8: bd80 pop {r7, pc}
8000dba: 46c0 nop ; (mov r8, r8)
8000dbc: 2000013c .word 0x2000013c
08000dc0 <SystemInit>:
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
8000dc0: b580 push {r7, lr}
8000dc2: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000dc4: 46c0 nop ; (mov r8, r8)
8000dc6: 46bd mov sp, r7
8000dc8: bd80 pop {r7, pc}
...
08000dcc <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8000dcc: 480d ldr r0, [pc, #52] ; (8000e04 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8000dce: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
8000dd0: f7ff fff6 bl 8000dc0 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000dd4: 480c ldr r0, [pc, #48] ; (8000e08 <LoopForever+0x6>)
ldr r1, =_edata
8000dd6: 490d ldr r1, [pc, #52] ; (8000e0c <LoopForever+0xa>)
ldr r2, =_sidata
8000dd8: 4a0d ldr r2, [pc, #52] ; (8000e10 <LoopForever+0xe>)
movs r3, #0
8000dda: 2300 movs r3, #0
b LoopCopyDataInit
8000ddc: e002 b.n 8000de4 <LoopCopyDataInit>
08000dde <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000dde: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000de0: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000de2: 3304 adds r3, #4
08000de4 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000de4: 18c4 adds r4, r0, r3
cmp r4, r1
8000de6: 428c cmp r4, r1
bcc CopyDataInit
8000de8: d3f9 bcc.n 8000dde <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000dea: 4a0a ldr r2, [pc, #40] ; (8000e14 <LoopForever+0x12>)
ldr r4, =_ebss
8000dec: 4c0a ldr r4, [pc, #40] ; (8000e18 <LoopForever+0x16>)
movs r3, #0
8000dee: 2300 movs r3, #0
b LoopFillZerobss
8000df0: e001 b.n 8000df6 <LoopFillZerobss>
08000df2 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000df2: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000df4: 3204 adds r2, #4
08000df6 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000df6: 42a2 cmp r2, r4
bcc FillZerobss
8000df8: d3fb bcc.n 8000df2 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000dfa: f002 fc91 bl 8003720 <__libc_init_array>
/* Call the application s entry point.*/
bl main
8000dfe: f7ff fa0b bl 8000218 <main>
08000e02 <LoopForever>:
LoopForever:
b LoopForever
8000e02: e7fe b.n 8000e02 <LoopForever>
ldr r0, =_estack
8000e04: 20009000 .word 0x20009000
ldr r0, =_sdata
8000e08: 20000000 .word 0x20000000
ldr r1, =_edata
8000e0c: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000e10: 08003864 .word 0x08003864
ldr r2, =_sbss
8000e14: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000e18: 200002b8 .word 0x200002b8
08000e1c <ADC1_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000e1c: e7fe b.n 8000e1c <ADC1_IRQHandler>
...
08000e20 <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000e20: b580 push {r7, lr}
8000e22: b082 sub sp, #8
8000e24: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8000e26: 1dfb adds r3, r7, #7
8000e28: 2200 movs r2, #0
8000e2a: 701a strb r2, [r3, #0]
#if (INSTRUCTION_CACHE_ENABLE == 0U)
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000e2c: 4b0b ldr r3, [pc, #44] ; (8000e5c <HAL_Init+0x3c>)
8000e2e: 681a ldr r2, [r3, #0]
8000e30: 4b0a ldr r3, [pc, #40] ; (8000e5c <HAL_Init+0x3c>)
8000e32: 2180 movs r1, #128 ; 0x80
8000e34: 0049 lsls r1, r1, #1
8000e36: 430a orrs r2, r1
8000e38: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8000e3a: 2003 movs r0, #3
8000e3c: f000 f810 bl 8000e60 <HAL_InitTick>
8000e40: 1e03 subs r3, r0, #0
8000e42: d003 beq.n 8000e4c <HAL_Init+0x2c>
{
status = HAL_ERROR;
8000e44: 1dfb adds r3, r7, #7
8000e46: 2201 movs r2, #1
8000e48: 701a strb r2, [r3, #0]
8000e4a: e001 b.n 8000e50 <HAL_Init+0x30>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8000e4c: f7ff fd86 bl 800095c <HAL_MspInit>
}
/* Return function status */
return status;
8000e50: 1dfb adds r3, r7, #7
8000e52: 781b ldrb r3, [r3, #0]
}
8000e54: 0018 movs r0, r3
8000e56: 46bd mov sp, r7
8000e58: b002 add sp, #8
8000e5a: bd80 pop {r7, pc}
8000e5c: 40022000 .word 0x40022000
08000e60 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000e60: b590 push {r4, r7, lr}
8000e62: b085 sub sp, #20
8000e64: af00 add r7, sp, #0
8000e66: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8000e68: 230f movs r3, #15
8000e6a: 18fb adds r3, r7, r3
8000e6c: 2200 movs r2, #0
8000e6e: 701a strb r2, [r3, #0]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
8000e70: 4b1d ldr r3, [pc, #116] ; (8000ee8 <HAL_InitTick+0x88>)
8000e72: 781b ldrb r3, [r3, #0]
8000e74: 2b00 cmp r3, #0
8000e76: d02b beq.n 8000ed0 <HAL_InitTick+0x70>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U)
8000e78: 4b1c ldr r3, [pc, #112] ; (8000eec <HAL_InitTick+0x8c>)
8000e7a: 681c ldr r4, [r3, #0]
8000e7c: 4b1a ldr r3, [pc, #104] ; (8000ee8 <HAL_InitTick+0x88>)
8000e7e: 781b ldrb r3, [r3, #0]
8000e80: 0019 movs r1, r3
8000e82: 23fa movs r3, #250 ; 0xfa
8000e84: 0098 lsls r0, r3, #2
8000e86: f7ff f93b bl 8000100 <__udivsi3>
8000e8a: 0003 movs r3, r0
8000e8c: 0019 movs r1, r3
8000e8e: 0020 movs r0, r4
8000e90: f7ff f936 bl 8000100 <__udivsi3>
8000e94: 0003 movs r3, r0
8000e96: 0018 movs r0, r3
8000e98: f000 f919 bl 80010ce <HAL_SYSTICK_Config>
8000e9c: 1e03 subs r3, r0, #0
8000e9e: d112 bne.n 8000ec6 <HAL_InitTick+0x66>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000ea0: 687b ldr r3, [r7, #4]
8000ea2: 2b03 cmp r3, #3
8000ea4: d80a bhi.n 8000ebc <HAL_InitTick+0x5c>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000ea6: 6879 ldr r1, [r7, #4]
8000ea8: 2301 movs r3, #1
8000eaa: 425b negs r3, r3
8000eac: 2200 movs r2, #0
8000eae: 0018 movs r0, r3
8000eb0: f000 f8e8 bl 8001084 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000eb4: 4b0e ldr r3, [pc, #56] ; (8000ef0 <HAL_InitTick+0x90>)
8000eb6: 687a ldr r2, [r7, #4]
8000eb8: 601a str r2, [r3, #0]
8000eba: e00d b.n 8000ed8 <HAL_InitTick+0x78>
}
else
{
status = HAL_ERROR;
8000ebc: 230f movs r3, #15
8000ebe: 18fb adds r3, r7, r3
8000ec0: 2201 movs r2, #1
8000ec2: 701a strb r2, [r3, #0]
8000ec4: e008 b.n 8000ed8 <HAL_InitTick+0x78>
}
}
else
{
status = HAL_ERROR;
8000ec6: 230f movs r3, #15
8000ec8: 18fb adds r3, r7, r3
8000eca: 2201 movs r2, #1
8000ecc: 701a strb r2, [r3, #0]
8000ece: e003 b.n 8000ed8 <HAL_InitTick+0x78>
}
}
else
{
status = HAL_ERROR;
8000ed0: 230f movs r3, #15
8000ed2: 18fb adds r3, r7, r3
8000ed4: 2201 movs r2, #1
8000ed6: 701a strb r2, [r3, #0]
}
/* Return function status */
return status;
8000ed8: 230f movs r3, #15
8000eda: 18fb adds r3, r7, r3
8000edc: 781b ldrb r3, [r3, #0]
}
8000ede: 0018 movs r0, r3
8000ee0: 46bd mov sp, r7
8000ee2: b005 add sp, #20
8000ee4: bd90 pop {r4, r7, pc}
8000ee6: 46c0 nop ; (mov r8, r8)
8000ee8: 20000008 .word 0x20000008
8000eec: 20000000 .word 0x20000000
8000ef0: 20000004 .word 0x20000004
08000ef4 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000ef4: b580 push {r7, lr}
8000ef6: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
8000ef8: 4b05 ldr r3, [pc, #20] ; (8000f10 <HAL_IncTick+0x1c>)
8000efa: 781b ldrb r3, [r3, #0]
8000efc: 001a movs r2, r3
8000efe: 4b05 ldr r3, [pc, #20] ; (8000f14 <HAL_IncTick+0x20>)
8000f00: 681b ldr r3, [r3, #0]
8000f02: 18d2 adds r2, r2, r3
8000f04: 4b03 ldr r3, [pc, #12] ; (8000f14 <HAL_IncTick+0x20>)
8000f06: 601a str r2, [r3, #0]
}
8000f08: 46c0 nop ; (mov r8, r8)
8000f0a: 46bd mov sp, r7
8000f0c: bd80 pop {r7, pc}
8000f0e: 46c0 nop ; (mov r8, r8)
8000f10: 20000008 .word 0x20000008
8000f14: 200002b4 .word 0x200002b4
08000f18 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000f18: b580 push {r7, lr}
8000f1a: af00 add r7, sp, #0
return uwTick;
8000f1c: 4b02 ldr r3, [pc, #8] ; (8000f28 <HAL_GetTick+0x10>)
8000f1e: 681b ldr r3, [r3, #0]
}
8000f20: 0018 movs r0, r3
8000f22: 46bd mov sp, r7
8000f24: bd80 pop {r7, pc}
8000f26: 46c0 nop ; (mov r8, r8)
8000f28: 200002b4 .word 0x200002b4
08000f2c <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8000f2c: b580 push {r7, lr}
8000f2e: b082 sub sp, #8
8000f30: af00 add r7, sp, #0
8000f32: 0002 movs r2, r0
8000f34: 1dfb adds r3, r7, #7
8000f36: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
8000f38: 1dfb adds r3, r7, #7
8000f3a: 781b ldrb r3, [r3, #0]
8000f3c: 2b7f cmp r3, #127 ; 0x7f
8000f3e: d809 bhi.n 8000f54 <__NVIC_EnableIRQ+0x28>
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8000f40: 1dfb adds r3, r7, #7
8000f42: 781b ldrb r3, [r3, #0]
8000f44: 001a movs r2, r3
8000f46: 231f movs r3, #31
8000f48: 401a ands r2, r3
8000f4a: 4b04 ldr r3, [pc, #16] ; (8000f5c <__NVIC_EnableIRQ+0x30>)
8000f4c: 2101 movs r1, #1
8000f4e: 4091 lsls r1, r2
8000f50: 000a movs r2, r1
8000f52: 601a str r2, [r3, #0]
__COMPILER_BARRIER();
}
}
8000f54: 46c0 nop ; (mov r8, r8)
8000f56: 46bd mov sp, r7
8000f58: b002 add sp, #8
8000f5a: bd80 pop {r7, pc}
8000f5c: e000e100 .word 0xe000e100
08000f60 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000f60: b590 push {r4, r7, lr}
8000f62: b083 sub sp, #12
8000f64: af00 add r7, sp, #0
8000f66: 0002 movs r2, r0
8000f68: 6039 str r1, [r7, #0]
8000f6a: 1dfb adds r3, r7, #7
8000f6c: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
8000f6e: 1dfb adds r3, r7, #7
8000f70: 781b ldrb r3, [r3, #0]
8000f72: 2b7f cmp r3, #127 ; 0x7f
8000f74: d828 bhi.n 8000fc8 <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000f76: 4a2f ldr r2, [pc, #188] ; (8001034 <__NVIC_SetPriority+0xd4>)
8000f78: 1dfb adds r3, r7, #7
8000f7a: 781b ldrb r3, [r3, #0]
8000f7c: b25b sxtb r3, r3
8000f7e: 089b lsrs r3, r3, #2
8000f80: 33c0 adds r3, #192 ; 0xc0
8000f82: 009b lsls r3, r3, #2
8000f84: 589b ldr r3, [r3, r2]
8000f86: 1dfa adds r2, r7, #7
8000f88: 7812 ldrb r2, [r2, #0]
8000f8a: 0011 movs r1, r2
8000f8c: 2203 movs r2, #3
8000f8e: 400a ands r2, r1
8000f90: 00d2 lsls r2, r2, #3
8000f92: 21ff movs r1, #255 ; 0xff
8000f94: 4091 lsls r1, r2
8000f96: 000a movs r2, r1
8000f98: 43d2 mvns r2, r2
8000f9a: 401a ands r2, r3
8000f9c: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8000f9e: 683b ldr r3, [r7, #0]
8000fa0: 019b lsls r3, r3, #6
8000fa2: 22ff movs r2, #255 ; 0xff
8000fa4: 401a ands r2, r3
8000fa6: 1dfb adds r3, r7, #7
8000fa8: 781b ldrb r3, [r3, #0]
8000faa: 0018 movs r0, r3
8000fac: 2303 movs r3, #3
8000fae: 4003 ands r3, r0
8000fb0: 00db lsls r3, r3, #3
8000fb2: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000fb4: 481f ldr r0, [pc, #124] ; (8001034 <__NVIC_SetPriority+0xd4>)
8000fb6: 1dfb adds r3, r7, #7
8000fb8: 781b ldrb r3, [r3, #0]
8000fba: b25b sxtb r3, r3
8000fbc: 089b lsrs r3, r3, #2
8000fbe: 430a orrs r2, r1
8000fc0: 33c0 adds r3, #192 ; 0xc0
8000fc2: 009b lsls r3, r3, #2
8000fc4: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
8000fc6: e031 b.n 800102c <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000fc8: 4a1b ldr r2, [pc, #108] ; (8001038 <__NVIC_SetPriority+0xd8>)
8000fca: 1dfb adds r3, r7, #7
8000fcc: 781b ldrb r3, [r3, #0]
8000fce: 0019 movs r1, r3
8000fd0: 230f movs r3, #15
8000fd2: 400b ands r3, r1
8000fd4: 3b08 subs r3, #8
8000fd6: 089b lsrs r3, r3, #2
8000fd8: 3306 adds r3, #6
8000fda: 009b lsls r3, r3, #2
8000fdc: 18d3 adds r3, r2, r3
8000fde: 3304 adds r3, #4
8000fe0: 681b ldr r3, [r3, #0]
8000fe2: 1dfa adds r2, r7, #7
8000fe4: 7812 ldrb r2, [r2, #0]
8000fe6: 0011 movs r1, r2
8000fe8: 2203 movs r2, #3
8000fea: 400a ands r2, r1
8000fec: 00d2 lsls r2, r2, #3
8000fee: 21ff movs r1, #255 ; 0xff
8000ff0: 4091 lsls r1, r2
8000ff2: 000a movs r2, r1
8000ff4: 43d2 mvns r2, r2
8000ff6: 401a ands r2, r3
8000ff8: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8000ffa: 683b ldr r3, [r7, #0]
8000ffc: 019b lsls r3, r3, #6
8000ffe: 22ff movs r2, #255 ; 0xff
8001000: 401a ands r2, r3
8001002: 1dfb adds r3, r7, #7
8001004: 781b ldrb r3, [r3, #0]
8001006: 0018 movs r0, r3
8001008: 2303 movs r3, #3
800100a: 4003 ands r3, r0
800100c: 00db lsls r3, r3, #3
800100e: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8001010: 4809 ldr r0, [pc, #36] ; (8001038 <__NVIC_SetPriority+0xd8>)
8001012: 1dfb adds r3, r7, #7
8001014: 781b ldrb r3, [r3, #0]
8001016: 001c movs r4, r3
8001018: 230f movs r3, #15
800101a: 4023 ands r3, r4
800101c: 3b08 subs r3, #8
800101e: 089b lsrs r3, r3, #2
8001020: 430a orrs r2, r1
8001022: 3306 adds r3, #6
8001024: 009b lsls r3, r3, #2
8001026: 18c3 adds r3, r0, r3
8001028: 3304 adds r3, #4
800102a: 601a str r2, [r3, #0]
}
800102c: 46c0 nop ; (mov r8, r8)
800102e: 46bd mov sp, r7
8001030: b003 add sp, #12
8001032: bd90 pop {r4, r7, pc}
8001034: e000e100 .word 0xe000e100
8001038: e000ed00 .word 0xe000ed00
0800103c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
800103c: b580 push {r7, lr}
800103e: b082 sub sp, #8
8001040: af00 add r7, sp, #0
8001042: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8001044: 687b ldr r3, [r7, #4]
8001046: 1e5a subs r2, r3, #1
8001048: 2380 movs r3, #128 ; 0x80
800104a: 045b lsls r3, r3, #17
800104c: 429a cmp r2, r3
800104e: d301 bcc.n 8001054 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
8001050: 2301 movs r3, #1
8001052: e010 b.n 8001076 <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8001054: 4b0a ldr r3, [pc, #40] ; (8001080 <SysTick_Config+0x44>)
8001056: 687a ldr r2, [r7, #4]
8001058: 3a01 subs r2, #1
800105a: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800105c: 2301 movs r3, #1
800105e: 425b negs r3, r3
8001060: 2103 movs r1, #3
8001062: 0018 movs r0, r3
8001064: f7ff ff7c bl 8000f60 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8001068: 4b05 ldr r3, [pc, #20] ; (8001080 <SysTick_Config+0x44>)
800106a: 2200 movs r2, #0
800106c: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800106e: 4b04 ldr r3, [pc, #16] ; (8001080 <SysTick_Config+0x44>)
8001070: 2207 movs r2, #7
8001072: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001074: 2300 movs r3, #0
}
8001076: 0018 movs r0, r3
8001078: 46bd mov sp, r7
800107a: b002 add sp, #8
800107c: bd80 pop {r7, pc}
800107e: 46c0 nop ; (mov r8, r8)
8001080: e000e010 .word 0xe000e010
08001084 <HAL_NVIC_SetPriority>:
* with stm32g0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0+ based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001084: b580 push {r7, lr}
8001086: b084 sub sp, #16
8001088: af00 add r7, sp, #0
800108a: 60b9 str r1, [r7, #8]
800108c: 607a str r2, [r7, #4]
800108e: 210f movs r1, #15
8001090: 187b adds r3, r7, r1
8001092: 1c02 adds r2, r0, #0
8001094: 701a strb r2, [r3, #0]
/* Prevent unused argument(s) compilation warning */
UNUSED(SubPriority);
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn, PreemptPriority);
8001096: 68ba ldr r2, [r7, #8]
8001098: 187b adds r3, r7, r1
800109a: 781b ldrb r3, [r3, #0]
800109c: b25b sxtb r3, r3
800109e: 0011 movs r1, r2
80010a0: 0018 movs r0, r3
80010a2: f7ff ff5d bl 8000f60 <__NVIC_SetPriority>
}
80010a6: 46c0 nop ; (mov r8, r8)
80010a8: 46bd mov sp, r7
80010aa: b004 add sp, #16
80010ac: bd80 pop {r7, pc}
080010ae <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80010ae: b580 push {r7, lr}
80010b0: b082 sub sp, #8
80010b2: af00 add r7, sp, #0
80010b4: 0002 movs r2, r0
80010b6: 1dfb adds r3, r7, #7
80010b8: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80010ba: 1dfb adds r3, r7, #7
80010bc: 781b ldrb r3, [r3, #0]
80010be: b25b sxtb r3, r3
80010c0: 0018 movs r0, r3
80010c2: f7ff ff33 bl 8000f2c <__NVIC_EnableIRQ>
}
80010c6: 46c0 nop ; (mov r8, r8)
80010c8: 46bd mov sp, r7
80010ca: b002 add sp, #8
80010cc: bd80 pop {r7, pc}
080010ce <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80010ce: b580 push {r7, lr}
80010d0: b082 sub sp, #8
80010d2: af00 add r7, sp, #0
80010d4: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80010d6: 687b ldr r3, [r7, #4]
80010d8: 0018 movs r0, r3
80010da: f7ff ffaf bl 800103c <SysTick_Config>
80010de: 0003 movs r3, r0
}
80010e0: 0018 movs r0, r3
80010e2: 46bd mov sp, r7
80010e4: b002 add sp, #8
80010e6: bd80 pop {r7, pc}
080010e8 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80010e8: b580 push {r7, lr}
80010ea: b086 sub sp, #24
80010ec: af00 add r7, sp, #0
80010ee: 6078 str r0, [r7, #4]
80010f0: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
80010f2: 2300 movs r3, #0
80010f4: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
80010f6: e147 b.n 8001388 <HAL_GPIO_Init+0x2a0>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
80010f8: 683b ldr r3, [r7, #0]
80010fa: 681b ldr r3, [r3, #0]
80010fc: 2101 movs r1, #1
80010fe: 697a ldr r2, [r7, #20]
8001100: 4091 lsls r1, r2
8001102: 000a movs r2, r1
8001104: 4013 ands r3, r2
8001106: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8001108: 68fb ldr r3, [r7, #12]
800110a: 2b00 cmp r3, #0
800110c: d100 bne.n 8001110 <HAL_GPIO_Init+0x28>
800110e: e138 b.n 8001382 <HAL_GPIO_Init+0x29a>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001110: 683b ldr r3, [r7, #0]
8001112: 685b ldr r3, [r3, #4]
8001114: 2203 movs r2, #3
8001116: 4013 ands r3, r2
8001118: 2b01 cmp r3, #1
800111a: d005 beq.n 8001128 <HAL_GPIO_Init+0x40>
800111c: 683b ldr r3, [r7, #0]
800111e: 685b ldr r3, [r3, #4]
8001120: 2203 movs r2, #3
8001122: 4013 ands r3, r2
8001124: 2b02 cmp r3, #2
8001126: d130 bne.n 800118a <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001128: 687b ldr r3, [r7, #4]
800112a: 689b ldr r3, [r3, #8]
800112c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
800112e: 697b ldr r3, [r7, #20]
8001130: 005b lsls r3, r3, #1
8001132: 2203 movs r2, #3
8001134: 409a lsls r2, r3
8001136: 0013 movs r3, r2
8001138: 43da mvns r2, r3
800113a: 693b ldr r3, [r7, #16]
800113c: 4013 ands r3, r2
800113e: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8001140: 683b ldr r3, [r7, #0]
8001142: 68da ldr r2, [r3, #12]
8001144: 697b ldr r3, [r7, #20]
8001146: 005b lsls r3, r3, #1
8001148: 409a lsls r2, r3
800114a: 0013 movs r3, r2
800114c: 693a ldr r2, [r7, #16]
800114e: 4313 orrs r3, r2
8001150: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8001152: 687b ldr r3, [r7, #4]
8001154: 693a ldr r2, [r7, #16]
8001156: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001158: 687b ldr r3, [r7, #4]
800115a: 685b ldr r3, [r3, #4]
800115c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
800115e: 2201 movs r2, #1
8001160: 697b ldr r3, [r7, #20]
8001162: 409a lsls r2, r3
8001164: 0013 movs r3, r2
8001166: 43da mvns r2, r3
8001168: 693b ldr r3, [r7, #16]
800116a: 4013 ands r3, r2
800116c: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800116e: 683b ldr r3, [r7, #0]
8001170: 685b ldr r3, [r3, #4]
8001172: 091b lsrs r3, r3, #4
8001174: 2201 movs r2, #1
8001176: 401a ands r2, r3
8001178: 697b ldr r3, [r7, #20]
800117a: 409a lsls r2, r3
800117c: 0013 movs r3, r2
800117e: 693a ldr r2, [r7, #16]
8001180: 4313 orrs r3, r2
8001182: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8001184: 687b ldr r3, [r7, #4]
8001186: 693a ldr r2, [r7, #16]
8001188: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
800118a: 683b ldr r3, [r7, #0]
800118c: 685b ldr r3, [r3, #4]
800118e: 2203 movs r2, #3
8001190: 4013 ands r3, r2
8001192: 2b03 cmp r3, #3
8001194: d017 beq.n 80011c6 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001196: 687b ldr r3, [r7, #4]
8001198: 68db ldr r3, [r3, #12]
800119a: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
800119c: 697b ldr r3, [r7, #20]
800119e: 005b lsls r3, r3, #1
80011a0: 2203 movs r2, #3
80011a2: 409a lsls r2, r3
80011a4: 0013 movs r3, r2
80011a6: 43da mvns r2, r3
80011a8: 693b ldr r3, [r7, #16]
80011aa: 4013 ands r3, r2
80011ac: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
80011ae: 683b ldr r3, [r7, #0]
80011b0: 689a ldr r2, [r3, #8]
80011b2: 697b ldr r3, [r7, #20]
80011b4: 005b lsls r3, r3, #1
80011b6: 409a lsls r2, r3
80011b8: 0013 movs r3, r2
80011ba: 693a ldr r2, [r7, #16]
80011bc: 4313 orrs r3, r2
80011be: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80011c0: 687b ldr r3, [r7, #4]
80011c2: 693a ldr r2, [r7, #16]
80011c4: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80011c6: 683b ldr r3, [r7, #0]
80011c8: 685b ldr r3, [r3, #4]
80011ca: 2203 movs r2, #3
80011cc: 4013 ands r3, r2
80011ce: 2b02 cmp r3, #2
80011d0: d123 bne.n 800121a <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
80011d2: 697b ldr r3, [r7, #20]
80011d4: 08da lsrs r2, r3, #3
80011d6: 687b ldr r3, [r7, #4]
80011d8: 3208 adds r2, #8
80011da: 0092 lsls r2, r2, #2
80011dc: 58d3 ldr r3, [r2, r3]
80011de: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
80011e0: 697b ldr r3, [r7, #20]
80011e2: 2207 movs r2, #7
80011e4: 4013 ands r3, r2
80011e6: 009b lsls r3, r3, #2
80011e8: 220f movs r2, #15
80011ea: 409a lsls r2, r3
80011ec: 0013 movs r3, r2
80011ee: 43da mvns r2, r3
80011f0: 693b ldr r3, [r7, #16]
80011f2: 4013 ands r3, r2
80011f4: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
80011f6: 683b ldr r3, [r7, #0]
80011f8: 691a ldr r2, [r3, #16]
80011fa: 697b ldr r3, [r7, #20]
80011fc: 2107 movs r1, #7
80011fe: 400b ands r3, r1
8001200: 009b lsls r3, r3, #2
8001202: 409a lsls r2, r3
8001204: 0013 movs r3, r2
8001206: 693a ldr r2, [r7, #16]
8001208: 4313 orrs r3, r2
800120a: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
800120c: 697b ldr r3, [r7, #20]
800120e: 08da lsrs r2, r3, #3
8001210: 687b ldr r3, [r7, #4]
8001212: 3208 adds r2, #8
8001214: 0092 lsls r2, r2, #2
8001216: 6939 ldr r1, [r7, #16]
8001218: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
800121a: 687b ldr r3, [r7, #4]
800121c: 681b ldr r3, [r3, #0]
800121e: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
8001220: 697b ldr r3, [r7, #20]
8001222: 005b lsls r3, r3, #1
8001224: 2203 movs r2, #3
8001226: 409a lsls r2, r3
8001228: 0013 movs r3, r2
800122a: 43da mvns r2, r3
800122c: 693b ldr r3, [r7, #16]
800122e: 4013 ands r3, r2
8001230: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8001232: 683b ldr r3, [r7, #0]
8001234: 685b ldr r3, [r3, #4]
8001236: 2203 movs r2, #3
8001238: 401a ands r2, r3
800123a: 697b ldr r3, [r7, #20]
800123c: 005b lsls r3, r3, #1
800123e: 409a lsls r2, r3
8001240: 0013 movs r3, r2
8001242: 693a ldr r2, [r7, #16]
8001244: 4313 orrs r3, r2
8001246: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001248: 687b ldr r3, [r7, #4]
800124a: 693a ldr r2, [r7, #16]
800124c: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
800124e: 683b ldr r3, [r7, #0]
8001250: 685a ldr r2, [r3, #4]
8001252: 23c0 movs r3, #192 ; 0xc0
8001254: 029b lsls r3, r3, #10
8001256: 4013 ands r3, r2
8001258: d100 bne.n 800125c <HAL_GPIO_Init+0x174>
800125a: e092 b.n 8001382 <HAL_GPIO_Init+0x29a>
{
temp = EXTI->EXTICR[position >> 2u];
800125c: 4a50 ldr r2, [pc, #320] ; (80013a0 <HAL_GPIO_Init+0x2b8>)
800125e: 697b ldr r3, [r7, #20]
8001260: 089b lsrs r3, r3, #2
8001262: 3318 adds r3, #24
8001264: 009b lsls r3, r3, #2
8001266: 589b ldr r3, [r3, r2]
8001268: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (8u * (position & 0x03u)));
800126a: 697b ldr r3, [r7, #20]
800126c: 2203 movs r2, #3
800126e: 4013 ands r3, r2
8001270: 00db lsls r3, r3, #3
8001272: 220f movs r2, #15
8001274: 409a lsls r2, r3
8001276: 0013 movs r3, r2
8001278: 43da mvns r2, r3
800127a: 693b ldr r3, [r7, #16]
800127c: 4013 ands r3, r2
800127e: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)));
8001280: 687a ldr r2, [r7, #4]
8001282: 23a0 movs r3, #160 ; 0xa0
8001284: 05db lsls r3, r3, #23
8001286: 429a cmp r2, r3
8001288: d013 beq.n 80012b2 <HAL_GPIO_Init+0x1ca>
800128a: 687b ldr r3, [r7, #4]
800128c: 4a45 ldr r2, [pc, #276] ; (80013a4 <HAL_GPIO_Init+0x2bc>)
800128e: 4293 cmp r3, r2
8001290: d00d beq.n 80012ae <HAL_GPIO_Init+0x1c6>
8001292: 687b ldr r3, [r7, #4]
8001294: 4a44 ldr r2, [pc, #272] ; (80013a8 <HAL_GPIO_Init+0x2c0>)
8001296: 4293 cmp r3, r2
8001298: d007 beq.n 80012aa <HAL_GPIO_Init+0x1c2>
800129a: 687b ldr r3, [r7, #4]
800129c: 4a43 ldr r2, [pc, #268] ; (80013ac <HAL_GPIO_Init+0x2c4>)
800129e: 4293 cmp r3, r2
80012a0: d101 bne.n 80012a6 <HAL_GPIO_Init+0x1be>
80012a2: 2303 movs r3, #3
80012a4: e006 b.n 80012b4 <HAL_GPIO_Init+0x1cc>
80012a6: 2305 movs r3, #5
80012a8: e004 b.n 80012b4 <HAL_GPIO_Init+0x1cc>
80012aa: 2302 movs r3, #2
80012ac: e002 b.n 80012b4 <HAL_GPIO_Init+0x1cc>
80012ae: 2301 movs r3, #1
80012b0: e000 b.n 80012b4 <HAL_GPIO_Init+0x1cc>
80012b2: 2300 movs r3, #0
80012b4: 697a ldr r2, [r7, #20]
80012b6: 2103 movs r1, #3
80012b8: 400a ands r2, r1
80012ba: 00d2 lsls r2, r2, #3
80012bc: 4093 lsls r3, r2
80012be: 693a ldr r2, [r7, #16]
80012c0: 4313 orrs r3, r2
80012c2: 613b str r3, [r7, #16]
EXTI->EXTICR[position >> 2u] = temp;
80012c4: 4936 ldr r1, [pc, #216] ; (80013a0 <HAL_GPIO_Init+0x2b8>)
80012c6: 697b ldr r3, [r7, #20]
80012c8: 089b lsrs r3, r3, #2
80012ca: 3318 adds r3, #24
80012cc: 009b lsls r3, r3, #2
80012ce: 693a ldr r2, [r7, #16]
80012d0: 505a str r2, [r3, r1]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
80012d2: 4b33 ldr r3, [pc, #204] ; (80013a0 <HAL_GPIO_Init+0x2b8>)
80012d4: 681b ldr r3, [r3, #0]
80012d6: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80012d8: 68fb ldr r3, [r7, #12]
80012da: 43da mvns r2, r3
80012dc: 693b ldr r3, [r7, #16]
80012de: 4013 ands r3, r2
80012e0: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
80012e2: 683b ldr r3, [r7, #0]
80012e4: 685a ldr r2, [r3, #4]
80012e6: 2380 movs r3, #128 ; 0x80
80012e8: 035b lsls r3, r3, #13
80012ea: 4013 ands r3, r2
80012ec: d003 beq.n 80012f6 <HAL_GPIO_Init+0x20e>
{
temp |= iocurrent;
80012ee: 693a ldr r2, [r7, #16]
80012f0: 68fb ldr r3, [r7, #12]
80012f2: 4313 orrs r3, r2
80012f4: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
80012f6: 4b2a ldr r3, [pc, #168] ; (80013a0 <HAL_GPIO_Init+0x2b8>)
80012f8: 693a ldr r2, [r7, #16]
80012fa: 601a str r2, [r3, #0]
temp = EXTI->FTSR1;
80012fc: 4b28 ldr r3, [pc, #160] ; (80013a0 <HAL_GPIO_Init+0x2b8>)
80012fe: 685b ldr r3, [r3, #4]
8001300: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001302: 68fb ldr r3, [r7, #12]
8001304: 43da mvns r2, r3
8001306: 693b ldr r3, [r7, #16]
8001308: 4013 ands r3, r2
800130a: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
800130c: 683b ldr r3, [r7, #0]
800130e: 685a ldr r2, [r3, #4]
8001310: 2380 movs r3, #128 ; 0x80
8001312: 039b lsls r3, r3, #14
8001314: 4013 ands r3, r2
8001316: d003 beq.n 8001320 <HAL_GPIO_Init+0x238>
{
temp |= iocurrent;
8001318: 693a ldr r2, [r7, #16]
800131a: 68fb ldr r3, [r7, #12]
800131c: 4313 orrs r3, r2
800131e: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8001320: 4b1f ldr r3, [pc, #124] ; (80013a0 <HAL_GPIO_Init+0x2b8>)
8001322: 693a ldr r2, [r7, #16]
8001324: 605a str r2, [r3, #4]
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
8001326: 4a1e ldr r2, [pc, #120] ; (80013a0 <HAL_GPIO_Init+0x2b8>)
8001328: 2384 movs r3, #132 ; 0x84
800132a: 58d3 ldr r3, [r2, r3]
800132c: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800132e: 68fb ldr r3, [r7, #12]
8001330: 43da mvns r2, r3
8001332: 693b ldr r3, [r7, #16]
8001334: 4013 ands r3, r2
8001336: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001338: 683b ldr r3, [r7, #0]
800133a: 685a ldr r2, [r3, #4]
800133c: 2380 movs r3, #128 ; 0x80
800133e: 029b lsls r3, r3, #10
8001340: 4013 ands r3, r2
8001342: d003 beq.n 800134c <HAL_GPIO_Init+0x264>
{
temp |= iocurrent;
8001344: 693a ldr r2, [r7, #16]
8001346: 68fb ldr r3, [r7, #12]
8001348: 4313 orrs r3, r2
800134a: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
800134c: 4914 ldr r1, [pc, #80] ; (80013a0 <HAL_GPIO_Init+0x2b8>)
800134e: 2284 movs r2, #132 ; 0x84
8001350: 693b ldr r3, [r7, #16]
8001352: 508b str r3, [r1, r2]
temp = EXTI->IMR1;
8001354: 4a12 ldr r2, [pc, #72] ; (80013a0 <HAL_GPIO_Init+0x2b8>)
8001356: 2380 movs r3, #128 ; 0x80
8001358: 58d3 ldr r3, [r2, r3]
800135a: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800135c: 68fb ldr r3, [r7, #12]
800135e: 43da mvns r2, r3
8001360: 693b ldr r3, [r7, #16]
8001362: 4013 ands r3, r2
8001364: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8001366: 683b ldr r3, [r7, #0]
8001368: 685a ldr r2, [r3, #4]
800136a: 2380 movs r3, #128 ; 0x80
800136c: 025b lsls r3, r3, #9
800136e: 4013 ands r3, r2
8001370: d003 beq.n 800137a <HAL_GPIO_Init+0x292>
{
temp |= iocurrent;
8001372: 693a ldr r2, [r7, #16]
8001374: 68fb ldr r3, [r7, #12]
8001376: 4313 orrs r3, r2
8001378: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
800137a: 4909 ldr r1, [pc, #36] ; (80013a0 <HAL_GPIO_Init+0x2b8>)
800137c: 2280 movs r2, #128 ; 0x80
800137e: 693b ldr r3, [r7, #16]
8001380: 508b str r3, [r1, r2]
}
}
position++;
8001382: 697b ldr r3, [r7, #20]
8001384: 3301 adds r3, #1
8001386: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001388: 683b ldr r3, [r7, #0]
800138a: 681a ldr r2, [r3, #0]
800138c: 697b ldr r3, [r7, #20]
800138e: 40da lsrs r2, r3
8001390: 1e13 subs r3, r2, #0
8001392: d000 beq.n 8001396 <HAL_GPIO_Init+0x2ae>
8001394: e6b0 b.n 80010f8 <HAL_GPIO_Init+0x10>
}
}
8001396: 46c0 nop ; (mov r8, r8)
8001398: 46c0 nop ; (mov r8, r8)
800139a: 46bd mov sp, r7
800139c: b006 add sp, #24
800139e: bd80 pop {r7, pc}
80013a0: 40021800 .word 0x40021800
80013a4: 50000400 .word 0x50000400
80013a8: 50000800 .word 0x50000800
80013ac: 50000c00 .word 0x50000c00
080013b0 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80013b0: b580 push {r7, lr}
80013b2: b082 sub sp, #8
80013b4: af00 add r7, sp, #0
80013b6: 6078 str r0, [r7, #4]
80013b8: 0008 movs r0, r1
80013ba: 0011 movs r1, r2
80013bc: 1cbb adds r3, r7, #2
80013be: 1c02 adds r2, r0, #0
80013c0: 801a strh r2, [r3, #0]
80013c2: 1c7b adds r3, r7, #1
80013c4: 1c0a adds r2, r1, #0
80013c6: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
80013c8: 1c7b adds r3, r7, #1
80013ca: 781b ldrb r3, [r3, #0]
80013cc: 2b00 cmp r3, #0
80013ce: d004 beq.n 80013da <HAL_GPIO_WritePin+0x2a>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
80013d0: 1cbb adds r3, r7, #2
80013d2: 881a ldrh r2, [r3, #0]
80013d4: 687b ldr r3, [r7, #4]
80013d6: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
80013d8: e003 b.n 80013e2 <HAL_GPIO_WritePin+0x32>
GPIOx->BRR = (uint32_t)GPIO_Pin;
80013da: 1cbb adds r3, r7, #2
80013dc: 881a ldrh r2, [r3, #0]
80013de: 687b ldr r3, [r7, #4]
80013e0: 629a str r2, [r3, #40] ; 0x28
}
80013e2: 46c0 nop ; (mov r8, r8)
80013e4: 46bd mov sp, r7
80013e6: b002 add sp, #8
80013e8: bd80 pop {r7, pc}
...
080013ec <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 6 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
80013ec: b580 push {r7, lr}
80013ee: b084 sub sp, #16
80013f0: af00 add r7, sp, #0
80013f2: 6078 str r0, [r7, #4]
uint32_t wait_loop_index;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
/* Modify voltage scaling range */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
80013f4: 4b19 ldr r3, [pc, #100] ; (800145c <HAL_PWREx_ControlVoltageScaling+0x70>)
80013f6: 681b ldr r3, [r3, #0]
80013f8: 4a19 ldr r2, [pc, #100] ; (8001460 <HAL_PWREx_ControlVoltageScaling+0x74>)
80013fa: 4013 ands r3, r2
80013fc: 0019 movs r1, r3
80013fe: 4b17 ldr r3, [pc, #92] ; (800145c <HAL_PWREx_ControlVoltageScaling+0x70>)
8001400: 687a ldr r2, [r7, #4]
8001402: 430a orrs r2, r1
8001404: 601a str r2, [r3, #0]
/* In case of Range 1 selected, we need to ensure that main regulator reaches new value */
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
8001406: 687a ldr r2, [r7, #4]
8001408: 2380 movs r3, #128 ; 0x80
800140a: 009b lsls r3, r3, #2
800140c: 429a cmp r2, r3
800140e: d11f bne.n 8001450 <HAL_PWREx_ControlVoltageScaling+0x64>
{
/* Set timeout value */
wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U;
8001410: 4b14 ldr r3, [pc, #80] ; (8001464 <HAL_PWREx_ControlVoltageScaling+0x78>)
8001412: 681a ldr r2, [r3, #0]
8001414: 0013 movs r3, r2
8001416: 005b lsls r3, r3, #1
8001418: 189b adds r3, r3, r2
800141a: 005b lsls r3, r3, #1
800141c: 4912 ldr r1, [pc, #72] ; (8001468 <HAL_PWREx_ControlVoltageScaling+0x7c>)
800141e: 0018 movs r0, r3
8001420: f7fe fe6e bl 8000100 <__udivsi3>
8001424: 0003 movs r3, r0
8001426: 3301 adds r3, #1
8001428: 60fb str r3, [r7, #12]
/* Wait until VOSF is reset */
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
800142a: e008 b.n 800143e <HAL_PWREx_ControlVoltageScaling+0x52>
{
if (wait_loop_index != 0U)
800142c: 68fb ldr r3, [r7, #12]
800142e: 2b00 cmp r3, #0
8001430: d003 beq.n 800143a <HAL_PWREx_ControlVoltageScaling+0x4e>
{
wait_loop_index--;
8001432: 68fb ldr r3, [r7, #12]
8001434: 3b01 subs r3, #1
8001436: 60fb str r3, [r7, #12]
8001438: e001 b.n 800143e <HAL_PWREx_ControlVoltageScaling+0x52>
}
else
{
return HAL_TIMEOUT;
800143a: 2303 movs r3, #3
800143c: e009 b.n 8001452 <HAL_PWREx_ControlVoltageScaling+0x66>
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
800143e: 4b07 ldr r3, [pc, #28] ; (800145c <HAL_PWREx_ControlVoltageScaling+0x70>)
8001440: 695a ldr r2, [r3, #20]
8001442: 2380 movs r3, #128 ; 0x80
8001444: 00db lsls r3, r3, #3
8001446: 401a ands r2, r3
8001448: 2380 movs r3, #128 ; 0x80
800144a: 00db lsls r3, r3, #3
800144c: 429a cmp r2, r3
800144e: d0ed beq.n 800142c <HAL_PWREx_ControlVoltageScaling+0x40>
}
}
}
return HAL_OK;
8001450: 2300 movs r3, #0
}
8001452: 0018 movs r0, r3
8001454: 46bd mov sp, r7
8001456: b004 add sp, #16
8001458: bd80 pop {r7, pc}
800145a: 46c0 nop ; (mov r8, r8)
800145c: 40007000 .word 0x40007000
8001460: fffff9ff .word 0xfffff9ff
8001464: 20000000 .word 0x20000000
8001468: 000f4240 .word 0x000f4240
0800146c <LL_RCC_GetAPB1Prescaler>:
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
{
800146c: b580 push {r7, lr}
800146e: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
8001470: 4b03 ldr r3, [pc, #12] ; (8001480 <LL_RCC_GetAPB1Prescaler+0x14>)
8001472: 689a ldr r2, [r3, #8]
8001474: 23e0 movs r3, #224 ; 0xe0
8001476: 01db lsls r3, r3, #7
8001478: 4013 ands r3, r2
}
800147a: 0018 movs r0, r3
800147c: 46bd mov sp, r7
800147e: bd80 pop {r7, pc}
8001480: 40021000 .word 0x40021000
08001484 <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to LSE Off
* first and then to LSE On or LSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001484: b580 push {r7, lr}
8001486: b088 sub sp, #32
8001488: af00 add r7, sp, #0
800148a: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t temp_sysclksrc;
uint32_t temp_pllckcfg;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
800148c: 687b ldr r3, [r7, #4]
800148e: 2b00 cmp r3, #0
8001490: d101 bne.n 8001496 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8001492: 2301 movs r3, #1
8001494: e2f3 b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001496: 687b ldr r3, [r7, #4]
8001498: 681b ldr r3, [r3, #0]
800149a: 2201 movs r2, #1
800149c: 4013 ands r3, r2
800149e: d100 bne.n 80014a2 <HAL_RCC_OscConfig+0x1e>
80014a0: e07c b.n 800159c <HAL_RCC_OscConfig+0x118>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
80014a2: 4bc3 ldr r3, [pc, #780] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80014a4: 689b ldr r3, [r3, #8]
80014a6: 2238 movs r2, #56 ; 0x38
80014a8: 4013 ands r3, r2
80014aa: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
80014ac: 4bc0 ldr r3, [pc, #768] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80014ae: 68db ldr r3, [r3, #12]
80014b0: 2203 movs r2, #3
80014b2: 4013 ands r3, r2
80014b4: 617b str r3, [r7, #20]
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE))
80014b6: 69bb ldr r3, [r7, #24]
80014b8: 2b10 cmp r3, #16
80014ba: d102 bne.n 80014c2 <HAL_RCC_OscConfig+0x3e>
80014bc: 697b ldr r3, [r7, #20]
80014be: 2b03 cmp r3, #3
80014c0: d002 beq.n 80014c8 <HAL_RCC_OscConfig+0x44>
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE))
80014c2: 69bb ldr r3, [r7, #24]
80014c4: 2b08 cmp r3, #8
80014c6: d10b bne.n 80014e0 <HAL_RCC_OscConfig+0x5c>
{
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80014c8: 4bb9 ldr r3, [pc, #740] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80014ca: 681a ldr r2, [r3, #0]
80014cc: 2380 movs r3, #128 ; 0x80
80014ce: 029b lsls r3, r3, #10
80014d0: 4013 ands r3, r2
80014d2: d062 beq.n 800159a <HAL_RCC_OscConfig+0x116>
80014d4: 687b ldr r3, [r7, #4]
80014d6: 685b ldr r3, [r3, #4]
80014d8: 2b00 cmp r3, #0
80014da: d15e bne.n 800159a <HAL_RCC_OscConfig+0x116>
{
return HAL_ERROR;
80014dc: 2301 movs r3, #1
80014de: e2ce b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80014e0: 687b ldr r3, [r7, #4]
80014e2: 685a ldr r2, [r3, #4]
80014e4: 2380 movs r3, #128 ; 0x80
80014e6: 025b lsls r3, r3, #9
80014e8: 429a cmp r2, r3
80014ea: d107 bne.n 80014fc <HAL_RCC_OscConfig+0x78>
80014ec: 4bb0 ldr r3, [pc, #704] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80014ee: 681a ldr r2, [r3, #0]
80014f0: 4baf ldr r3, [pc, #700] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80014f2: 2180 movs r1, #128 ; 0x80
80014f4: 0249 lsls r1, r1, #9
80014f6: 430a orrs r2, r1
80014f8: 601a str r2, [r3, #0]
80014fa: e020 b.n 800153e <HAL_RCC_OscConfig+0xba>
80014fc: 687b ldr r3, [r7, #4]
80014fe: 685a ldr r2, [r3, #4]
8001500: 23a0 movs r3, #160 ; 0xa0
8001502: 02db lsls r3, r3, #11
8001504: 429a cmp r2, r3
8001506: d10e bne.n 8001526 <HAL_RCC_OscConfig+0xa2>
8001508: 4ba9 ldr r3, [pc, #676] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
800150a: 681a ldr r2, [r3, #0]
800150c: 4ba8 ldr r3, [pc, #672] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
800150e: 2180 movs r1, #128 ; 0x80
8001510: 02c9 lsls r1, r1, #11
8001512: 430a orrs r2, r1
8001514: 601a str r2, [r3, #0]
8001516: 4ba6 ldr r3, [pc, #664] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001518: 681a ldr r2, [r3, #0]
800151a: 4ba5 ldr r3, [pc, #660] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
800151c: 2180 movs r1, #128 ; 0x80
800151e: 0249 lsls r1, r1, #9
8001520: 430a orrs r2, r1
8001522: 601a str r2, [r3, #0]
8001524: e00b b.n 800153e <HAL_RCC_OscConfig+0xba>
8001526: 4ba2 ldr r3, [pc, #648] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001528: 681a ldr r2, [r3, #0]
800152a: 4ba1 ldr r3, [pc, #644] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
800152c: 49a1 ldr r1, [pc, #644] ; (80017b4 <HAL_RCC_OscConfig+0x330>)
800152e: 400a ands r2, r1
8001530: 601a str r2, [r3, #0]
8001532: 4b9f ldr r3, [pc, #636] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001534: 681a ldr r2, [r3, #0]
8001536: 4b9e ldr r3, [pc, #632] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001538: 499f ldr r1, [pc, #636] ; (80017b8 <HAL_RCC_OscConfig+0x334>)
800153a: 400a ands r2, r1
800153c: 601a str r2, [r3, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800153e: 687b ldr r3, [r7, #4]
8001540: 685b ldr r3, [r3, #4]
8001542: 2b00 cmp r3, #0
8001544: d014 beq.n 8001570 <HAL_RCC_OscConfig+0xec>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001546: f7ff fce7 bl 8000f18 <HAL_GetTick>
800154a: 0003 movs r3, r0
800154c: 613b str r3, [r7, #16]
/* Wait till HSE is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
800154e: e008 b.n 8001562 <HAL_RCC_OscConfig+0xde>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8001550: f7ff fce2 bl 8000f18 <HAL_GetTick>
8001554: 0002 movs r2, r0
8001556: 693b ldr r3, [r7, #16]
8001558: 1ad3 subs r3, r2, r3
800155a: 2b64 cmp r3, #100 ; 0x64
800155c: d901 bls.n 8001562 <HAL_RCC_OscConfig+0xde>
{
return HAL_TIMEOUT;
800155e: 2303 movs r3, #3
8001560: e28d b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8001562: 4b93 ldr r3, [pc, #588] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001564: 681a ldr r2, [r3, #0]
8001566: 2380 movs r3, #128 ; 0x80
8001568: 029b lsls r3, r3, #10
800156a: 4013 ands r3, r2
800156c: d0f0 beq.n 8001550 <HAL_RCC_OscConfig+0xcc>
800156e: e015 b.n 800159c <HAL_RCC_OscConfig+0x118>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001570: f7ff fcd2 bl 8000f18 <HAL_GetTick>
8001574: 0003 movs r3, r0
8001576: 613b str r3, [r7, #16]
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8001578: e008 b.n 800158c <HAL_RCC_OscConfig+0x108>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800157a: f7ff fccd bl 8000f18 <HAL_GetTick>
800157e: 0002 movs r2, r0
8001580: 693b ldr r3, [r7, #16]
8001582: 1ad3 subs r3, r2, r3
8001584: 2b64 cmp r3, #100 ; 0x64
8001586: d901 bls.n 800158c <HAL_RCC_OscConfig+0x108>
{
return HAL_TIMEOUT;
8001588: 2303 movs r3, #3
800158a: e278 b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
800158c: 4b88 ldr r3, [pc, #544] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
800158e: 681a ldr r2, [r3, #0]
8001590: 2380 movs r3, #128 ; 0x80
8001592: 029b lsls r3, r3, #10
8001594: 4013 ands r3, r2
8001596: d1f0 bne.n 800157a <HAL_RCC_OscConfig+0xf6>
8001598: e000 b.n 800159c <HAL_RCC_OscConfig+0x118>
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800159a: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800159c: 687b ldr r3, [r7, #4]
800159e: 681b ldr r3, [r3, #0]
80015a0: 2202 movs r2, #2
80015a2: 4013 ands r3, r2
80015a4: d100 bne.n 80015a8 <HAL_RCC_OscConfig+0x124>
80015a6: e099 b.n 80016dc <HAL_RCC_OscConfig+0x258>
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv));
/* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
80015a8: 4b81 ldr r3, [pc, #516] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80015aa: 689b ldr r3, [r3, #8]
80015ac: 2238 movs r2, #56 ; 0x38
80015ae: 4013 ands r3, r2
80015b0: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
80015b2: 4b7f ldr r3, [pc, #508] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80015b4: 68db ldr r3, [r3, #12]
80015b6: 2203 movs r2, #3
80015b8: 4013 ands r3, r2
80015ba: 617b str r3, [r7, #20]
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI))
80015bc: 69bb ldr r3, [r7, #24]
80015be: 2b10 cmp r3, #16
80015c0: d102 bne.n 80015c8 <HAL_RCC_OscConfig+0x144>
80015c2: 697b ldr r3, [r7, #20]
80015c4: 2b02 cmp r3, #2
80015c6: d002 beq.n 80015ce <HAL_RCC_OscConfig+0x14a>
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI))
80015c8: 69bb ldr r3, [r7, #24]
80015ca: 2b00 cmp r3, #0
80015cc: d135 bne.n 800163a <HAL_RCC_OscConfig+0x1b6>
{
/* When HSI is used as system clock or as PLL input clock it can not be disabled */
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
80015ce: 4b78 ldr r3, [pc, #480] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80015d0: 681a ldr r2, [r3, #0]
80015d2: 2380 movs r3, #128 ; 0x80
80015d4: 00db lsls r3, r3, #3
80015d6: 4013 ands r3, r2
80015d8: d005 beq.n 80015e6 <HAL_RCC_OscConfig+0x162>
80015da: 687b ldr r3, [r7, #4]
80015dc: 68db ldr r3, [r3, #12]
80015de: 2b00 cmp r3, #0
80015e0: d101 bne.n 80015e6 <HAL_RCC_OscConfig+0x162>
{
return HAL_ERROR;
80015e2: 2301 movs r3, #1
80015e4: e24b b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80015e6: 4b72 ldr r3, [pc, #456] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80015e8: 685b ldr r3, [r3, #4]
80015ea: 4a74 ldr r2, [pc, #464] ; (80017bc <HAL_RCC_OscConfig+0x338>)
80015ec: 4013 ands r3, r2
80015ee: 0019 movs r1, r3
80015f0: 687b ldr r3, [r7, #4]
80015f2: 695b ldr r3, [r3, #20]
80015f4: 021a lsls r2, r3, #8
80015f6: 4b6e ldr r3, [pc, #440] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80015f8: 430a orrs r2, r1
80015fa: 605a str r2, [r3, #4]
if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)
80015fc: 69bb ldr r3, [r7, #24]
80015fe: 2b00 cmp r3, #0
8001600: d112 bne.n 8001628 <HAL_RCC_OscConfig+0x1a4>
{
/* Adjust the HSI16 division factor */
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
8001602: 4b6b ldr r3, [pc, #428] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001604: 681b ldr r3, [r3, #0]
8001606: 4a6e ldr r2, [pc, #440] ; (80017c0 <HAL_RCC_OscConfig+0x33c>)
8001608: 4013 ands r3, r2
800160a: 0019 movs r1, r3
800160c: 687b ldr r3, [r7, #4]
800160e: 691a ldr r2, [r3, #16]
8001610: 4b67 ldr r3, [pc, #412] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001612: 430a orrs r2, r1
8001614: 601a str r2, [r3, #0]
/* Update the SystemCoreClock global variable with HSISYS value */
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
8001616: 4b66 ldr r3, [pc, #408] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001618: 681b ldr r3, [r3, #0]
800161a: 0adb lsrs r3, r3, #11
800161c: 2207 movs r2, #7
800161e: 4013 ands r3, r2
8001620: 4a68 ldr r2, [pc, #416] ; (80017c4 <HAL_RCC_OscConfig+0x340>)
8001622: 40da lsrs r2, r3
8001624: 4b68 ldr r3, [pc, #416] ; (80017c8 <HAL_RCC_OscConfig+0x344>)
8001626: 601a str r2, [r3, #0]
}
/* Adapt Systick interrupt period */
if (HAL_InitTick(uwTickPrio) != HAL_OK)
8001628: 4b68 ldr r3, [pc, #416] ; (80017cc <HAL_RCC_OscConfig+0x348>)
800162a: 681b ldr r3, [r3, #0]
800162c: 0018 movs r0, r3
800162e: f7ff fc17 bl 8000e60 <HAL_InitTick>
8001632: 1e03 subs r3, r0, #0
8001634: d051 beq.n 80016da <HAL_RCC_OscConfig+0x256>
{
return HAL_ERROR;
8001636: 2301 movs r3, #1
8001638: e221 b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
800163a: 687b ldr r3, [r7, #4]
800163c: 68db ldr r3, [r3, #12]
800163e: 2b00 cmp r3, #0
8001640: d030 beq.n 80016a4 <HAL_RCC_OscConfig+0x220>
{
/* Configure the HSI16 division factor */
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
8001642: 4b5b ldr r3, [pc, #364] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001644: 681b ldr r3, [r3, #0]
8001646: 4a5e ldr r2, [pc, #376] ; (80017c0 <HAL_RCC_OscConfig+0x33c>)
8001648: 4013 ands r3, r2
800164a: 0019 movs r1, r3
800164c: 687b ldr r3, [r7, #4]
800164e: 691a ldr r2, [r3, #16]
8001650: 4b57 ldr r3, [pc, #348] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001652: 430a orrs r2, r1
8001654: 601a str r2, [r3, #0]
/* Enable the Internal High Speed oscillator (HSI16). */
__HAL_RCC_HSI_ENABLE();
8001656: 4b56 ldr r3, [pc, #344] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001658: 681a ldr r2, [r3, #0]
800165a: 4b55 ldr r3, [pc, #340] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
800165c: 2180 movs r1, #128 ; 0x80
800165e: 0049 lsls r1, r1, #1
8001660: 430a orrs r2, r1
8001662: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001664: f7ff fc58 bl 8000f18 <HAL_GetTick>
8001668: 0003 movs r3, r0
800166a: 613b str r3, [r7, #16]
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800166c: e008 b.n 8001680 <HAL_RCC_OscConfig+0x1fc>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800166e: f7ff fc53 bl 8000f18 <HAL_GetTick>
8001672: 0002 movs r2, r0
8001674: 693b ldr r3, [r7, #16]
8001676: 1ad3 subs r3, r2, r3
8001678: 2b02 cmp r3, #2
800167a: d901 bls.n 8001680 <HAL_RCC_OscConfig+0x1fc>
{
return HAL_TIMEOUT;
800167c: 2303 movs r3, #3
800167e: e1fe b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8001680: 4b4b ldr r3, [pc, #300] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001682: 681a ldr r2, [r3, #0]
8001684: 2380 movs r3, #128 ; 0x80
8001686: 00db lsls r3, r3, #3
8001688: 4013 ands r3, r2
800168a: d0f0 beq.n 800166e <HAL_RCC_OscConfig+0x1ea>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800168c: 4b48 ldr r3, [pc, #288] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
800168e: 685b ldr r3, [r3, #4]
8001690: 4a4a ldr r2, [pc, #296] ; (80017bc <HAL_RCC_OscConfig+0x338>)
8001692: 4013 ands r3, r2
8001694: 0019 movs r1, r3
8001696: 687b ldr r3, [r7, #4]
8001698: 695b ldr r3, [r3, #20]
800169a: 021a lsls r2, r3, #8
800169c: 4b44 ldr r3, [pc, #272] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
800169e: 430a orrs r2, r1
80016a0: 605a str r2, [r3, #4]
80016a2: e01b b.n 80016dc <HAL_RCC_OscConfig+0x258>
}
else
{
/* Disable the Internal High Speed oscillator (HSI16). */
__HAL_RCC_HSI_DISABLE();
80016a4: 4b42 ldr r3, [pc, #264] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80016a6: 681a ldr r2, [r3, #0]
80016a8: 4b41 ldr r3, [pc, #260] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80016aa: 4949 ldr r1, [pc, #292] ; (80017d0 <HAL_RCC_OscConfig+0x34c>)
80016ac: 400a ands r2, r1
80016ae: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80016b0: f7ff fc32 bl 8000f18 <HAL_GetTick>
80016b4: 0003 movs r3, r0
80016b6: 613b str r3, [r7, #16]
/* Wait till HSI is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
80016b8: e008 b.n 80016cc <HAL_RCC_OscConfig+0x248>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80016ba: f7ff fc2d bl 8000f18 <HAL_GetTick>
80016be: 0002 movs r2, r0
80016c0: 693b ldr r3, [r7, #16]
80016c2: 1ad3 subs r3, r2, r3
80016c4: 2b02 cmp r3, #2
80016c6: d901 bls.n 80016cc <HAL_RCC_OscConfig+0x248>
{
return HAL_TIMEOUT;
80016c8: 2303 movs r3, #3
80016ca: e1d8 b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
80016cc: 4b38 ldr r3, [pc, #224] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80016ce: 681a ldr r2, [r3, #0]
80016d0: 2380 movs r3, #128 ; 0x80
80016d2: 00db lsls r3, r3, #3
80016d4: 4013 ands r3, r2
80016d6: d1f0 bne.n 80016ba <HAL_RCC_OscConfig+0x236>
80016d8: e000 b.n 80016dc <HAL_RCC_OscConfig+0x258>
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
80016da: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80016dc: 687b ldr r3, [r7, #4]
80016de: 681b ldr r3, [r3, #0]
80016e0: 2208 movs r2, #8
80016e2: 4013 ands r3, r2
80016e4: d047 beq.n 8001776 <HAL_RCC_OscConfig+0x2f2>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check if LSI is used as system clock */
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
80016e6: 4b32 ldr r3, [pc, #200] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80016e8: 689b ldr r3, [r3, #8]
80016ea: 2238 movs r2, #56 ; 0x38
80016ec: 4013 ands r3, r2
80016ee: 2b18 cmp r3, #24
80016f0: d10a bne.n 8001708 <HAL_RCC_OscConfig+0x284>
{
/* When LSI is used as system clock it will not be disabled */
if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF))
80016f2: 4b2f ldr r3, [pc, #188] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
80016f4: 6e1b ldr r3, [r3, #96] ; 0x60
80016f6: 2202 movs r2, #2
80016f8: 4013 ands r3, r2
80016fa: d03c beq.n 8001776 <HAL_RCC_OscConfig+0x2f2>
80016fc: 687b ldr r3, [r7, #4]
80016fe: 699b ldr r3, [r3, #24]
8001700: 2b00 cmp r3, #0
8001702: d138 bne.n 8001776 <HAL_RCC_OscConfig+0x2f2>
{
return HAL_ERROR;
8001704: 2301 movs r3, #1
8001706: e1ba b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
}
}
else
{
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8001708: 687b ldr r3, [r7, #4]
800170a: 699b ldr r3, [r3, #24]
800170c: 2b00 cmp r3, #0
800170e: d019 beq.n 8001744 <HAL_RCC_OscConfig+0x2c0>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001710: 4b27 ldr r3, [pc, #156] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001712: 6e1a ldr r2, [r3, #96] ; 0x60
8001714: 4b26 ldr r3, [pc, #152] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001716: 2101 movs r1, #1
8001718: 430a orrs r2, r1
800171a: 661a str r2, [r3, #96] ; 0x60
/* Get Start Tick*/
tickstart = HAL_GetTick();
800171c: f7ff fbfc bl 8000f18 <HAL_GetTick>
8001720: 0003 movs r3, r0
8001722: 613b str r3, [r7, #16]
/* Wait till LSI is ready */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8001724: e008 b.n 8001738 <HAL_RCC_OscConfig+0x2b4>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8001726: f7ff fbf7 bl 8000f18 <HAL_GetTick>
800172a: 0002 movs r2, r0
800172c: 693b ldr r3, [r7, #16]
800172e: 1ad3 subs r3, r2, r3
8001730: 2b02 cmp r3, #2
8001732: d901 bls.n 8001738 <HAL_RCC_OscConfig+0x2b4>
{
return HAL_TIMEOUT;
8001734: 2303 movs r3, #3
8001736: e1a2 b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8001738: 4b1d ldr r3, [pc, #116] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
800173a: 6e1b ldr r3, [r3, #96] ; 0x60
800173c: 2202 movs r2, #2
800173e: 4013 ands r3, r2
8001740: d0f1 beq.n 8001726 <HAL_RCC_OscConfig+0x2a2>
8001742: e018 b.n 8001776 <HAL_RCC_OscConfig+0x2f2>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001744: 4b1a ldr r3, [pc, #104] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001746: 6e1a ldr r2, [r3, #96] ; 0x60
8001748: 4b19 ldr r3, [pc, #100] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
800174a: 2101 movs r1, #1
800174c: 438a bics r2, r1
800174e: 661a str r2, [r3, #96] ; 0x60
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001750: f7ff fbe2 bl 8000f18 <HAL_GetTick>
8001754: 0003 movs r3, r0
8001756: 613b str r3, [r7, #16]
/* Wait till LSI is disabled */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8001758: e008 b.n 800176c <HAL_RCC_OscConfig+0x2e8>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800175a: f7ff fbdd bl 8000f18 <HAL_GetTick>
800175e: 0002 movs r2, r0
8001760: 693b ldr r3, [r7, #16]
8001762: 1ad3 subs r3, r2, r3
8001764: 2b02 cmp r3, #2
8001766: d901 bls.n 800176c <HAL_RCC_OscConfig+0x2e8>
{
return HAL_TIMEOUT;
8001768: 2303 movs r3, #3
800176a: e188 b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
800176c: 4b10 ldr r3, [pc, #64] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
800176e: 6e1b ldr r3, [r3, #96] ; 0x60
8001770: 2202 movs r2, #2
8001772: 4013 ands r3, r2
8001774: d1f1 bne.n 800175a <HAL_RCC_OscConfig+0x2d6>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001776: 687b ldr r3, [r7, #4]
8001778: 681b ldr r3, [r3, #0]
800177a: 2204 movs r2, #4
800177c: 4013 ands r3, r2
800177e: d100 bne.n 8001782 <HAL_RCC_OscConfig+0x2fe>
8001780: e0c6 b.n 8001910 <HAL_RCC_OscConfig+0x48c>
{
FlagStatus pwrclkchanged = RESET;
8001782: 231f movs r3, #31
8001784: 18fb adds r3, r7, r3
8001786: 2200 movs r2, #0
8001788: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* When the LSE is used as system clock, it is not allowed disable it */
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
800178a: 4b09 ldr r3, [pc, #36] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
800178c: 689b ldr r3, [r3, #8]
800178e: 2238 movs r2, #56 ; 0x38
8001790: 4013 ands r3, r2
8001792: 2b20 cmp r3, #32
8001794: d11e bne.n 80017d4 <HAL_RCC_OscConfig+0x350>
{
if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF))
8001796: 4b06 ldr r3, [pc, #24] ; (80017b0 <HAL_RCC_OscConfig+0x32c>)
8001798: 6ddb ldr r3, [r3, #92] ; 0x5c
800179a: 2202 movs r2, #2
800179c: 4013 ands r3, r2
800179e: d100 bne.n 80017a2 <HAL_RCC_OscConfig+0x31e>
80017a0: e0b6 b.n 8001910 <HAL_RCC_OscConfig+0x48c>
80017a2: 687b ldr r3, [r7, #4]
80017a4: 689b ldr r3, [r3, #8]
80017a6: 2b00 cmp r3, #0
80017a8: d000 beq.n 80017ac <HAL_RCC_OscConfig+0x328>
80017aa: e0b1 b.n 8001910 <HAL_RCC_OscConfig+0x48c>
{
return HAL_ERROR;
80017ac: 2301 movs r3, #1
80017ae: e166 b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
80017b0: 40021000 .word 0x40021000
80017b4: fffeffff .word 0xfffeffff
80017b8: fffbffff .word 0xfffbffff
80017bc: ffff80ff .word 0xffff80ff
80017c0: ffffc7ff .word 0xffffc7ff
80017c4: 00f42400 .word 0x00f42400
80017c8: 20000000 .word 0x20000000
80017cc: 20000004 .word 0x20000004
80017d0: fffffeff .word 0xfffffeff
}
else
{
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
80017d4: 4bac ldr r3, [pc, #688] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
80017d6: 6bda ldr r2, [r3, #60] ; 0x3c
80017d8: 2380 movs r3, #128 ; 0x80
80017da: 055b lsls r3, r3, #21
80017dc: 4013 ands r3, r2
80017de: d101 bne.n 80017e4 <HAL_RCC_OscConfig+0x360>
80017e0: 2301 movs r3, #1
80017e2: e000 b.n 80017e6 <HAL_RCC_OscConfig+0x362>
80017e4: 2300 movs r3, #0
80017e6: 2b00 cmp r3, #0
80017e8: d011 beq.n 800180e <HAL_RCC_OscConfig+0x38a>
{
__HAL_RCC_PWR_CLK_ENABLE();
80017ea: 4ba7 ldr r3, [pc, #668] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
80017ec: 6bda ldr r2, [r3, #60] ; 0x3c
80017ee: 4ba6 ldr r3, [pc, #664] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
80017f0: 2180 movs r1, #128 ; 0x80
80017f2: 0549 lsls r1, r1, #21
80017f4: 430a orrs r2, r1
80017f6: 63da str r2, [r3, #60] ; 0x3c
80017f8: 4ba3 ldr r3, [pc, #652] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
80017fa: 6bda ldr r2, [r3, #60] ; 0x3c
80017fc: 2380 movs r3, #128 ; 0x80
80017fe: 055b lsls r3, r3, #21
8001800: 4013 ands r3, r2
8001802: 60fb str r3, [r7, #12]
8001804: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8001806: 231f movs r3, #31
8001808: 18fb adds r3, r7, r3
800180a: 2201 movs r2, #1
800180c: 701a strb r2, [r3, #0]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
800180e: 4b9f ldr r3, [pc, #636] ; (8001a8c <HAL_RCC_OscConfig+0x608>)
8001810: 681a ldr r2, [r3, #0]
8001812: 2380 movs r3, #128 ; 0x80
8001814: 005b lsls r3, r3, #1
8001816: 4013 ands r3, r2
8001818: d11a bne.n 8001850 <HAL_RCC_OscConfig+0x3cc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
800181a: 4b9c ldr r3, [pc, #624] ; (8001a8c <HAL_RCC_OscConfig+0x608>)
800181c: 681a ldr r2, [r3, #0]
800181e: 4b9b ldr r3, [pc, #620] ; (8001a8c <HAL_RCC_OscConfig+0x608>)
8001820: 2180 movs r1, #128 ; 0x80
8001822: 0049 lsls r1, r1, #1
8001824: 430a orrs r2, r1
8001826: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001828: f7ff fb76 bl 8000f18 <HAL_GetTick>
800182c: 0003 movs r3, r0
800182e: 613b str r3, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001830: e008 b.n 8001844 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001832: f7ff fb71 bl 8000f18 <HAL_GetTick>
8001836: 0002 movs r2, r0
8001838: 693b ldr r3, [r7, #16]
800183a: 1ad3 subs r3, r2, r3
800183c: 2b02 cmp r3, #2
800183e: d901 bls.n 8001844 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8001840: 2303 movs r3, #3
8001842: e11c b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001844: 4b91 ldr r3, [pc, #580] ; (8001a8c <HAL_RCC_OscConfig+0x608>)
8001846: 681a ldr r2, [r3, #0]
8001848: 2380 movs r3, #128 ; 0x80
800184a: 005b lsls r3, r3, #1
800184c: 4013 ands r3, r2
800184e: d0f0 beq.n 8001832 <HAL_RCC_OscConfig+0x3ae>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001850: 687b ldr r3, [r7, #4]
8001852: 689b ldr r3, [r3, #8]
8001854: 2b01 cmp r3, #1
8001856: d106 bne.n 8001866 <HAL_RCC_OscConfig+0x3e2>
8001858: 4b8b ldr r3, [pc, #556] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
800185a: 6dda ldr r2, [r3, #92] ; 0x5c
800185c: 4b8a ldr r3, [pc, #552] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
800185e: 2101 movs r1, #1
8001860: 430a orrs r2, r1
8001862: 65da str r2, [r3, #92] ; 0x5c
8001864: e01c b.n 80018a0 <HAL_RCC_OscConfig+0x41c>
8001866: 687b ldr r3, [r7, #4]
8001868: 689b ldr r3, [r3, #8]
800186a: 2b05 cmp r3, #5
800186c: d10c bne.n 8001888 <HAL_RCC_OscConfig+0x404>
800186e: 4b86 ldr r3, [pc, #536] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001870: 6dda ldr r2, [r3, #92] ; 0x5c
8001872: 4b85 ldr r3, [pc, #532] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001874: 2104 movs r1, #4
8001876: 430a orrs r2, r1
8001878: 65da str r2, [r3, #92] ; 0x5c
800187a: 4b83 ldr r3, [pc, #524] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
800187c: 6dda ldr r2, [r3, #92] ; 0x5c
800187e: 4b82 ldr r3, [pc, #520] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001880: 2101 movs r1, #1
8001882: 430a orrs r2, r1
8001884: 65da str r2, [r3, #92] ; 0x5c
8001886: e00b b.n 80018a0 <HAL_RCC_OscConfig+0x41c>
8001888: 4b7f ldr r3, [pc, #508] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
800188a: 6dda ldr r2, [r3, #92] ; 0x5c
800188c: 4b7e ldr r3, [pc, #504] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
800188e: 2101 movs r1, #1
8001890: 438a bics r2, r1
8001892: 65da str r2, [r3, #92] ; 0x5c
8001894: 4b7c ldr r3, [pc, #496] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001896: 6dda ldr r2, [r3, #92] ; 0x5c
8001898: 4b7b ldr r3, [pc, #492] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
800189a: 2104 movs r1, #4
800189c: 438a bics r2, r1
800189e: 65da str r2, [r3, #92] ; 0x5c
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80018a0: 687b ldr r3, [r7, #4]
80018a2: 689b ldr r3, [r3, #8]
80018a4: 2b00 cmp r3, #0
80018a6: d014 beq.n 80018d2 <HAL_RCC_OscConfig+0x44e>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80018a8: f7ff fb36 bl 8000f18 <HAL_GetTick>
80018ac: 0003 movs r3, r0
80018ae: 613b str r3, [r7, #16]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
80018b0: e009 b.n 80018c6 <HAL_RCC_OscConfig+0x442>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80018b2: f7ff fb31 bl 8000f18 <HAL_GetTick>
80018b6: 0002 movs r2, r0
80018b8: 693b ldr r3, [r7, #16]
80018ba: 1ad3 subs r3, r2, r3
80018bc: 4a74 ldr r2, [pc, #464] ; (8001a90 <HAL_RCC_OscConfig+0x60c>)
80018be: 4293 cmp r3, r2
80018c0: d901 bls.n 80018c6 <HAL_RCC_OscConfig+0x442>
{
return HAL_TIMEOUT;
80018c2: 2303 movs r3, #3
80018c4: e0db b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
80018c6: 4b70 ldr r3, [pc, #448] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
80018c8: 6ddb ldr r3, [r3, #92] ; 0x5c
80018ca: 2202 movs r2, #2
80018cc: 4013 ands r3, r2
80018ce: d0f0 beq.n 80018b2 <HAL_RCC_OscConfig+0x42e>
80018d0: e013 b.n 80018fa <HAL_RCC_OscConfig+0x476>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80018d2: f7ff fb21 bl 8000f18 <HAL_GetTick>
80018d6: 0003 movs r3, r0
80018d8: 613b str r3, [r7, #16]
/* Wait till LSE is disabled */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
80018da: e009 b.n 80018f0 <HAL_RCC_OscConfig+0x46c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80018dc: f7ff fb1c bl 8000f18 <HAL_GetTick>
80018e0: 0002 movs r2, r0
80018e2: 693b ldr r3, [r7, #16]
80018e4: 1ad3 subs r3, r2, r3
80018e6: 4a6a ldr r2, [pc, #424] ; (8001a90 <HAL_RCC_OscConfig+0x60c>)
80018e8: 4293 cmp r3, r2
80018ea: d901 bls.n 80018f0 <HAL_RCC_OscConfig+0x46c>
{
return HAL_TIMEOUT;
80018ec: 2303 movs r3, #3
80018ee: e0c6 b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
80018f0: 4b65 ldr r3, [pc, #404] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
80018f2: 6ddb ldr r3, [r3, #92] ; 0x5c
80018f4: 2202 movs r2, #2
80018f6: 4013 ands r3, r2
80018f8: d1f0 bne.n 80018dc <HAL_RCC_OscConfig+0x458>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
80018fa: 231f movs r3, #31
80018fc: 18fb adds r3, r7, r3
80018fe: 781b ldrb r3, [r3, #0]
8001900: 2b01 cmp r3, #1
8001902: d105 bne.n 8001910 <HAL_RCC_OscConfig+0x48c>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001904: 4b60 ldr r3, [pc, #384] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001906: 6bda ldr r2, [r3, #60] ; 0x3c
8001908: 4b5f ldr r3, [pc, #380] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
800190a: 4962 ldr r1, [pc, #392] ; (8001a94 <HAL_RCC_OscConfig+0x610>)
800190c: 400a ands r2, r1
800190e: 63da str r2, [r3, #60] ; 0x3c
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
8001910: 687b ldr r3, [r7, #4]
8001912: 69db ldr r3, [r3, #28]
8001914: 2b00 cmp r3, #0
8001916: d100 bne.n 800191a <HAL_RCC_OscConfig+0x496>
8001918: e0b0 b.n 8001a7c <HAL_RCC_OscConfig+0x5f8>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
800191a: 4b5b ldr r3, [pc, #364] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
800191c: 689b ldr r3, [r3, #8]
800191e: 2238 movs r2, #56 ; 0x38
8001920: 4013 ands r3, r2
8001922: 2b10 cmp r3, #16
8001924: d100 bne.n 8001928 <HAL_RCC_OscConfig+0x4a4>
8001926: e078 b.n 8001a1a <HAL_RCC_OscConfig+0x596>
{
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
8001928: 687b ldr r3, [r7, #4]
800192a: 69db ldr r3, [r3, #28]
800192c: 2b02 cmp r3, #2
800192e: d153 bne.n 80019d8 <HAL_RCC_OscConfig+0x554>
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
#endif /* RCC_PLLQ_SUPPORT */
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001930: 4b55 ldr r3, [pc, #340] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001932: 681a ldr r2, [r3, #0]
8001934: 4b54 ldr r3, [pc, #336] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001936: 4958 ldr r1, [pc, #352] ; (8001a98 <HAL_RCC_OscConfig+0x614>)
8001938: 400a ands r2, r1
800193a: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800193c: f7ff faec bl 8000f18 <HAL_GetTick>
8001940: 0003 movs r3, r0
8001942: 613b str r3, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8001944: e008 b.n 8001958 <HAL_RCC_OscConfig+0x4d4>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001946: f7ff fae7 bl 8000f18 <HAL_GetTick>
800194a: 0002 movs r2, r0
800194c: 693b ldr r3, [r7, #16]
800194e: 1ad3 subs r3, r2, r3
8001950: 2b02 cmp r3, #2
8001952: d901 bls.n 8001958 <HAL_RCC_OscConfig+0x4d4>
{
return HAL_TIMEOUT;
8001954: 2303 movs r3, #3
8001956: e092 b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8001958: 4b4b ldr r3, [pc, #300] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
800195a: 681a ldr r2, [r3, #0]
800195c: 2380 movs r3, #128 ; 0x80
800195e: 049b lsls r3, r3, #18
8001960: 4013 ands r3, r2
8001962: d1f0 bne.n 8001946 <HAL_RCC_OscConfig+0x4c2>
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#else /* !RCC_PLLQ_SUPPORT */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001964: 4b48 ldr r3, [pc, #288] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001966: 68db ldr r3, [r3, #12]
8001968: 4a4c ldr r2, [pc, #304] ; (8001a9c <HAL_RCC_OscConfig+0x618>)
800196a: 4013 ands r3, r2
800196c: 0019 movs r1, r3
800196e: 687b ldr r3, [r7, #4]
8001970: 6a1a ldr r2, [r3, #32]
8001972: 687b ldr r3, [r7, #4]
8001974: 6a5b ldr r3, [r3, #36] ; 0x24
8001976: 431a orrs r2, r3
8001978: 687b ldr r3, [r7, #4]
800197a: 6a9b ldr r3, [r3, #40] ; 0x28
800197c: 021b lsls r3, r3, #8
800197e: 431a orrs r2, r3
8001980: 687b ldr r3, [r7, #4]
8001982: 6adb ldr r3, [r3, #44] ; 0x2c
8001984: 431a orrs r2, r3
8001986: 687b ldr r3, [r7, #4]
8001988: 6b1b ldr r3, [r3, #48] ; 0x30
800198a: 431a orrs r2, r3
800198c: 4b3e ldr r3, [pc, #248] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
800198e: 430a orrs r2, r1
8001990: 60da str r2, [r3, #12]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLR);
#endif /* RCC_PLLQ_SUPPORT */
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001992: 4b3d ldr r3, [pc, #244] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001994: 681a ldr r2, [r3, #0]
8001996: 4b3c ldr r3, [pc, #240] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001998: 2180 movs r1, #128 ; 0x80
800199a: 0449 lsls r1, r1, #17
800199c: 430a orrs r2, r1
800199e: 601a str r2, [r3, #0]
/* Enable PLLR Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK);
80019a0: 4b39 ldr r3, [pc, #228] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
80019a2: 68da ldr r2, [r3, #12]
80019a4: 4b38 ldr r3, [pc, #224] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
80019a6: 2180 movs r1, #128 ; 0x80
80019a8: 0549 lsls r1, r1, #21
80019aa: 430a orrs r2, r1
80019ac: 60da str r2, [r3, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80019ae: f7ff fab3 bl 8000f18 <HAL_GetTick>
80019b2: 0003 movs r3, r0
80019b4: 613b str r3, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80019b6: e008 b.n 80019ca <HAL_RCC_OscConfig+0x546>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80019b8: f7ff faae bl 8000f18 <HAL_GetTick>
80019bc: 0002 movs r2, r0
80019be: 693b ldr r3, [r7, #16]
80019c0: 1ad3 subs r3, r2, r3
80019c2: 2b02 cmp r3, #2
80019c4: d901 bls.n 80019ca <HAL_RCC_OscConfig+0x546>
{
return HAL_TIMEOUT;
80019c6: 2303 movs r3, #3
80019c8: e059 b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80019ca: 4b2f ldr r3, [pc, #188] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
80019cc: 681a ldr r2, [r3, #0]
80019ce: 2380 movs r3, #128 ; 0x80
80019d0: 049b lsls r3, r3, #18
80019d2: 4013 ands r3, r2
80019d4: d0f0 beq.n 80019b8 <HAL_RCC_OscConfig+0x534>
80019d6: e051 b.n 8001a7c <HAL_RCC_OscConfig+0x5f8>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80019d8: 4b2b ldr r3, [pc, #172] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
80019da: 681a ldr r2, [r3, #0]
80019dc: 4b2a ldr r3, [pc, #168] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
80019de: 492e ldr r1, [pc, #184] ; (8001a98 <HAL_RCC_OscConfig+0x614>)
80019e0: 400a ands r2, r1
80019e2: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80019e4: f7ff fa98 bl 8000f18 <HAL_GetTick>
80019e8: 0003 movs r3, r0
80019ea: 613b str r3, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80019ec: e008 b.n 8001a00 <HAL_RCC_OscConfig+0x57c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80019ee: f7ff fa93 bl 8000f18 <HAL_GetTick>
80019f2: 0002 movs r2, r0
80019f4: 693b ldr r3, [r7, #16]
80019f6: 1ad3 subs r3, r2, r3
80019f8: 2b02 cmp r3, #2
80019fa: d901 bls.n 8001a00 <HAL_RCC_OscConfig+0x57c>
{
return HAL_TIMEOUT;
80019fc: 2303 movs r3, #3
80019fe: e03e b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8001a00: 4b21 ldr r3, [pc, #132] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001a02: 681a ldr r2, [r3, #0]
8001a04: 2380 movs r3, #128 ; 0x80
8001a06: 049b lsls r3, r3, #18
8001a08: 4013 ands r3, r2
8001a0a: d1f0 bne.n 80019ee <HAL_RCC_OscConfig+0x56a>
}
/* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLQ_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN);
#else
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLREN);
8001a0c: 4b1e ldr r3, [pc, #120] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001a0e: 68da ldr r2, [r3, #12]
8001a10: 4b1d ldr r3, [pc, #116] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001a12: 4923 ldr r1, [pc, #140] ; (8001aa0 <HAL_RCC_OscConfig+0x61c>)
8001a14: 400a ands r2, r1
8001a16: 60da str r2, [r3, #12]
8001a18: e030 b.n 8001a7c <HAL_RCC_OscConfig+0x5f8>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001a1a: 687b ldr r3, [r7, #4]
8001a1c: 69db ldr r3, [r3, #28]
8001a1e: 2b01 cmp r3, #1
8001a20: d101 bne.n 8001a26 <HAL_RCC_OscConfig+0x5a2>
{
return HAL_ERROR;
8001a22: 2301 movs r3, #1
8001a24: e02b b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
temp_pllckcfg = RCC->PLLCFGR;
8001a26: 4b18 ldr r3, [pc, #96] ; (8001a88 <HAL_RCC_OscConfig+0x604>)
8001a28: 68db ldr r3, [r3, #12]
8001a2a: 617b str r3, [r7, #20]
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001a2c: 697b ldr r3, [r7, #20]
8001a2e: 2203 movs r2, #3
8001a30: 401a ands r2, r3
8001a32: 687b ldr r3, [r7, #4]
8001a34: 6a1b ldr r3, [r3, #32]
8001a36: 429a cmp r2, r3
8001a38: d11e bne.n 8001a78 <HAL_RCC_OscConfig+0x5f4>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8001a3a: 697b ldr r3, [r7, #20]
8001a3c: 2270 movs r2, #112 ; 0x70
8001a3e: 401a ands r2, r3
8001a40: 687b ldr r3, [r7, #4]
8001a42: 6a5b ldr r3, [r3, #36] ; 0x24
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001a44: 429a cmp r2, r3
8001a46: d117 bne.n 8001a78 <HAL_RCC_OscConfig+0x5f4>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8001a48: 697a ldr r2, [r7, #20]
8001a4a: 23fe movs r3, #254 ; 0xfe
8001a4c: 01db lsls r3, r3, #7
8001a4e: 401a ands r2, r3
8001a50: 687b ldr r3, [r7, #4]
8001a52: 6a9b ldr r3, [r3, #40] ; 0x28
8001a54: 021b lsls r3, r3, #8
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8001a56: 429a cmp r2, r3
8001a58: d10e bne.n 8001a78 <HAL_RCC_OscConfig+0x5f4>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
8001a5a: 697a ldr r2, [r7, #20]
8001a5c: 23f8 movs r3, #248 ; 0xf8
8001a5e: 039b lsls r3, r3, #14
8001a60: 401a ands r2, r3
8001a62: 687b ldr r3, [r7, #4]
8001a64: 6adb ldr r3, [r3, #44] ; 0x2c
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8001a66: 429a cmp r2, r3
8001a68: d106 bne.n 8001a78 <HAL_RCC_OscConfig+0x5f4>
#if defined (RCC_PLLQ_SUPPORT)
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
#endif /* RCC_PLLQ_SUPPORT */
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
8001a6a: 697b ldr r3, [r7, #20]
8001a6c: 0f5b lsrs r3, r3, #29
8001a6e: 075a lsls r2, r3, #29
8001a70: 687b ldr r3, [r7, #4]
8001a72: 6b1b ldr r3, [r3, #48] ; 0x30
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
8001a74: 429a cmp r2, r3
8001a76: d001 beq.n 8001a7c <HAL_RCC_OscConfig+0x5f8>
{
return HAL_ERROR;
8001a78: 2301 movs r3, #1
8001a7a: e000 b.n 8001a7e <HAL_RCC_OscConfig+0x5fa>
}
}
}
}
return HAL_OK;
8001a7c: 2300 movs r3, #0
}
8001a7e: 0018 movs r0, r3
8001a80: 46bd mov sp, r7
8001a82: b008 add sp, #32
8001a84: bd80 pop {r7, pc}
8001a86: 46c0 nop ; (mov r8, r8)
8001a88: 40021000 .word 0x40021000
8001a8c: 40007000 .word 0x40007000
8001a90: 00001388 .word 0x00001388
8001a94: efffffff .word 0xefffffff
8001a98: feffffff .word 0xfeffffff
8001a9c: 1fc1808c .word 0x1fc1808c
8001aa0: effefffc .word 0xeffefffc
08001aa4 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001aa4: b580 push {r7, lr}
8001aa6: b084 sub sp, #16
8001aa8: af00 add r7, sp, #0
8001aaa: 6078 str r0, [r7, #4]
8001aac: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8001aae: 687b ldr r3, [r7, #4]
8001ab0: 2b00 cmp r3, #0
8001ab2: d101 bne.n 8001ab8 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001ab4: 2301 movs r3, #1
8001ab6: e0e9 b.n 8001c8c <HAL_RCC_ClockConfig+0x1e8>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the FLASH clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8001ab8: 4b76 ldr r3, [pc, #472] ; (8001c94 <HAL_RCC_ClockConfig+0x1f0>)
8001aba: 681b ldr r3, [r3, #0]
8001abc: 2207 movs r2, #7
8001abe: 4013 ands r3, r2
8001ac0: 683a ldr r2, [r7, #0]
8001ac2: 429a cmp r2, r3
8001ac4: d91e bls.n 8001b04 <HAL_RCC_ClockConfig+0x60>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001ac6: 4b73 ldr r3, [pc, #460] ; (8001c94 <HAL_RCC_ClockConfig+0x1f0>)
8001ac8: 681b ldr r3, [r3, #0]
8001aca: 2207 movs r2, #7
8001acc: 4393 bics r3, r2
8001ace: 0019 movs r1, r3
8001ad0: 4b70 ldr r3, [pc, #448] ; (8001c94 <HAL_RCC_ClockConfig+0x1f0>)
8001ad2: 683a ldr r2, [r7, #0]
8001ad4: 430a orrs r2, r1
8001ad6: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
8001ad8: f7ff fa1e bl 8000f18 <HAL_GetTick>
8001adc: 0003 movs r3, r0
8001ade: 60fb str r3, [r7, #12]
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8001ae0: e009 b.n 8001af6 <HAL_RCC_ClockConfig+0x52>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8001ae2: f7ff fa19 bl 8000f18 <HAL_GetTick>
8001ae6: 0002 movs r2, r0
8001ae8: 68fb ldr r3, [r7, #12]
8001aea: 1ad3 subs r3, r2, r3
8001aec: 4a6a ldr r2, [pc, #424] ; (8001c98 <HAL_RCC_ClockConfig+0x1f4>)
8001aee: 4293 cmp r3, r2
8001af0: d901 bls.n 8001af6 <HAL_RCC_ClockConfig+0x52>
{
return HAL_TIMEOUT;
8001af2: 2303 movs r3, #3
8001af4: e0ca b.n 8001c8c <HAL_RCC_ClockConfig+0x1e8>
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8001af6: 4b67 ldr r3, [pc, #412] ; (8001c94 <HAL_RCC_ClockConfig+0x1f0>)
8001af8: 681b ldr r3, [r3, #0]
8001afa: 2207 movs r2, #7
8001afc: 4013 ands r3, r2
8001afe: 683a ldr r2, [r7, #0]
8001b00: 429a cmp r2, r3
8001b02: d1ee bne.n 8001ae2 <HAL_RCC_ClockConfig+0x3e>
}
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8001b04: 687b ldr r3, [r7, #4]
8001b06: 681b ldr r3, [r3, #0]
8001b08: 2202 movs r2, #2
8001b0a: 4013 ands r3, r2
8001b0c: d015 beq.n 8001b3a <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001b0e: 687b ldr r3, [r7, #4]
8001b10: 681b ldr r3, [r3, #0]
8001b12: 2204 movs r2, #4
8001b14: 4013 ands r3, r2
8001b16: d006 beq.n 8001b26 <HAL_RCC_ClockConfig+0x82>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
8001b18: 4b60 ldr r3, [pc, #384] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001b1a: 689a ldr r2, [r3, #8]
8001b1c: 4b5f ldr r3, [pc, #380] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001b1e: 21e0 movs r1, #224 ; 0xe0
8001b20: 01c9 lsls r1, r1, #7
8001b22: 430a orrs r2, r1
8001b24: 609a str r2, [r3, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001b26: 4b5d ldr r3, [pc, #372] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001b28: 689b ldr r3, [r3, #8]
8001b2a: 4a5d ldr r2, [pc, #372] ; (8001ca0 <HAL_RCC_ClockConfig+0x1fc>)
8001b2c: 4013 ands r3, r2
8001b2e: 0019 movs r1, r3
8001b30: 687b ldr r3, [r7, #4]
8001b32: 689a ldr r2, [r3, #8]
8001b34: 4b59 ldr r3, [pc, #356] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001b36: 430a orrs r2, r1
8001b38: 609a str r2, [r3, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001b3a: 687b ldr r3, [r7, #4]
8001b3c: 681b ldr r3, [r3, #0]
8001b3e: 2201 movs r2, #1
8001b40: 4013 ands r3, r2
8001b42: d057 beq.n 8001bf4 <HAL_RCC_ClockConfig+0x150>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001b44: 687b ldr r3, [r7, #4]
8001b46: 685b ldr r3, [r3, #4]
8001b48: 2b01 cmp r3, #1
8001b4a: d107 bne.n 8001b5c <HAL_RCC_ClockConfig+0xb8>
{
/* Check the HSE ready flag */
if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8001b4c: 4b53 ldr r3, [pc, #332] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001b4e: 681a ldr r2, [r3, #0]
8001b50: 2380 movs r3, #128 ; 0x80
8001b52: 029b lsls r3, r3, #10
8001b54: 4013 ands r3, r2
8001b56: d12b bne.n 8001bb0 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8001b58: 2301 movs r3, #1
8001b5a: e097 b.n 8001c8c <HAL_RCC_ClockConfig+0x1e8>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8001b5c: 687b ldr r3, [r7, #4]
8001b5e: 685b ldr r3, [r3, #4]
8001b60: 2b02 cmp r3, #2
8001b62: d107 bne.n 8001b74 <HAL_RCC_ClockConfig+0xd0>
{
/* Check the PLL ready flag */
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8001b64: 4b4d ldr r3, [pc, #308] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001b66: 681a ldr r2, [r3, #0]
8001b68: 2380 movs r3, #128 ; 0x80
8001b6a: 049b lsls r3, r3, #18
8001b6c: 4013 ands r3, r2
8001b6e: d11f bne.n 8001bb0 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8001b70: 2301 movs r3, #1
8001b72: e08b b.n 8001c8c <HAL_RCC_ClockConfig+0x1e8>
}
}
/* HSI is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8001b74: 687b ldr r3, [r7, #4]
8001b76: 685b ldr r3, [r3, #4]
8001b78: 2b00 cmp r3, #0
8001b7a: d107 bne.n 8001b8c <HAL_RCC_ClockConfig+0xe8>
{
/* Check the HSI ready flag */
if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8001b7c: 4b47 ldr r3, [pc, #284] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001b7e: 681a ldr r2, [r3, #0]
8001b80: 2380 movs r3, #128 ; 0x80
8001b82: 00db lsls r3, r3, #3
8001b84: 4013 ands r3, r2
8001b86: d113 bne.n 8001bb0 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8001b88: 2301 movs r3, #1
8001b8a: e07f b.n 8001c8c <HAL_RCC_ClockConfig+0x1e8>
}
}
/* LSI is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
8001b8c: 687b ldr r3, [r7, #4]
8001b8e: 685b ldr r3, [r3, #4]
8001b90: 2b03 cmp r3, #3
8001b92: d106 bne.n 8001ba2 <HAL_RCC_ClockConfig+0xfe>
{
/* Check the LSI ready flag */
if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8001b94: 4b41 ldr r3, [pc, #260] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001b96: 6e1b ldr r3, [r3, #96] ; 0x60
8001b98: 2202 movs r2, #2
8001b9a: 4013 ands r3, r2
8001b9c: d108 bne.n 8001bb0 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8001b9e: 2301 movs r3, #1
8001ba0: e074 b.n 8001c8c <HAL_RCC_ClockConfig+0x1e8>
}
/* LSE is selected as System Clock Source */
else
{
/* Check the LSE ready flag */
if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8001ba2: 4b3e ldr r3, [pc, #248] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001ba4: 6ddb ldr r3, [r3, #92] ; 0x5c
8001ba6: 2202 movs r2, #2
8001ba8: 4013 ands r3, r2
8001baa: d101 bne.n 8001bb0 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8001bac: 2301 movs r3, #1
8001bae: e06d b.n 8001c8c <HAL_RCC_ClockConfig+0x1e8>
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
8001bb0: 4b3a ldr r3, [pc, #232] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001bb2: 689b ldr r3, [r3, #8]
8001bb4: 2207 movs r2, #7
8001bb6: 4393 bics r3, r2
8001bb8: 0019 movs r1, r3
8001bba: 687b ldr r3, [r7, #4]
8001bbc: 685a ldr r2, [r3, #4]
8001bbe: 4b37 ldr r3, [pc, #220] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001bc0: 430a orrs r2, r1
8001bc2: 609a str r2, [r3, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001bc4: f7ff f9a8 bl 8000f18 <HAL_GetTick>
8001bc8: 0003 movs r3, r0
8001bca: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001bcc: e009 b.n 8001be2 <HAL_RCC_ClockConfig+0x13e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8001bce: f7ff f9a3 bl 8000f18 <HAL_GetTick>
8001bd2: 0002 movs r2, r0
8001bd4: 68fb ldr r3, [r7, #12]
8001bd6: 1ad3 subs r3, r2, r3
8001bd8: 4a2f ldr r2, [pc, #188] ; (8001c98 <HAL_RCC_ClockConfig+0x1f4>)
8001bda: 4293 cmp r3, r2
8001bdc: d901 bls.n 8001be2 <HAL_RCC_ClockConfig+0x13e>
{
return HAL_TIMEOUT;
8001bde: 2303 movs r3, #3
8001be0: e054 b.n 8001c8c <HAL_RCC_ClockConfig+0x1e8>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001be2: 4b2e ldr r3, [pc, #184] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001be4: 689b ldr r3, [r3, #8]
8001be6: 2238 movs r2, #56 ; 0x38
8001be8: 401a ands r2, r3
8001bea: 687b ldr r3, [r7, #4]
8001bec: 685b ldr r3, [r3, #4]
8001bee: 00db lsls r3, r3, #3
8001bf0: 429a cmp r2, r3
8001bf2: d1ec bne.n 8001bce <HAL_RCC_ClockConfig+0x12a>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8001bf4: 4b27 ldr r3, [pc, #156] ; (8001c94 <HAL_RCC_ClockConfig+0x1f0>)
8001bf6: 681b ldr r3, [r3, #0]
8001bf8: 2207 movs r2, #7
8001bfa: 4013 ands r3, r2
8001bfc: 683a ldr r2, [r7, #0]
8001bfe: 429a cmp r2, r3
8001c00: d21e bcs.n 8001c40 <HAL_RCC_ClockConfig+0x19c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001c02: 4b24 ldr r3, [pc, #144] ; (8001c94 <HAL_RCC_ClockConfig+0x1f0>)
8001c04: 681b ldr r3, [r3, #0]
8001c06: 2207 movs r2, #7
8001c08: 4393 bics r3, r2
8001c0a: 0019 movs r1, r3
8001c0c: 4b21 ldr r3, [pc, #132] ; (8001c94 <HAL_RCC_ClockConfig+0x1f0>)
8001c0e: 683a ldr r2, [r7, #0]
8001c10: 430a orrs r2, r1
8001c12: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
8001c14: f7ff f980 bl 8000f18 <HAL_GetTick>
8001c18: 0003 movs r3, r0
8001c1a: 60fb str r3, [r7, #12]
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8001c1c: e009 b.n 8001c32 <HAL_RCC_ClockConfig+0x18e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8001c1e: f7ff f97b bl 8000f18 <HAL_GetTick>
8001c22: 0002 movs r2, r0
8001c24: 68fb ldr r3, [r7, #12]
8001c26: 1ad3 subs r3, r2, r3
8001c28: 4a1b ldr r2, [pc, #108] ; (8001c98 <HAL_RCC_ClockConfig+0x1f4>)
8001c2a: 4293 cmp r3, r2
8001c2c: d901 bls.n 8001c32 <HAL_RCC_ClockConfig+0x18e>
{
return HAL_TIMEOUT;
8001c2e: 2303 movs r3, #3
8001c30: e02c b.n 8001c8c <HAL_RCC_ClockConfig+0x1e8>
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8001c32: 4b18 ldr r3, [pc, #96] ; (8001c94 <HAL_RCC_ClockConfig+0x1f0>)
8001c34: 681b ldr r3, [r3, #0]
8001c36: 2207 movs r2, #7
8001c38: 4013 ands r3, r2
8001c3a: 683a ldr r2, [r7, #0]
8001c3c: 429a cmp r2, r3
8001c3e: d1ee bne.n 8001c1e <HAL_RCC_ClockConfig+0x17a>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001c40: 687b ldr r3, [r7, #4]
8001c42: 681b ldr r3, [r3, #0]
8001c44: 2204 movs r2, #4
8001c46: 4013 ands r3, r2
8001c48: d009 beq.n 8001c5e <HAL_RCC_ClockConfig+0x1ba>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
8001c4a: 4b14 ldr r3, [pc, #80] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001c4c: 689b ldr r3, [r3, #8]
8001c4e: 4a15 ldr r2, [pc, #84] ; (8001ca4 <HAL_RCC_ClockConfig+0x200>)
8001c50: 4013 ands r3, r2
8001c52: 0019 movs r1, r3
8001c54: 687b ldr r3, [r7, #4]
8001c56: 68da ldr r2, [r3, #12]
8001c58: 4b10 ldr r3, [pc, #64] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001c5a: 430a orrs r2, r1
8001c5c: 609a str r2, [r3, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
8001c5e: f000 f829 bl 8001cb4 <HAL_RCC_GetSysClockFreq>
8001c62: 0001 movs r1, r0
8001c64: 4b0d ldr r3, [pc, #52] ; (8001c9c <HAL_RCC_ClockConfig+0x1f8>)
8001c66: 689b ldr r3, [r3, #8]
8001c68: 0a1b lsrs r3, r3, #8
8001c6a: 220f movs r2, #15
8001c6c: 401a ands r2, r3
8001c6e: 4b0e ldr r3, [pc, #56] ; (8001ca8 <HAL_RCC_ClockConfig+0x204>)
8001c70: 0092 lsls r2, r2, #2
8001c72: 58d3 ldr r3, [r2, r3]
8001c74: 221f movs r2, #31
8001c76: 4013 ands r3, r2
8001c78: 000a movs r2, r1
8001c7a: 40da lsrs r2, r3
8001c7c: 4b0b ldr r3, [pc, #44] ; (8001cac <HAL_RCC_ClockConfig+0x208>)
8001c7e: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(uwTickPrio);
8001c80: 4b0b ldr r3, [pc, #44] ; (8001cb0 <HAL_RCC_ClockConfig+0x20c>)
8001c82: 681b ldr r3, [r3, #0]
8001c84: 0018 movs r0, r3
8001c86: f7ff f8eb bl 8000e60 <HAL_InitTick>
8001c8a: 0003 movs r3, r0
}
8001c8c: 0018 movs r0, r3
8001c8e: 46bd mov sp, r7
8001c90: b004 add sp, #16
8001c92: bd80 pop {r7, pc}
8001c94: 40022000 .word 0x40022000
8001c98: 00001388 .word 0x00001388
8001c9c: 40021000 .word 0x40021000
8001ca0: fffff0ff .word 0xfffff0ff
8001ca4: ffff8fff .word 0xffff8fff
8001ca8: 08003790 .word 0x08003790
8001cac: 20000000 .word 0x20000000
8001cb0: 20000004 .word 0x20000004
08001cb4 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001cb4: b580 push {r7, lr}
8001cb6: b086 sub sp, #24
8001cb8: af00 add r7, sp, #0
uint32_t pllvco, pllsource, pllr, pllm, hsidiv;
uint32_t sysclockfreq;
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8001cba: 4b3c ldr r3, [pc, #240] ; (8001dac <HAL_RCC_GetSysClockFreq+0xf8>)
8001cbc: 689b ldr r3, [r3, #8]
8001cbe: 2238 movs r2, #56 ; 0x38
8001cc0: 4013 ands r3, r2
8001cc2: d10f bne.n 8001ce4 <HAL_RCC_GetSysClockFreq+0x30>
{
/* HSISYS can be derived for HSI16 */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
8001cc4: 4b39 ldr r3, [pc, #228] ; (8001dac <HAL_RCC_GetSysClockFreq+0xf8>)
8001cc6: 681b ldr r3, [r3, #0]
8001cc8: 0adb lsrs r3, r3, #11
8001cca: 2207 movs r2, #7
8001ccc: 4013 ands r3, r2
8001cce: 2201 movs r2, #1
8001cd0: 409a lsls r2, r3
8001cd2: 0013 movs r3, r2
8001cd4: 603b str r3, [r7, #0]
/* HSI used as system clock source */
sysclockfreq = (HSI_VALUE / hsidiv);
8001cd6: 6839 ldr r1, [r7, #0]
8001cd8: 4835 ldr r0, [pc, #212] ; (8001db0 <HAL_RCC_GetSysClockFreq+0xfc>)
8001cda: f7fe fa11 bl 8000100 <__udivsi3>
8001cde: 0003 movs r3, r0
8001ce0: 613b str r3, [r7, #16]
8001ce2: e05d b.n 8001da0 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8001ce4: 4b31 ldr r3, [pc, #196] ; (8001dac <HAL_RCC_GetSysClockFreq+0xf8>)
8001ce6: 689b ldr r3, [r3, #8]
8001ce8: 2238 movs r2, #56 ; 0x38
8001cea: 4013 ands r3, r2
8001cec: 2b08 cmp r3, #8
8001cee: d102 bne.n 8001cf6 <HAL_RCC_GetSysClockFreq+0x42>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8001cf0: 4b2f ldr r3, [pc, #188] ; (8001db0 <HAL_RCC_GetSysClockFreq+0xfc>)
8001cf2: 613b str r3, [r7, #16]
8001cf4: e054 b.n 8001da0 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001cf6: 4b2d ldr r3, [pc, #180] ; (8001dac <HAL_RCC_GetSysClockFreq+0xf8>)
8001cf8: 689b ldr r3, [r3, #8]
8001cfa: 2238 movs r2, #56 ; 0x38
8001cfc: 4013 ands r3, r2
8001cfe: 2b10 cmp r3, #16
8001d00: d138 bne.n 8001d74 <HAL_RCC_GetSysClockFreq+0xc0>
/* PLL used as system clock source */
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
8001d02: 4b2a ldr r3, [pc, #168] ; (8001dac <HAL_RCC_GetSysClockFreq+0xf8>)
8001d04: 68db ldr r3, [r3, #12]
8001d06: 2203 movs r2, #3
8001d08: 4013 ands r3, r2
8001d0a: 60fb str r3, [r7, #12]
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8001d0c: 4b27 ldr r3, [pc, #156] ; (8001dac <HAL_RCC_GetSysClockFreq+0xf8>)
8001d0e: 68db ldr r3, [r3, #12]
8001d10: 091b lsrs r3, r3, #4
8001d12: 2207 movs r2, #7
8001d14: 4013 ands r3, r2
8001d16: 3301 adds r3, #1
8001d18: 60bb str r3, [r7, #8]
switch (pllsource)
8001d1a: 68fb ldr r3, [r7, #12]
8001d1c: 2b03 cmp r3, #3
8001d1e: d10d bne.n 8001d3c <HAL_RCC_GetSysClockFreq+0x88>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8001d20: 68b9 ldr r1, [r7, #8]
8001d22: 4823 ldr r0, [pc, #140] ; (8001db0 <HAL_RCC_GetSysClockFreq+0xfc>)
8001d24: f7fe f9ec bl 8000100 <__udivsi3>
8001d28: 0003 movs r3, r0
8001d2a: 0019 movs r1, r3
8001d2c: 4b1f ldr r3, [pc, #124] ; (8001dac <HAL_RCC_GetSysClockFreq+0xf8>)
8001d2e: 68db ldr r3, [r3, #12]
8001d30: 0a1b lsrs r3, r3, #8
8001d32: 227f movs r2, #127 ; 0x7f
8001d34: 4013 ands r3, r2
8001d36: 434b muls r3, r1
8001d38: 617b str r3, [r7, #20]
break;
8001d3a: e00d b.n 8001d58 <HAL_RCC_GetSysClockFreq+0xa4>
case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */
default: /* HSI16 used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ;
8001d3c: 68b9 ldr r1, [r7, #8]
8001d3e: 481c ldr r0, [pc, #112] ; (8001db0 <HAL_RCC_GetSysClockFreq+0xfc>)
8001d40: f7fe f9de bl 8000100 <__udivsi3>
8001d44: 0003 movs r3, r0
8001d46: 0019 movs r1, r3
8001d48: 4b18 ldr r3, [pc, #96] ; (8001dac <HAL_RCC_GetSysClockFreq+0xf8>)
8001d4a: 68db ldr r3, [r3, #12]
8001d4c: 0a1b lsrs r3, r3, #8
8001d4e: 227f movs r2, #127 ; 0x7f
8001d50: 4013 ands r3, r2
8001d52: 434b muls r3, r1
8001d54: 617b str r3, [r7, #20]
break;
8001d56: 46c0 nop ; (mov r8, r8)
}
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
8001d58: 4b14 ldr r3, [pc, #80] ; (8001dac <HAL_RCC_GetSysClockFreq+0xf8>)
8001d5a: 68db ldr r3, [r3, #12]
8001d5c: 0f5b lsrs r3, r3, #29
8001d5e: 2207 movs r2, #7
8001d60: 4013 ands r3, r2
8001d62: 3301 adds r3, #1
8001d64: 607b str r3, [r7, #4]
sysclockfreq = pllvco / pllr;
8001d66: 6879 ldr r1, [r7, #4]
8001d68: 6978 ldr r0, [r7, #20]
8001d6a: f7fe f9c9 bl 8000100 <__udivsi3>
8001d6e: 0003 movs r3, r0
8001d70: 613b str r3, [r7, #16]
8001d72: e015 b.n 8001da0 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
8001d74: 4b0d ldr r3, [pc, #52] ; (8001dac <HAL_RCC_GetSysClockFreq+0xf8>)
8001d76: 689b ldr r3, [r3, #8]
8001d78: 2238 movs r2, #56 ; 0x38
8001d7a: 4013 ands r3, r2
8001d7c: 2b20 cmp r3, #32
8001d7e: d103 bne.n 8001d88 <HAL_RCC_GetSysClockFreq+0xd4>
{
/* LSE used as system clock source */
sysclockfreq = LSE_VALUE;
8001d80: 2380 movs r3, #128 ; 0x80
8001d82: 021b lsls r3, r3, #8
8001d84: 613b str r3, [r7, #16]
8001d86: e00b b.n 8001da0 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
8001d88: 4b08 ldr r3, [pc, #32] ; (8001dac <HAL_RCC_GetSysClockFreq+0xf8>)
8001d8a: 689b ldr r3, [r3, #8]
8001d8c: 2238 movs r2, #56 ; 0x38
8001d8e: 4013 ands r3, r2
8001d90: 2b18 cmp r3, #24
8001d92: d103 bne.n 8001d9c <HAL_RCC_GetSysClockFreq+0xe8>
{
/* LSI used as system clock source */
sysclockfreq = LSI_VALUE;
8001d94: 23fa movs r3, #250 ; 0xfa
8001d96: 01db lsls r3, r3, #7
8001d98: 613b str r3, [r7, #16]
8001d9a: e001 b.n 8001da0 <HAL_RCC_GetSysClockFreq+0xec>
}
else
{
sysclockfreq = 0U;
8001d9c: 2300 movs r3, #0
8001d9e: 613b str r3, [r7, #16]
}
return sysclockfreq;
8001da0: 693b ldr r3, [r7, #16]
}
8001da2: 0018 movs r0, r3
8001da4: 46bd mov sp, r7
8001da6: b006 add sp, #24
8001da8: bd80 pop {r7, pc}
8001daa: 46c0 nop ; (mov r8, r8)
8001dac: 40021000 .word 0x40021000
8001db0: 00f42400 .word 0x00f42400
08001db4 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8001db4: b580 push {r7, lr}
8001db6: af00 add r7, sp, #0
return SystemCoreClock;
8001db8: 4b02 ldr r3, [pc, #8] ; (8001dc4 <HAL_RCC_GetHCLKFreq+0x10>)
8001dba: 681b ldr r3, [r3, #0]
}
8001dbc: 0018 movs r0, r3
8001dbe: 46bd mov sp, r7
8001dc0: bd80 pop {r7, pc}
8001dc2: 46c0 nop ; (mov r8, r8)
8001dc4: 20000000 .word 0x20000000
08001dc8 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8001dc8: b5b0 push {r4, r5, r7, lr}
8001dca: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler())));
8001dcc: f7ff fff2 bl 8001db4 <HAL_RCC_GetHCLKFreq>
8001dd0: 0004 movs r4, r0
8001dd2: f7ff fb4b bl 800146c <LL_RCC_GetAPB1Prescaler>
8001dd6: 0003 movs r3, r0
8001dd8: 0b1a lsrs r2, r3, #12
8001dda: 4b05 ldr r3, [pc, #20] ; (8001df0 <HAL_RCC_GetPCLK1Freq+0x28>)
8001ddc: 0092 lsls r2, r2, #2
8001dde: 58d3 ldr r3, [r2, r3]
8001de0: 221f movs r2, #31
8001de2: 4013 ands r3, r2
8001de4: 40dc lsrs r4, r3
8001de6: 0023 movs r3, r4
}
8001de8: 0018 movs r0, r3
8001dea: 46bd mov sp, r7
8001dec: bdb0 pop {r4, r5, r7, pc}
8001dee: 46c0 nop ; (mov r8, r8)
8001df0: 080037d0 .word 0x080037d0
08001df4 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8001df4: b580 push {r7, lr}
8001df6: b084 sub sp, #16
8001df8: af00 add r7, sp, #0
8001dfa: 6078 str r0, [r7, #4]
uint32_t frxth;
/* Check the SPI handle allocation */
if (hspi == NULL)
8001dfc: 687b ldr r3, [r7, #4]
8001dfe: 2b00 cmp r3, #0
8001e00: d101 bne.n 8001e06 <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8001e02: 2301 movs r3, #1
8001e04: e0a8 b.n 8001f58 <HAL_SPI_Init+0x164>
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
8001e06: 687b ldr r3, [r7, #4]
8001e08: 6a5b ldr r3, [r3, #36] ; 0x24
8001e0a: 2b00 cmp r3, #0
8001e0c: d109 bne.n 8001e22 <HAL_SPI_Init+0x2e>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
8001e0e: 687b ldr r3, [r7, #4]
8001e10: 685a ldr r2, [r3, #4]
8001e12: 2382 movs r3, #130 ; 0x82
8001e14: 005b lsls r3, r3, #1
8001e16: 429a cmp r2, r3
8001e18: d009 beq.n 8001e2e <HAL_SPI_Init+0x3a>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8001e1a: 687b ldr r3, [r7, #4]
8001e1c: 2200 movs r2, #0
8001e1e: 61da str r2, [r3, #28]
8001e20: e005 b.n 8001e2e <HAL_SPI_Init+0x3a>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
8001e22: 687b ldr r3, [r7, #4]
8001e24: 2200 movs r2, #0
8001e26: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
8001e28: 687b ldr r3, [r7, #4]
8001e2a: 2200 movs r2, #0
8001e2c: 615a str r2, [r3, #20]
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8001e2e: 687b ldr r3, [r7, #4]
8001e30: 2200 movs r2, #0
8001e32: 629a str r2, [r3, #40] ; 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
8001e34: 687b ldr r3, [r7, #4]
8001e36: 225d movs r2, #93 ; 0x5d
8001e38: 5c9b ldrb r3, [r3, r2]
8001e3a: b2db uxtb r3, r3
8001e3c: 2b00 cmp r3, #0
8001e3e: d107 bne.n 8001e50 <HAL_SPI_Init+0x5c>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
8001e40: 687b ldr r3, [r7, #4]
8001e42: 225c movs r2, #92 ; 0x5c
8001e44: 2100 movs r1, #0
8001e46: 5499 strb r1, [r3, r2]
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8001e48: 687b ldr r3, [r7, #4]
8001e4a: 0018 movs r0, r3
8001e4c: f7fe fdaa bl 80009a4 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8001e50: 687b ldr r3, [r7, #4]
8001e52: 225d movs r2, #93 ; 0x5d
8001e54: 2102 movs r1, #2
8001e56: 5499 strb r1, [r3, r2]
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8001e58: 687b ldr r3, [r7, #4]
8001e5a: 681b ldr r3, [r3, #0]
8001e5c: 681a ldr r2, [r3, #0]
8001e5e: 687b ldr r3, [r7, #4]
8001e60: 681b ldr r3, [r3, #0]
8001e62: 2140 movs r1, #64 ; 0x40
8001e64: 438a bics r2, r1
8001e66: 601a str r2, [r3, #0]
/* Align by default the rs fifo threshold on the data size */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8001e68: 687b ldr r3, [r7, #4]
8001e6a: 68da ldr r2, [r3, #12]
8001e6c: 23e0 movs r3, #224 ; 0xe0
8001e6e: 00db lsls r3, r3, #3
8001e70: 429a cmp r2, r3
8001e72: d902 bls.n 8001e7a <HAL_SPI_Init+0x86>
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
8001e74: 2300 movs r3, #0
8001e76: 60fb str r3, [r7, #12]
8001e78: e002 b.n 8001e80 <HAL_SPI_Init+0x8c>
}
else
{
frxth = SPI_RXFIFO_THRESHOLD_QF;
8001e7a: 2380 movs r3, #128 ; 0x80
8001e7c: 015b lsls r3, r3, #5
8001e7e: 60fb str r3, [r7, #12]
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
8001e80: 687b ldr r3, [r7, #4]
8001e82: 68da ldr r2, [r3, #12]
8001e84: 23f0 movs r3, #240 ; 0xf0
8001e86: 011b lsls r3, r3, #4
8001e88: 429a cmp r2, r3
8001e8a: d008 beq.n 8001e9e <HAL_SPI_Init+0xaa>
8001e8c: 687b ldr r3, [r7, #4]
8001e8e: 68da ldr r2, [r3, #12]
8001e90: 23e0 movs r3, #224 ; 0xe0
8001e92: 00db lsls r3, r3, #3
8001e94: 429a cmp r2, r3
8001e96: d002 beq.n 8001e9e <HAL_SPI_Init+0xaa>
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8001e98: 687b ldr r3, [r7, #4]
8001e9a: 2200 movs r2, #0
8001e9c: 629a str r2, [r3, #40] ; 0x28
}
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
8001e9e: 687b ldr r3, [r7, #4]
8001ea0: 685a ldr r2, [r3, #4]
8001ea2: 2382 movs r3, #130 ; 0x82
8001ea4: 005b lsls r3, r3, #1
8001ea6: 401a ands r2, r3
8001ea8: 687b ldr r3, [r7, #4]
8001eaa: 6899 ldr r1, [r3, #8]
8001eac: 2384 movs r3, #132 ; 0x84
8001eae: 021b lsls r3, r3, #8
8001eb0: 400b ands r3, r1
8001eb2: 431a orrs r2, r3
8001eb4: 687b ldr r3, [r7, #4]
8001eb6: 691b ldr r3, [r3, #16]
8001eb8: 2102 movs r1, #2
8001eba: 400b ands r3, r1
8001ebc: 431a orrs r2, r3
8001ebe: 687b ldr r3, [r7, #4]
8001ec0: 695b ldr r3, [r3, #20]
8001ec2: 2101 movs r1, #1
8001ec4: 400b ands r3, r1
8001ec6: 431a orrs r2, r3
8001ec8: 687b ldr r3, [r7, #4]
8001eca: 6999 ldr r1, [r3, #24]
8001ecc: 2380 movs r3, #128 ; 0x80
8001ece: 009b lsls r3, r3, #2
8001ed0: 400b ands r3, r1
8001ed2: 431a orrs r2, r3
8001ed4: 687b ldr r3, [r7, #4]
8001ed6: 69db ldr r3, [r3, #28]
8001ed8: 2138 movs r1, #56 ; 0x38
8001eda: 400b ands r3, r1
8001edc: 431a orrs r2, r3
8001ede: 687b ldr r3, [r7, #4]
8001ee0: 6a1b ldr r3, [r3, #32]
8001ee2: 2180 movs r1, #128 ; 0x80
8001ee4: 400b ands r3, r1
8001ee6: 431a orrs r2, r3
8001ee8: 0011 movs r1, r2
8001eea: 687b ldr r3, [r7, #4]
8001eec: 6a9a ldr r2, [r3, #40] ; 0x28
8001eee: 2380 movs r3, #128 ; 0x80
8001ef0: 019b lsls r3, r3, #6
8001ef2: 401a ands r2, r3
8001ef4: 687b ldr r3, [r7, #4]
8001ef6: 681b ldr r3, [r3, #0]
8001ef8: 430a orrs r2, r1
8001efa: 601a str r2, [r3, #0]
}
}
#endif /* USE_SPI_CRC */
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
8001efc: 687b ldr r3, [r7, #4]
8001efe: 699b ldr r3, [r3, #24]
8001f00: 0c1b lsrs r3, r3, #16
8001f02: 2204 movs r2, #4
8001f04: 401a ands r2, r3
8001f06: 687b ldr r3, [r7, #4]
8001f08: 6a5b ldr r3, [r3, #36] ; 0x24
8001f0a: 2110 movs r1, #16
8001f0c: 400b ands r3, r1
8001f0e: 431a orrs r2, r3
8001f10: 687b ldr r3, [r7, #4]
8001f12: 6b5b ldr r3, [r3, #52] ; 0x34
8001f14: 2108 movs r1, #8
8001f16: 400b ands r3, r1
8001f18: 431a orrs r2, r3
8001f1a: 687b ldr r3, [r7, #4]
8001f1c: 68d9 ldr r1, [r3, #12]
8001f1e: 23f0 movs r3, #240 ; 0xf0
8001f20: 011b lsls r3, r3, #4
8001f22: 400b ands r3, r1
8001f24: 431a orrs r2, r3
8001f26: 0011 movs r1, r2
8001f28: 68fa ldr r2, [r7, #12]
8001f2a: 2380 movs r3, #128 ; 0x80
8001f2c: 015b lsls r3, r3, #5
8001f2e: 401a ands r2, r3
8001f30: 687b ldr r3, [r7, #4]
8001f32: 681b ldr r3, [r3, #0]
8001f34: 430a orrs r2, r1
8001f36: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8001f38: 687b ldr r3, [r7, #4]
8001f3a: 681b ldr r3, [r3, #0]
8001f3c: 69da ldr r2, [r3, #28]
8001f3e: 687b ldr r3, [r7, #4]
8001f40: 681b ldr r3, [r3, #0]
8001f42: 4907 ldr r1, [pc, #28] ; (8001f60 <HAL_SPI_Init+0x16c>)
8001f44: 400a ands r2, r1
8001f46: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8001f48: 687b ldr r3, [r7, #4]
8001f4a: 2200 movs r2, #0
8001f4c: 661a str r2, [r3, #96] ; 0x60
hspi->State = HAL_SPI_STATE_READY;
8001f4e: 687b ldr r3, [r7, #4]
8001f50: 225d movs r2, #93 ; 0x5d
8001f52: 2101 movs r1, #1
8001f54: 5499 strb r1, [r3, r2]
return HAL_OK;
8001f56: 2300 movs r3, #0
}
8001f58: 0018 movs r0, r3
8001f5a: 46bd mov sp, r7
8001f5c: b004 add sp, #16
8001f5e: bd80 pop {r7, pc}
8001f60: fffff7ff .word 0xfffff7ff
08001f64 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8001f64: b580 push {r7, lr}
8001f66: b082 sub sp, #8
8001f68: af00 add r7, sp, #0
8001f6a: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001f6c: 687b ldr r3, [r7, #4]
8001f6e: 2b00 cmp r3, #0
8001f70: d101 bne.n 8001f76 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8001f72: 2301 movs r3, #1
8001f74: e04a b.n 800200c <HAL_TIM_Base_Init+0xa8>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8001f76: 687b ldr r3, [r7, #4]
8001f78: 223d movs r2, #61 ; 0x3d
8001f7a: 5c9b ldrb r3, [r3, r2]
8001f7c: b2db uxtb r3, r3
8001f7e: 2b00 cmp r3, #0
8001f80: d107 bne.n 8001f92 <HAL_TIM_Base_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8001f82: 687b ldr r3, [r7, #4]
8001f84: 223c movs r2, #60 ; 0x3c
8001f86: 2100 movs r1, #0
8001f88: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8001f8a: 687b ldr r3, [r7, #4]
8001f8c: 0018 movs r0, r3
8001f8e: f7fe fde1 bl 8000b54 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001f92: 687b ldr r3, [r7, #4]
8001f94: 223d movs r2, #61 ; 0x3d
8001f96: 2102 movs r1, #2
8001f98: 5499 strb r1, [r3, r2]
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8001f9a: 687b ldr r3, [r7, #4]
8001f9c: 681a ldr r2, [r3, #0]
8001f9e: 687b ldr r3, [r7, #4]
8001fa0: 3304 adds r3, #4
8001fa2: 0019 movs r1, r3
8001fa4: 0010 movs r0, r2
8001fa6: f000 fb97 bl 80026d8 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8001faa: 687b ldr r3, [r7, #4]
8001fac: 2248 movs r2, #72 ; 0x48
8001fae: 2101 movs r1, #1
8001fb0: 5499 strb r1, [r3, r2]
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001fb2: 687b ldr r3, [r7, #4]
8001fb4: 223e movs r2, #62 ; 0x3e
8001fb6: 2101 movs r1, #1
8001fb8: 5499 strb r1, [r3, r2]
8001fba: 687b ldr r3, [r7, #4]
8001fbc: 223f movs r2, #63 ; 0x3f
8001fbe: 2101 movs r1, #1
8001fc0: 5499 strb r1, [r3, r2]
8001fc2: 687b ldr r3, [r7, #4]
8001fc4: 2240 movs r2, #64 ; 0x40
8001fc6: 2101 movs r1, #1
8001fc8: 5499 strb r1, [r3, r2]
8001fca: 687b ldr r3, [r7, #4]
8001fcc: 2241 movs r2, #65 ; 0x41
8001fce: 2101 movs r1, #1
8001fd0: 5499 strb r1, [r3, r2]
8001fd2: 687b ldr r3, [r7, #4]
8001fd4: 2242 movs r2, #66 ; 0x42
8001fd6: 2101 movs r1, #1
8001fd8: 5499 strb r1, [r3, r2]
8001fda: 687b ldr r3, [r7, #4]
8001fdc: 2243 movs r2, #67 ; 0x43
8001fde: 2101 movs r1, #1
8001fe0: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001fe2: 687b ldr r3, [r7, #4]
8001fe4: 2244 movs r2, #68 ; 0x44
8001fe6: 2101 movs r1, #1
8001fe8: 5499 strb r1, [r3, r2]
8001fea: 687b ldr r3, [r7, #4]
8001fec: 2245 movs r2, #69 ; 0x45
8001fee: 2101 movs r1, #1
8001ff0: 5499 strb r1, [r3, r2]
8001ff2: 687b ldr r3, [r7, #4]
8001ff4: 2246 movs r2, #70 ; 0x46
8001ff6: 2101 movs r1, #1
8001ff8: 5499 strb r1, [r3, r2]
8001ffa: 687b ldr r3, [r7, #4]
8001ffc: 2247 movs r2, #71 ; 0x47
8001ffe: 2101 movs r1, #1
8002000: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8002002: 687b ldr r3, [r7, #4]
8002004: 223d movs r2, #61 ; 0x3d
8002006: 2101 movs r1, #1
8002008: 5499 strb r1, [r3, r2]
return HAL_OK;
800200a: 2300 movs r3, #0
}
800200c: 0018 movs r0, r3
800200e: 46bd mov sp, r7
8002010: b002 add sp, #8
8002012: bd80 pop {r7, pc}
08002014 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8002014: b580 push {r7, lr}
8002016: b082 sub sp, #8
8002018: af00 add r7, sp, #0
800201a: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
800201c: 687b ldr r3, [r7, #4]
800201e: 2b00 cmp r3, #0
8002020: d101 bne.n 8002026 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8002022: 2301 movs r3, #1
8002024: e04a b.n 80020bc <HAL_TIM_PWM_Init+0xa8>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8002026: 687b ldr r3, [r7, #4]
8002028: 223d movs r2, #61 ; 0x3d
800202a: 5c9b ldrb r3, [r3, r2]
800202c: b2db uxtb r3, r3
800202e: 2b00 cmp r3, #0
8002030: d107 bne.n 8002042 <HAL_TIM_PWM_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8002032: 687b ldr r3, [r7, #4]
8002034: 223c movs r2, #60 ; 0x3c
8002036: 2100 movs r1, #0
8002038: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
800203a: 687b ldr r3, [r7, #4]
800203c: 0018 movs r0, r3
800203e: f000 f841 bl 80020c4 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002042: 687b ldr r3, [r7, #4]
8002044: 223d movs r2, #61 ; 0x3d
8002046: 2102 movs r1, #2
8002048: 5499 strb r1, [r3, r2]
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800204a: 687b ldr r3, [r7, #4]
800204c: 681a ldr r2, [r3, #0]
800204e: 687b ldr r3, [r7, #4]
8002050: 3304 adds r3, #4
8002052: 0019 movs r1, r3
8002054: 0010 movs r0, r2
8002056: f000 fb3f bl 80026d8 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800205a: 687b ldr r3, [r7, #4]
800205c: 2248 movs r2, #72 ; 0x48
800205e: 2101 movs r1, #1
8002060: 5499 strb r1, [r3, r2]
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002062: 687b ldr r3, [r7, #4]
8002064: 223e movs r2, #62 ; 0x3e
8002066: 2101 movs r1, #1
8002068: 5499 strb r1, [r3, r2]
800206a: 687b ldr r3, [r7, #4]
800206c: 223f movs r2, #63 ; 0x3f
800206e: 2101 movs r1, #1
8002070: 5499 strb r1, [r3, r2]
8002072: 687b ldr r3, [r7, #4]
8002074: 2240 movs r2, #64 ; 0x40
8002076: 2101 movs r1, #1
8002078: 5499 strb r1, [r3, r2]
800207a: 687b ldr r3, [r7, #4]
800207c: 2241 movs r2, #65 ; 0x41
800207e: 2101 movs r1, #1
8002080: 5499 strb r1, [r3, r2]
8002082: 687b ldr r3, [r7, #4]
8002084: 2242 movs r2, #66 ; 0x42
8002086: 2101 movs r1, #1
8002088: 5499 strb r1, [r3, r2]
800208a: 687b ldr r3, [r7, #4]
800208c: 2243 movs r2, #67 ; 0x43
800208e: 2101 movs r1, #1
8002090: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002092: 687b ldr r3, [r7, #4]
8002094: 2244 movs r2, #68 ; 0x44
8002096: 2101 movs r1, #1
8002098: 5499 strb r1, [r3, r2]
800209a: 687b ldr r3, [r7, #4]
800209c: 2245 movs r2, #69 ; 0x45
800209e: 2101 movs r1, #1
80020a0: 5499 strb r1, [r3, r2]
80020a2: 687b ldr r3, [r7, #4]
80020a4: 2246 movs r2, #70 ; 0x46
80020a6: 2101 movs r1, #1
80020a8: 5499 strb r1, [r3, r2]
80020aa: 687b ldr r3, [r7, #4]
80020ac: 2247 movs r2, #71 ; 0x47
80020ae: 2101 movs r1, #1
80020b0: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80020b2: 687b ldr r3, [r7, #4]
80020b4: 223d movs r2, #61 ; 0x3d
80020b6: 2101 movs r1, #1
80020b8: 5499 strb r1, [r3, r2]
return HAL_OK;
80020ba: 2300 movs r3, #0
}
80020bc: 0018 movs r0, r3
80020be: 46bd mov sp, r7
80020c0: b002 add sp, #8
80020c2: bd80 pop {r7, pc}
080020c4 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
80020c4: b580 push {r7, lr}
80020c6: b082 sub sp, #8
80020c8: af00 add r7, sp, #0
80020ca: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
80020cc: 46c0 nop ; (mov r8, r8)
80020ce: 46bd mov sp, r7
80020d0: b002 add sp, #8
80020d2: bd80 pop {r7, pc}
080020d4 <HAL_TIM_Encoder_Init>:
* @param htim TIM Encoder Interface handle
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
{
80020d4: b580 push {r7, lr}
80020d6: b086 sub sp, #24
80020d8: af00 add r7, sp, #0
80020da: 6078 str r0, [r7, #4]
80020dc: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Check the TIM handle allocation */
if (htim == NULL)
80020de: 687b ldr r3, [r7, #4]
80020e0: 2b00 cmp r3, #0
80020e2: d101 bne.n 80020e8 <HAL_TIM_Encoder_Init+0x14>
{
return HAL_ERROR;
80020e4: 2301 movs r3, #1
80020e6: e090 b.n 800220a <HAL_TIM_Encoder_Init+0x136>
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
if (htim->State == HAL_TIM_STATE_RESET)
80020e8: 687b ldr r3, [r7, #4]
80020ea: 223d movs r2, #61 ; 0x3d
80020ec: 5c9b ldrb r3, [r3, r2]
80020ee: b2db uxtb r3, r3
80020f0: 2b00 cmp r3, #0
80020f2: d107 bne.n 8002104 <HAL_TIM_Encoder_Init+0x30>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80020f4: 687b ldr r3, [r7, #4]
80020f6: 223c movs r2, #60 ; 0x3c
80020f8: 2100 movs r1, #0
80020fa: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Encoder_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
80020fc: 687b ldr r3, [r7, #4]
80020fe: 0018 movs r0, r3
8002100: f7fe fcd6 bl 8000ab0 <HAL_TIM_Encoder_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002104: 687b ldr r3, [r7, #4]
8002106: 223d movs r2, #61 ; 0x3d
8002108: 2102 movs r1, #2
800210a: 5499 strb r1, [r3, r2]
/* Reset the SMS and ECE bits */
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
800210c: 687b ldr r3, [r7, #4]
800210e: 681b ldr r3, [r3, #0]
8002110: 689a ldr r2, [r3, #8]
8002112: 687b ldr r3, [r7, #4]
8002114: 681b ldr r3, [r3, #0]
8002116: 493f ldr r1, [pc, #252] ; (8002214 <HAL_TIM_Encoder_Init+0x140>)
8002118: 400a ands r2, r1
800211a: 609a str r2, [r3, #8]
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800211c: 687b ldr r3, [r7, #4]
800211e: 681a ldr r2, [r3, #0]
8002120: 687b ldr r3, [r7, #4]
8002122: 3304 adds r3, #4
8002124: 0019 movs r1, r3
8002126: 0010 movs r0, r2
8002128: f000 fad6 bl 80026d8 <TIM_Base_SetConfig>
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
800212c: 687b ldr r3, [r7, #4]
800212e: 681b ldr r3, [r3, #0]
8002130: 689b ldr r3, [r3, #8]
8002132: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmr1 = htim->Instance->CCMR1;
8002134: 687b ldr r3, [r7, #4]
8002136: 681b ldr r3, [r3, #0]
8002138: 699b ldr r3, [r3, #24]
800213a: 613b str r3, [r7, #16]
/* Get the TIMx CCER register value */
tmpccer = htim->Instance->CCER;
800213c: 687b ldr r3, [r7, #4]
800213e: 681b ldr r3, [r3, #0]
8002140: 6a1b ldr r3, [r3, #32]
8002142: 60fb str r3, [r7, #12]
/* Set the encoder Mode */
tmpsmcr |= sConfig->EncoderMode;
8002144: 683b ldr r3, [r7, #0]
8002146: 681b ldr r3, [r3, #0]
8002148: 697a ldr r2, [r7, #20]
800214a: 4313 orrs r3, r2
800214c: 617b str r3, [r7, #20]
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
800214e: 693b ldr r3, [r7, #16]
8002150: 4a31 ldr r2, [pc, #196] ; (8002218 <HAL_TIM_Encoder_Init+0x144>)
8002152: 4013 ands r3, r2
8002154: 613b str r3, [r7, #16]
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
8002156: 683b ldr r3, [r7, #0]
8002158: 689a ldr r2, [r3, #8]
800215a: 683b ldr r3, [r7, #0]
800215c: 699b ldr r3, [r3, #24]
800215e: 021b lsls r3, r3, #8
8002160: 4313 orrs r3, r2
8002162: 693a ldr r2, [r7, #16]
8002164: 4313 orrs r3, r2
8002166: 613b str r3, [r7, #16]
/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
8002168: 693b ldr r3, [r7, #16]
800216a: 4a2c ldr r2, [pc, #176] ; (800221c <HAL_TIM_Encoder_Init+0x148>)
800216c: 4013 ands r3, r2
800216e: 613b str r3, [r7, #16]
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
8002170: 693b ldr r3, [r7, #16]
8002172: 4a2b ldr r2, [pc, #172] ; (8002220 <HAL_TIM_Encoder_Init+0x14c>)
8002174: 4013 ands r3, r2
8002176: 613b str r3, [r7, #16]
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
8002178: 683b ldr r3, [r7, #0]
800217a: 68da ldr r2, [r3, #12]
800217c: 683b ldr r3, [r7, #0]
800217e: 69db ldr r3, [r3, #28]
8002180: 021b lsls r3, r3, #8
8002182: 4313 orrs r3, r2
8002184: 693a ldr r2, [r7, #16]
8002186: 4313 orrs r3, r2
8002188: 613b str r3, [r7, #16]
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
800218a: 683b ldr r3, [r7, #0]
800218c: 691b ldr r3, [r3, #16]
800218e: 011a lsls r2, r3, #4
8002190: 683b ldr r3, [r7, #0]
8002192: 6a1b ldr r3, [r3, #32]
8002194: 031b lsls r3, r3, #12
8002196: 4313 orrs r3, r2
8002198: 693a ldr r2, [r7, #16]
800219a: 4313 orrs r3, r2
800219c: 613b str r3, [r7, #16]
/* Set the TI1 and the TI2 Polarities */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
800219e: 68fb ldr r3, [r7, #12]
80021a0: 2222 movs r2, #34 ; 0x22
80021a2: 4393 bics r3, r2
80021a4: 60fb str r3, [r7, #12]
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
80021a6: 68fb ldr r3, [r7, #12]
80021a8: 2288 movs r2, #136 ; 0x88
80021aa: 4393 bics r3, r2
80021ac: 60fb str r3, [r7, #12]
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
80021ae: 683b ldr r3, [r7, #0]
80021b0: 685a ldr r2, [r3, #4]
80021b2: 683b ldr r3, [r7, #0]
80021b4: 695b ldr r3, [r3, #20]
80021b6: 011b lsls r3, r3, #4
80021b8: 4313 orrs r3, r2
80021ba: 68fa ldr r2, [r7, #12]
80021bc: 4313 orrs r3, r2
80021be: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
80021c0: 687b ldr r3, [r7, #4]
80021c2: 681b ldr r3, [r3, #0]
80021c4: 697a ldr r2, [r7, #20]
80021c6: 609a str r2, [r3, #8]
/* Write to TIMx CCMR1 */
htim->Instance->CCMR1 = tmpccmr1;
80021c8: 687b ldr r3, [r7, #4]
80021ca: 681b ldr r3, [r3, #0]
80021cc: 693a ldr r2, [r7, #16]
80021ce: 619a str r2, [r3, #24]
/* Write to TIMx CCER */
htim->Instance->CCER = tmpccer;
80021d0: 687b ldr r3, [r7, #4]
80021d2: 681b ldr r3, [r3, #0]
80021d4: 68fa ldr r2, [r7, #12]
80021d6: 621a str r2, [r3, #32]
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80021d8: 687b ldr r3, [r7, #4]
80021da: 2248 movs r2, #72 ; 0x48
80021dc: 2101 movs r1, #1
80021de: 5499 strb r1, [r3, r2]
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
80021e0: 687b ldr r3, [r7, #4]
80021e2: 223e movs r2, #62 ; 0x3e
80021e4: 2101 movs r1, #1
80021e6: 5499 strb r1, [r3, r2]
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
80021e8: 687b ldr r3, [r7, #4]
80021ea: 223f movs r2, #63 ; 0x3f
80021ec: 2101 movs r1, #1
80021ee: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
80021f0: 687b ldr r3, [r7, #4]
80021f2: 2244 movs r2, #68 ; 0x44
80021f4: 2101 movs r1, #1
80021f6: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
80021f8: 687b ldr r3, [r7, #4]
80021fa: 2245 movs r2, #69 ; 0x45
80021fc: 2101 movs r1, #1
80021fe: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8002200: 687b ldr r3, [r7, #4]
8002202: 223d movs r2, #61 ; 0x3d
8002204: 2101 movs r1, #1
8002206: 5499 strb r1, [r3, r2]
return HAL_OK;
8002208: 2300 movs r3, #0
}
800220a: 0018 movs r0, r3
800220c: 46bd mov sp, r7
800220e: b006 add sp, #24
8002210: bd80 pop {r7, pc}
8002212: 46c0 nop ; (mov r8, r8)
8002214: fffebff8 .word 0xfffebff8
8002218: fffffcfc .word 0xfffffcfc
800221c: fffff3f3 .word 0xfffff3f3
8002220: ffff0f0f .word 0xffff0f0f
08002224 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8002224: b580 push {r7, lr}
8002226: b082 sub sp, #8
8002228: af00 add r7, sp, #0
800222a: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
800222c: 687b ldr r3, [r7, #4]
800222e: 681b ldr r3, [r3, #0]
8002230: 691b ldr r3, [r3, #16]
8002232: 2202 movs r2, #2
8002234: 4013 ands r3, r2
8002236: 2b02 cmp r3, #2
8002238: d124 bne.n 8002284 <HAL_TIM_IRQHandler+0x60>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
800223a: 687b ldr r3, [r7, #4]
800223c: 681b ldr r3, [r3, #0]
800223e: 68db ldr r3, [r3, #12]
8002240: 2202 movs r2, #2
8002242: 4013 ands r3, r2
8002244: 2b02 cmp r3, #2
8002246: d11d bne.n 8002284 <HAL_TIM_IRQHandler+0x60>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8002248: 687b ldr r3, [r7, #4]
800224a: 681b ldr r3, [r3, #0]
800224c: 2203 movs r2, #3
800224e: 4252 negs r2, r2
8002250: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8002252: 687b ldr r3, [r7, #4]
8002254: 2201 movs r2, #1
8002256: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8002258: 687b ldr r3, [r7, #4]
800225a: 681b ldr r3, [r3, #0]
800225c: 699b ldr r3, [r3, #24]
800225e: 2203 movs r2, #3
8002260: 4013 ands r3, r2
8002262: d004 beq.n 800226e <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002264: 687b ldr r3, [r7, #4]
8002266: 0018 movs r0, r3
8002268: f000 fa1e bl 80026a8 <HAL_TIM_IC_CaptureCallback>
800226c: e007 b.n 800227e <HAL_TIM_IRQHandler+0x5a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800226e: 687b ldr r3, [r7, #4]
8002270: 0018 movs r0, r3
8002272: f000 fa11 bl 8002698 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002276: 687b ldr r3, [r7, #4]
8002278: 0018 movs r0, r3
800227a: f000 fa1d bl 80026b8 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800227e: 687b ldr r3, [r7, #4]
8002280: 2200 movs r2, #0
8002282: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8002284: 687b ldr r3, [r7, #4]
8002286: 681b ldr r3, [r3, #0]
8002288: 691b ldr r3, [r3, #16]
800228a: 2204 movs r2, #4
800228c: 4013 ands r3, r2
800228e: 2b04 cmp r3, #4
8002290: d125 bne.n 80022de <HAL_TIM_IRQHandler+0xba>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8002292: 687b ldr r3, [r7, #4]
8002294: 681b ldr r3, [r3, #0]
8002296: 68db ldr r3, [r3, #12]
8002298: 2204 movs r2, #4
800229a: 4013 ands r3, r2
800229c: 2b04 cmp r3, #4
800229e: d11e bne.n 80022de <HAL_TIM_IRQHandler+0xba>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
80022a0: 687b ldr r3, [r7, #4]
80022a2: 681b ldr r3, [r3, #0]
80022a4: 2205 movs r2, #5
80022a6: 4252 negs r2, r2
80022a8: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
80022aa: 687b ldr r3, [r7, #4]
80022ac: 2202 movs r2, #2
80022ae: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
80022b0: 687b ldr r3, [r7, #4]
80022b2: 681b ldr r3, [r3, #0]
80022b4: 699a ldr r2, [r3, #24]
80022b6: 23c0 movs r3, #192 ; 0xc0
80022b8: 009b lsls r3, r3, #2
80022ba: 4013 ands r3, r2
80022bc: d004 beq.n 80022c8 <HAL_TIM_IRQHandler+0xa4>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80022be: 687b ldr r3, [r7, #4]
80022c0: 0018 movs r0, r3
80022c2: f000 f9f1 bl 80026a8 <HAL_TIM_IC_CaptureCallback>
80022c6: e007 b.n 80022d8 <HAL_TIM_IRQHandler+0xb4>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80022c8: 687b ldr r3, [r7, #4]
80022ca: 0018 movs r0, r3
80022cc: f000 f9e4 bl 8002698 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80022d0: 687b ldr r3, [r7, #4]
80022d2: 0018 movs r0, r3
80022d4: f000 f9f0 bl 80026b8 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80022d8: 687b ldr r3, [r7, #4]
80022da: 2200 movs r2, #0
80022dc: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
80022de: 687b ldr r3, [r7, #4]
80022e0: 681b ldr r3, [r3, #0]
80022e2: 691b ldr r3, [r3, #16]
80022e4: 2208 movs r2, #8
80022e6: 4013 ands r3, r2
80022e8: 2b08 cmp r3, #8
80022ea: d124 bne.n 8002336 <HAL_TIM_IRQHandler+0x112>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
80022ec: 687b ldr r3, [r7, #4]
80022ee: 681b ldr r3, [r3, #0]
80022f0: 68db ldr r3, [r3, #12]
80022f2: 2208 movs r2, #8
80022f4: 4013 ands r3, r2
80022f6: 2b08 cmp r3, #8
80022f8: d11d bne.n 8002336 <HAL_TIM_IRQHandler+0x112>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
80022fa: 687b ldr r3, [r7, #4]
80022fc: 681b ldr r3, [r3, #0]
80022fe: 2209 movs r2, #9
8002300: 4252 negs r2, r2
8002302: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8002304: 687b ldr r3, [r7, #4]
8002306: 2204 movs r2, #4
8002308: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
800230a: 687b ldr r3, [r7, #4]
800230c: 681b ldr r3, [r3, #0]
800230e: 69db ldr r3, [r3, #28]
8002310: 2203 movs r2, #3
8002312: 4013 ands r3, r2
8002314: d004 beq.n 8002320 <HAL_TIM_IRQHandler+0xfc>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002316: 687b ldr r3, [r7, #4]
8002318: 0018 movs r0, r3
800231a: f000 f9c5 bl 80026a8 <HAL_TIM_IC_CaptureCallback>
800231e: e007 b.n 8002330 <HAL_TIM_IRQHandler+0x10c>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002320: 687b ldr r3, [r7, #4]
8002322: 0018 movs r0, r3
8002324: f000 f9b8 bl 8002698 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002328: 687b ldr r3, [r7, #4]
800232a: 0018 movs r0, r3
800232c: f000 f9c4 bl 80026b8 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002330: 687b ldr r3, [r7, #4]
8002332: 2200 movs r2, #0
8002334: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8002336: 687b ldr r3, [r7, #4]
8002338: 681b ldr r3, [r3, #0]
800233a: 691b ldr r3, [r3, #16]
800233c: 2210 movs r2, #16
800233e: 4013 ands r3, r2
8002340: 2b10 cmp r3, #16
8002342: d125 bne.n 8002390 <HAL_TIM_IRQHandler+0x16c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8002344: 687b ldr r3, [r7, #4]
8002346: 681b ldr r3, [r3, #0]
8002348: 68db ldr r3, [r3, #12]
800234a: 2210 movs r2, #16
800234c: 4013 ands r3, r2
800234e: 2b10 cmp r3, #16
8002350: d11e bne.n 8002390 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8002352: 687b ldr r3, [r7, #4]
8002354: 681b ldr r3, [r3, #0]
8002356: 2211 movs r2, #17
8002358: 4252 negs r2, r2
800235a: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
800235c: 687b ldr r3, [r7, #4]
800235e: 2208 movs r2, #8
8002360: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8002362: 687b ldr r3, [r7, #4]
8002364: 681b ldr r3, [r3, #0]
8002366: 69da ldr r2, [r3, #28]
8002368: 23c0 movs r3, #192 ; 0xc0
800236a: 009b lsls r3, r3, #2
800236c: 4013 ands r3, r2
800236e: d004 beq.n 800237a <HAL_TIM_IRQHandler+0x156>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002370: 687b ldr r3, [r7, #4]
8002372: 0018 movs r0, r3
8002374: f000 f998 bl 80026a8 <HAL_TIM_IC_CaptureCallback>
8002378: e007 b.n 800238a <HAL_TIM_IRQHandler+0x166>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800237a: 687b ldr r3, [r7, #4]
800237c: 0018 movs r0, r3
800237e: f000 f98b bl 8002698 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002382: 687b ldr r3, [r7, #4]
8002384: 0018 movs r0, r3
8002386: f000 f997 bl 80026b8 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800238a: 687b ldr r3, [r7, #4]
800238c: 2200 movs r2, #0
800238e: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8002390: 687b ldr r3, [r7, #4]
8002392: 681b ldr r3, [r3, #0]
8002394: 691b ldr r3, [r3, #16]
8002396: 2201 movs r2, #1
8002398: 4013 ands r3, r2
800239a: 2b01 cmp r3, #1
800239c: d10f bne.n 80023be <HAL_TIM_IRQHandler+0x19a>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
800239e: 687b ldr r3, [r7, #4]
80023a0: 681b ldr r3, [r3, #0]
80023a2: 68db ldr r3, [r3, #12]
80023a4: 2201 movs r2, #1
80023a6: 4013 ands r3, r2
80023a8: 2b01 cmp r3, #1
80023aa: d108 bne.n 80023be <HAL_TIM_IRQHandler+0x19a>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
80023ac: 687b ldr r3, [r7, #4]
80023ae: 681b ldr r3, [r3, #0]
80023b0: 2202 movs r2, #2
80023b2: 4252 negs r2, r2
80023b4: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
80023b6: 687b ldr r3, [r7, #4]
80023b8: 0018 movs r0, r3
80023ba: f000 f965 bl 8002688 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
80023be: 687b ldr r3, [r7, #4]
80023c0: 681b ldr r3, [r3, #0]
80023c2: 691b ldr r3, [r3, #16]
80023c4: 2280 movs r2, #128 ; 0x80
80023c6: 4013 ands r3, r2
80023c8: 2b80 cmp r3, #128 ; 0x80
80023ca: d10f bne.n 80023ec <HAL_TIM_IRQHandler+0x1c8>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
80023cc: 687b ldr r3, [r7, #4]
80023ce: 681b ldr r3, [r3, #0]
80023d0: 68db ldr r3, [r3, #12]
80023d2: 2280 movs r2, #128 ; 0x80
80023d4: 4013 ands r3, r2
80023d6: 2b80 cmp r3, #128 ; 0x80
80023d8: d108 bne.n 80023ec <HAL_TIM_IRQHandler+0x1c8>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
80023da: 687b ldr r3, [r7, #4]
80023dc: 681b ldr r3, [r3, #0]
80023de: 2281 movs r2, #129 ; 0x81
80023e0: 4252 negs r2, r2
80023e2: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
80023e4: 687b ldr r3, [r7, #4]
80023e6: 0018 movs r0, r3
80023e8: f000 fdc6 bl 8002f78 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
80023ec: 687b ldr r3, [r7, #4]
80023ee: 681b ldr r3, [r3, #0]
80023f0: 691a ldr r2, [r3, #16]
80023f2: 2380 movs r3, #128 ; 0x80
80023f4: 005b lsls r3, r3, #1
80023f6: 401a ands r2, r3
80023f8: 2380 movs r3, #128 ; 0x80
80023fa: 005b lsls r3, r3, #1
80023fc: 429a cmp r2, r3
80023fe: d10e bne.n 800241e <HAL_TIM_IRQHandler+0x1fa>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8002400: 687b ldr r3, [r7, #4]
8002402: 681b ldr r3, [r3, #0]
8002404: 68db ldr r3, [r3, #12]
8002406: 2280 movs r2, #128 ; 0x80
8002408: 4013 ands r3, r2
800240a: 2b80 cmp r3, #128 ; 0x80
800240c: d107 bne.n 800241e <HAL_TIM_IRQHandler+0x1fa>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
800240e: 687b ldr r3, [r7, #4]
8002410: 681b ldr r3, [r3, #0]
8002412: 4a1c ldr r2, [pc, #112] ; (8002484 <HAL_TIM_IRQHandler+0x260>)
8002414: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
8002416: 687b ldr r3, [r7, #4]
8002418: 0018 movs r0, r3
800241a: f000 fdb5 bl 8002f88 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
800241e: 687b ldr r3, [r7, #4]
8002420: 681b ldr r3, [r3, #0]
8002422: 691b ldr r3, [r3, #16]
8002424: 2240 movs r2, #64 ; 0x40
8002426: 4013 ands r3, r2
8002428: 2b40 cmp r3, #64 ; 0x40
800242a: d10f bne.n 800244c <HAL_TIM_IRQHandler+0x228>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
800242c: 687b ldr r3, [r7, #4]
800242e: 681b ldr r3, [r3, #0]
8002430: 68db ldr r3, [r3, #12]
8002432: 2240 movs r2, #64 ; 0x40
8002434: 4013 ands r3, r2
8002436: 2b40 cmp r3, #64 ; 0x40
8002438: d108 bne.n 800244c <HAL_TIM_IRQHandler+0x228>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
800243a: 687b ldr r3, [r7, #4]
800243c: 681b ldr r3, [r3, #0]
800243e: 2241 movs r2, #65 ; 0x41
8002440: 4252 negs r2, r2
8002442: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8002444: 687b ldr r3, [r7, #4]
8002446: 0018 movs r0, r3
8002448: f000 f93e bl 80026c8 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
800244c: 687b ldr r3, [r7, #4]
800244e: 681b ldr r3, [r3, #0]
8002450: 691b ldr r3, [r3, #16]
8002452: 2220 movs r2, #32
8002454: 4013 ands r3, r2
8002456: 2b20 cmp r3, #32
8002458: d10f bne.n 800247a <HAL_TIM_IRQHandler+0x256>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
800245a: 687b ldr r3, [r7, #4]
800245c: 681b ldr r3, [r3, #0]
800245e: 68db ldr r3, [r3, #12]
8002460: 2220 movs r2, #32
8002462: 4013 ands r3, r2
8002464: 2b20 cmp r3, #32
8002466: d108 bne.n 800247a <HAL_TIM_IRQHandler+0x256>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8002468: 687b ldr r3, [r7, #4]
800246a: 681b ldr r3, [r3, #0]
800246c: 2221 movs r2, #33 ; 0x21
800246e: 4252 negs r2, r2
8002470: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8002472: 687b ldr r3, [r7, #4]
8002474: 0018 movs r0, r3
8002476: f000 fd77 bl 8002f68 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
800247a: 46c0 nop ; (mov r8, r8)
800247c: 46bd mov sp, r7
800247e: b002 add sp, #8
8002480: bd80 pop {r7, pc}
8002482: 46c0 nop ; (mov r8, r8)
8002484: fffffeff .word 0xfffffeff
08002488 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8002488: b580 push {r7, lr}
800248a: b086 sub sp, #24
800248c: af00 add r7, sp, #0
800248e: 60f8 str r0, [r7, #12]
8002490: 60b9 str r1, [r7, #8]
8002492: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8002494: 2317 movs r3, #23
8002496: 18fb adds r3, r7, r3
8002498: 2200 movs r2, #0
800249a: 701a strb r2, [r3, #0]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
800249c: 68fb ldr r3, [r7, #12]
800249e: 223c movs r2, #60 ; 0x3c
80024a0: 5c9b ldrb r3, [r3, r2]
80024a2: 2b01 cmp r3, #1
80024a4: d101 bne.n 80024aa <HAL_TIM_PWM_ConfigChannel+0x22>
80024a6: 2302 movs r3, #2
80024a8: e0e5 b.n 8002676 <HAL_TIM_PWM_ConfigChannel+0x1ee>
80024aa: 68fb ldr r3, [r7, #12]
80024ac: 223c movs r2, #60 ; 0x3c
80024ae: 2101 movs r1, #1
80024b0: 5499 strb r1, [r3, r2]
switch (Channel)
80024b2: 687b ldr r3, [r7, #4]
80024b4: 2b14 cmp r3, #20
80024b6: d900 bls.n 80024ba <HAL_TIM_PWM_ConfigChannel+0x32>
80024b8: e0d1 b.n 800265e <HAL_TIM_PWM_ConfigChannel+0x1d6>
80024ba: 687b ldr r3, [r7, #4]
80024bc: 009a lsls r2, r3, #2
80024be: 4b70 ldr r3, [pc, #448] ; (8002680 <HAL_TIM_PWM_ConfigChannel+0x1f8>)
80024c0: 18d3 adds r3, r2, r3
80024c2: 681b ldr r3, [r3, #0]
80024c4: 469f mov pc, r3
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
80024c6: 68fb ldr r3, [r7, #12]
80024c8: 681b ldr r3, [r3, #0]
80024ca: 68ba ldr r2, [r7, #8]
80024cc: 0011 movs r1, r2
80024ce: 0018 movs r0, r3
80024d0: f000 f978 bl 80027c4 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
80024d4: 68fb ldr r3, [r7, #12]
80024d6: 681b ldr r3, [r3, #0]
80024d8: 699a ldr r2, [r3, #24]
80024da: 68fb ldr r3, [r7, #12]
80024dc: 681b ldr r3, [r3, #0]
80024de: 2108 movs r1, #8
80024e0: 430a orrs r2, r1
80024e2: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
80024e4: 68fb ldr r3, [r7, #12]
80024e6: 681b ldr r3, [r3, #0]
80024e8: 699a ldr r2, [r3, #24]
80024ea: 68fb ldr r3, [r7, #12]
80024ec: 681b ldr r3, [r3, #0]
80024ee: 2104 movs r1, #4
80024f0: 438a bics r2, r1
80024f2: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
80024f4: 68fb ldr r3, [r7, #12]
80024f6: 681b ldr r3, [r3, #0]
80024f8: 6999 ldr r1, [r3, #24]
80024fa: 68bb ldr r3, [r7, #8]
80024fc: 691a ldr r2, [r3, #16]
80024fe: 68fb ldr r3, [r7, #12]
8002500: 681b ldr r3, [r3, #0]
8002502: 430a orrs r2, r1
8002504: 619a str r2, [r3, #24]
break;
8002506: e0af b.n 8002668 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8002508: 68fb ldr r3, [r7, #12]
800250a: 681b ldr r3, [r3, #0]
800250c: 68ba ldr r2, [r7, #8]
800250e: 0011 movs r1, r2
8002510: 0018 movs r0, r3
8002512: f000 f9e1 bl 80028d8 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8002516: 68fb ldr r3, [r7, #12]
8002518: 681b ldr r3, [r3, #0]
800251a: 699a ldr r2, [r3, #24]
800251c: 68fb ldr r3, [r7, #12]
800251e: 681b ldr r3, [r3, #0]
8002520: 2180 movs r1, #128 ; 0x80
8002522: 0109 lsls r1, r1, #4
8002524: 430a orrs r2, r1
8002526: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8002528: 68fb ldr r3, [r7, #12]
800252a: 681b ldr r3, [r3, #0]
800252c: 699a ldr r2, [r3, #24]
800252e: 68fb ldr r3, [r7, #12]
8002530: 681b ldr r3, [r3, #0]
8002532: 4954 ldr r1, [pc, #336] ; (8002684 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
8002534: 400a ands r2, r1
8002536: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8002538: 68fb ldr r3, [r7, #12]
800253a: 681b ldr r3, [r3, #0]
800253c: 6999 ldr r1, [r3, #24]
800253e: 68bb ldr r3, [r7, #8]
8002540: 691b ldr r3, [r3, #16]
8002542: 021a lsls r2, r3, #8
8002544: 68fb ldr r3, [r7, #12]
8002546: 681b ldr r3, [r3, #0]
8002548: 430a orrs r2, r1
800254a: 619a str r2, [r3, #24]
break;
800254c: e08c b.n 8002668 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
800254e: 68fb ldr r3, [r7, #12]
8002550: 681b ldr r3, [r3, #0]
8002552: 68ba ldr r2, [r7, #8]
8002554: 0011 movs r1, r2
8002556: 0018 movs r0, r3
8002558: f000 fa42 bl 80029e0 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
800255c: 68fb ldr r3, [r7, #12]
800255e: 681b ldr r3, [r3, #0]
8002560: 69da ldr r2, [r3, #28]
8002562: 68fb ldr r3, [r7, #12]
8002564: 681b ldr r3, [r3, #0]
8002566: 2108 movs r1, #8
8002568: 430a orrs r2, r1
800256a: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
800256c: 68fb ldr r3, [r7, #12]
800256e: 681b ldr r3, [r3, #0]
8002570: 69da ldr r2, [r3, #28]
8002572: 68fb ldr r3, [r7, #12]
8002574: 681b ldr r3, [r3, #0]
8002576: 2104 movs r1, #4
8002578: 438a bics r2, r1
800257a: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
800257c: 68fb ldr r3, [r7, #12]
800257e: 681b ldr r3, [r3, #0]
8002580: 69d9 ldr r1, [r3, #28]
8002582: 68bb ldr r3, [r7, #8]
8002584: 691a ldr r2, [r3, #16]
8002586: 68fb ldr r3, [r7, #12]
8002588: 681b ldr r3, [r3, #0]
800258a: 430a orrs r2, r1
800258c: 61da str r2, [r3, #28]
break;
800258e: e06b b.n 8002668 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8002590: 68fb ldr r3, [r7, #12]
8002592: 681b ldr r3, [r3, #0]
8002594: 68ba ldr r2, [r7, #8]
8002596: 0011 movs r1, r2
8002598: 0018 movs r0, r3
800259a: f000 faa9 bl 8002af0 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
800259e: 68fb ldr r3, [r7, #12]
80025a0: 681b ldr r3, [r3, #0]
80025a2: 69da ldr r2, [r3, #28]
80025a4: 68fb ldr r3, [r7, #12]
80025a6: 681b ldr r3, [r3, #0]
80025a8: 2180 movs r1, #128 ; 0x80
80025aa: 0109 lsls r1, r1, #4
80025ac: 430a orrs r2, r1
80025ae: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
80025b0: 68fb ldr r3, [r7, #12]
80025b2: 681b ldr r3, [r3, #0]
80025b4: 69da ldr r2, [r3, #28]
80025b6: 68fb ldr r3, [r7, #12]
80025b8: 681b ldr r3, [r3, #0]
80025ba: 4932 ldr r1, [pc, #200] ; (8002684 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
80025bc: 400a ands r2, r1
80025be: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
80025c0: 68fb ldr r3, [r7, #12]
80025c2: 681b ldr r3, [r3, #0]
80025c4: 69d9 ldr r1, [r3, #28]
80025c6: 68bb ldr r3, [r7, #8]
80025c8: 691b ldr r3, [r3, #16]
80025ca: 021a lsls r2, r3, #8
80025cc: 68fb ldr r3, [r7, #12]
80025ce: 681b ldr r3, [r3, #0]
80025d0: 430a orrs r2, r1
80025d2: 61da str r2, [r3, #28]
break;
80025d4: e048 b.n 8002668 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
80025d6: 68fb ldr r3, [r7, #12]
80025d8: 681b ldr r3, [r3, #0]
80025da: 68ba ldr r2, [r7, #8]
80025dc: 0011 movs r1, r2
80025de: 0018 movs r0, r3
80025e0: f000 faf0 bl 8002bc4 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
80025e4: 68fb ldr r3, [r7, #12]
80025e6: 681b ldr r3, [r3, #0]
80025e8: 6d5a ldr r2, [r3, #84] ; 0x54
80025ea: 68fb ldr r3, [r7, #12]
80025ec: 681b ldr r3, [r3, #0]
80025ee: 2108 movs r1, #8
80025f0: 430a orrs r2, r1
80025f2: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
80025f4: 68fb ldr r3, [r7, #12]
80025f6: 681b ldr r3, [r3, #0]
80025f8: 6d5a ldr r2, [r3, #84] ; 0x54
80025fa: 68fb ldr r3, [r7, #12]
80025fc: 681b ldr r3, [r3, #0]
80025fe: 2104 movs r1, #4
8002600: 438a bics r2, r1
8002602: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
8002604: 68fb ldr r3, [r7, #12]
8002606: 681b ldr r3, [r3, #0]
8002608: 6d59 ldr r1, [r3, #84] ; 0x54
800260a: 68bb ldr r3, [r7, #8]
800260c: 691a ldr r2, [r3, #16]
800260e: 68fb ldr r3, [r7, #12]
8002610: 681b ldr r3, [r3, #0]
8002612: 430a orrs r2, r1
8002614: 655a str r2, [r3, #84] ; 0x54
break;
8002616: e027 b.n 8002668 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
8002618: 68fb ldr r3, [r7, #12]
800261a: 681b ldr r3, [r3, #0]
800261c: 68ba ldr r2, [r7, #8]
800261e: 0011 movs r1, r2
8002620: 0018 movs r0, r3
8002622: f000 fb2f bl 8002c84 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
8002626: 68fb ldr r3, [r7, #12]
8002628: 681b ldr r3, [r3, #0]
800262a: 6d5a ldr r2, [r3, #84] ; 0x54
800262c: 68fb ldr r3, [r7, #12]
800262e: 681b ldr r3, [r3, #0]
8002630: 2180 movs r1, #128 ; 0x80
8002632: 0109 lsls r1, r1, #4
8002634: 430a orrs r2, r1
8002636: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
8002638: 68fb ldr r3, [r7, #12]
800263a: 681b ldr r3, [r3, #0]
800263c: 6d5a ldr r2, [r3, #84] ; 0x54
800263e: 68fb ldr r3, [r7, #12]
8002640: 681b ldr r3, [r3, #0]
8002642: 4910 ldr r1, [pc, #64] ; (8002684 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
8002644: 400a ands r2, r1
8002646: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
8002648: 68fb ldr r3, [r7, #12]
800264a: 681b ldr r3, [r3, #0]
800264c: 6d59 ldr r1, [r3, #84] ; 0x54
800264e: 68bb ldr r3, [r7, #8]
8002650: 691b ldr r3, [r3, #16]
8002652: 021a lsls r2, r3, #8
8002654: 68fb ldr r3, [r7, #12]
8002656: 681b ldr r3, [r3, #0]
8002658: 430a orrs r2, r1
800265a: 655a str r2, [r3, #84] ; 0x54
break;
800265c: e004 b.n 8002668 <HAL_TIM_PWM_ConfigChannel+0x1e0>
}
default:
status = HAL_ERROR;
800265e: 2317 movs r3, #23
8002660: 18fb adds r3, r7, r3
8002662: 2201 movs r2, #1
8002664: 701a strb r2, [r3, #0]
break;
8002666: 46c0 nop ; (mov r8, r8)
}
__HAL_UNLOCK(htim);
8002668: 68fb ldr r3, [r7, #12]
800266a: 223c movs r2, #60 ; 0x3c
800266c: 2100 movs r1, #0
800266e: 5499 strb r1, [r3, r2]
return status;
8002670: 2317 movs r3, #23
8002672: 18fb adds r3, r7, r3
8002674: 781b ldrb r3, [r3, #0]
}
8002676: 0018 movs r0, r3
8002678: 46bd mov sp, r7
800267a: b006 add sp, #24
800267c: bd80 pop {r7, pc}
800267e: 46c0 nop ; (mov r8, r8)
8002680: 080037f0 .word 0x080037f0
8002684: fffffbff .word 0xfffffbff
08002688 <HAL_TIM_PeriodElapsedCallback>:
* @brief Period elapsed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8002688: b580 push {r7, lr}
800268a: b082 sub sp, #8
800268c: af00 add r7, sp, #0
800268e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
}
8002690: 46c0 nop ; (mov r8, r8)
8002692: 46bd mov sp, r7
8002694: b002 add sp, #8
8002696: bd80 pop {r7, pc}
08002698 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8002698: b580 push {r7, lr}
800269a: b082 sub sp, #8
800269c: af00 add r7, sp, #0
800269e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
80026a0: 46c0 nop ; (mov r8, r8)
80026a2: 46bd mov sp, r7
80026a4: b002 add sp, #8
80026a6: bd80 pop {r7, pc}
080026a8 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
80026a8: b580 push {r7, lr}
80026aa: b082 sub sp, #8
80026ac: af00 add r7, sp, #0
80026ae: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
80026b0: 46c0 nop ; (mov r8, r8)
80026b2: 46bd mov sp, r7
80026b4: b002 add sp, #8
80026b6: bd80 pop {r7, pc}
080026b8 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
80026b8: b580 push {r7, lr}
80026ba: b082 sub sp, #8
80026bc: af00 add r7, sp, #0
80026be: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
80026c0: 46c0 nop ; (mov r8, r8)
80026c2: 46bd mov sp, r7
80026c4: b002 add sp, #8
80026c6: bd80 pop {r7, pc}
080026c8 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
80026c8: b580 push {r7, lr}
80026ca: b082 sub sp, #8
80026cc: af00 add r7, sp, #0
80026ce: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
80026d0: 46c0 nop ; (mov r8, r8)
80026d2: 46bd mov sp, r7
80026d4: b002 add sp, #8
80026d6: bd80 pop {r7, pc}
080026d8 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
80026d8: b580 push {r7, lr}
80026da: b084 sub sp, #16
80026dc: af00 add r7, sp, #0
80026de: 6078 str r0, [r7, #4]
80026e0: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
80026e2: 687b ldr r3, [r7, #4]
80026e4: 681b ldr r3, [r3, #0]
80026e6: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
80026e8: 687b ldr r3, [r7, #4]
80026ea: 4a2f ldr r2, [pc, #188] ; (80027a8 <TIM_Base_SetConfig+0xd0>)
80026ec: 4293 cmp r3, r2
80026ee: d003 beq.n 80026f8 <TIM_Base_SetConfig+0x20>
80026f0: 687b ldr r3, [r7, #4]
80026f2: 4a2e ldr r2, [pc, #184] ; (80027ac <TIM_Base_SetConfig+0xd4>)
80026f4: 4293 cmp r3, r2
80026f6: d108 bne.n 800270a <TIM_Base_SetConfig+0x32>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
80026f8: 68fb ldr r3, [r7, #12]
80026fa: 2270 movs r2, #112 ; 0x70
80026fc: 4393 bics r3, r2
80026fe: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8002700: 683b ldr r3, [r7, #0]
8002702: 685b ldr r3, [r3, #4]
8002704: 68fa ldr r2, [r7, #12]
8002706: 4313 orrs r3, r2
8002708: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800270a: 687b ldr r3, [r7, #4]
800270c: 4a26 ldr r2, [pc, #152] ; (80027a8 <TIM_Base_SetConfig+0xd0>)
800270e: 4293 cmp r3, r2
8002710: d013 beq.n 800273a <TIM_Base_SetConfig+0x62>
8002712: 687b ldr r3, [r7, #4]
8002714: 4a25 ldr r2, [pc, #148] ; (80027ac <TIM_Base_SetConfig+0xd4>)
8002716: 4293 cmp r3, r2
8002718: d00f beq.n 800273a <TIM_Base_SetConfig+0x62>
800271a: 687b ldr r3, [r7, #4]
800271c: 4a24 ldr r2, [pc, #144] ; (80027b0 <TIM_Base_SetConfig+0xd8>)
800271e: 4293 cmp r3, r2
8002720: d00b beq.n 800273a <TIM_Base_SetConfig+0x62>
8002722: 687b ldr r3, [r7, #4]
8002724: 4a23 ldr r2, [pc, #140] ; (80027b4 <TIM_Base_SetConfig+0xdc>)
8002726: 4293 cmp r3, r2
8002728: d007 beq.n 800273a <TIM_Base_SetConfig+0x62>
800272a: 687b ldr r3, [r7, #4]
800272c: 4a22 ldr r2, [pc, #136] ; (80027b8 <TIM_Base_SetConfig+0xe0>)
800272e: 4293 cmp r3, r2
8002730: d003 beq.n 800273a <TIM_Base_SetConfig+0x62>
8002732: 687b ldr r3, [r7, #4]
8002734: 4a21 ldr r2, [pc, #132] ; (80027bc <TIM_Base_SetConfig+0xe4>)
8002736: 4293 cmp r3, r2
8002738: d108 bne.n 800274c <TIM_Base_SetConfig+0x74>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800273a: 68fb ldr r3, [r7, #12]
800273c: 4a20 ldr r2, [pc, #128] ; (80027c0 <TIM_Base_SetConfig+0xe8>)
800273e: 4013 ands r3, r2
8002740: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8002742: 683b ldr r3, [r7, #0]
8002744: 68db ldr r3, [r3, #12]
8002746: 68fa ldr r2, [r7, #12]
8002748: 4313 orrs r3, r2
800274a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800274c: 68fb ldr r3, [r7, #12]
800274e: 2280 movs r2, #128 ; 0x80
8002750: 4393 bics r3, r2
8002752: 001a movs r2, r3
8002754: 683b ldr r3, [r7, #0]
8002756: 695b ldr r3, [r3, #20]
8002758: 4313 orrs r3, r2
800275a: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
800275c: 687b ldr r3, [r7, #4]
800275e: 68fa ldr r2, [r7, #12]
8002760: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8002762: 683b ldr r3, [r7, #0]
8002764: 689a ldr r2, [r3, #8]
8002766: 687b ldr r3, [r7, #4]
8002768: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
800276a: 683b ldr r3, [r7, #0]
800276c: 681a ldr r2, [r3, #0]
800276e: 687b ldr r3, [r7, #4]
8002770: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8002772: 687b ldr r3, [r7, #4]
8002774: 4a0c ldr r2, [pc, #48] ; (80027a8 <TIM_Base_SetConfig+0xd0>)
8002776: 4293 cmp r3, r2
8002778: d00b beq.n 8002792 <TIM_Base_SetConfig+0xba>
800277a: 687b ldr r3, [r7, #4]
800277c: 4a0d ldr r2, [pc, #52] ; (80027b4 <TIM_Base_SetConfig+0xdc>)
800277e: 4293 cmp r3, r2
8002780: d007 beq.n 8002792 <TIM_Base_SetConfig+0xba>
8002782: 687b ldr r3, [r7, #4]
8002784: 4a0c ldr r2, [pc, #48] ; (80027b8 <TIM_Base_SetConfig+0xe0>)
8002786: 4293 cmp r3, r2
8002788: d003 beq.n 8002792 <TIM_Base_SetConfig+0xba>
800278a: 687b ldr r3, [r7, #4]
800278c: 4a0b ldr r2, [pc, #44] ; (80027bc <TIM_Base_SetConfig+0xe4>)
800278e: 4293 cmp r3, r2
8002790: d103 bne.n 800279a <TIM_Base_SetConfig+0xc2>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8002792: 683b ldr r3, [r7, #0]
8002794: 691a ldr r2, [r3, #16]
8002796: 687b ldr r3, [r7, #4]
8002798: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
800279a: 687b ldr r3, [r7, #4]
800279c: 2201 movs r2, #1
800279e: 615a str r2, [r3, #20]
}
80027a0: 46c0 nop ; (mov r8, r8)
80027a2: 46bd mov sp, r7
80027a4: b004 add sp, #16
80027a6: bd80 pop {r7, pc}
80027a8: 40012c00 .word 0x40012c00
80027ac: 40000400 .word 0x40000400
80027b0: 40002000 .word 0x40002000
80027b4: 40014000 .word 0x40014000
80027b8: 40014400 .word 0x40014400
80027bc: 40014800 .word 0x40014800
80027c0: fffffcff .word 0xfffffcff
080027c4 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80027c4: b580 push {r7, lr}
80027c6: b086 sub sp, #24
80027c8: af00 add r7, sp, #0
80027ca: 6078 str r0, [r7, #4]
80027cc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
80027ce: 687b ldr r3, [r7, #4]
80027d0: 6a1b ldr r3, [r3, #32]
80027d2: 2201 movs r2, #1
80027d4: 4393 bics r3, r2
80027d6: 001a movs r2, r3
80027d8: 687b ldr r3, [r7, #4]
80027da: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80027dc: 687b ldr r3, [r7, #4]
80027de: 6a1b ldr r3, [r3, #32]
80027e0: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80027e2: 687b ldr r3, [r7, #4]
80027e4: 685b ldr r3, [r3, #4]
80027e6: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
80027e8: 687b ldr r3, [r7, #4]
80027ea: 699b ldr r3, [r3, #24]
80027ec: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
80027ee: 68fb ldr r3, [r7, #12]
80027f0: 4a32 ldr r2, [pc, #200] ; (80028bc <TIM_OC1_SetConfig+0xf8>)
80027f2: 4013 ands r3, r2
80027f4: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
80027f6: 68fb ldr r3, [r7, #12]
80027f8: 2203 movs r2, #3
80027fa: 4393 bics r3, r2
80027fc: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80027fe: 683b ldr r3, [r7, #0]
8002800: 681b ldr r3, [r3, #0]
8002802: 68fa ldr r2, [r7, #12]
8002804: 4313 orrs r3, r2
8002806: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8002808: 697b ldr r3, [r7, #20]
800280a: 2202 movs r2, #2
800280c: 4393 bics r3, r2
800280e: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8002810: 683b ldr r3, [r7, #0]
8002812: 689b ldr r3, [r3, #8]
8002814: 697a ldr r2, [r7, #20]
8002816: 4313 orrs r3, r2
8002818: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
800281a: 687b ldr r3, [r7, #4]
800281c: 4a28 ldr r2, [pc, #160] ; (80028c0 <TIM_OC1_SetConfig+0xfc>)
800281e: 4293 cmp r3, r2
8002820: d00b beq.n 800283a <TIM_OC1_SetConfig+0x76>
8002822: 687b ldr r3, [r7, #4]
8002824: 4a27 ldr r2, [pc, #156] ; (80028c4 <TIM_OC1_SetConfig+0x100>)
8002826: 4293 cmp r3, r2
8002828: d007 beq.n 800283a <TIM_OC1_SetConfig+0x76>
800282a: 687b ldr r3, [r7, #4]
800282c: 4a26 ldr r2, [pc, #152] ; (80028c8 <TIM_OC1_SetConfig+0x104>)
800282e: 4293 cmp r3, r2
8002830: d003 beq.n 800283a <TIM_OC1_SetConfig+0x76>
8002832: 687b ldr r3, [r7, #4]
8002834: 4a25 ldr r2, [pc, #148] ; (80028cc <TIM_OC1_SetConfig+0x108>)
8002836: 4293 cmp r3, r2
8002838: d10c bne.n 8002854 <TIM_OC1_SetConfig+0x90>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
800283a: 697b ldr r3, [r7, #20]
800283c: 2208 movs r2, #8
800283e: 4393 bics r3, r2
8002840: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8002842: 683b ldr r3, [r7, #0]
8002844: 68db ldr r3, [r3, #12]
8002846: 697a ldr r2, [r7, #20]
8002848: 4313 orrs r3, r2
800284a: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
800284c: 697b ldr r3, [r7, #20]
800284e: 2204 movs r2, #4
8002850: 4393 bics r3, r2
8002852: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002854: 687b ldr r3, [r7, #4]
8002856: 4a1a ldr r2, [pc, #104] ; (80028c0 <TIM_OC1_SetConfig+0xfc>)
8002858: 4293 cmp r3, r2
800285a: d00b beq.n 8002874 <TIM_OC1_SetConfig+0xb0>
800285c: 687b ldr r3, [r7, #4]
800285e: 4a19 ldr r2, [pc, #100] ; (80028c4 <TIM_OC1_SetConfig+0x100>)
8002860: 4293 cmp r3, r2
8002862: d007 beq.n 8002874 <TIM_OC1_SetConfig+0xb0>
8002864: 687b ldr r3, [r7, #4]
8002866: 4a18 ldr r2, [pc, #96] ; (80028c8 <TIM_OC1_SetConfig+0x104>)
8002868: 4293 cmp r3, r2
800286a: d003 beq.n 8002874 <TIM_OC1_SetConfig+0xb0>
800286c: 687b ldr r3, [r7, #4]
800286e: 4a17 ldr r2, [pc, #92] ; (80028cc <TIM_OC1_SetConfig+0x108>)
8002870: 4293 cmp r3, r2
8002872: d111 bne.n 8002898 <TIM_OC1_SetConfig+0xd4>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8002874: 693b ldr r3, [r7, #16]
8002876: 4a16 ldr r2, [pc, #88] ; (80028d0 <TIM_OC1_SetConfig+0x10c>)
8002878: 4013 ands r3, r2
800287a: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
800287c: 693b ldr r3, [r7, #16]
800287e: 4a15 ldr r2, [pc, #84] ; (80028d4 <TIM_OC1_SetConfig+0x110>)
8002880: 4013 ands r3, r2
8002882: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8002884: 683b ldr r3, [r7, #0]
8002886: 695b ldr r3, [r3, #20]
8002888: 693a ldr r2, [r7, #16]
800288a: 4313 orrs r3, r2
800288c: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
800288e: 683b ldr r3, [r7, #0]
8002890: 699b ldr r3, [r3, #24]
8002892: 693a ldr r2, [r7, #16]
8002894: 4313 orrs r3, r2
8002896: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002898: 687b ldr r3, [r7, #4]
800289a: 693a ldr r2, [r7, #16]
800289c: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800289e: 687b ldr r3, [r7, #4]
80028a0: 68fa ldr r2, [r7, #12]
80028a2: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
80028a4: 683b ldr r3, [r7, #0]
80028a6: 685a ldr r2, [r3, #4]
80028a8: 687b ldr r3, [r7, #4]
80028aa: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80028ac: 687b ldr r3, [r7, #4]
80028ae: 697a ldr r2, [r7, #20]
80028b0: 621a str r2, [r3, #32]
}
80028b2: 46c0 nop ; (mov r8, r8)
80028b4: 46bd mov sp, r7
80028b6: b006 add sp, #24
80028b8: bd80 pop {r7, pc}
80028ba: 46c0 nop ; (mov r8, r8)
80028bc: fffeff8f .word 0xfffeff8f
80028c0: 40012c00 .word 0x40012c00
80028c4: 40014000 .word 0x40014000
80028c8: 40014400 .word 0x40014400
80028cc: 40014800 .word 0x40014800
80028d0: fffffeff .word 0xfffffeff
80028d4: fffffdff .word 0xfffffdff
080028d8 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80028d8: b580 push {r7, lr}
80028da: b086 sub sp, #24
80028dc: af00 add r7, sp, #0
80028de: 6078 str r0, [r7, #4]
80028e0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
80028e2: 687b ldr r3, [r7, #4]
80028e4: 6a1b ldr r3, [r3, #32]
80028e6: 2210 movs r2, #16
80028e8: 4393 bics r3, r2
80028ea: 001a movs r2, r3
80028ec: 687b ldr r3, [r7, #4]
80028ee: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80028f0: 687b ldr r3, [r7, #4]
80028f2: 6a1b ldr r3, [r3, #32]
80028f4: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80028f6: 687b ldr r3, [r7, #4]
80028f8: 685b ldr r3, [r3, #4]
80028fa: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
80028fc: 687b ldr r3, [r7, #4]
80028fe: 699b ldr r3, [r3, #24]
8002900: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8002902: 68fb ldr r3, [r7, #12]
8002904: 4a2e ldr r2, [pc, #184] ; (80029c0 <TIM_OC2_SetConfig+0xe8>)
8002906: 4013 ands r3, r2
8002908: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
800290a: 68fb ldr r3, [r7, #12]
800290c: 4a2d ldr r2, [pc, #180] ; (80029c4 <TIM_OC2_SetConfig+0xec>)
800290e: 4013 ands r3, r2
8002910: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8002912: 683b ldr r3, [r7, #0]
8002914: 681b ldr r3, [r3, #0]
8002916: 021b lsls r3, r3, #8
8002918: 68fa ldr r2, [r7, #12]
800291a: 4313 orrs r3, r2
800291c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
800291e: 697b ldr r3, [r7, #20]
8002920: 2220 movs r2, #32
8002922: 4393 bics r3, r2
8002924: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8002926: 683b ldr r3, [r7, #0]
8002928: 689b ldr r3, [r3, #8]
800292a: 011b lsls r3, r3, #4
800292c: 697a ldr r2, [r7, #20]
800292e: 4313 orrs r3, r2
8002930: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8002932: 687b ldr r3, [r7, #4]
8002934: 4a24 ldr r2, [pc, #144] ; (80029c8 <TIM_OC2_SetConfig+0xf0>)
8002936: 4293 cmp r3, r2
8002938: d10d bne.n 8002956 <TIM_OC2_SetConfig+0x7e>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
800293a: 697b ldr r3, [r7, #20]
800293c: 2280 movs r2, #128 ; 0x80
800293e: 4393 bics r3, r2
8002940: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8002942: 683b ldr r3, [r7, #0]
8002944: 68db ldr r3, [r3, #12]
8002946: 011b lsls r3, r3, #4
8002948: 697a ldr r2, [r7, #20]
800294a: 4313 orrs r3, r2
800294c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
800294e: 697b ldr r3, [r7, #20]
8002950: 2240 movs r2, #64 ; 0x40
8002952: 4393 bics r3, r2
8002954: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002956: 687b ldr r3, [r7, #4]
8002958: 4a1b ldr r2, [pc, #108] ; (80029c8 <TIM_OC2_SetConfig+0xf0>)
800295a: 4293 cmp r3, r2
800295c: d00b beq.n 8002976 <TIM_OC2_SetConfig+0x9e>
800295e: 687b ldr r3, [r7, #4]
8002960: 4a1a ldr r2, [pc, #104] ; (80029cc <TIM_OC2_SetConfig+0xf4>)
8002962: 4293 cmp r3, r2
8002964: d007 beq.n 8002976 <TIM_OC2_SetConfig+0x9e>
8002966: 687b ldr r3, [r7, #4]
8002968: 4a19 ldr r2, [pc, #100] ; (80029d0 <TIM_OC2_SetConfig+0xf8>)
800296a: 4293 cmp r3, r2
800296c: d003 beq.n 8002976 <TIM_OC2_SetConfig+0x9e>
800296e: 687b ldr r3, [r7, #4]
8002970: 4a18 ldr r2, [pc, #96] ; (80029d4 <TIM_OC2_SetConfig+0xfc>)
8002972: 4293 cmp r3, r2
8002974: d113 bne.n 800299e <TIM_OC2_SetConfig+0xc6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8002976: 693b ldr r3, [r7, #16]
8002978: 4a17 ldr r2, [pc, #92] ; (80029d8 <TIM_OC2_SetConfig+0x100>)
800297a: 4013 ands r3, r2
800297c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
800297e: 693b ldr r3, [r7, #16]
8002980: 4a16 ldr r2, [pc, #88] ; (80029dc <TIM_OC2_SetConfig+0x104>)
8002982: 4013 ands r3, r2
8002984: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8002986: 683b ldr r3, [r7, #0]
8002988: 695b ldr r3, [r3, #20]
800298a: 009b lsls r3, r3, #2
800298c: 693a ldr r2, [r7, #16]
800298e: 4313 orrs r3, r2
8002990: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8002992: 683b ldr r3, [r7, #0]
8002994: 699b ldr r3, [r3, #24]
8002996: 009b lsls r3, r3, #2
8002998: 693a ldr r2, [r7, #16]
800299a: 4313 orrs r3, r2
800299c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800299e: 687b ldr r3, [r7, #4]
80029a0: 693a ldr r2, [r7, #16]
80029a2: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
80029a4: 687b ldr r3, [r7, #4]
80029a6: 68fa ldr r2, [r7, #12]
80029a8: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
80029aa: 683b ldr r3, [r7, #0]
80029ac: 685a ldr r2, [r3, #4]
80029ae: 687b ldr r3, [r7, #4]
80029b0: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80029b2: 687b ldr r3, [r7, #4]
80029b4: 697a ldr r2, [r7, #20]
80029b6: 621a str r2, [r3, #32]
}
80029b8: 46c0 nop ; (mov r8, r8)
80029ba: 46bd mov sp, r7
80029bc: b006 add sp, #24
80029be: bd80 pop {r7, pc}
80029c0: feff8fff .word 0xfeff8fff
80029c4: fffffcff .word 0xfffffcff
80029c8: 40012c00 .word 0x40012c00
80029cc: 40014000 .word 0x40014000
80029d0: 40014400 .word 0x40014400
80029d4: 40014800 .word 0x40014800
80029d8: fffffbff .word 0xfffffbff
80029dc: fffff7ff .word 0xfffff7ff
080029e0 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80029e0: b580 push {r7, lr}
80029e2: b086 sub sp, #24
80029e4: af00 add r7, sp, #0
80029e6: 6078 str r0, [r7, #4]
80029e8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
80029ea: 687b ldr r3, [r7, #4]
80029ec: 6a1b ldr r3, [r3, #32]
80029ee: 4a35 ldr r2, [pc, #212] ; (8002ac4 <TIM_OC3_SetConfig+0xe4>)
80029f0: 401a ands r2, r3
80029f2: 687b ldr r3, [r7, #4]
80029f4: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80029f6: 687b ldr r3, [r7, #4]
80029f8: 6a1b ldr r3, [r3, #32]
80029fa: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80029fc: 687b ldr r3, [r7, #4]
80029fe: 685b ldr r3, [r3, #4]
8002a00: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8002a02: 687b ldr r3, [r7, #4]
8002a04: 69db ldr r3, [r3, #28]
8002a06: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8002a08: 68fb ldr r3, [r7, #12]
8002a0a: 4a2f ldr r2, [pc, #188] ; (8002ac8 <TIM_OC3_SetConfig+0xe8>)
8002a0c: 4013 ands r3, r2
8002a0e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8002a10: 68fb ldr r3, [r7, #12]
8002a12: 2203 movs r2, #3
8002a14: 4393 bics r3, r2
8002a16: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8002a18: 683b ldr r3, [r7, #0]
8002a1a: 681b ldr r3, [r3, #0]
8002a1c: 68fa ldr r2, [r7, #12]
8002a1e: 4313 orrs r3, r2
8002a20: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8002a22: 697b ldr r3, [r7, #20]
8002a24: 4a29 ldr r2, [pc, #164] ; (8002acc <TIM_OC3_SetConfig+0xec>)
8002a26: 4013 ands r3, r2
8002a28: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8002a2a: 683b ldr r3, [r7, #0]
8002a2c: 689b ldr r3, [r3, #8]
8002a2e: 021b lsls r3, r3, #8
8002a30: 697a ldr r2, [r7, #20]
8002a32: 4313 orrs r3, r2
8002a34: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8002a36: 687b ldr r3, [r7, #4]
8002a38: 4a25 ldr r2, [pc, #148] ; (8002ad0 <TIM_OC3_SetConfig+0xf0>)
8002a3a: 4293 cmp r3, r2
8002a3c: d10d bne.n 8002a5a <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8002a3e: 697b ldr r3, [r7, #20]
8002a40: 4a24 ldr r2, [pc, #144] ; (8002ad4 <TIM_OC3_SetConfig+0xf4>)
8002a42: 4013 ands r3, r2
8002a44: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8002a46: 683b ldr r3, [r7, #0]
8002a48: 68db ldr r3, [r3, #12]
8002a4a: 021b lsls r3, r3, #8
8002a4c: 697a ldr r2, [r7, #20]
8002a4e: 4313 orrs r3, r2
8002a50: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8002a52: 697b ldr r3, [r7, #20]
8002a54: 4a20 ldr r2, [pc, #128] ; (8002ad8 <TIM_OC3_SetConfig+0xf8>)
8002a56: 4013 ands r3, r2
8002a58: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002a5a: 687b ldr r3, [r7, #4]
8002a5c: 4a1c ldr r2, [pc, #112] ; (8002ad0 <TIM_OC3_SetConfig+0xf0>)
8002a5e: 4293 cmp r3, r2
8002a60: d00b beq.n 8002a7a <TIM_OC3_SetConfig+0x9a>
8002a62: 687b ldr r3, [r7, #4]
8002a64: 4a1d ldr r2, [pc, #116] ; (8002adc <TIM_OC3_SetConfig+0xfc>)
8002a66: 4293 cmp r3, r2
8002a68: d007 beq.n 8002a7a <TIM_OC3_SetConfig+0x9a>
8002a6a: 687b ldr r3, [r7, #4]
8002a6c: 4a1c ldr r2, [pc, #112] ; (8002ae0 <TIM_OC3_SetConfig+0x100>)
8002a6e: 4293 cmp r3, r2
8002a70: d003 beq.n 8002a7a <TIM_OC3_SetConfig+0x9a>
8002a72: 687b ldr r3, [r7, #4]
8002a74: 4a1b ldr r2, [pc, #108] ; (8002ae4 <TIM_OC3_SetConfig+0x104>)
8002a76: 4293 cmp r3, r2
8002a78: d113 bne.n 8002aa2 <TIM_OC3_SetConfig+0xc2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8002a7a: 693b ldr r3, [r7, #16]
8002a7c: 4a1a ldr r2, [pc, #104] ; (8002ae8 <TIM_OC3_SetConfig+0x108>)
8002a7e: 4013 ands r3, r2
8002a80: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8002a82: 693b ldr r3, [r7, #16]
8002a84: 4a19 ldr r2, [pc, #100] ; (8002aec <TIM_OC3_SetConfig+0x10c>)
8002a86: 4013 ands r3, r2
8002a88: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8002a8a: 683b ldr r3, [r7, #0]
8002a8c: 695b ldr r3, [r3, #20]
8002a8e: 011b lsls r3, r3, #4
8002a90: 693a ldr r2, [r7, #16]
8002a92: 4313 orrs r3, r2
8002a94: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8002a96: 683b ldr r3, [r7, #0]
8002a98: 699b ldr r3, [r3, #24]
8002a9a: 011b lsls r3, r3, #4
8002a9c: 693a ldr r2, [r7, #16]
8002a9e: 4313 orrs r3, r2
8002aa0: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002aa2: 687b ldr r3, [r7, #4]
8002aa4: 693a ldr r2, [r7, #16]
8002aa6: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8002aa8: 687b ldr r3, [r7, #4]
8002aaa: 68fa ldr r2, [r7, #12]
8002aac: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8002aae: 683b ldr r3, [r7, #0]
8002ab0: 685a ldr r2, [r3, #4]
8002ab2: 687b ldr r3, [r7, #4]
8002ab4: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002ab6: 687b ldr r3, [r7, #4]
8002ab8: 697a ldr r2, [r7, #20]
8002aba: 621a str r2, [r3, #32]
}
8002abc: 46c0 nop ; (mov r8, r8)
8002abe: 46bd mov sp, r7
8002ac0: b006 add sp, #24
8002ac2: bd80 pop {r7, pc}
8002ac4: fffffeff .word 0xfffffeff
8002ac8: fffeff8f .word 0xfffeff8f
8002acc: fffffdff .word 0xfffffdff
8002ad0: 40012c00 .word 0x40012c00
8002ad4: fffff7ff .word 0xfffff7ff
8002ad8: fffffbff .word 0xfffffbff
8002adc: 40014000 .word 0x40014000
8002ae0: 40014400 .word 0x40014400
8002ae4: 40014800 .word 0x40014800
8002ae8: ffffefff .word 0xffffefff
8002aec: ffffdfff .word 0xffffdfff
08002af0 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8002af0: b580 push {r7, lr}
8002af2: b086 sub sp, #24
8002af4: af00 add r7, sp, #0
8002af6: 6078 str r0, [r7, #4]
8002af8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8002afa: 687b ldr r3, [r7, #4]
8002afc: 6a1b ldr r3, [r3, #32]
8002afe: 4a28 ldr r2, [pc, #160] ; (8002ba0 <TIM_OC4_SetConfig+0xb0>)
8002b00: 401a ands r2, r3
8002b02: 687b ldr r3, [r7, #4]
8002b04: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8002b06: 687b ldr r3, [r7, #4]
8002b08: 6a1b ldr r3, [r3, #32]
8002b0a: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002b0c: 687b ldr r3, [r7, #4]
8002b0e: 685b ldr r3, [r3, #4]
8002b10: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8002b12: 687b ldr r3, [r7, #4]
8002b14: 69db ldr r3, [r3, #28]
8002b16: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8002b18: 68fb ldr r3, [r7, #12]
8002b1a: 4a22 ldr r2, [pc, #136] ; (8002ba4 <TIM_OC4_SetConfig+0xb4>)
8002b1c: 4013 ands r3, r2
8002b1e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8002b20: 68fb ldr r3, [r7, #12]
8002b22: 4a21 ldr r2, [pc, #132] ; (8002ba8 <TIM_OC4_SetConfig+0xb8>)
8002b24: 4013 ands r3, r2
8002b26: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8002b28: 683b ldr r3, [r7, #0]
8002b2a: 681b ldr r3, [r3, #0]
8002b2c: 021b lsls r3, r3, #8
8002b2e: 68fa ldr r2, [r7, #12]
8002b30: 4313 orrs r3, r2
8002b32: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8002b34: 693b ldr r3, [r7, #16]
8002b36: 4a1d ldr r2, [pc, #116] ; (8002bac <TIM_OC4_SetConfig+0xbc>)
8002b38: 4013 ands r3, r2
8002b3a: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8002b3c: 683b ldr r3, [r7, #0]
8002b3e: 689b ldr r3, [r3, #8]
8002b40: 031b lsls r3, r3, #12
8002b42: 693a ldr r2, [r7, #16]
8002b44: 4313 orrs r3, r2
8002b46: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002b48: 687b ldr r3, [r7, #4]
8002b4a: 4a19 ldr r2, [pc, #100] ; (8002bb0 <TIM_OC4_SetConfig+0xc0>)
8002b4c: 4293 cmp r3, r2
8002b4e: d00b beq.n 8002b68 <TIM_OC4_SetConfig+0x78>
8002b50: 687b ldr r3, [r7, #4]
8002b52: 4a18 ldr r2, [pc, #96] ; (8002bb4 <TIM_OC4_SetConfig+0xc4>)
8002b54: 4293 cmp r3, r2
8002b56: d007 beq.n 8002b68 <TIM_OC4_SetConfig+0x78>
8002b58: 687b ldr r3, [r7, #4]
8002b5a: 4a17 ldr r2, [pc, #92] ; (8002bb8 <TIM_OC4_SetConfig+0xc8>)
8002b5c: 4293 cmp r3, r2
8002b5e: d003 beq.n 8002b68 <TIM_OC4_SetConfig+0x78>
8002b60: 687b ldr r3, [r7, #4]
8002b62: 4a16 ldr r2, [pc, #88] ; (8002bbc <TIM_OC4_SetConfig+0xcc>)
8002b64: 4293 cmp r3, r2
8002b66: d109 bne.n 8002b7c <TIM_OC4_SetConfig+0x8c>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8002b68: 697b ldr r3, [r7, #20]
8002b6a: 4a15 ldr r2, [pc, #84] ; (8002bc0 <TIM_OC4_SetConfig+0xd0>)
8002b6c: 4013 ands r3, r2
8002b6e: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8002b70: 683b ldr r3, [r7, #0]
8002b72: 695b ldr r3, [r3, #20]
8002b74: 019b lsls r3, r3, #6
8002b76: 697a ldr r2, [r7, #20]
8002b78: 4313 orrs r3, r2
8002b7a: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002b7c: 687b ldr r3, [r7, #4]
8002b7e: 697a ldr r2, [r7, #20]
8002b80: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8002b82: 687b ldr r3, [r7, #4]
8002b84: 68fa ldr r2, [r7, #12]
8002b86: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8002b88: 683b ldr r3, [r7, #0]
8002b8a: 685a ldr r2, [r3, #4]
8002b8c: 687b ldr r3, [r7, #4]
8002b8e: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002b90: 687b ldr r3, [r7, #4]
8002b92: 693a ldr r2, [r7, #16]
8002b94: 621a str r2, [r3, #32]
}
8002b96: 46c0 nop ; (mov r8, r8)
8002b98: 46bd mov sp, r7
8002b9a: b006 add sp, #24
8002b9c: bd80 pop {r7, pc}
8002b9e: 46c0 nop ; (mov r8, r8)
8002ba0: ffffefff .word 0xffffefff
8002ba4: feff8fff .word 0xfeff8fff
8002ba8: fffffcff .word 0xfffffcff
8002bac: ffffdfff .word 0xffffdfff
8002bb0: 40012c00 .word 0x40012c00
8002bb4: 40014000 .word 0x40014000
8002bb8: 40014400 .word 0x40014400
8002bbc: 40014800 .word 0x40014800
8002bc0: ffffbfff .word 0xffffbfff
08002bc4 <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8002bc4: b580 push {r7, lr}
8002bc6: b086 sub sp, #24
8002bc8: af00 add r7, sp, #0
8002bca: 6078 str r0, [r7, #4]
8002bcc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
8002bce: 687b ldr r3, [r7, #4]
8002bd0: 6a1b ldr r3, [r3, #32]
8002bd2: 4a25 ldr r2, [pc, #148] ; (8002c68 <TIM_OC5_SetConfig+0xa4>)
8002bd4: 401a ands r2, r3
8002bd6: 687b ldr r3, [r7, #4]
8002bd8: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8002bda: 687b ldr r3, [r7, #4]
8002bdc: 6a1b ldr r3, [r3, #32]
8002bde: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002be0: 687b ldr r3, [r7, #4]
8002be2: 685b ldr r3, [r3, #4]
8002be4: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8002be6: 687b ldr r3, [r7, #4]
8002be8: 6d5b ldr r3, [r3, #84] ; 0x54
8002bea: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
8002bec: 68fb ldr r3, [r7, #12]
8002bee: 4a1f ldr r2, [pc, #124] ; (8002c6c <TIM_OC5_SetConfig+0xa8>)
8002bf0: 4013 ands r3, r2
8002bf2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8002bf4: 683b ldr r3, [r7, #0]
8002bf6: 681b ldr r3, [r3, #0]
8002bf8: 68fa ldr r2, [r7, #12]
8002bfa: 4313 orrs r3, r2
8002bfc: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
8002bfe: 693b ldr r3, [r7, #16]
8002c00: 4a1b ldr r2, [pc, #108] ; (8002c70 <TIM_OC5_SetConfig+0xac>)
8002c02: 4013 ands r3, r2
8002c04: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
8002c06: 683b ldr r3, [r7, #0]
8002c08: 689b ldr r3, [r3, #8]
8002c0a: 041b lsls r3, r3, #16
8002c0c: 693a ldr r2, [r7, #16]
8002c0e: 4313 orrs r3, r2
8002c10: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002c12: 687b ldr r3, [r7, #4]
8002c14: 4a17 ldr r2, [pc, #92] ; (8002c74 <TIM_OC5_SetConfig+0xb0>)
8002c16: 4293 cmp r3, r2
8002c18: d00b beq.n 8002c32 <TIM_OC5_SetConfig+0x6e>
8002c1a: 687b ldr r3, [r7, #4]
8002c1c: 4a16 ldr r2, [pc, #88] ; (8002c78 <TIM_OC5_SetConfig+0xb4>)
8002c1e: 4293 cmp r3, r2
8002c20: d007 beq.n 8002c32 <TIM_OC5_SetConfig+0x6e>
8002c22: 687b ldr r3, [r7, #4]
8002c24: 4a15 ldr r2, [pc, #84] ; (8002c7c <TIM_OC5_SetConfig+0xb8>)
8002c26: 4293 cmp r3, r2
8002c28: d003 beq.n 8002c32 <TIM_OC5_SetConfig+0x6e>
8002c2a: 687b ldr r3, [r7, #4]
8002c2c: 4a14 ldr r2, [pc, #80] ; (8002c80 <TIM_OC5_SetConfig+0xbc>)
8002c2e: 4293 cmp r3, r2
8002c30: d109 bne.n 8002c46 <TIM_OC5_SetConfig+0x82>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
8002c32: 697b ldr r3, [r7, #20]
8002c34: 4a0c ldr r2, [pc, #48] ; (8002c68 <TIM_OC5_SetConfig+0xa4>)
8002c36: 4013 ands r3, r2
8002c38: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
8002c3a: 683b ldr r3, [r7, #0]
8002c3c: 695b ldr r3, [r3, #20]
8002c3e: 021b lsls r3, r3, #8
8002c40: 697a ldr r2, [r7, #20]
8002c42: 4313 orrs r3, r2
8002c44: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002c46: 687b ldr r3, [r7, #4]
8002c48: 697a ldr r2, [r7, #20]
8002c4a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8002c4c: 687b ldr r3, [r7, #4]
8002c4e: 68fa ldr r2, [r7, #12]
8002c50: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
8002c52: 683b ldr r3, [r7, #0]
8002c54: 685a ldr r2, [r3, #4]
8002c56: 687b ldr r3, [r7, #4]
8002c58: 659a str r2, [r3, #88] ; 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002c5a: 687b ldr r3, [r7, #4]
8002c5c: 693a ldr r2, [r7, #16]
8002c5e: 621a str r2, [r3, #32]
}
8002c60: 46c0 nop ; (mov r8, r8)
8002c62: 46bd mov sp, r7
8002c64: b006 add sp, #24
8002c66: bd80 pop {r7, pc}
8002c68: fffeffff .word 0xfffeffff
8002c6c: fffeff8f .word 0xfffeff8f
8002c70: fffdffff .word 0xfffdffff
8002c74: 40012c00 .word 0x40012c00
8002c78: 40014000 .word 0x40014000
8002c7c: 40014400 .word 0x40014400
8002c80: 40014800 .word 0x40014800
08002c84 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8002c84: b580 push {r7, lr}
8002c86: b086 sub sp, #24
8002c88: af00 add r7, sp, #0
8002c8a: 6078 str r0, [r7, #4]
8002c8c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
8002c8e: 687b ldr r3, [r7, #4]
8002c90: 6a1b ldr r3, [r3, #32]
8002c92: 4a26 ldr r2, [pc, #152] ; (8002d2c <TIM_OC6_SetConfig+0xa8>)
8002c94: 401a ands r2, r3
8002c96: 687b ldr r3, [r7, #4]
8002c98: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8002c9a: 687b ldr r3, [r7, #4]
8002c9c: 6a1b ldr r3, [r3, #32]
8002c9e: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002ca0: 687b ldr r3, [r7, #4]
8002ca2: 685b ldr r3, [r3, #4]
8002ca4: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8002ca6: 687b ldr r3, [r7, #4]
8002ca8: 6d5b ldr r3, [r3, #84] ; 0x54
8002caa: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
8002cac: 68fb ldr r3, [r7, #12]
8002cae: 4a20 ldr r2, [pc, #128] ; (8002d30 <TIM_OC6_SetConfig+0xac>)
8002cb0: 4013 ands r3, r2
8002cb2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8002cb4: 683b ldr r3, [r7, #0]
8002cb6: 681b ldr r3, [r3, #0]
8002cb8: 021b lsls r3, r3, #8
8002cba: 68fa ldr r2, [r7, #12]
8002cbc: 4313 orrs r3, r2
8002cbe: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
8002cc0: 693b ldr r3, [r7, #16]
8002cc2: 4a1c ldr r2, [pc, #112] ; (8002d34 <TIM_OC6_SetConfig+0xb0>)
8002cc4: 4013 ands r3, r2
8002cc6: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
8002cc8: 683b ldr r3, [r7, #0]
8002cca: 689b ldr r3, [r3, #8]
8002ccc: 051b lsls r3, r3, #20
8002cce: 693a ldr r2, [r7, #16]
8002cd0: 4313 orrs r3, r2
8002cd2: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002cd4: 687b ldr r3, [r7, #4]
8002cd6: 4a18 ldr r2, [pc, #96] ; (8002d38 <TIM_OC6_SetConfig+0xb4>)
8002cd8: 4293 cmp r3, r2
8002cda: d00b beq.n 8002cf4 <TIM_OC6_SetConfig+0x70>
8002cdc: 687b ldr r3, [r7, #4]
8002cde: 4a17 ldr r2, [pc, #92] ; (8002d3c <TIM_OC6_SetConfig+0xb8>)
8002ce0: 4293 cmp r3, r2
8002ce2: d007 beq.n 8002cf4 <TIM_OC6_SetConfig+0x70>
8002ce4: 687b ldr r3, [r7, #4]
8002ce6: 4a16 ldr r2, [pc, #88] ; (8002d40 <TIM_OC6_SetConfig+0xbc>)
8002ce8: 4293 cmp r3, r2
8002cea: d003 beq.n 8002cf4 <TIM_OC6_SetConfig+0x70>
8002cec: 687b ldr r3, [r7, #4]
8002cee: 4a15 ldr r2, [pc, #84] ; (8002d44 <TIM_OC6_SetConfig+0xc0>)
8002cf0: 4293 cmp r3, r2
8002cf2: d109 bne.n 8002d08 <TIM_OC6_SetConfig+0x84>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
8002cf4: 697b ldr r3, [r7, #20]
8002cf6: 4a14 ldr r2, [pc, #80] ; (8002d48 <TIM_OC6_SetConfig+0xc4>)
8002cf8: 4013 ands r3, r2
8002cfa: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
8002cfc: 683b ldr r3, [r7, #0]
8002cfe: 695b ldr r3, [r3, #20]
8002d00: 029b lsls r3, r3, #10
8002d02: 697a ldr r2, [r7, #20]
8002d04: 4313 orrs r3, r2
8002d06: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002d08: 687b ldr r3, [r7, #4]
8002d0a: 697a ldr r2, [r7, #20]
8002d0c: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8002d0e: 687b ldr r3, [r7, #4]
8002d10: 68fa ldr r2, [r7, #12]
8002d12: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
8002d14: 683b ldr r3, [r7, #0]
8002d16: 685a ldr r2, [r3, #4]
8002d18: 687b ldr r3, [r7, #4]
8002d1a: 65da str r2, [r3, #92] ; 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002d1c: 687b ldr r3, [r7, #4]
8002d1e: 693a ldr r2, [r7, #16]
8002d20: 621a str r2, [r3, #32]
}
8002d22: 46c0 nop ; (mov r8, r8)
8002d24: 46bd mov sp, r7
8002d26: b006 add sp, #24
8002d28: bd80 pop {r7, pc}
8002d2a: 46c0 nop ; (mov r8, r8)
8002d2c: ffefffff .word 0xffefffff
8002d30: feff8fff .word 0xfeff8fff
8002d34: ffdfffff .word 0xffdfffff
8002d38: 40012c00 .word 0x40012c00
8002d3c: 40014000 .word 0x40014000
8002d40: 40014400 .word 0x40014400
8002d44: 40014800 .word 0x40014800
8002d48: fffbffff .word 0xfffbffff
08002d4c <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8002d4c: b580 push {r7, lr}
8002d4e: b084 sub sp, #16
8002d50: af00 add r7, sp, #0
8002d52: 6078 str r0, [r7, #4]
8002d54: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8002d56: 687b ldr r3, [r7, #4]
8002d58: 223c movs r2, #60 ; 0x3c
8002d5a: 5c9b ldrb r3, [r3, r2]
8002d5c: 2b01 cmp r3, #1
8002d5e: d101 bne.n 8002d64 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8002d60: 2302 movs r3, #2
8002d62: e04f b.n 8002e04 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8002d64: 687b ldr r3, [r7, #4]
8002d66: 223c movs r2, #60 ; 0x3c
8002d68: 2101 movs r1, #1
8002d6a: 5499 strb r1, [r3, r2]
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8002d6c: 687b ldr r3, [r7, #4]
8002d6e: 223d movs r2, #61 ; 0x3d
8002d70: 2102 movs r1, #2
8002d72: 5499 strb r1, [r3, r2]
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8002d74: 687b ldr r3, [r7, #4]
8002d76: 681b ldr r3, [r3, #0]
8002d78: 685b ldr r3, [r3, #4]
8002d7a: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8002d7c: 687b ldr r3, [r7, #4]
8002d7e: 681b ldr r3, [r3, #0]
8002d80: 689b ldr r3, [r3, #8]
8002d82: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
8002d84: 687b ldr r3, [r7, #4]
8002d86: 681b ldr r3, [r3, #0]
8002d88: 4a20 ldr r2, [pc, #128] ; (8002e0c <HAL_TIMEx_MasterConfigSynchronization+0xc0>)
8002d8a: 4293 cmp r3, r2
8002d8c: d108 bne.n 8002da0 <HAL_TIMEx_MasterConfigSynchronization+0x54>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
8002d8e: 68fb ldr r3, [r7, #12]
8002d90: 4a1f ldr r2, [pc, #124] ; (8002e10 <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
8002d92: 4013 ands r3, r2
8002d94: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
8002d96: 683b ldr r3, [r7, #0]
8002d98: 685b ldr r3, [r3, #4]
8002d9a: 68fa ldr r2, [r7, #12]
8002d9c: 4313 orrs r3, r2
8002d9e: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8002da0: 68fb ldr r3, [r7, #12]
8002da2: 2270 movs r2, #112 ; 0x70
8002da4: 4393 bics r3, r2
8002da6: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8002da8: 683b ldr r3, [r7, #0]
8002daa: 681b ldr r3, [r3, #0]
8002dac: 68fa ldr r2, [r7, #12]
8002dae: 4313 orrs r3, r2
8002db0: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8002db2: 687b ldr r3, [r7, #4]
8002db4: 681b ldr r3, [r3, #0]
8002db6: 68fa ldr r2, [r7, #12]
8002db8: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8002dba: 687b ldr r3, [r7, #4]
8002dbc: 681b ldr r3, [r3, #0]
8002dbe: 4a13 ldr r2, [pc, #76] ; (8002e0c <HAL_TIMEx_MasterConfigSynchronization+0xc0>)
8002dc0: 4293 cmp r3, r2
8002dc2: d009 beq.n 8002dd8 <HAL_TIMEx_MasterConfigSynchronization+0x8c>
8002dc4: 687b ldr r3, [r7, #4]
8002dc6: 681b ldr r3, [r3, #0]
8002dc8: 4a12 ldr r2, [pc, #72] ; (8002e14 <HAL_TIMEx_MasterConfigSynchronization+0xc8>)
8002dca: 4293 cmp r3, r2
8002dcc: d004 beq.n 8002dd8 <HAL_TIMEx_MasterConfigSynchronization+0x8c>
8002dce: 687b ldr r3, [r7, #4]
8002dd0: 681b ldr r3, [r3, #0]
8002dd2: 4a11 ldr r2, [pc, #68] ; (8002e18 <HAL_TIMEx_MasterConfigSynchronization+0xcc>)
8002dd4: 4293 cmp r3, r2
8002dd6: d10c bne.n 8002df2 <HAL_TIMEx_MasterConfigSynchronization+0xa6>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8002dd8: 68bb ldr r3, [r7, #8]
8002dda: 2280 movs r2, #128 ; 0x80
8002ddc: 4393 bics r3, r2
8002dde: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8002de0: 683b ldr r3, [r7, #0]
8002de2: 689b ldr r3, [r3, #8]
8002de4: 68ba ldr r2, [r7, #8]
8002de6: 4313 orrs r3, r2
8002de8: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8002dea: 687b ldr r3, [r7, #4]
8002dec: 681b ldr r3, [r3, #0]
8002dee: 68ba ldr r2, [r7, #8]
8002df0: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8002df2: 687b ldr r3, [r7, #4]
8002df4: 223d movs r2, #61 ; 0x3d
8002df6: 2101 movs r1, #1
8002df8: 5499 strb r1, [r3, r2]
__HAL_UNLOCK(htim);
8002dfa: 687b ldr r3, [r7, #4]
8002dfc: 223c movs r2, #60 ; 0x3c
8002dfe: 2100 movs r1, #0
8002e00: 5499 strb r1, [r3, r2]
return HAL_OK;
8002e02: 2300 movs r3, #0
}
8002e04: 0018 movs r0, r3
8002e06: 46bd mov sp, r7
8002e08: b004 add sp, #16
8002e0a: bd80 pop {r7, pc}
8002e0c: 40012c00 .word 0x40012c00
8002e10: ff0fffff .word 0xff0fffff
8002e14: 40000400 .word 0x40000400
8002e18: 40014000 .word 0x40014000
08002e1c <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
8002e1c: b580 push {r7, lr}
8002e1e: b084 sub sp, #16
8002e20: af00 add r7, sp, #0
8002e22: 6078 str r0, [r7, #4]
8002e24: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
8002e26: 2300 movs r3, #0
8002e28: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
8002e2a: 687b ldr r3, [r7, #4]
8002e2c: 223c movs r2, #60 ; 0x3c
8002e2e: 5c9b ldrb r3, [r3, r2]
8002e30: 2b01 cmp r3, #1
8002e32: d101 bne.n 8002e38 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
8002e34: 2302 movs r3, #2
8002e36: e079 b.n 8002f2c <HAL_TIMEx_ConfigBreakDeadTime+0x110>
8002e38: 687b ldr r3, [r7, #4]
8002e3a: 223c movs r2, #60 ; 0x3c
8002e3c: 2101 movs r1, #1
8002e3e: 5499 strb r1, [r3, r2]
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
8002e40: 68fb ldr r3, [r7, #12]
8002e42: 22ff movs r2, #255 ; 0xff
8002e44: 4393 bics r3, r2
8002e46: 001a movs r2, r3
8002e48: 683b ldr r3, [r7, #0]
8002e4a: 68db ldr r3, [r3, #12]
8002e4c: 4313 orrs r3, r2
8002e4e: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
8002e50: 68fb ldr r3, [r7, #12]
8002e52: 4a38 ldr r2, [pc, #224] ; (8002f34 <HAL_TIMEx_ConfigBreakDeadTime+0x118>)
8002e54: 401a ands r2, r3
8002e56: 683b ldr r3, [r7, #0]
8002e58: 689b ldr r3, [r3, #8]
8002e5a: 4313 orrs r3, r2
8002e5c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
8002e5e: 68fb ldr r3, [r7, #12]
8002e60: 4a35 ldr r2, [pc, #212] ; (8002f38 <HAL_TIMEx_ConfigBreakDeadTime+0x11c>)
8002e62: 401a ands r2, r3
8002e64: 683b ldr r3, [r7, #0]
8002e66: 685b ldr r3, [r3, #4]
8002e68: 4313 orrs r3, r2
8002e6a: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
8002e6c: 68fb ldr r3, [r7, #12]
8002e6e: 4a33 ldr r2, [pc, #204] ; (8002f3c <HAL_TIMEx_ConfigBreakDeadTime+0x120>)
8002e70: 401a ands r2, r3
8002e72: 683b ldr r3, [r7, #0]
8002e74: 681b ldr r3, [r3, #0]
8002e76: 4313 orrs r3, r2
8002e78: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
8002e7a: 68fb ldr r3, [r7, #12]
8002e7c: 4a30 ldr r2, [pc, #192] ; (8002f40 <HAL_TIMEx_ConfigBreakDeadTime+0x124>)
8002e7e: 401a ands r2, r3
8002e80: 683b ldr r3, [r7, #0]
8002e82: 691b ldr r3, [r3, #16]
8002e84: 4313 orrs r3, r2
8002e86: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
8002e88: 68fb ldr r3, [r7, #12]
8002e8a: 4a2e ldr r2, [pc, #184] ; (8002f44 <HAL_TIMEx_ConfigBreakDeadTime+0x128>)
8002e8c: 401a ands r2, r3
8002e8e: 683b ldr r3, [r7, #0]
8002e90: 695b ldr r3, [r3, #20]
8002e92: 4313 orrs r3, r2
8002e94: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
8002e96: 68fb ldr r3, [r7, #12]
8002e98: 4a2b ldr r2, [pc, #172] ; (8002f48 <HAL_TIMEx_ConfigBreakDeadTime+0x12c>)
8002e9a: 401a ands r2, r3
8002e9c: 683b ldr r3, [r7, #0]
8002e9e: 6b1b ldr r3, [r3, #48] ; 0x30
8002ea0: 4313 orrs r3, r2
8002ea2: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
8002ea4: 68fb ldr r3, [r7, #12]
8002ea6: 4a29 ldr r2, [pc, #164] ; (8002f4c <HAL_TIMEx_ConfigBreakDeadTime+0x130>)
8002ea8: 401a ands r2, r3
8002eaa: 683b ldr r3, [r7, #0]
8002eac: 699b ldr r3, [r3, #24]
8002eae: 041b lsls r3, r3, #16
8002eb0: 4313 orrs r3, r2
8002eb2: 60fb str r3, [r7, #12]
if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
8002eb4: 687b ldr r3, [r7, #4]
8002eb6: 681b ldr r3, [r3, #0]
8002eb8: 4a25 ldr r2, [pc, #148] ; (8002f50 <HAL_TIMEx_ConfigBreakDeadTime+0x134>)
8002eba: 4293 cmp r3, r2
8002ebc: d106 bne.n 8002ecc <HAL_TIMEx_ConfigBreakDeadTime+0xb0>
{
/* Check the parameters */
assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
/* Set BREAK AF mode */
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
8002ebe: 68fb ldr r3, [r7, #12]
8002ec0: 4a24 ldr r2, [pc, #144] ; (8002f54 <HAL_TIMEx_ConfigBreakDeadTime+0x138>)
8002ec2: 401a ands r2, r3
8002ec4: 683b ldr r3, [r7, #0]
8002ec6: 69db ldr r3, [r3, #28]
8002ec8: 4313 orrs r3, r2
8002eca: 60fb str r3, [r7, #12]
}
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
8002ecc: 687b ldr r3, [r7, #4]
8002ece: 681b ldr r3, [r3, #0]
8002ed0: 4a1f ldr r2, [pc, #124] ; (8002f50 <HAL_TIMEx_ConfigBreakDeadTime+0x134>)
8002ed2: 4293 cmp r3, r2
8002ed4: d121 bne.n 8002f1a <HAL_TIMEx_ConfigBreakDeadTime+0xfe>
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
8002ed6: 68fb ldr r3, [r7, #12]
8002ed8: 4a1f ldr r2, [pc, #124] ; (8002f58 <HAL_TIMEx_ConfigBreakDeadTime+0x13c>)
8002eda: 401a ands r2, r3
8002edc: 683b ldr r3, [r7, #0]
8002ede: 6a9b ldr r3, [r3, #40] ; 0x28
8002ee0: 051b lsls r3, r3, #20
8002ee2: 4313 orrs r3, r2
8002ee4: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
8002ee6: 68fb ldr r3, [r7, #12]
8002ee8: 4a1c ldr r2, [pc, #112] ; (8002f5c <HAL_TIMEx_ConfigBreakDeadTime+0x140>)
8002eea: 401a ands r2, r3
8002eec: 683b ldr r3, [r7, #0]
8002eee: 6a1b ldr r3, [r3, #32]
8002ef0: 4313 orrs r3, r2
8002ef2: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
8002ef4: 68fb ldr r3, [r7, #12]
8002ef6: 4a1a ldr r2, [pc, #104] ; (8002f60 <HAL_TIMEx_ConfigBreakDeadTime+0x144>)
8002ef8: 401a ands r2, r3
8002efa: 683b ldr r3, [r7, #0]
8002efc: 6a5b ldr r3, [r3, #36] ; 0x24
8002efe: 4313 orrs r3, r2
8002f00: 60fb str r3, [r7, #12]
if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
8002f02: 687b ldr r3, [r7, #4]
8002f04: 681b ldr r3, [r3, #0]
8002f06: 4a12 ldr r2, [pc, #72] ; (8002f50 <HAL_TIMEx_ConfigBreakDeadTime+0x134>)
8002f08: 4293 cmp r3, r2
8002f0a: d106 bne.n 8002f1a <HAL_TIMEx_ConfigBreakDeadTime+0xfe>
{
/* Check the parameters */
assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
/* Set BREAK2 AF mode */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
8002f0c: 68fb ldr r3, [r7, #12]
8002f0e: 4a15 ldr r2, [pc, #84] ; (8002f64 <HAL_TIMEx_ConfigBreakDeadTime+0x148>)
8002f10: 401a ands r2, r3
8002f12: 683b ldr r3, [r7, #0]
8002f14: 6adb ldr r3, [r3, #44] ; 0x2c
8002f16: 4313 orrs r3, r2
8002f18: 60fb str r3, [r7, #12]
}
}
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
8002f1a: 687b ldr r3, [r7, #4]
8002f1c: 681b ldr r3, [r3, #0]
8002f1e: 68fa ldr r2, [r7, #12]
8002f20: 645a str r2, [r3, #68] ; 0x44
__HAL_UNLOCK(htim);
8002f22: 687b ldr r3, [r7, #4]
8002f24: 223c movs r2, #60 ; 0x3c
8002f26: 2100 movs r1, #0
8002f28: 5499 strb r1, [r3, r2]
return HAL_OK;
8002f2a: 2300 movs r3, #0
}
8002f2c: 0018 movs r0, r3
8002f2e: 46bd mov sp, r7
8002f30: b004 add sp, #16
8002f32: bd80 pop {r7, pc}
8002f34: fffffcff .word 0xfffffcff
8002f38: fffffbff .word 0xfffffbff
8002f3c: fffff7ff .word 0xfffff7ff
8002f40: ffffefff .word 0xffffefff
8002f44: ffffdfff .word 0xffffdfff
8002f48: ffffbfff .word 0xffffbfff
8002f4c: fff0ffff .word 0xfff0ffff
8002f50: 40012c00 .word 0x40012c00
8002f54: efffffff .word 0xefffffff
8002f58: ff0fffff .word 0xff0fffff
8002f5c: feffffff .word 0xfeffffff
8002f60: fdffffff .word 0xfdffffff
8002f64: dfffffff .word 0xdfffffff
08002f68 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8002f68: b580 push {r7, lr}
8002f6a: b082 sub sp, #8
8002f6c: af00 add r7, sp, #0
8002f6e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8002f70: 46c0 nop ; (mov r8, r8)
8002f72: 46bd mov sp, r7
8002f74: b002 add sp, #8
8002f76: bd80 pop {r7, pc}
08002f78 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8002f78: b580 push {r7, lr}
8002f7a: b082 sub sp, #8
8002f7c: af00 add r7, sp, #0
8002f7e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8002f80: 46c0 nop ; (mov r8, r8)
8002f82: 46bd mov sp, r7
8002f84: b002 add sp, #8
8002f86: bd80 pop {r7, pc}
08002f88 <HAL_TIMEx_Break2Callback>:
* @brief Hall Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
8002f88: b580 push {r7, lr}
8002f8a: b082 sub sp, #8
8002f8c: af00 add r7, sp, #0
8002f8e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
8002f90: 46c0 nop ; (mov r8, r8)
8002f92: 46bd mov sp, r7
8002f94: b002 add sp, #8
8002f96: bd80 pop {r7, pc}
08002f98 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8002f98: b580 push {r7, lr}
8002f9a: b082 sub sp, #8
8002f9c: af00 add r7, sp, #0
8002f9e: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8002fa0: 687b ldr r3, [r7, #4]
8002fa2: 2b00 cmp r3, #0
8002fa4: d101 bne.n 8002faa <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8002fa6: 2301 movs r3, #1
8002fa8: e046 b.n 8003038 <HAL_UART_Init+0xa0>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
8002faa: 687b ldr r3, [r7, #4]
8002fac: 2288 movs r2, #136 ; 0x88
8002fae: 589b ldr r3, [r3, r2]
8002fb0: 2b00 cmp r3, #0
8002fb2: d107 bne.n 8002fc4 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8002fb4: 687b ldr r3, [r7, #4]
8002fb6: 2284 movs r2, #132 ; 0x84
8002fb8: 2100 movs r1, #0
8002fba: 5499 strb r1, [r3, r2]
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8002fbc: 687b ldr r3, [r7, #4]
8002fbe: 0018 movs r0, r3
8002fc0: f7fd fe82 bl 8000cc8 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8002fc4: 687b ldr r3, [r7, #4]
8002fc6: 2288 movs r2, #136 ; 0x88
8002fc8: 2124 movs r1, #36 ; 0x24
8002fca: 5099 str r1, [r3, r2]
__HAL_UART_DISABLE(huart);
8002fcc: 687b ldr r3, [r7, #4]
8002fce: 681b ldr r3, [r3, #0]
8002fd0: 681a ldr r2, [r3, #0]
8002fd2: 687b ldr r3, [r7, #4]
8002fd4: 681b ldr r3, [r3, #0]
8002fd6: 2101 movs r1, #1
8002fd8: 438a bics r2, r1
8002fda: 601a str r2, [r3, #0]
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
8002fdc: 687b ldr r3, [r7, #4]
8002fde: 0018 movs r0, r3
8002fe0: f000 f830 bl 8003044 <UART_SetConfig>
8002fe4: 0003 movs r3, r0
8002fe6: 2b01 cmp r3, #1
8002fe8: d101 bne.n 8002fee <HAL_UART_Init+0x56>
{
return HAL_ERROR;
8002fea: 2301 movs r3, #1
8002fec: e024 b.n 8003038 <HAL_UART_Init+0xa0>
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
8002fee: 687b ldr r3, [r7, #4]
8002ff0: 6a9b ldr r3, [r3, #40] ; 0x28
8002ff2: 2b00 cmp r3, #0
8002ff4: d003 beq.n 8002ffe <HAL_UART_Init+0x66>
{
UART_AdvFeatureConfig(huart);
8002ff6: 687b ldr r3, [r7, #4]
8002ff8: 0018 movs r0, r3
8002ffa: f000 f9c7 bl 800338c <UART_AdvFeatureConfig>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8002ffe: 687b ldr r3, [r7, #4]
8003000: 681b ldr r3, [r3, #0]
8003002: 685a ldr r2, [r3, #4]
8003004: 687b ldr r3, [r7, #4]
8003006: 681b ldr r3, [r3, #0]
8003008: 490d ldr r1, [pc, #52] ; (8003040 <HAL_UART_Init+0xa8>)
800300a: 400a ands r2, r1
800300c: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
800300e: 687b ldr r3, [r7, #4]
8003010: 681b ldr r3, [r3, #0]
8003012: 689a ldr r2, [r3, #8]
8003014: 687b ldr r3, [r7, #4]
8003016: 681b ldr r3, [r3, #0]
8003018: 212a movs r1, #42 ; 0x2a
800301a: 438a bics r2, r1
800301c: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
800301e: 687b ldr r3, [r7, #4]
8003020: 681b ldr r3, [r3, #0]
8003022: 681a ldr r2, [r3, #0]
8003024: 687b ldr r3, [r7, #4]
8003026: 681b ldr r3, [r3, #0]
8003028: 2101 movs r1, #1
800302a: 430a orrs r2, r1
800302c: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
800302e: 687b ldr r3, [r7, #4]
8003030: 0018 movs r0, r3
8003032: f000 fa5f bl 80034f4 <UART_CheckIdleState>
8003036: 0003 movs r3, r0
}
8003038: 0018 movs r0, r3
800303a: 46bd mov sp, r7
800303c: b002 add sp, #8
800303e: bd80 pop {r7, pc}
8003040: ffffb7ff .word 0xffffb7ff
08003044 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8003044: b580 push {r7, lr}
8003046: b088 sub sp, #32
8003048: af00 add r7, sp, #0
800304a: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
800304c: 231a movs r3, #26
800304e: 18fb adds r3, r7, r3
8003050: 2200 movs r2, #0
8003052: 701a strb r2, [r3, #0]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8003054: 687b ldr r3, [r7, #4]
8003056: 689a ldr r2, [r3, #8]
8003058: 687b ldr r3, [r7, #4]
800305a: 691b ldr r3, [r3, #16]
800305c: 431a orrs r2, r3
800305e: 687b ldr r3, [r7, #4]
8003060: 695b ldr r3, [r3, #20]
8003062: 431a orrs r2, r3
8003064: 687b ldr r3, [r7, #4]
8003066: 69db ldr r3, [r3, #28]
8003068: 4313 orrs r3, r2
800306a: 61fb str r3, [r7, #28]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
800306c: 687b ldr r3, [r7, #4]
800306e: 681b ldr r3, [r3, #0]
8003070: 681b ldr r3, [r3, #0]
8003072: 4abc ldr r2, [pc, #752] ; (8003364 <UART_SetConfig+0x320>)
8003074: 4013 ands r3, r2
8003076: 0019 movs r1, r3
8003078: 687b ldr r3, [r7, #4]
800307a: 681b ldr r3, [r3, #0]
800307c: 69fa ldr r2, [r7, #28]
800307e: 430a orrs r2, r1
8003080: 601a str r2, [r3, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8003082: 687b ldr r3, [r7, #4]
8003084: 681b ldr r3, [r3, #0]
8003086: 685b ldr r3, [r3, #4]
8003088: 4ab7 ldr r2, [pc, #732] ; (8003368 <UART_SetConfig+0x324>)
800308a: 4013 ands r3, r2
800308c: 0019 movs r1, r3
800308e: 687b ldr r3, [r7, #4]
8003090: 68da ldr r2, [r3, #12]
8003092: 687b ldr r3, [r7, #4]
8003094: 681b ldr r3, [r3, #0]
8003096: 430a orrs r2, r1
8003098: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
800309a: 687b ldr r3, [r7, #4]
800309c: 699b ldr r3, [r3, #24]
800309e: 61fb str r3, [r7, #28]
if (!(UART_INSTANCE_LOWPOWER(huart)))
{
tmpreg |= huart->Init.OneBitSampling;
80030a0: 687b ldr r3, [r7, #4]
80030a2: 6a1b ldr r3, [r3, #32]
80030a4: 69fa ldr r2, [r7, #28]
80030a6: 4313 orrs r3, r2
80030a8: 61fb str r3, [r7, #28]
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
80030aa: 687b ldr r3, [r7, #4]
80030ac: 681b ldr r3, [r3, #0]
80030ae: 689b ldr r3, [r3, #8]
80030b0: 4aae ldr r2, [pc, #696] ; (800336c <UART_SetConfig+0x328>)
80030b2: 4013 ands r3, r2
80030b4: 0019 movs r1, r3
80030b6: 687b ldr r3, [r7, #4]
80030b8: 681b ldr r3, [r3, #0]
80030ba: 69fa ldr r2, [r7, #28]
80030bc: 430a orrs r2, r1
80030be: 609a str r2, [r3, #8]
/*-------------------------- USART PRESC Configuration -----------------------*/
/* Configure
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
80030c0: 687b ldr r3, [r7, #4]
80030c2: 681b ldr r3, [r3, #0]
80030c4: 6adb ldr r3, [r3, #44] ; 0x2c
80030c6: 220f movs r2, #15
80030c8: 4393 bics r3, r2
80030ca: 0019 movs r1, r3
80030cc: 687b ldr r3, [r7, #4]
80030ce: 6a5a ldr r2, [r3, #36] ; 0x24
80030d0: 687b ldr r3, [r7, #4]
80030d2: 681b ldr r3, [r3, #0]
80030d4: 430a orrs r2, r1
80030d6: 62da str r2, [r3, #44] ; 0x2c
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
80030d8: 687b ldr r3, [r7, #4]
80030da: 681b ldr r3, [r3, #0]
80030dc: 4aa4 ldr r2, [pc, #656] ; (8003370 <UART_SetConfig+0x32c>)
80030de: 4293 cmp r3, r2
80030e0: d127 bne.n 8003132 <UART_SetConfig+0xee>
80030e2: 4ba4 ldr r3, [pc, #656] ; (8003374 <UART_SetConfig+0x330>)
80030e4: 6d5b ldr r3, [r3, #84] ; 0x54
80030e6: 2203 movs r2, #3
80030e8: 4013 ands r3, r2
80030ea: 2b03 cmp r3, #3
80030ec: d017 beq.n 800311e <UART_SetConfig+0xda>
80030ee: d81b bhi.n 8003128 <UART_SetConfig+0xe4>
80030f0: 2b02 cmp r3, #2
80030f2: d00a beq.n 800310a <UART_SetConfig+0xc6>
80030f4: d818 bhi.n 8003128 <UART_SetConfig+0xe4>
80030f6: 2b00 cmp r3, #0
80030f8: d002 beq.n 8003100 <UART_SetConfig+0xbc>
80030fa: 2b01 cmp r3, #1
80030fc: d00a beq.n 8003114 <UART_SetConfig+0xd0>
80030fe: e013 b.n 8003128 <UART_SetConfig+0xe4>
8003100: 231b movs r3, #27
8003102: 18fb adds r3, r7, r3
8003104: 2200 movs r2, #0
8003106: 701a strb r2, [r3, #0]
8003108: e058 b.n 80031bc <UART_SetConfig+0x178>
800310a: 231b movs r3, #27
800310c: 18fb adds r3, r7, r3
800310e: 2202 movs r2, #2
8003110: 701a strb r2, [r3, #0]
8003112: e053 b.n 80031bc <UART_SetConfig+0x178>
8003114: 231b movs r3, #27
8003116: 18fb adds r3, r7, r3
8003118: 2204 movs r2, #4
800311a: 701a strb r2, [r3, #0]
800311c: e04e b.n 80031bc <UART_SetConfig+0x178>
800311e: 231b movs r3, #27
8003120: 18fb adds r3, r7, r3
8003122: 2208 movs r2, #8
8003124: 701a strb r2, [r3, #0]
8003126: e049 b.n 80031bc <UART_SetConfig+0x178>
8003128: 231b movs r3, #27
800312a: 18fb adds r3, r7, r3
800312c: 2210 movs r2, #16
800312e: 701a strb r2, [r3, #0]
8003130: e044 b.n 80031bc <UART_SetConfig+0x178>
8003132: 687b ldr r3, [r7, #4]
8003134: 681b ldr r3, [r3, #0]
8003136: 4a90 ldr r2, [pc, #576] ; (8003378 <UART_SetConfig+0x334>)
8003138: 4293 cmp r3, r2
800313a: d127 bne.n 800318c <UART_SetConfig+0x148>
800313c: 4b8d ldr r3, [pc, #564] ; (8003374 <UART_SetConfig+0x330>)
800313e: 6d5b ldr r3, [r3, #84] ; 0x54
8003140: 220c movs r2, #12
8003142: 4013 ands r3, r2
8003144: 2b0c cmp r3, #12
8003146: d017 beq.n 8003178 <UART_SetConfig+0x134>
8003148: d81b bhi.n 8003182 <UART_SetConfig+0x13e>
800314a: 2b08 cmp r3, #8
800314c: d00a beq.n 8003164 <UART_SetConfig+0x120>
800314e: d818 bhi.n 8003182 <UART_SetConfig+0x13e>
8003150: 2b00 cmp r3, #0
8003152: d002 beq.n 800315a <UART_SetConfig+0x116>
8003154: 2b04 cmp r3, #4
8003156: d00a beq.n 800316e <UART_SetConfig+0x12a>
8003158: e013 b.n 8003182 <UART_SetConfig+0x13e>
800315a: 231b movs r3, #27
800315c: 18fb adds r3, r7, r3
800315e: 2200 movs r2, #0
8003160: 701a strb r2, [r3, #0]
8003162: e02b b.n 80031bc <UART_SetConfig+0x178>
8003164: 231b movs r3, #27
8003166: 18fb adds r3, r7, r3
8003168: 2202 movs r2, #2
800316a: 701a strb r2, [r3, #0]
800316c: e026 b.n 80031bc <UART_SetConfig+0x178>
800316e: 231b movs r3, #27
8003170: 18fb adds r3, r7, r3
8003172: 2204 movs r2, #4
8003174: 701a strb r2, [r3, #0]
8003176: e021 b.n 80031bc <UART_SetConfig+0x178>
8003178: 231b movs r3, #27
800317a: 18fb adds r3, r7, r3
800317c: 2208 movs r2, #8
800317e: 701a strb r2, [r3, #0]
8003180: e01c b.n 80031bc <UART_SetConfig+0x178>
8003182: 231b movs r3, #27
8003184: 18fb adds r3, r7, r3
8003186: 2210 movs r2, #16
8003188: 701a strb r2, [r3, #0]
800318a: e017 b.n 80031bc <UART_SetConfig+0x178>
800318c: 687b ldr r3, [r7, #4]
800318e: 681b ldr r3, [r3, #0]
8003190: 4a7a ldr r2, [pc, #488] ; (800337c <UART_SetConfig+0x338>)
8003192: 4293 cmp r3, r2
8003194: d104 bne.n 80031a0 <UART_SetConfig+0x15c>
8003196: 231b movs r3, #27
8003198: 18fb adds r3, r7, r3
800319a: 2200 movs r2, #0
800319c: 701a strb r2, [r3, #0]
800319e: e00d b.n 80031bc <UART_SetConfig+0x178>
80031a0: 687b ldr r3, [r7, #4]
80031a2: 681b ldr r3, [r3, #0]
80031a4: 4a76 ldr r2, [pc, #472] ; (8003380 <UART_SetConfig+0x33c>)
80031a6: 4293 cmp r3, r2
80031a8: d104 bne.n 80031b4 <UART_SetConfig+0x170>
80031aa: 231b movs r3, #27
80031ac: 18fb adds r3, r7, r3
80031ae: 2200 movs r2, #0
80031b0: 701a strb r2, [r3, #0]
80031b2: e003 b.n 80031bc <UART_SetConfig+0x178>
80031b4: 231b movs r3, #27
80031b6: 18fb adds r3, r7, r3
80031b8: 2210 movs r2, #16
80031ba: 701a strb r2, [r3, #0]
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
80031bc: 687b ldr r3, [r7, #4]
80031be: 69da ldr r2, [r3, #28]
80031c0: 2380 movs r3, #128 ; 0x80
80031c2: 021b lsls r3, r3, #8
80031c4: 429a cmp r2, r3
80031c6: d000 beq.n 80031ca <UART_SetConfig+0x186>
80031c8: e065 b.n 8003296 <UART_SetConfig+0x252>
{
switch (clocksource)
80031ca: 231b movs r3, #27
80031cc: 18fb adds r3, r7, r3
80031ce: 781b ldrb r3, [r3, #0]
80031d0: 2b08 cmp r3, #8
80031d2: d015 beq.n 8003200 <UART_SetConfig+0x1bc>
80031d4: dc18 bgt.n 8003208 <UART_SetConfig+0x1c4>
80031d6: 2b04 cmp r3, #4
80031d8: d00d beq.n 80031f6 <UART_SetConfig+0x1b2>
80031da: dc15 bgt.n 8003208 <UART_SetConfig+0x1c4>
80031dc: 2b00 cmp r3, #0
80031de: d002 beq.n 80031e6 <UART_SetConfig+0x1a2>
80031e0: 2b02 cmp r3, #2
80031e2: d005 beq.n 80031f0 <UART_SetConfig+0x1ac>
80031e4: e010 b.n 8003208 <UART_SetConfig+0x1c4>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80031e6: f7fe fdef bl 8001dc8 <HAL_RCC_GetPCLK1Freq>
80031ea: 0003 movs r3, r0
80031ec: 617b str r3, [r7, #20]
break;
80031ee: e012 b.n 8003216 <UART_SetConfig+0x1d2>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80031f0: 4b64 ldr r3, [pc, #400] ; (8003384 <UART_SetConfig+0x340>)
80031f2: 617b str r3, [r7, #20]
break;
80031f4: e00f b.n 8003216 <UART_SetConfig+0x1d2>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80031f6: f7fe fd5d bl 8001cb4 <HAL_RCC_GetSysClockFreq>
80031fa: 0003 movs r3, r0
80031fc: 617b str r3, [r7, #20]
break;
80031fe: e00a b.n 8003216 <UART_SetConfig+0x1d2>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8003200: 2380 movs r3, #128 ; 0x80
8003202: 021b lsls r3, r3, #8
8003204: 617b str r3, [r7, #20]
break;
8003206: e006 b.n 8003216 <UART_SetConfig+0x1d2>
default:
pclk = 0U;
8003208: 2300 movs r3, #0
800320a: 617b str r3, [r7, #20]
ret = HAL_ERROR;
800320c: 231a movs r3, #26
800320e: 18fb adds r3, r7, r3
8003210: 2201 movs r2, #1
8003212: 701a strb r2, [r3, #0]
break;
8003214: 46c0 nop ; (mov r8, r8)
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
8003216: 697b ldr r3, [r7, #20]
8003218: 2b00 cmp r3, #0
800321a: d100 bne.n 800321e <UART_SetConfig+0x1da>
800321c: e08d b.n 800333a <UART_SetConfig+0x2f6>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
800321e: 687b ldr r3, [r7, #4]
8003220: 6a5a ldr r2, [r3, #36] ; 0x24
8003222: 4b59 ldr r3, [pc, #356] ; (8003388 <UART_SetConfig+0x344>)
8003224: 0052 lsls r2, r2, #1
8003226: 5ad3 ldrh r3, [r2, r3]
8003228: 0019 movs r1, r3
800322a: 6978 ldr r0, [r7, #20]
800322c: f7fc ff68 bl 8000100 <__udivsi3>
8003230: 0003 movs r3, r0
8003232: 005a lsls r2, r3, #1
8003234: 687b ldr r3, [r7, #4]
8003236: 685b ldr r3, [r3, #4]
8003238: 085b lsrs r3, r3, #1
800323a: 18d2 adds r2, r2, r3
800323c: 687b ldr r3, [r7, #4]
800323e: 685b ldr r3, [r3, #4]
8003240: 0019 movs r1, r3
8003242: 0010 movs r0, r2
8003244: f7fc ff5c bl 8000100 <__udivsi3>
8003248: 0003 movs r3, r0
800324a: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
800324c: 693b ldr r3, [r7, #16]
800324e: 2b0f cmp r3, #15
8003250: d91c bls.n 800328c <UART_SetConfig+0x248>
8003252: 693a ldr r2, [r7, #16]
8003254: 2380 movs r3, #128 ; 0x80
8003256: 025b lsls r3, r3, #9
8003258: 429a cmp r2, r3
800325a: d217 bcs.n 800328c <UART_SetConfig+0x248>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
800325c: 693b ldr r3, [r7, #16]
800325e: b29a uxth r2, r3
8003260: 200e movs r0, #14
8003262: 183b adds r3, r7, r0
8003264: 210f movs r1, #15
8003266: 438a bics r2, r1
8003268: 801a strh r2, [r3, #0]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
800326a: 693b ldr r3, [r7, #16]
800326c: 085b lsrs r3, r3, #1
800326e: b29b uxth r3, r3
8003270: 2207 movs r2, #7
8003272: 4013 ands r3, r2
8003274: b299 uxth r1, r3
8003276: 183b adds r3, r7, r0
8003278: 183a adds r2, r7, r0
800327a: 8812 ldrh r2, [r2, #0]
800327c: 430a orrs r2, r1
800327e: 801a strh r2, [r3, #0]
huart->Instance->BRR = brrtemp;
8003280: 687b ldr r3, [r7, #4]
8003282: 681b ldr r3, [r3, #0]
8003284: 183a adds r2, r7, r0
8003286: 8812 ldrh r2, [r2, #0]
8003288: 60da str r2, [r3, #12]
800328a: e056 b.n 800333a <UART_SetConfig+0x2f6>
}
else
{
ret = HAL_ERROR;
800328c: 231a movs r3, #26
800328e: 18fb adds r3, r7, r3
8003290: 2201 movs r2, #1
8003292: 701a strb r2, [r3, #0]
8003294: e051 b.n 800333a <UART_SetConfig+0x2f6>
}
}
}
else
{
switch (clocksource)
8003296: 231b movs r3, #27
8003298: 18fb adds r3, r7, r3
800329a: 781b ldrb r3, [r3, #0]
800329c: 2b08 cmp r3, #8
800329e: d015 beq.n 80032cc <UART_SetConfig+0x288>
80032a0: dc18 bgt.n 80032d4 <UART_SetConfig+0x290>
80032a2: 2b04 cmp r3, #4
80032a4: d00d beq.n 80032c2 <UART_SetConfig+0x27e>
80032a6: dc15 bgt.n 80032d4 <UART_SetConfig+0x290>
80032a8: 2b00 cmp r3, #0
80032aa: d002 beq.n 80032b2 <UART_SetConfig+0x26e>
80032ac: 2b02 cmp r3, #2
80032ae: d005 beq.n 80032bc <UART_SetConfig+0x278>
80032b0: e010 b.n 80032d4 <UART_SetConfig+0x290>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80032b2: f7fe fd89 bl 8001dc8 <HAL_RCC_GetPCLK1Freq>
80032b6: 0003 movs r3, r0
80032b8: 617b str r3, [r7, #20]
break;
80032ba: e012 b.n 80032e2 <UART_SetConfig+0x29e>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80032bc: 4b31 ldr r3, [pc, #196] ; (8003384 <UART_SetConfig+0x340>)
80032be: 617b str r3, [r7, #20]
break;
80032c0: e00f b.n 80032e2 <UART_SetConfig+0x29e>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80032c2: f7fe fcf7 bl 8001cb4 <HAL_RCC_GetSysClockFreq>
80032c6: 0003 movs r3, r0
80032c8: 617b str r3, [r7, #20]
break;
80032ca: e00a b.n 80032e2 <UART_SetConfig+0x29e>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80032cc: 2380 movs r3, #128 ; 0x80
80032ce: 021b lsls r3, r3, #8
80032d0: 617b str r3, [r7, #20]
break;
80032d2: e006 b.n 80032e2 <UART_SetConfig+0x29e>
default:
pclk = 0U;
80032d4: 2300 movs r3, #0
80032d6: 617b str r3, [r7, #20]
ret = HAL_ERROR;
80032d8: 231a movs r3, #26
80032da: 18fb adds r3, r7, r3
80032dc: 2201 movs r2, #1
80032de: 701a strb r2, [r3, #0]
break;
80032e0: 46c0 nop ; (mov r8, r8)
}
if (pclk != 0U)
80032e2: 697b ldr r3, [r7, #20]
80032e4: 2b00 cmp r3, #0
80032e6: d028 beq.n 800333a <UART_SetConfig+0x2f6>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
80032e8: 687b ldr r3, [r7, #4]
80032ea: 6a5a ldr r2, [r3, #36] ; 0x24
80032ec: 4b26 ldr r3, [pc, #152] ; (8003388 <UART_SetConfig+0x344>)
80032ee: 0052 lsls r2, r2, #1
80032f0: 5ad3 ldrh r3, [r2, r3]
80032f2: 0019 movs r1, r3
80032f4: 6978 ldr r0, [r7, #20]
80032f6: f7fc ff03 bl 8000100 <__udivsi3>
80032fa: 0003 movs r3, r0
80032fc: 001a movs r2, r3
80032fe: 687b ldr r3, [r7, #4]
8003300: 685b ldr r3, [r3, #4]
8003302: 085b lsrs r3, r3, #1
8003304: 18d2 adds r2, r2, r3
8003306: 687b ldr r3, [r7, #4]
8003308: 685b ldr r3, [r3, #4]
800330a: 0019 movs r1, r3
800330c: 0010 movs r0, r2
800330e: f7fc fef7 bl 8000100 <__udivsi3>
8003312: 0003 movs r3, r0
8003314: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8003316: 693b ldr r3, [r7, #16]
8003318: 2b0f cmp r3, #15
800331a: d90a bls.n 8003332 <UART_SetConfig+0x2ee>
800331c: 693a ldr r2, [r7, #16]
800331e: 2380 movs r3, #128 ; 0x80
8003320: 025b lsls r3, r3, #9
8003322: 429a cmp r2, r3
8003324: d205 bcs.n 8003332 <UART_SetConfig+0x2ee>
{
huart->Instance->BRR = (uint16_t)usartdiv;
8003326: 693b ldr r3, [r7, #16]
8003328: b29a uxth r2, r3
800332a: 687b ldr r3, [r7, #4]
800332c: 681b ldr r3, [r3, #0]
800332e: 60da str r2, [r3, #12]
8003330: e003 b.n 800333a <UART_SetConfig+0x2f6>
}
else
{
ret = HAL_ERROR;
8003332: 231a movs r3, #26
8003334: 18fb adds r3, r7, r3
8003336: 2201 movs r2, #1
8003338: 701a strb r2, [r3, #0]
}
}
}
/* Initialize the number of data to process during RX/TX ISR execution */
huart->NbTxDataToProcess = 1;
800333a: 687b ldr r3, [r7, #4]
800333c: 226a movs r2, #106 ; 0x6a
800333e: 2101 movs r1, #1
8003340: 5299 strh r1, [r3, r2]
huart->NbRxDataToProcess = 1;
8003342: 687b ldr r3, [r7, #4]
8003344: 2268 movs r2, #104 ; 0x68
8003346: 2101 movs r1, #1
8003348: 5299 strh r1, [r3, r2]
/* Clear ISR function pointers */
huart->RxISR = NULL;
800334a: 687b ldr r3, [r7, #4]
800334c: 2200 movs r2, #0
800334e: 675a str r2, [r3, #116] ; 0x74
huart->TxISR = NULL;
8003350: 687b ldr r3, [r7, #4]
8003352: 2200 movs r2, #0
8003354: 679a str r2, [r3, #120] ; 0x78
return ret;
8003356: 231a movs r3, #26
8003358: 18fb adds r3, r7, r3
800335a: 781b ldrb r3, [r3, #0]
}
800335c: 0018 movs r0, r3
800335e: 46bd mov sp, r7
8003360: b008 add sp, #32
8003362: bd80 pop {r7, pc}
8003364: cfff69f3 .word 0xcfff69f3
8003368: ffffcfff .word 0xffffcfff
800336c: 11fff4ff .word 0x11fff4ff
8003370: 40013800 .word 0x40013800
8003374: 40021000 .word 0x40021000
8003378: 40004400 .word 0x40004400
800337c: 40004800 .word 0x40004800
8003380: 40004c00 .word 0x40004c00
8003384: 00f42400 .word 0x00f42400
8003388: 08003844 .word 0x08003844
0800338c <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
800338c: b580 push {r7, lr}
800338e: b082 sub sp, #8
8003390: af00 add r7, sp, #0
8003392: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8003394: 687b ldr r3, [r7, #4]
8003396: 6a9b ldr r3, [r3, #40] ; 0x28
8003398: 2201 movs r2, #1
800339a: 4013 ands r3, r2
800339c: d00b beq.n 80033b6 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
800339e: 687b ldr r3, [r7, #4]
80033a0: 681b ldr r3, [r3, #0]
80033a2: 685b ldr r3, [r3, #4]
80033a4: 4a4a ldr r2, [pc, #296] ; (80034d0 <UART_AdvFeatureConfig+0x144>)
80033a6: 4013 ands r3, r2
80033a8: 0019 movs r1, r3
80033aa: 687b ldr r3, [r7, #4]
80033ac: 6ada ldr r2, [r3, #44] ; 0x2c
80033ae: 687b ldr r3, [r7, #4]
80033b0: 681b ldr r3, [r3, #0]
80033b2: 430a orrs r2, r1
80033b4: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
80033b6: 687b ldr r3, [r7, #4]
80033b8: 6a9b ldr r3, [r3, #40] ; 0x28
80033ba: 2202 movs r2, #2
80033bc: 4013 ands r3, r2
80033be: d00b beq.n 80033d8 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
80033c0: 687b ldr r3, [r7, #4]
80033c2: 681b ldr r3, [r3, #0]
80033c4: 685b ldr r3, [r3, #4]
80033c6: 4a43 ldr r2, [pc, #268] ; (80034d4 <UART_AdvFeatureConfig+0x148>)
80033c8: 4013 ands r3, r2
80033ca: 0019 movs r1, r3
80033cc: 687b ldr r3, [r7, #4]
80033ce: 6b1a ldr r2, [r3, #48] ; 0x30
80033d0: 687b ldr r3, [r7, #4]
80033d2: 681b ldr r3, [r3, #0]
80033d4: 430a orrs r2, r1
80033d6: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
80033d8: 687b ldr r3, [r7, #4]
80033da: 6a9b ldr r3, [r3, #40] ; 0x28
80033dc: 2204 movs r2, #4
80033de: 4013 ands r3, r2
80033e0: d00b beq.n 80033fa <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
80033e2: 687b ldr r3, [r7, #4]
80033e4: 681b ldr r3, [r3, #0]
80033e6: 685b ldr r3, [r3, #4]
80033e8: 4a3b ldr r2, [pc, #236] ; (80034d8 <UART_AdvFeatureConfig+0x14c>)
80033ea: 4013 ands r3, r2
80033ec: 0019 movs r1, r3
80033ee: 687b ldr r3, [r7, #4]
80033f0: 6b5a ldr r2, [r3, #52] ; 0x34
80033f2: 687b ldr r3, [r7, #4]
80033f4: 681b ldr r3, [r3, #0]
80033f6: 430a orrs r2, r1
80033f8: 605a str r2, [r3, #4]
}
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
80033fa: 687b ldr r3, [r7, #4]
80033fc: 6a9b ldr r3, [r3, #40] ; 0x28
80033fe: 2208 movs r2, #8
8003400: 4013 ands r3, r2
8003402: d00b beq.n 800341c <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8003404: 687b ldr r3, [r7, #4]
8003406: 681b ldr r3, [r3, #0]
8003408: 685b ldr r3, [r3, #4]
800340a: 4a34 ldr r2, [pc, #208] ; (80034dc <UART_AdvFeatureConfig+0x150>)
800340c: 4013 ands r3, r2
800340e: 0019 movs r1, r3
8003410: 687b ldr r3, [r7, #4]
8003412: 6b9a ldr r2, [r3, #56] ; 0x38
8003414: 687b ldr r3, [r7, #4]
8003416: 681b ldr r3, [r3, #0]
8003418: 430a orrs r2, r1
800341a: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
800341c: 687b ldr r3, [r7, #4]
800341e: 6a9b ldr r3, [r3, #40] ; 0x28
8003420: 2210 movs r2, #16
8003422: 4013 ands r3, r2
8003424: d00b beq.n 800343e <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8003426: 687b ldr r3, [r7, #4]
8003428: 681b ldr r3, [r3, #0]
800342a: 689b ldr r3, [r3, #8]
800342c: 4a2c ldr r2, [pc, #176] ; (80034e0 <UART_AdvFeatureConfig+0x154>)
800342e: 4013 ands r3, r2
8003430: 0019 movs r1, r3
8003432: 687b ldr r3, [r7, #4]
8003434: 6bda ldr r2, [r3, #60] ; 0x3c
8003436: 687b ldr r3, [r7, #4]
8003438: 681b ldr r3, [r3, #0]
800343a: 430a orrs r2, r1
800343c: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
800343e: 687b ldr r3, [r7, #4]
8003440: 6a9b ldr r3, [r3, #40] ; 0x28
8003442: 2220 movs r2, #32
8003444: 4013 ands r3, r2
8003446: d00b beq.n 8003460 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
8003448: 687b ldr r3, [r7, #4]
800344a: 681b ldr r3, [r3, #0]
800344c: 689b ldr r3, [r3, #8]
800344e: 4a25 ldr r2, [pc, #148] ; (80034e4 <UART_AdvFeatureConfig+0x158>)
8003450: 4013 ands r3, r2
8003452: 0019 movs r1, r3
8003454: 687b ldr r3, [r7, #4]
8003456: 6c1a ldr r2, [r3, #64] ; 0x40
8003458: 687b ldr r3, [r7, #4]
800345a: 681b ldr r3, [r3, #0]
800345c: 430a orrs r2, r1
800345e: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8003460: 687b ldr r3, [r7, #4]
8003462: 6a9b ldr r3, [r3, #40] ; 0x28
8003464: 2240 movs r2, #64 ; 0x40
8003466: 4013 ands r3, r2
8003468: d01d beq.n 80034a6 <UART_AdvFeatureConfig+0x11a>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
800346a: 687b ldr r3, [r7, #4]
800346c: 681b ldr r3, [r3, #0]
800346e: 685b ldr r3, [r3, #4]
8003470: 4a1d ldr r2, [pc, #116] ; (80034e8 <UART_AdvFeatureConfig+0x15c>)
8003472: 4013 ands r3, r2
8003474: 0019 movs r1, r3
8003476: 687b ldr r3, [r7, #4]
8003478: 6c5a ldr r2, [r3, #68] ; 0x44
800347a: 687b ldr r3, [r7, #4]
800347c: 681b ldr r3, [r3, #0]
800347e: 430a orrs r2, r1
8003480: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8003482: 687b ldr r3, [r7, #4]
8003484: 6c5a ldr r2, [r3, #68] ; 0x44
8003486: 2380 movs r3, #128 ; 0x80
8003488: 035b lsls r3, r3, #13
800348a: 429a cmp r2, r3
800348c: d10b bne.n 80034a6 <UART_AdvFeatureConfig+0x11a>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
800348e: 687b ldr r3, [r7, #4]
8003490: 681b ldr r3, [r3, #0]
8003492: 685b ldr r3, [r3, #4]
8003494: 4a15 ldr r2, [pc, #84] ; (80034ec <UART_AdvFeatureConfig+0x160>)
8003496: 4013 ands r3, r2
8003498: 0019 movs r1, r3
800349a: 687b ldr r3, [r7, #4]
800349c: 6c9a ldr r2, [r3, #72] ; 0x48
800349e: 687b ldr r3, [r7, #4]
80034a0: 681b ldr r3, [r3, #0]
80034a2: 430a orrs r2, r1
80034a4: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
80034a6: 687b ldr r3, [r7, #4]
80034a8: 6a9b ldr r3, [r3, #40] ; 0x28
80034aa: 2280 movs r2, #128 ; 0x80
80034ac: 4013 ands r3, r2
80034ae: d00b beq.n 80034c8 <UART_AdvFeatureConfig+0x13c>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
80034b0: 687b ldr r3, [r7, #4]
80034b2: 681b ldr r3, [r3, #0]
80034b4: 685b ldr r3, [r3, #4]
80034b6: 4a0e ldr r2, [pc, #56] ; (80034f0 <UART_AdvFeatureConfig+0x164>)
80034b8: 4013 ands r3, r2
80034ba: 0019 movs r1, r3
80034bc: 687b ldr r3, [r7, #4]
80034be: 6cda ldr r2, [r3, #76] ; 0x4c
80034c0: 687b ldr r3, [r7, #4]
80034c2: 681b ldr r3, [r3, #0]
80034c4: 430a orrs r2, r1
80034c6: 605a str r2, [r3, #4]
}
}
80034c8: 46c0 nop ; (mov r8, r8)
80034ca: 46bd mov sp, r7
80034cc: b002 add sp, #8
80034ce: bd80 pop {r7, pc}
80034d0: fffdffff .word 0xfffdffff
80034d4: fffeffff .word 0xfffeffff
80034d8: fffbffff .word 0xfffbffff
80034dc: ffff7fff .word 0xffff7fff
80034e0: ffffefff .word 0xffffefff
80034e4: ffffdfff .word 0xffffdfff
80034e8: ffefffff .word 0xffefffff
80034ec: ff9fffff .word 0xff9fffff
80034f0: fff7ffff .word 0xfff7ffff
080034f4 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
80034f4: b580 push {r7, lr}
80034f6: b086 sub sp, #24
80034f8: af02 add r7, sp, #8
80034fa: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80034fc: 687b ldr r3, [r7, #4]
80034fe: 2290 movs r2, #144 ; 0x90
8003500: 2100 movs r1, #0
8003502: 5099 str r1, [r3, r2]
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8003504: f7fd fd08 bl 8000f18 <HAL_GetTick>
8003508: 0003 movs r3, r0
800350a: 60fb str r3, [r7, #12]
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
800350c: 687b ldr r3, [r7, #4]
800350e: 681b ldr r3, [r3, #0]
8003510: 681b ldr r3, [r3, #0]
8003512: 2208 movs r2, #8
8003514: 4013 ands r3, r2
8003516: 2b08 cmp r3, #8
8003518: d10c bne.n 8003534 <UART_CheckIdleState+0x40>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
800351a: 68fb ldr r3, [r7, #12]
800351c: 2280 movs r2, #128 ; 0x80
800351e: 0391 lsls r1, r2, #14
8003520: 6878 ldr r0, [r7, #4]
8003522: 4a1a ldr r2, [pc, #104] ; (800358c <UART_CheckIdleState+0x98>)
8003524: 9200 str r2, [sp, #0]
8003526: 2200 movs r2, #0
8003528: f000 f832 bl 8003590 <UART_WaitOnFlagUntilTimeout>
800352c: 1e03 subs r3, r0, #0
800352e: d001 beq.n 8003534 <UART_CheckIdleState+0x40>
{
/* Timeout occurred */
return HAL_TIMEOUT;
8003530: 2303 movs r3, #3
8003532: e026 b.n 8003582 <UART_CheckIdleState+0x8e>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
8003534: 687b ldr r3, [r7, #4]
8003536: 681b ldr r3, [r3, #0]
8003538: 681b ldr r3, [r3, #0]
800353a: 2204 movs r2, #4
800353c: 4013 ands r3, r2
800353e: 2b04 cmp r3, #4
8003540: d10c bne.n 800355c <UART_CheckIdleState+0x68>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8003542: 68fb ldr r3, [r7, #12]
8003544: 2280 movs r2, #128 ; 0x80
8003546: 03d1 lsls r1, r2, #15
8003548: 6878 ldr r0, [r7, #4]
800354a: 4a10 ldr r2, [pc, #64] ; (800358c <UART_CheckIdleState+0x98>)
800354c: 9200 str r2, [sp, #0]
800354e: 2200 movs r2, #0
8003550: f000 f81e bl 8003590 <UART_WaitOnFlagUntilTimeout>
8003554: 1e03 subs r3, r0, #0
8003556: d001 beq.n 800355c <UART_CheckIdleState+0x68>
{
/* Timeout occurred */
return HAL_TIMEOUT;
8003558: 2303 movs r3, #3
800355a: e012 b.n 8003582 <UART_CheckIdleState+0x8e>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
800355c: 687b ldr r3, [r7, #4]
800355e: 2288 movs r2, #136 ; 0x88
8003560: 2120 movs r1, #32
8003562: 5099 str r1, [r3, r2]
huart->RxState = HAL_UART_STATE_READY;
8003564: 687b ldr r3, [r7, #4]
8003566: 228c movs r2, #140 ; 0x8c
8003568: 2120 movs r1, #32
800356a: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800356c: 687b ldr r3, [r7, #4]
800356e: 2200 movs r2, #0
8003570: 66da str r2, [r3, #108] ; 0x6c
huart->RxEventType = HAL_UART_RXEVENT_TC;
8003572: 687b ldr r3, [r7, #4]
8003574: 2200 movs r2, #0
8003576: 671a str r2, [r3, #112] ; 0x70
__HAL_UNLOCK(huart);
8003578: 687b ldr r3, [r7, #4]
800357a: 2284 movs r2, #132 ; 0x84
800357c: 2100 movs r1, #0
800357e: 5499 strb r1, [r3, r2]
return HAL_OK;
8003580: 2300 movs r3, #0
}
8003582: 0018 movs r0, r3
8003584: 46bd mov sp, r7
8003586: b004 add sp, #16
8003588: bd80 pop {r7, pc}
800358a: 46c0 nop ; (mov r8, r8)
800358c: 01ffffff .word 0x01ffffff
08003590 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8003590: b580 push {r7, lr}
8003592: b094 sub sp, #80 ; 0x50
8003594: af00 add r7, sp, #0
8003596: 60f8 str r0, [r7, #12]
8003598: 60b9 str r1, [r7, #8]
800359a: 603b str r3, [r7, #0]
800359c: 1dfb adds r3, r7, #7
800359e: 701a strb r2, [r3, #0]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80035a0: e0a7 b.n 80036f2 <UART_WaitOnFlagUntilTimeout+0x162>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80035a2: 6dbb ldr r3, [r7, #88] ; 0x58
80035a4: 3301 adds r3, #1
80035a6: d100 bne.n 80035aa <UART_WaitOnFlagUntilTimeout+0x1a>
80035a8: e0a3 b.n 80036f2 <UART_WaitOnFlagUntilTimeout+0x162>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80035aa: f7fd fcb5 bl 8000f18 <HAL_GetTick>
80035ae: 0002 movs r2, r0
80035b0: 683b ldr r3, [r7, #0]
80035b2: 1ad3 subs r3, r2, r3
80035b4: 6dba ldr r2, [r7, #88] ; 0x58
80035b6: 429a cmp r2, r3
80035b8: d302 bcc.n 80035c0 <UART_WaitOnFlagUntilTimeout+0x30>
80035ba: 6dbb ldr r3, [r7, #88] ; 0x58
80035bc: 2b00 cmp r3, #0
80035be: d13f bne.n 8003640 <UART_WaitOnFlagUntilTimeout+0xb0>
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80035c0: f3ef 8310 mrs r3, PRIMASK
80035c4: 62bb str r3, [r7, #40] ; 0x28
return(result);
80035c6: 6abb ldr r3, [r7, #40] ; 0x28
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
80035c8: 647b str r3, [r7, #68] ; 0x44
80035ca: 2301 movs r3, #1
80035cc: 62fb str r3, [r7, #44] ; 0x2c
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80035ce: 6afb ldr r3, [r7, #44] ; 0x2c
80035d0: f383 8810 msr PRIMASK, r3
}
80035d4: 46c0 nop ; (mov r8, r8)
80035d6: 68fb ldr r3, [r7, #12]
80035d8: 681b ldr r3, [r3, #0]
80035da: 681a ldr r2, [r3, #0]
80035dc: 68fb ldr r3, [r7, #12]
80035de: 681b ldr r3, [r3, #0]
80035e0: 494e ldr r1, [pc, #312] ; (800371c <UART_WaitOnFlagUntilTimeout+0x18c>)
80035e2: 400a ands r2, r1
80035e4: 601a str r2, [r3, #0]
80035e6: 6c7b ldr r3, [r7, #68] ; 0x44
80035e8: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80035ea: 6b3b ldr r3, [r7, #48] ; 0x30
80035ec: f383 8810 msr PRIMASK, r3
}
80035f0: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80035f2: f3ef 8310 mrs r3, PRIMASK
80035f6: 637b str r3, [r7, #52] ; 0x34
return(result);
80035f8: 6b7b ldr r3, [r7, #52] ; 0x34
USART_CR1_TXEIE_TXFNFIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80035fa: 643b str r3, [r7, #64] ; 0x40
80035fc: 2301 movs r3, #1
80035fe: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8003600: 6bbb ldr r3, [r7, #56] ; 0x38
8003602: f383 8810 msr PRIMASK, r3
}
8003606: 46c0 nop ; (mov r8, r8)
8003608: 68fb ldr r3, [r7, #12]
800360a: 681b ldr r3, [r3, #0]
800360c: 689a ldr r2, [r3, #8]
800360e: 68fb ldr r3, [r7, #12]
8003610: 681b ldr r3, [r3, #0]
8003612: 2101 movs r1, #1
8003614: 438a bics r2, r1
8003616: 609a str r2, [r3, #8]
8003618: 6c3b ldr r3, [r7, #64] ; 0x40
800361a: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800361c: 6bfb ldr r3, [r7, #60] ; 0x3c
800361e: f383 8810 msr PRIMASK, r3
}
8003622: 46c0 nop ; (mov r8, r8)
huart->gState = HAL_UART_STATE_READY;
8003624: 68fb ldr r3, [r7, #12]
8003626: 2288 movs r2, #136 ; 0x88
8003628: 2120 movs r1, #32
800362a: 5099 str r1, [r3, r2]
huart->RxState = HAL_UART_STATE_READY;
800362c: 68fb ldr r3, [r7, #12]
800362e: 228c movs r2, #140 ; 0x8c
8003630: 2120 movs r1, #32
8003632: 5099 str r1, [r3, r2]
__HAL_UNLOCK(huart);
8003634: 68fb ldr r3, [r7, #12]
8003636: 2284 movs r2, #132 ; 0x84
8003638: 2100 movs r1, #0
800363a: 5499 strb r1, [r3, r2]
return HAL_TIMEOUT;
800363c: 2303 movs r3, #3
800363e: e069 b.n 8003714 <UART_WaitOnFlagUntilTimeout+0x184>
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
8003640: 68fb ldr r3, [r7, #12]
8003642: 681b ldr r3, [r3, #0]
8003644: 681b ldr r3, [r3, #0]
8003646: 2204 movs r2, #4
8003648: 4013 ands r3, r2
800364a: d052 beq.n 80036f2 <UART_WaitOnFlagUntilTimeout+0x162>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
800364c: 68fb ldr r3, [r7, #12]
800364e: 681b ldr r3, [r3, #0]
8003650: 69da ldr r2, [r3, #28]
8003652: 2380 movs r3, #128 ; 0x80
8003654: 011b lsls r3, r3, #4
8003656: 401a ands r2, r3
8003658: 2380 movs r3, #128 ; 0x80
800365a: 011b lsls r3, r3, #4
800365c: 429a cmp r2, r3
800365e: d148 bne.n 80036f2 <UART_WaitOnFlagUntilTimeout+0x162>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8003660: 68fb ldr r3, [r7, #12]
8003662: 681b ldr r3, [r3, #0]
8003664: 2280 movs r2, #128 ; 0x80
8003666: 0112 lsls r2, r2, #4
8003668: 621a str r2, [r3, #32]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
800366a: f3ef 8310 mrs r3, PRIMASK
800366e: 613b str r3, [r7, #16]
return(result);
8003670: 693b ldr r3, [r7, #16]
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
8003672: 64fb str r3, [r7, #76] ; 0x4c
8003674: 2301 movs r3, #1
8003676: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8003678: 697b ldr r3, [r7, #20]
800367a: f383 8810 msr PRIMASK, r3
}
800367e: 46c0 nop ; (mov r8, r8)
8003680: 68fb ldr r3, [r7, #12]
8003682: 681b ldr r3, [r3, #0]
8003684: 681a ldr r2, [r3, #0]
8003686: 68fb ldr r3, [r7, #12]
8003688: 681b ldr r3, [r3, #0]
800368a: 4924 ldr r1, [pc, #144] ; (800371c <UART_WaitOnFlagUntilTimeout+0x18c>)
800368c: 400a ands r2, r1
800368e: 601a str r2, [r3, #0]
8003690: 6cfb ldr r3, [r7, #76] ; 0x4c
8003692: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8003694: 69bb ldr r3, [r7, #24]
8003696: f383 8810 msr PRIMASK, r3
}
800369a: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
800369c: f3ef 8310 mrs r3, PRIMASK
80036a0: 61fb str r3, [r7, #28]
return(result);
80036a2: 69fb ldr r3, [r7, #28]
USART_CR1_TXEIE_TXFNFIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80036a4: 64bb str r3, [r7, #72] ; 0x48
80036a6: 2301 movs r3, #1
80036a8: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80036aa: 6a3b ldr r3, [r7, #32]
80036ac: f383 8810 msr PRIMASK, r3
}
80036b0: 46c0 nop ; (mov r8, r8)
80036b2: 68fb ldr r3, [r7, #12]
80036b4: 681b ldr r3, [r3, #0]
80036b6: 689a ldr r2, [r3, #8]
80036b8: 68fb ldr r3, [r7, #12]
80036ba: 681b ldr r3, [r3, #0]
80036bc: 2101 movs r1, #1
80036be: 438a bics r2, r1
80036c0: 609a str r2, [r3, #8]
80036c2: 6cbb ldr r3, [r7, #72] ; 0x48
80036c4: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80036c6: 6a7b ldr r3, [r7, #36] ; 0x24
80036c8: f383 8810 msr PRIMASK, r3
}
80036cc: 46c0 nop ; (mov r8, r8)
huart->gState = HAL_UART_STATE_READY;
80036ce: 68fb ldr r3, [r7, #12]
80036d0: 2288 movs r2, #136 ; 0x88
80036d2: 2120 movs r1, #32
80036d4: 5099 str r1, [r3, r2]
huart->RxState = HAL_UART_STATE_READY;
80036d6: 68fb ldr r3, [r7, #12]
80036d8: 228c movs r2, #140 ; 0x8c
80036da: 2120 movs r1, #32
80036dc: 5099 str r1, [r3, r2]
huart->ErrorCode = HAL_UART_ERROR_RTO;
80036de: 68fb ldr r3, [r7, #12]
80036e0: 2290 movs r2, #144 ; 0x90
80036e2: 2120 movs r1, #32
80036e4: 5099 str r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(huart);
80036e6: 68fb ldr r3, [r7, #12]
80036e8: 2284 movs r2, #132 ; 0x84
80036ea: 2100 movs r1, #0
80036ec: 5499 strb r1, [r3, r2]
return HAL_TIMEOUT;
80036ee: 2303 movs r3, #3
80036f0: e010 b.n 8003714 <UART_WaitOnFlagUntilTimeout+0x184>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80036f2: 68fb ldr r3, [r7, #12]
80036f4: 681b ldr r3, [r3, #0]
80036f6: 69db ldr r3, [r3, #28]
80036f8: 68ba ldr r2, [r7, #8]
80036fa: 4013 ands r3, r2
80036fc: 68ba ldr r2, [r7, #8]
80036fe: 1ad3 subs r3, r2, r3
8003700: 425a negs r2, r3
8003702: 4153 adcs r3, r2
8003704: b2db uxtb r3, r3
8003706: 001a movs r2, r3
8003708: 1dfb adds r3, r7, #7
800370a: 781b ldrb r3, [r3, #0]
800370c: 429a cmp r2, r3
800370e: d100 bne.n 8003712 <UART_WaitOnFlagUntilTimeout+0x182>
8003710: e747 b.n 80035a2 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8003712: 2300 movs r3, #0
}
8003714: 0018 movs r0, r3
8003716: 46bd mov sp, r7
8003718: b014 add sp, #80 ; 0x50
800371a: bd80 pop {r7, pc}
800371c: fffffe5f .word 0xfffffe5f
08003720 <__libc_init_array>:
8003720: b570 push {r4, r5, r6, lr}
8003722: 2600 movs r6, #0
8003724: 4d0c ldr r5, [pc, #48] ; (8003758 <__libc_init_array+0x38>)
8003726: 4c0d ldr r4, [pc, #52] ; (800375c <__libc_init_array+0x3c>)
8003728: 1b64 subs r4, r4, r5
800372a: 10a4 asrs r4, r4, #2
800372c: 42a6 cmp r6, r4
800372e: d109 bne.n 8003744 <__libc_init_array+0x24>
8003730: 2600 movs r6, #0
8003732: f000 f821 bl 8003778 <_init>
8003736: 4d0a ldr r5, [pc, #40] ; (8003760 <__libc_init_array+0x40>)
8003738: 4c0a ldr r4, [pc, #40] ; (8003764 <__libc_init_array+0x44>)
800373a: 1b64 subs r4, r4, r5
800373c: 10a4 asrs r4, r4, #2
800373e: 42a6 cmp r6, r4
8003740: d105 bne.n 800374e <__libc_init_array+0x2e>
8003742: bd70 pop {r4, r5, r6, pc}
8003744: 00b3 lsls r3, r6, #2
8003746: 58eb ldr r3, [r5, r3]
8003748: 4798 blx r3
800374a: 3601 adds r6, #1
800374c: e7ee b.n 800372c <__libc_init_array+0xc>
800374e: 00b3 lsls r3, r6, #2
8003750: 58eb ldr r3, [r5, r3]
8003752: 4798 blx r3
8003754: 3601 adds r6, #1
8003756: e7f2 b.n 800373e <__libc_init_array+0x1e>
8003758: 0800385c .word 0x0800385c
800375c: 0800385c .word 0x0800385c
8003760: 0800385c .word 0x0800385c
8003764: 08003860 .word 0x08003860
08003768 <memset>:
8003768: 0003 movs r3, r0
800376a: 1882 adds r2, r0, r2
800376c: 4293 cmp r3, r2
800376e: d100 bne.n 8003772 <memset+0xa>
8003770: 4770 bx lr
8003772: 7019 strb r1, [r3, #0]
8003774: 3301 adds r3, #1
8003776: e7f9 b.n 800376c <memset+0x4>
08003778 <_init>:
8003778: b5f8 push {r3, r4, r5, r6, r7, lr}
800377a: 46c0 nop ; (mov r8, r8)
800377c: bcf8 pop {r3, r4, r5, r6, r7}
800377e: bc08 pop {r3}
8003780: 469e mov lr, r3
8003782: 4770 bx lr
08003784 <_fini>:
8003784: b5f8 push {r3, r4, r5, r6, r7, lr}
8003786: 46c0 nop ; (mov r8, r8)
8003788: bcf8 pop {r3, r4, r5, r6, r7}
800378a: bc08 pop {r3}
800378c: 469e mov lr, r3
800378e: 4770 bx lr
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