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Lorence
2023-09-01 17:16:20 +08:00
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1.PCB_Project/DHO800_BatteryPack_IP5389_V1.1_Realse/DHO800_BatteryPack_IP5389_V1.1.PrjPcb Normal file
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1.PCB_Project/DHO800_BatteryPack_IP5389_V1.1_Realse/Project Outputs for DHO800_Battery_Pack_IP5389_V1.1/Design Rule Check - PCB.drc Normal file
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Protel Design System Design Rule Check
PCB File : G:\<5C>ĵ<EFBFBD>\2023\DHO800\Realse\DHO800_Battery_Pack_IP5389_V1.1_Realse\PCB.PcbDoc
Date : 1/9/2023
Time : <20><><EFBFBD><EFBFBD> 2:37:31
Processing Rule : Clearance Constraint (Gap=4mil) (All),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=8mil) (Max=500mil) (Preferred=10mil) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=1mil) (Max=500mil) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0mil) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0mil) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0mil) (IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0mil) (All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0
Violations Detected : 0
Waived Violations : 0
Time Elapsed : 00:00:02

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1.PCB_Project/DHO800_BatteryPack_IP5389_V1.1_Realse/Project Outputs for DHO800_Battery_Pack_IP5389_V1.1/Design Rule Check - PCB.html Normal file
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</script><title>Design Rule Verification Report</title>
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<body onload=""><img ALT="Altium" src="
file://C:\Users\Public\Documents\Altium\AD21\Templates\AD_logo.png
"><h1>Design Rule Verification Report</h1>
<table class="header_holder">
<td class="column1">
<table class="front_matter">
<tr class="front_matter">
<td class="front_matter_column1">Date:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">1/9/2023</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3"><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 2:37:31</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Elapsed Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">00:00:02</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Filename:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3"><a href="file:///G:\%E6%96%87%E6%A1%A3\2023\DHO800\Realse\DHO800_Battery_Pack_IP5389_V1.1_Realse\PCB.PcbDoc" class="file"><acronym title="G:\<5C>ĵ<EFBFBD>\2023\DHO800\Realse\DHO800_Battery_Pack_IP5389_V1.1_Realse\PCB.PcbDoc">G:\<5C>ĵ<EFBFBD>\2023\DHO800\Realse\DHO800_Battery_Pack_IP5389_V1.1_Realse\PCB.PcbDoc</acronym></a></td>
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<td class="DRC_summary_header_col1">Warnings:</td>
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<td class="DRC_summary_header_col3">0</td></tr>
<tr>
<td class="DRC_summary_header_col1">Rule Violations:</td>
<td class="DRC_summary_header_col2"></td>
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</table><a name="IDAB3B2SZG1GXVE44WUM0WV2MG1BJXRFFIROKGLRF3AZWLQEC4PJXN"><h2>Summary</h2></a><table>
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<th class="column1">Warnings</th>
<th class="column2">Count</th>
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<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
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<tr>
<th class="column1">Rule Violations</th>
<th class="column2">Count</th>
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<td class="column1"><a href="#IDVSCP4ZLBIOKMCWZVVXMEWOVF1PNG35IIOKLMNV2SD4X2ABFHXHD">Clearance Constraint (Gap=4mil) (All),(All)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#ID4SQ2ZEO0RKZNG2QXD4W5THPBT0YB1PMN0XZJREHE5TFM0O4KNFH">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
<td class="column2">0</td>
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<td class="column2">0</td>
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