18259 lines
667 KiB
Plaintext
18259 lines
667 KiB
Plaintext
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DiLight.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000000bc 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 000066e8 080000c0 080000c0 000100c0 2**3
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 000000d4 080067a8 080067a8 000167a8 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 0800687c 0800687c 00020098 2**0
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CONTENTS
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4 .ARM 00000000 0800687c 0800687c 00020098 2**0
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CONTENTS
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5 .preinit_array 00000000 0800687c 0800687c 00020098 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 0800687c 0800687c 0001687c 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .fini_array 00000004 08006880 08006880 00016880 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .data 00000098 20000000 08006884 00020000 2**2
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CONTENTS, ALLOC, LOAD, CODE
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9 .bss 000001cc 20000098 0800691c 00020098 2**3
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ALLOC
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10 ._user_heap_stack 00000604 20000264 0800691c 00020264 2**0
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ALLOC
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11 .ARM.attributes 00000028 00000000 00000000 00020098 2**0
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CONTENTS, READONLY
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12 .debug_info 000112c0 00000000 00000000 000200c0 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00002b9b 00000000 00000000 00031380 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00001138 00000000 00000000 00033f20 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_ranges 00001000 00000000 00000000 00035058 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00017358 00000000 00000000 00036058 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 00013e1a 00000000 00000000 0004d3b0 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 0009247c 00000000 00000000 000611ca 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000050 00000000 00000000 000f3646 2**0
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CONTENTS, READONLY
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20 .debug_frame 00004038 00000000 00000000 000f3698 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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080000c0 <__do_global_dtors_aux>:
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80000c0: b510 push {r4, lr}
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80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
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80000c4: 7823 ldrb r3, [r4, #0]
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80000c6: 2b00 cmp r3, #0
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80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
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80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
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80000cc: 2b00 cmp r3, #0
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80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
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80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
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80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
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80000d4: bf00 nop
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80000d6: 2301 movs r3, #1
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80000d8: 7023 strb r3, [r4, #0]
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80000da: bd10 pop {r4, pc}
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80000dc: 20000098 .word 0x20000098
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80000e0: 00000000 .word 0x00000000
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80000e4: 08006780 .word 0x08006780
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080000e8 <frame_dummy>:
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80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc <frame_dummy+0x14>)
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80000ea: b510 push {r4, lr}
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80000ec: 2b00 cmp r3, #0
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80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
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80000f0: 4903 ldr r1, [pc, #12] ; (8000100 <frame_dummy+0x18>)
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80000f2: 4804 ldr r0, [pc, #16] ; (8000104 <frame_dummy+0x1c>)
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80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
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80000f6: bf00 nop
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80000f8: bd10 pop {r4, pc}
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80000fa: 46c0 nop ; (mov r8, r8)
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80000fc: 00000000 .word 0x00000000
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8000100: 2000009c .word 0x2000009c
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8000104: 08006780 .word 0x08006780
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08000108 <__udivsi3>:
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8000108: 2200 movs r2, #0
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800010a: 0843 lsrs r3, r0, #1
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800010c: 428b cmp r3, r1
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800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
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8000110: 0903 lsrs r3, r0, #4
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8000112: 428b cmp r3, r1
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8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
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8000116: 0a03 lsrs r3, r0, #8
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8000118: 428b cmp r3, r1
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800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
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800011c: 0b03 lsrs r3, r0, #12
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800011e: 428b cmp r3, r1
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8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
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8000122: 0c03 lsrs r3, r0, #16
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8000124: 428b cmp r3, r1
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8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
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8000128: 22ff movs r2, #255 ; 0xff
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800012a: 0209 lsls r1, r1, #8
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800012c: ba12 rev r2, r2
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800012e: 0c03 lsrs r3, r0, #16
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8000130: 428b cmp r3, r1
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8000132: d302 bcc.n 800013a <__udivsi3+0x32>
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8000134: 1212 asrs r2, r2, #8
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8000136: 0209 lsls r1, r1, #8
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8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
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800013a: 0b03 lsrs r3, r0, #12
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800013c: 428b cmp r3, r1
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800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
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8000140: e000 b.n 8000144 <__udivsi3+0x3c>
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8000142: 0a09 lsrs r1, r1, #8
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8000144: 0bc3 lsrs r3, r0, #15
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8000146: 428b cmp r3, r1
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8000148: d301 bcc.n 800014e <__udivsi3+0x46>
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800014a: 03cb lsls r3, r1, #15
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800014c: 1ac0 subs r0, r0, r3
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800014e: 4152 adcs r2, r2
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8000150: 0b83 lsrs r3, r0, #14
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8000152: 428b cmp r3, r1
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8000154: d301 bcc.n 800015a <__udivsi3+0x52>
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8000156: 038b lsls r3, r1, #14
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8000158: 1ac0 subs r0, r0, r3
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800015a: 4152 adcs r2, r2
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800015c: 0b43 lsrs r3, r0, #13
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800015e: 428b cmp r3, r1
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8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
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8000162: 034b lsls r3, r1, #13
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8000164: 1ac0 subs r0, r0, r3
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8000166: 4152 adcs r2, r2
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8000168: 0b03 lsrs r3, r0, #12
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800016a: 428b cmp r3, r1
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800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
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800016e: 030b lsls r3, r1, #12
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8000170: 1ac0 subs r0, r0, r3
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8000172: 4152 adcs r2, r2
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8000174: 0ac3 lsrs r3, r0, #11
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8000176: 428b cmp r3, r1
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8000178: d301 bcc.n 800017e <__udivsi3+0x76>
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800017a: 02cb lsls r3, r1, #11
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800017c: 1ac0 subs r0, r0, r3
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800017e: 4152 adcs r2, r2
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8000180: 0a83 lsrs r3, r0, #10
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8000182: 428b cmp r3, r1
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8000184: d301 bcc.n 800018a <__udivsi3+0x82>
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8000186: 028b lsls r3, r1, #10
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8000188: 1ac0 subs r0, r0, r3
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800018a: 4152 adcs r2, r2
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800018c: 0a43 lsrs r3, r0, #9
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800018e: 428b cmp r3, r1
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8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
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8000192: 024b lsls r3, r1, #9
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8000194: 1ac0 subs r0, r0, r3
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8000196: 4152 adcs r2, r2
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8000198: 0a03 lsrs r3, r0, #8
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800019a: 428b cmp r3, r1
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800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
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800019e: 020b lsls r3, r1, #8
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80001a0: 1ac0 subs r0, r0, r3
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80001a2: 4152 adcs r2, r2
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80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
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80001a6: 09c3 lsrs r3, r0, #7
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80001a8: 428b cmp r3, r1
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80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
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80001ac: 01cb lsls r3, r1, #7
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80001ae: 1ac0 subs r0, r0, r3
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80001b0: 4152 adcs r2, r2
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80001b2: 0983 lsrs r3, r0, #6
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80001b4: 428b cmp r3, r1
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80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
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80001b8: 018b lsls r3, r1, #6
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80001ba: 1ac0 subs r0, r0, r3
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80001bc: 4152 adcs r2, r2
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80001be: 0943 lsrs r3, r0, #5
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80001c0: 428b cmp r3, r1
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80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
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80001c4: 014b lsls r3, r1, #5
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80001c6: 1ac0 subs r0, r0, r3
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80001c8: 4152 adcs r2, r2
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80001ca: 0903 lsrs r3, r0, #4
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80001cc: 428b cmp r3, r1
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80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
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80001d0: 010b lsls r3, r1, #4
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80001d2: 1ac0 subs r0, r0, r3
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80001d4: 4152 adcs r2, r2
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80001d6: 08c3 lsrs r3, r0, #3
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80001d8: 428b cmp r3, r1
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80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
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80001dc: 00cb lsls r3, r1, #3
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80001de: 1ac0 subs r0, r0, r3
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80001e0: 4152 adcs r2, r2
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80001e2: 0883 lsrs r3, r0, #2
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80001e4: 428b cmp r3, r1
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80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
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80001e8: 008b lsls r3, r1, #2
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80001ea: 1ac0 subs r0, r0, r3
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80001ec: 4152 adcs r2, r2
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80001ee: 0843 lsrs r3, r0, #1
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80001f0: 428b cmp r3, r1
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80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
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80001f4: 004b lsls r3, r1, #1
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80001f6: 1ac0 subs r0, r0, r3
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80001f8: 4152 adcs r2, r2
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80001fa: 1a41 subs r1, r0, r1
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80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
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80001fe: 4601 mov r1, r0
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8000200: 4152 adcs r2, r2
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8000202: 4610 mov r0, r2
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8000204: 4770 bx lr
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8000206: e7ff b.n 8000208 <__udivsi3+0x100>
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8000208: b501 push {r0, lr}
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800020a: 2000 movs r0, #0
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800020c: f000 f8f0 bl 80003f0 <__aeabi_idiv0>
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8000210: bd02 pop {r1, pc}
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8000212: 46c0 nop ; (mov r8, r8)
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08000214 <__aeabi_uidivmod>:
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8000214: 2900 cmp r1, #0
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8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
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8000218: e776 b.n 8000108 <__udivsi3>
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800021a: 4770 bx lr
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0800021c <__divsi3>:
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800021c: 4603 mov r3, r0
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800021e: 430b orrs r3, r1
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8000220: d47f bmi.n 8000322 <__divsi3+0x106>
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8000222: 2200 movs r2, #0
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8000224: 0843 lsrs r3, r0, #1
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8000226: 428b cmp r3, r1
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8000228: d374 bcc.n 8000314 <__divsi3+0xf8>
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800022a: 0903 lsrs r3, r0, #4
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800022c: 428b cmp r3, r1
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800022e: d35f bcc.n 80002f0 <__divsi3+0xd4>
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8000230: 0a03 lsrs r3, r0, #8
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8000232: 428b cmp r3, r1
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8000234: d344 bcc.n 80002c0 <__divsi3+0xa4>
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8000236: 0b03 lsrs r3, r0, #12
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8000238: 428b cmp r3, r1
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800023a: d328 bcc.n 800028e <__divsi3+0x72>
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800023c: 0c03 lsrs r3, r0, #16
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800023e: 428b cmp r3, r1
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8000240: d30d bcc.n 800025e <__divsi3+0x42>
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8000242: 22ff movs r2, #255 ; 0xff
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8000244: 0209 lsls r1, r1, #8
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8000246: ba12 rev r2, r2
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8000248: 0c03 lsrs r3, r0, #16
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800024a: 428b cmp r3, r1
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800024c: d302 bcc.n 8000254 <__divsi3+0x38>
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800024e: 1212 asrs r2, r2, #8
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8000250: 0209 lsls r1, r1, #8
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8000252: d065 beq.n 8000320 <__divsi3+0x104>
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8000254: 0b03 lsrs r3, r0, #12
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8000256: 428b cmp r3, r1
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8000258: d319 bcc.n 800028e <__divsi3+0x72>
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800025a: e000 b.n 800025e <__divsi3+0x42>
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800025c: 0a09 lsrs r1, r1, #8
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800025e: 0bc3 lsrs r3, r0, #15
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8000260: 428b cmp r3, r1
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8000262: d301 bcc.n 8000268 <__divsi3+0x4c>
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8000264: 03cb lsls r3, r1, #15
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8000266: 1ac0 subs r0, r0, r3
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8000268: 4152 adcs r2, r2
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800026a: 0b83 lsrs r3, r0, #14
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800026c: 428b cmp r3, r1
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800026e: d301 bcc.n 8000274 <__divsi3+0x58>
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8000270: 038b lsls r3, r1, #14
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8000272: 1ac0 subs r0, r0, r3
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8000274: 4152 adcs r2, r2
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8000276: 0b43 lsrs r3, r0, #13
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8000278: 428b cmp r3, r1
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800027a: d301 bcc.n 8000280 <__divsi3+0x64>
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800027c: 034b lsls r3, r1, #13
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800027e: 1ac0 subs r0, r0, r3
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8000280: 4152 adcs r2, r2
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8000282: 0b03 lsrs r3, r0, #12
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8000284: 428b cmp r3, r1
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8000286: d301 bcc.n 800028c <__divsi3+0x70>
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8000288: 030b lsls r3, r1, #12
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800028a: 1ac0 subs r0, r0, r3
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800028c: 4152 adcs r2, r2
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800028e: 0ac3 lsrs r3, r0, #11
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8000290: 428b cmp r3, r1
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8000292: d301 bcc.n 8000298 <__divsi3+0x7c>
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8000294: 02cb lsls r3, r1, #11
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8000296: 1ac0 subs r0, r0, r3
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8000298: 4152 adcs r2, r2
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800029a: 0a83 lsrs r3, r0, #10
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800029c: 428b cmp r3, r1
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800029e: d301 bcc.n 80002a4 <__divsi3+0x88>
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80002a0: 028b lsls r3, r1, #10
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80002a2: 1ac0 subs r0, r0, r3
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80002a4: 4152 adcs r2, r2
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80002a6: 0a43 lsrs r3, r0, #9
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80002a8: 428b cmp r3, r1
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80002aa: d301 bcc.n 80002b0 <__divsi3+0x94>
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80002ac: 024b lsls r3, r1, #9
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80002ae: 1ac0 subs r0, r0, r3
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80002b0: 4152 adcs r2, r2
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80002b2: 0a03 lsrs r3, r0, #8
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80002b4: 428b cmp r3, r1
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80002b6: d301 bcc.n 80002bc <__divsi3+0xa0>
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80002b8: 020b lsls r3, r1, #8
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80002ba: 1ac0 subs r0, r0, r3
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80002bc: 4152 adcs r2, r2
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80002be: d2cd bcs.n 800025c <__divsi3+0x40>
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80002c0: 09c3 lsrs r3, r0, #7
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80002c2: 428b cmp r3, r1
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80002c4: d301 bcc.n 80002ca <__divsi3+0xae>
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80002c6: 01cb lsls r3, r1, #7
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80002c8: 1ac0 subs r0, r0, r3
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80002ca: 4152 adcs r2, r2
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80002cc: 0983 lsrs r3, r0, #6
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80002ce: 428b cmp r3, r1
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80002d0: d301 bcc.n 80002d6 <__divsi3+0xba>
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80002d2: 018b lsls r3, r1, #6
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80002d4: 1ac0 subs r0, r0, r3
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80002d6: 4152 adcs r2, r2
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80002d8: 0943 lsrs r3, r0, #5
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80002da: 428b cmp r3, r1
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80002dc: d301 bcc.n 80002e2 <__divsi3+0xc6>
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80002de: 014b lsls r3, r1, #5
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80002e0: 1ac0 subs r0, r0, r3
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80002e2: 4152 adcs r2, r2
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80002e4: 0903 lsrs r3, r0, #4
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80002e6: 428b cmp r3, r1
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80002e8: d301 bcc.n 80002ee <__divsi3+0xd2>
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80002ea: 010b lsls r3, r1, #4
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80002ec: 1ac0 subs r0, r0, r3
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80002ee: 4152 adcs r2, r2
|
|
80002f0: 08c3 lsrs r3, r0, #3
|
|
80002f2: 428b cmp r3, r1
|
|
80002f4: d301 bcc.n 80002fa <__divsi3+0xde>
|
|
80002f6: 00cb lsls r3, r1, #3
|
|
80002f8: 1ac0 subs r0, r0, r3
|
|
80002fa: 4152 adcs r2, r2
|
|
80002fc: 0883 lsrs r3, r0, #2
|
|
80002fe: 428b cmp r3, r1
|
|
8000300: d301 bcc.n 8000306 <__divsi3+0xea>
|
|
8000302: 008b lsls r3, r1, #2
|
|
8000304: 1ac0 subs r0, r0, r3
|
|
8000306: 4152 adcs r2, r2
|
|
8000308: 0843 lsrs r3, r0, #1
|
|
800030a: 428b cmp r3, r1
|
|
800030c: d301 bcc.n 8000312 <__divsi3+0xf6>
|
|
800030e: 004b lsls r3, r1, #1
|
|
8000310: 1ac0 subs r0, r0, r3
|
|
8000312: 4152 adcs r2, r2
|
|
8000314: 1a41 subs r1, r0, r1
|
|
8000316: d200 bcs.n 800031a <__divsi3+0xfe>
|
|
8000318: 4601 mov r1, r0
|
|
800031a: 4152 adcs r2, r2
|
|
800031c: 4610 mov r0, r2
|
|
800031e: 4770 bx lr
|
|
8000320: e05d b.n 80003de <__divsi3+0x1c2>
|
|
8000322: 0fca lsrs r2, r1, #31
|
|
8000324: d000 beq.n 8000328 <__divsi3+0x10c>
|
|
8000326: 4249 negs r1, r1
|
|
8000328: 1003 asrs r3, r0, #32
|
|
800032a: d300 bcc.n 800032e <__divsi3+0x112>
|
|
800032c: 4240 negs r0, r0
|
|
800032e: 4053 eors r3, r2
|
|
8000330: 2200 movs r2, #0
|
|
8000332: 469c mov ip, r3
|
|
8000334: 0903 lsrs r3, r0, #4
|
|
8000336: 428b cmp r3, r1
|
|
8000338: d32d bcc.n 8000396 <__divsi3+0x17a>
|
|
800033a: 0a03 lsrs r3, r0, #8
|
|
800033c: 428b cmp r3, r1
|
|
800033e: d312 bcc.n 8000366 <__divsi3+0x14a>
|
|
8000340: 22fc movs r2, #252 ; 0xfc
|
|
8000342: 0189 lsls r1, r1, #6
|
|
8000344: ba12 rev r2, r2
|
|
8000346: 0a03 lsrs r3, r0, #8
|
|
8000348: 428b cmp r3, r1
|
|
800034a: d30c bcc.n 8000366 <__divsi3+0x14a>
|
|
800034c: 0189 lsls r1, r1, #6
|
|
800034e: 1192 asrs r2, r2, #6
|
|
8000350: 428b cmp r3, r1
|
|
8000352: d308 bcc.n 8000366 <__divsi3+0x14a>
|
|
8000354: 0189 lsls r1, r1, #6
|
|
8000356: 1192 asrs r2, r2, #6
|
|
8000358: 428b cmp r3, r1
|
|
800035a: d304 bcc.n 8000366 <__divsi3+0x14a>
|
|
800035c: 0189 lsls r1, r1, #6
|
|
800035e: d03a beq.n 80003d6 <__divsi3+0x1ba>
|
|
8000360: 1192 asrs r2, r2, #6
|
|
8000362: e000 b.n 8000366 <__divsi3+0x14a>
|
|
8000364: 0989 lsrs r1, r1, #6
|
|
8000366: 09c3 lsrs r3, r0, #7
|
|
8000368: 428b cmp r3, r1
|
|
800036a: d301 bcc.n 8000370 <__divsi3+0x154>
|
|
800036c: 01cb lsls r3, r1, #7
|
|
800036e: 1ac0 subs r0, r0, r3
|
|
8000370: 4152 adcs r2, r2
|
|
8000372: 0983 lsrs r3, r0, #6
|
|
8000374: 428b cmp r3, r1
|
|
8000376: d301 bcc.n 800037c <__divsi3+0x160>
|
|
8000378: 018b lsls r3, r1, #6
|
|
800037a: 1ac0 subs r0, r0, r3
|
|
800037c: 4152 adcs r2, r2
|
|
800037e: 0943 lsrs r3, r0, #5
|
|
8000380: 428b cmp r3, r1
|
|
8000382: d301 bcc.n 8000388 <__divsi3+0x16c>
|
|
8000384: 014b lsls r3, r1, #5
|
|
8000386: 1ac0 subs r0, r0, r3
|
|
8000388: 4152 adcs r2, r2
|
|
800038a: 0903 lsrs r3, r0, #4
|
|
800038c: 428b cmp r3, r1
|
|
800038e: d301 bcc.n 8000394 <__divsi3+0x178>
|
|
8000390: 010b lsls r3, r1, #4
|
|
8000392: 1ac0 subs r0, r0, r3
|
|
8000394: 4152 adcs r2, r2
|
|
8000396: 08c3 lsrs r3, r0, #3
|
|
8000398: 428b cmp r3, r1
|
|
800039a: d301 bcc.n 80003a0 <__divsi3+0x184>
|
|
800039c: 00cb lsls r3, r1, #3
|
|
800039e: 1ac0 subs r0, r0, r3
|
|
80003a0: 4152 adcs r2, r2
|
|
80003a2: 0883 lsrs r3, r0, #2
|
|
80003a4: 428b cmp r3, r1
|
|
80003a6: d301 bcc.n 80003ac <__divsi3+0x190>
|
|
80003a8: 008b lsls r3, r1, #2
|
|
80003aa: 1ac0 subs r0, r0, r3
|
|
80003ac: 4152 adcs r2, r2
|
|
80003ae: d2d9 bcs.n 8000364 <__divsi3+0x148>
|
|
80003b0: 0843 lsrs r3, r0, #1
|
|
80003b2: 428b cmp r3, r1
|
|
80003b4: d301 bcc.n 80003ba <__divsi3+0x19e>
|
|
80003b6: 004b lsls r3, r1, #1
|
|
80003b8: 1ac0 subs r0, r0, r3
|
|
80003ba: 4152 adcs r2, r2
|
|
80003bc: 1a41 subs r1, r0, r1
|
|
80003be: d200 bcs.n 80003c2 <__divsi3+0x1a6>
|
|
80003c0: 4601 mov r1, r0
|
|
80003c2: 4663 mov r3, ip
|
|
80003c4: 4152 adcs r2, r2
|
|
80003c6: 105b asrs r3, r3, #1
|
|
80003c8: 4610 mov r0, r2
|
|
80003ca: d301 bcc.n 80003d0 <__divsi3+0x1b4>
|
|
80003cc: 4240 negs r0, r0
|
|
80003ce: 2b00 cmp r3, #0
|
|
80003d0: d500 bpl.n 80003d4 <__divsi3+0x1b8>
|
|
80003d2: 4249 negs r1, r1
|
|
80003d4: 4770 bx lr
|
|
80003d6: 4663 mov r3, ip
|
|
80003d8: 105b asrs r3, r3, #1
|
|
80003da: d300 bcc.n 80003de <__divsi3+0x1c2>
|
|
80003dc: 4240 negs r0, r0
|
|
80003de: b501 push {r0, lr}
|
|
80003e0: 2000 movs r0, #0
|
|
80003e2: f000 f805 bl 80003f0 <__aeabi_idiv0>
|
|
80003e6: bd02 pop {r1, pc}
|
|
|
|
080003e8 <__aeabi_idivmod>:
|
|
80003e8: 2900 cmp r1, #0
|
|
80003ea: d0f8 beq.n 80003de <__divsi3+0x1c2>
|
|
80003ec: e716 b.n 800021c <__divsi3>
|
|
80003ee: 4770 bx lr
|
|
|
|
080003f0 <__aeabi_idiv0>:
|
|
80003f0: 4770 bx lr
|
|
80003f2: 46c0 nop ; (mov r8, r8)
|
|
|
|
080003f4 <__aeabi_cdrcmple>:
|
|
80003f4: 4684 mov ip, r0
|
|
80003f6: 0010 movs r0, r2
|
|
80003f8: 4662 mov r2, ip
|
|
80003fa: 468c mov ip, r1
|
|
80003fc: 0019 movs r1, r3
|
|
80003fe: 4663 mov r3, ip
|
|
8000400: e000 b.n 8000404 <__aeabi_cdcmpeq>
|
|
8000402: 46c0 nop ; (mov r8, r8)
|
|
|
|
08000404 <__aeabi_cdcmpeq>:
|
|
8000404: b51f push {r0, r1, r2, r3, r4, lr}
|
|
8000406: f000 fcd1 bl 8000dac <__ledf2>
|
|
800040a: 2800 cmp r0, #0
|
|
800040c: d401 bmi.n 8000412 <__aeabi_cdcmpeq+0xe>
|
|
800040e: 2100 movs r1, #0
|
|
8000410: 42c8 cmn r0, r1
|
|
8000412: bd1f pop {r0, r1, r2, r3, r4, pc}
|
|
|
|
08000414 <__aeabi_dcmpeq>:
|
|
8000414: b510 push {r4, lr}
|
|
8000416: f000 fc21 bl 8000c5c <__eqdf2>
|
|
800041a: 4240 negs r0, r0
|
|
800041c: 3001 adds r0, #1
|
|
800041e: bd10 pop {r4, pc}
|
|
|
|
08000420 <__aeabi_dcmplt>:
|
|
8000420: b510 push {r4, lr}
|
|
8000422: f000 fcc3 bl 8000dac <__ledf2>
|
|
8000426: 2800 cmp r0, #0
|
|
8000428: db01 blt.n 800042e <__aeabi_dcmplt+0xe>
|
|
800042a: 2000 movs r0, #0
|
|
800042c: bd10 pop {r4, pc}
|
|
800042e: 2001 movs r0, #1
|
|
8000430: bd10 pop {r4, pc}
|
|
8000432: 46c0 nop ; (mov r8, r8)
|
|
|
|
08000434 <__aeabi_dcmple>:
|
|
8000434: b510 push {r4, lr}
|
|
8000436: f000 fcb9 bl 8000dac <__ledf2>
|
|
800043a: 2800 cmp r0, #0
|
|
800043c: dd01 ble.n 8000442 <__aeabi_dcmple+0xe>
|
|
800043e: 2000 movs r0, #0
|
|
8000440: bd10 pop {r4, pc}
|
|
8000442: 2001 movs r0, #1
|
|
8000444: bd10 pop {r4, pc}
|
|
8000446: 46c0 nop ; (mov r8, r8)
|
|
|
|
08000448 <__aeabi_dcmpgt>:
|
|
8000448: b510 push {r4, lr}
|
|
800044a: f000 fc49 bl 8000ce0 <__gedf2>
|
|
800044e: 2800 cmp r0, #0
|
|
8000450: dc01 bgt.n 8000456 <__aeabi_dcmpgt+0xe>
|
|
8000452: 2000 movs r0, #0
|
|
8000454: bd10 pop {r4, pc}
|
|
8000456: 2001 movs r0, #1
|
|
8000458: bd10 pop {r4, pc}
|
|
800045a: 46c0 nop ; (mov r8, r8)
|
|
|
|
0800045c <__aeabi_dcmpge>:
|
|
800045c: b510 push {r4, lr}
|
|
800045e: f000 fc3f bl 8000ce0 <__gedf2>
|
|
8000462: 2800 cmp r0, #0
|
|
8000464: da01 bge.n 800046a <__aeabi_dcmpge+0xe>
|
|
8000466: 2000 movs r0, #0
|
|
8000468: bd10 pop {r4, pc}
|
|
800046a: 2001 movs r0, #1
|
|
800046c: bd10 pop {r4, pc}
|
|
800046e: 46c0 nop ; (mov r8, r8)
|
|
|
|
08000470 <__aeabi_cfrcmple>:
|
|
8000470: 4684 mov ip, r0
|
|
8000472: 0008 movs r0, r1
|
|
8000474: 4661 mov r1, ip
|
|
8000476: e7ff b.n 8000478 <__aeabi_cfcmpeq>
|
|
|
|
08000478 <__aeabi_cfcmpeq>:
|
|
8000478: b51f push {r0, r1, r2, r3, r4, lr}
|
|
800047a: f000 f8b7 bl 80005ec <__lesf2>
|
|
800047e: 2800 cmp r0, #0
|
|
8000480: d401 bmi.n 8000486 <__aeabi_cfcmpeq+0xe>
|
|
8000482: 2100 movs r1, #0
|
|
8000484: 42c8 cmn r0, r1
|
|
8000486: bd1f pop {r0, r1, r2, r3, r4, pc}
|
|
|
|
08000488 <__aeabi_fcmpeq>:
|
|
8000488: b510 push {r4, lr}
|
|
800048a: f000 f843 bl 8000514 <__eqsf2>
|
|
800048e: 4240 negs r0, r0
|
|
8000490: 3001 adds r0, #1
|
|
8000492: bd10 pop {r4, pc}
|
|
|
|
08000494 <__aeabi_fcmplt>:
|
|
8000494: b510 push {r4, lr}
|
|
8000496: f000 f8a9 bl 80005ec <__lesf2>
|
|
800049a: 2800 cmp r0, #0
|
|
800049c: db01 blt.n 80004a2 <__aeabi_fcmplt+0xe>
|
|
800049e: 2000 movs r0, #0
|
|
80004a0: bd10 pop {r4, pc}
|
|
80004a2: 2001 movs r0, #1
|
|
80004a4: bd10 pop {r4, pc}
|
|
80004a6: 46c0 nop ; (mov r8, r8)
|
|
|
|
080004a8 <__aeabi_fcmple>:
|
|
80004a8: b510 push {r4, lr}
|
|
80004aa: f000 f89f bl 80005ec <__lesf2>
|
|
80004ae: 2800 cmp r0, #0
|
|
80004b0: dd01 ble.n 80004b6 <__aeabi_fcmple+0xe>
|
|
80004b2: 2000 movs r0, #0
|
|
80004b4: bd10 pop {r4, pc}
|
|
80004b6: 2001 movs r0, #1
|
|
80004b8: bd10 pop {r4, pc}
|
|
80004ba: 46c0 nop ; (mov r8, r8)
|
|
|
|
080004bc <__aeabi_fcmpgt>:
|
|
80004bc: b510 push {r4, lr}
|
|
80004be: f000 f84f bl 8000560 <__gesf2>
|
|
80004c2: 2800 cmp r0, #0
|
|
80004c4: dc01 bgt.n 80004ca <__aeabi_fcmpgt+0xe>
|
|
80004c6: 2000 movs r0, #0
|
|
80004c8: bd10 pop {r4, pc}
|
|
80004ca: 2001 movs r0, #1
|
|
80004cc: bd10 pop {r4, pc}
|
|
80004ce: 46c0 nop ; (mov r8, r8)
|
|
|
|
080004d0 <__aeabi_fcmpge>:
|
|
80004d0: b510 push {r4, lr}
|
|
80004d2: f000 f845 bl 8000560 <__gesf2>
|
|
80004d6: 2800 cmp r0, #0
|
|
80004d8: da01 bge.n 80004de <__aeabi_fcmpge+0xe>
|
|
80004da: 2000 movs r0, #0
|
|
80004dc: bd10 pop {r4, pc}
|
|
80004de: 2001 movs r0, #1
|
|
80004e0: bd10 pop {r4, pc}
|
|
80004e2: 46c0 nop ; (mov r8, r8)
|
|
|
|
080004e4 <__aeabi_f2uiz>:
|
|
80004e4: 219e movs r1, #158 ; 0x9e
|
|
80004e6: b510 push {r4, lr}
|
|
80004e8: 05c9 lsls r1, r1, #23
|
|
80004ea: 1c04 adds r4, r0, #0
|
|
80004ec: f7ff fff0 bl 80004d0 <__aeabi_fcmpge>
|
|
80004f0: 2800 cmp r0, #0
|
|
80004f2: d103 bne.n 80004fc <__aeabi_f2uiz+0x18>
|
|
80004f4: 1c20 adds r0, r4, #0
|
|
80004f6: f000 fb91 bl 8000c1c <__aeabi_f2iz>
|
|
80004fa: bd10 pop {r4, pc}
|
|
80004fc: 219e movs r1, #158 ; 0x9e
|
|
80004fe: 1c20 adds r0, r4, #0
|
|
8000500: 05c9 lsls r1, r1, #23
|
|
8000502: f000 f9dd bl 80008c0 <__aeabi_fsub>
|
|
8000506: f000 fb89 bl 8000c1c <__aeabi_f2iz>
|
|
800050a: 2380 movs r3, #128 ; 0x80
|
|
800050c: 061b lsls r3, r3, #24
|
|
800050e: 469c mov ip, r3
|
|
8000510: 4460 add r0, ip
|
|
8000512: e7f2 b.n 80004fa <__aeabi_f2uiz+0x16>
|
|
|
|
08000514 <__eqsf2>:
|
|
8000514: b570 push {r4, r5, r6, lr}
|
|
8000516: 0042 lsls r2, r0, #1
|
|
8000518: 0245 lsls r5, r0, #9
|
|
800051a: 024e lsls r6, r1, #9
|
|
800051c: 004c lsls r4, r1, #1
|
|
800051e: 0fc3 lsrs r3, r0, #31
|
|
8000520: 0a6d lsrs r5, r5, #9
|
|
8000522: 2001 movs r0, #1
|
|
8000524: 0e12 lsrs r2, r2, #24
|
|
8000526: 0a76 lsrs r6, r6, #9
|
|
8000528: 0e24 lsrs r4, r4, #24
|
|
800052a: 0fc9 lsrs r1, r1, #31
|
|
800052c: 2aff cmp r2, #255 ; 0xff
|
|
800052e: d006 beq.n 800053e <__eqsf2+0x2a>
|
|
8000530: 2cff cmp r4, #255 ; 0xff
|
|
8000532: d003 beq.n 800053c <__eqsf2+0x28>
|
|
8000534: 42a2 cmp r2, r4
|
|
8000536: d101 bne.n 800053c <__eqsf2+0x28>
|
|
8000538: 42b5 cmp r5, r6
|
|
800053a: d006 beq.n 800054a <__eqsf2+0x36>
|
|
800053c: bd70 pop {r4, r5, r6, pc}
|
|
800053e: 2d00 cmp r5, #0
|
|
8000540: d1fc bne.n 800053c <__eqsf2+0x28>
|
|
8000542: 2cff cmp r4, #255 ; 0xff
|
|
8000544: d1fa bne.n 800053c <__eqsf2+0x28>
|
|
8000546: 2e00 cmp r6, #0
|
|
8000548: d1f8 bne.n 800053c <__eqsf2+0x28>
|
|
800054a: 428b cmp r3, r1
|
|
800054c: d006 beq.n 800055c <__eqsf2+0x48>
|
|
800054e: 2001 movs r0, #1
|
|
8000550: 2a00 cmp r2, #0
|
|
8000552: d1f3 bne.n 800053c <__eqsf2+0x28>
|
|
8000554: 0028 movs r0, r5
|
|
8000556: 1e43 subs r3, r0, #1
|
|
8000558: 4198 sbcs r0, r3
|
|
800055a: e7ef b.n 800053c <__eqsf2+0x28>
|
|
800055c: 2000 movs r0, #0
|
|
800055e: e7ed b.n 800053c <__eqsf2+0x28>
|
|
|
|
08000560 <__gesf2>:
|
|
8000560: b570 push {r4, r5, r6, lr}
|
|
8000562: 0042 lsls r2, r0, #1
|
|
8000564: 0245 lsls r5, r0, #9
|
|
8000566: 024e lsls r6, r1, #9
|
|
8000568: 004c lsls r4, r1, #1
|
|
800056a: 0fc3 lsrs r3, r0, #31
|
|
800056c: 0a6d lsrs r5, r5, #9
|
|
800056e: 0e12 lsrs r2, r2, #24
|
|
8000570: 0a76 lsrs r6, r6, #9
|
|
8000572: 0e24 lsrs r4, r4, #24
|
|
8000574: 0fc8 lsrs r0, r1, #31
|
|
8000576: 2aff cmp r2, #255 ; 0xff
|
|
8000578: d01b beq.n 80005b2 <__gesf2+0x52>
|
|
800057a: 2cff cmp r4, #255 ; 0xff
|
|
800057c: d00e beq.n 800059c <__gesf2+0x3c>
|
|
800057e: 2a00 cmp r2, #0
|
|
8000580: d11b bne.n 80005ba <__gesf2+0x5a>
|
|
8000582: 2c00 cmp r4, #0
|
|
8000584: d101 bne.n 800058a <__gesf2+0x2a>
|
|
8000586: 2e00 cmp r6, #0
|
|
8000588: d01c beq.n 80005c4 <__gesf2+0x64>
|
|
800058a: 2d00 cmp r5, #0
|
|
800058c: d00c beq.n 80005a8 <__gesf2+0x48>
|
|
800058e: 4283 cmp r3, r0
|
|
8000590: d01c beq.n 80005cc <__gesf2+0x6c>
|
|
8000592: 2102 movs r1, #2
|
|
8000594: 1e58 subs r0, r3, #1
|
|
8000596: 4008 ands r0, r1
|
|
8000598: 3801 subs r0, #1
|
|
800059a: bd70 pop {r4, r5, r6, pc}
|
|
800059c: 2e00 cmp r6, #0
|
|
800059e: d122 bne.n 80005e6 <__gesf2+0x86>
|
|
80005a0: 2a00 cmp r2, #0
|
|
80005a2: d1f4 bne.n 800058e <__gesf2+0x2e>
|
|
80005a4: 2d00 cmp r5, #0
|
|
80005a6: d1f2 bne.n 800058e <__gesf2+0x2e>
|
|
80005a8: 2800 cmp r0, #0
|
|
80005aa: d1f6 bne.n 800059a <__gesf2+0x3a>
|
|
80005ac: 2001 movs r0, #1
|
|
80005ae: 4240 negs r0, r0
|
|
80005b0: e7f3 b.n 800059a <__gesf2+0x3a>
|
|
80005b2: 2d00 cmp r5, #0
|
|
80005b4: d117 bne.n 80005e6 <__gesf2+0x86>
|
|
80005b6: 2cff cmp r4, #255 ; 0xff
|
|
80005b8: d0f0 beq.n 800059c <__gesf2+0x3c>
|
|
80005ba: 2c00 cmp r4, #0
|
|
80005bc: d1e7 bne.n 800058e <__gesf2+0x2e>
|
|
80005be: 2e00 cmp r6, #0
|
|
80005c0: d1e5 bne.n 800058e <__gesf2+0x2e>
|
|
80005c2: e7e6 b.n 8000592 <__gesf2+0x32>
|
|
80005c4: 2000 movs r0, #0
|
|
80005c6: 2d00 cmp r5, #0
|
|
80005c8: d0e7 beq.n 800059a <__gesf2+0x3a>
|
|
80005ca: e7e2 b.n 8000592 <__gesf2+0x32>
|
|
80005cc: 42a2 cmp r2, r4
|
|
80005ce: dc05 bgt.n 80005dc <__gesf2+0x7c>
|
|
80005d0: dbea blt.n 80005a8 <__gesf2+0x48>
|
|
80005d2: 42b5 cmp r5, r6
|
|
80005d4: d802 bhi.n 80005dc <__gesf2+0x7c>
|
|
80005d6: d3e7 bcc.n 80005a8 <__gesf2+0x48>
|
|
80005d8: 2000 movs r0, #0
|
|
80005da: e7de b.n 800059a <__gesf2+0x3a>
|
|
80005dc: 4243 negs r3, r0
|
|
80005de: 4158 adcs r0, r3
|
|
80005e0: 0040 lsls r0, r0, #1
|
|
80005e2: 3801 subs r0, #1
|
|
80005e4: e7d9 b.n 800059a <__gesf2+0x3a>
|
|
80005e6: 2002 movs r0, #2
|
|
80005e8: 4240 negs r0, r0
|
|
80005ea: e7d6 b.n 800059a <__gesf2+0x3a>
|
|
|
|
080005ec <__lesf2>:
|
|
80005ec: b570 push {r4, r5, r6, lr}
|
|
80005ee: 0042 lsls r2, r0, #1
|
|
80005f0: 0245 lsls r5, r0, #9
|
|
80005f2: 024e lsls r6, r1, #9
|
|
80005f4: 004c lsls r4, r1, #1
|
|
80005f6: 0fc3 lsrs r3, r0, #31
|
|
80005f8: 0a6d lsrs r5, r5, #9
|
|
80005fa: 0e12 lsrs r2, r2, #24
|
|
80005fc: 0a76 lsrs r6, r6, #9
|
|
80005fe: 0e24 lsrs r4, r4, #24
|
|
8000600: 0fc8 lsrs r0, r1, #31
|
|
8000602: 2aff cmp r2, #255 ; 0xff
|
|
8000604: d00b beq.n 800061e <__lesf2+0x32>
|
|
8000606: 2cff cmp r4, #255 ; 0xff
|
|
8000608: d00d beq.n 8000626 <__lesf2+0x3a>
|
|
800060a: 2a00 cmp r2, #0
|
|
800060c: d11f bne.n 800064e <__lesf2+0x62>
|
|
800060e: 2c00 cmp r4, #0
|
|
8000610: d116 bne.n 8000640 <__lesf2+0x54>
|
|
8000612: 2e00 cmp r6, #0
|
|
8000614: d114 bne.n 8000640 <__lesf2+0x54>
|
|
8000616: 2000 movs r0, #0
|
|
8000618: 2d00 cmp r5, #0
|
|
800061a: d010 beq.n 800063e <__lesf2+0x52>
|
|
800061c: e009 b.n 8000632 <__lesf2+0x46>
|
|
800061e: 2d00 cmp r5, #0
|
|
8000620: d10c bne.n 800063c <__lesf2+0x50>
|
|
8000622: 2cff cmp r4, #255 ; 0xff
|
|
8000624: d113 bne.n 800064e <__lesf2+0x62>
|
|
8000626: 2e00 cmp r6, #0
|
|
8000628: d108 bne.n 800063c <__lesf2+0x50>
|
|
800062a: 2a00 cmp r2, #0
|
|
800062c: d008 beq.n 8000640 <__lesf2+0x54>
|
|
800062e: 4283 cmp r3, r0
|
|
8000630: d012 beq.n 8000658 <__lesf2+0x6c>
|
|
8000632: 2102 movs r1, #2
|
|
8000634: 1e58 subs r0, r3, #1
|
|
8000636: 4008 ands r0, r1
|
|
8000638: 3801 subs r0, #1
|
|
800063a: e000 b.n 800063e <__lesf2+0x52>
|
|
800063c: 2002 movs r0, #2
|
|
800063e: bd70 pop {r4, r5, r6, pc}
|
|
8000640: 2d00 cmp r5, #0
|
|
8000642: d1f4 bne.n 800062e <__lesf2+0x42>
|
|
8000644: 2800 cmp r0, #0
|
|
8000646: d1fa bne.n 800063e <__lesf2+0x52>
|
|
8000648: 2001 movs r0, #1
|
|
800064a: 4240 negs r0, r0
|
|
800064c: e7f7 b.n 800063e <__lesf2+0x52>
|
|
800064e: 2c00 cmp r4, #0
|
|
8000650: d1ed bne.n 800062e <__lesf2+0x42>
|
|
8000652: 2e00 cmp r6, #0
|
|
8000654: d1eb bne.n 800062e <__lesf2+0x42>
|
|
8000656: e7ec b.n 8000632 <__lesf2+0x46>
|
|
8000658: 42a2 cmp r2, r4
|
|
800065a: dc05 bgt.n 8000668 <__lesf2+0x7c>
|
|
800065c: dbf2 blt.n 8000644 <__lesf2+0x58>
|
|
800065e: 42b5 cmp r5, r6
|
|
8000660: d802 bhi.n 8000668 <__lesf2+0x7c>
|
|
8000662: d3ef bcc.n 8000644 <__lesf2+0x58>
|
|
8000664: 2000 movs r0, #0
|
|
8000666: e7ea b.n 800063e <__lesf2+0x52>
|
|
8000668: 4243 negs r3, r0
|
|
800066a: 4158 adcs r0, r3
|
|
800066c: 0040 lsls r0, r0, #1
|
|
800066e: 3801 subs r0, #1
|
|
8000670: e7e5 b.n 800063e <__lesf2+0x52>
|
|
8000672: 46c0 nop ; (mov r8, r8)
|
|
|
|
08000674 <__aeabi_fmul>:
|
|
8000674: b5f0 push {r4, r5, r6, r7, lr}
|
|
8000676: 464f mov r7, r9
|
|
8000678: 4646 mov r6, r8
|
|
800067a: 46d6 mov lr, sl
|
|
800067c: 0244 lsls r4, r0, #9
|
|
800067e: 0045 lsls r5, r0, #1
|
|
8000680: b5c0 push {r6, r7, lr}
|
|
8000682: 0a64 lsrs r4, r4, #9
|
|
8000684: 1c0f adds r7, r1, #0
|
|
8000686: 0e2d lsrs r5, r5, #24
|
|
8000688: 0fc6 lsrs r6, r0, #31
|
|
800068a: 2d00 cmp r5, #0
|
|
800068c: d100 bne.n 8000690 <__aeabi_fmul+0x1c>
|
|
800068e: e08d b.n 80007ac <__aeabi_fmul+0x138>
|
|
8000690: 2dff cmp r5, #255 ; 0xff
|
|
8000692: d100 bne.n 8000696 <__aeabi_fmul+0x22>
|
|
8000694: e092 b.n 80007bc <__aeabi_fmul+0x148>
|
|
8000696: 2300 movs r3, #0
|
|
8000698: 2080 movs r0, #128 ; 0x80
|
|
800069a: 4699 mov r9, r3
|
|
800069c: 469a mov sl, r3
|
|
800069e: 00e4 lsls r4, r4, #3
|
|
80006a0: 04c0 lsls r0, r0, #19
|
|
80006a2: 4304 orrs r4, r0
|
|
80006a4: 3d7f subs r5, #127 ; 0x7f
|
|
80006a6: 0278 lsls r0, r7, #9
|
|
80006a8: 0a43 lsrs r3, r0, #9
|
|
80006aa: 4698 mov r8, r3
|
|
80006ac: 007b lsls r3, r7, #1
|
|
80006ae: 0e1b lsrs r3, r3, #24
|
|
80006b0: 0fff lsrs r7, r7, #31
|
|
80006b2: 2b00 cmp r3, #0
|
|
80006b4: d100 bne.n 80006b8 <__aeabi_fmul+0x44>
|
|
80006b6: e070 b.n 800079a <__aeabi_fmul+0x126>
|
|
80006b8: 2bff cmp r3, #255 ; 0xff
|
|
80006ba: d100 bne.n 80006be <__aeabi_fmul+0x4a>
|
|
80006bc: e086 b.n 80007cc <__aeabi_fmul+0x158>
|
|
80006be: 4642 mov r2, r8
|
|
80006c0: 00d0 lsls r0, r2, #3
|
|
80006c2: 2280 movs r2, #128 ; 0x80
|
|
80006c4: 3b7f subs r3, #127 ; 0x7f
|
|
80006c6: 18ed adds r5, r5, r3
|
|
80006c8: 2300 movs r3, #0
|
|
80006ca: 04d2 lsls r2, r2, #19
|
|
80006cc: 4302 orrs r2, r0
|
|
80006ce: 4690 mov r8, r2
|
|
80006d0: 469c mov ip, r3
|
|
80006d2: 0031 movs r1, r6
|
|
80006d4: 464b mov r3, r9
|
|
80006d6: 4079 eors r1, r7
|
|
80006d8: 1c68 adds r0, r5, #1
|
|
80006da: 2b0f cmp r3, #15
|
|
80006dc: d81c bhi.n 8000718 <__aeabi_fmul+0xa4>
|
|
80006de: 4a76 ldr r2, [pc, #472] ; (80008b8 <__aeabi_fmul+0x244>)
|
|
80006e0: 009b lsls r3, r3, #2
|
|
80006e2: 58d3 ldr r3, [r2, r3]
|
|
80006e4: 469f mov pc, r3
|
|
80006e6: 0039 movs r1, r7
|
|
80006e8: 4644 mov r4, r8
|
|
80006ea: 46e2 mov sl, ip
|
|
80006ec: 4653 mov r3, sl
|
|
80006ee: 2b02 cmp r3, #2
|
|
80006f0: d00f beq.n 8000712 <__aeabi_fmul+0x9e>
|
|
80006f2: 2b03 cmp r3, #3
|
|
80006f4: d100 bne.n 80006f8 <__aeabi_fmul+0x84>
|
|
80006f6: e0d7 b.n 80008a8 <__aeabi_fmul+0x234>
|
|
80006f8: 2b01 cmp r3, #1
|
|
80006fa: d137 bne.n 800076c <__aeabi_fmul+0xf8>
|
|
80006fc: 2000 movs r0, #0
|
|
80006fe: 2400 movs r4, #0
|
|
8000700: 05c0 lsls r0, r0, #23
|
|
8000702: 4320 orrs r0, r4
|
|
8000704: 07c9 lsls r1, r1, #31
|
|
8000706: 4308 orrs r0, r1
|
|
8000708: bce0 pop {r5, r6, r7}
|
|
800070a: 46ba mov sl, r7
|
|
800070c: 46b1 mov r9, r6
|
|
800070e: 46a8 mov r8, r5
|
|
8000710: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8000712: 20ff movs r0, #255 ; 0xff
|
|
8000714: 2400 movs r4, #0
|
|
8000716: e7f3 b.n 8000700 <__aeabi_fmul+0x8c>
|
|
8000718: 0c26 lsrs r6, r4, #16
|
|
800071a: 0424 lsls r4, r4, #16
|
|
800071c: 0c22 lsrs r2, r4, #16
|
|
800071e: 4644 mov r4, r8
|
|
8000720: 0424 lsls r4, r4, #16
|
|
8000722: 0c24 lsrs r4, r4, #16
|
|
8000724: 4643 mov r3, r8
|
|
8000726: 0027 movs r7, r4
|
|
8000728: 0c1b lsrs r3, r3, #16
|
|
800072a: 4357 muls r7, r2
|
|
800072c: 4374 muls r4, r6
|
|
800072e: 435a muls r2, r3
|
|
8000730: 435e muls r6, r3
|
|
8000732: 1912 adds r2, r2, r4
|
|
8000734: 0c3b lsrs r3, r7, #16
|
|
8000736: 189b adds r3, r3, r2
|
|
8000738: 429c cmp r4, r3
|
|
800073a: d903 bls.n 8000744 <__aeabi_fmul+0xd0>
|
|
800073c: 2280 movs r2, #128 ; 0x80
|
|
800073e: 0252 lsls r2, r2, #9
|
|
8000740: 4694 mov ip, r2
|
|
8000742: 4466 add r6, ip
|
|
8000744: 043f lsls r7, r7, #16
|
|
8000746: 041a lsls r2, r3, #16
|
|
8000748: 0c3f lsrs r7, r7, #16
|
|
800074a: 19d2 adds r2, r2, r7
|
|
800074c: 0194 lsls r4, r2, #6
|
|
800074e: 1e67 subs r7, r4, #1
|
|
8000750: 41bc sbcs r4, r7
|
|
8000752: 0c1b lsrs r3, r3, #16
|
|
8000754: 0e92 lsrs r2, r2, #26
|
|
8000756: 199b adds r3, r3, r6
|
|
8000758: 4314 orrs r4, r2
|
|
800075a: 019b lsls r3, r3, #6
|
|
800075c: 431c orrs r4, r3
|
|
800075e: 011b lsls r3, r3, #4
|
|
8000760: d400 bmi.n 8000764 <__aeabi_fmul+0xf0>
|
|
8000762: e09b b.n 800089c <__aeabi_fmul+0x228>
|
|
8000764: 2301 movs r3, #1
|
|
8000766: 0862 lsrs r2, r4, #1
|
|
8000768: 401c ands r4, r3
|
|
800076a: 4314 orrs r4, r2
|
|
800076c: 0002 movs r2, r0
|
|
800076e: 327f adds r2, #127 ; 0x7f
|
|
8000770: 2a00 cmp r2, #0
|
|
8000772: dd64 ble.n 800083e <__aeabi_fmul+0x1ca>
|
|
8000774: 0763 lsls r3, r4, #29
|
|
8000776: d004 beq.n 8000782 <__aeabi_fmul+0x10e>
|
|
8000778: 230f movs r3, #15
|
|
800077a: 4023 ands r3, r4
|
|
800077c: 2b04 cmp r3, #4
|
|
800077e: d000 beq.n 8000782 <__aeabi_fmul+0x10e>
|
|
8000780: 3404 adds r4, #4
|
|
8000782: 0123 lsls r3, r4, #4
|
|
8000784: d503 bpl.n 800078e <__aeabi_fmul+0x11a>
|
|
8000786: 0002 movs r2, r0
|
|
8000788: 4b4c ldr r3, [pc, #304] ; (80008bc <__aeabi_fmul+0x248>)
|
|
800078a: 3280 adds r2, #128 ; 0x80
|
|
800078c: 401c ands r4, r3
|
|
800078e: 2afe cmp r2, #254 ; 0xfe
|
|
8000790: dcbf bgt.n 8000712 <__aeabi_fmul+0x9e>
|
|
8000792: 01a4 lsls r4, r4, #6
|
|
8000794: 0a64 lsrs r4, r4, #9
|
|
8000796: b2d0 uxtb r0, r2
|
|
8000798: e7b2 b.n 8000700 <__aeabi_fmul+0x8c>
|
|
800079a: 4643 mov r3, r8
|
|
800079c: 2b00 cmp r3, #0
|
|
800079e: d13d bne.n 800081c <__aeabi_fmul+0x1a8>
|
|
80007a0: 464a mov r2, r9
|
|
80007a2: 3301 adds r3, #1
|
|
80007a4: 431a orrs r2, r3
|
|
80007a6: 4691 mov r9, r2
|
|
80007a8: 469c mov ip, r3
|
|
80007aa: e792 b.n 80006d2 <__aeabi_fmul+0x5e>
|
|
80007ac: 2c00 cmp r4, #0
|
|
80007ae: d129 bne.n 8000804 <__aeabi_fmul+0x190>
|
|
80007b0: 2304 movs r3, #4
|
|
80007b2: 4699 mov r9, r3
|
|
80007b4: 3b03 subs r3, #3
|
|
80007b6: 2500 movs r5, #0
|
|
80007b8: 469a mov sl, r3
|
|
80007ba: e774 b.n 80006a6 <__aeabi_fmul+0x32>
|
|
80007bc: 2c00 cmp r4, #0
|
|
80007be: d11b bne.n 80007f8 <__aeabi_fmul+0x184>
|
|
80007c0: 2308 movs r3, #8
|
|
80007c2: 4699 mov r9, r3
|
|
80007c4: 3b06 subs r3, #6
|
|
80007c6: 25ff movs r5, #255 ; 0xff
|
|
80007c8: 469a mov sl, r3
|
|
80007ca: e76c b.n 80006a6 <__aeabi_fmul+0x32>
|
|
80007cc: 4643 mov r3, r8
|
|
80007ce: 35ff adds r5, #255 ; 0xff
|
|
80007d0: 2b00 cmp r3, #0
|
|
80007d2: d10b bne.n 80007ec <__aeabi_fmul+0x178>
|
|
80007d4: 2302 movs r3, #2
|
|
80007d6: 464a mov r2, r9
|
|
80007d8: 431a orrs r2, r3
|
|
80007da: 4691 mov r9, r2
|
|
80007dc: 469c mov ip, r3
|
|
80007de: e778 b.n 80006d2 <__aeabi_fmul+0x5e>
|
|
80007e0: 4653 mov r3, sl
|
|
80007e2: 0031 movs r1, r6
|
|
80007e4: 2b02 cmp r3, #2
|
|
80007e6: d000 beq.n 80007ea <__aeabi_fmul+0x176>
|
|
80007e8: e783 b.n 80006f2 <__aeabi_fmul+0x7e>
|
|
80007ea: e792 b.n 8000712 <__aeabi_fmul+0x9e>
|
|
80007ec: 2303 movs r3, #3
|
|
80007ee: 464a mov r2, r9
|
|
80007f0: 431a orrs r2, r3
|
|
80007f2: 4691 mov r9, r2
|
|
80007f4: 469c mov ip, r3
|
|
80007f6: e76c b.n 80006d2 <__aeabi_fmul+0x5e>
|
|
80007f8: 230c movs r3, #12
|
|
80007fa: 4699 mov r9, r3
|
|
80007fc: 3b09 subs r3, #9
|
|
80007fe: 25ff movs r5, #255 ; 0xff
|
|
8000800: 469a mov sl, r3
|
|
8000802: e750 b.n 80006a6 <__aeabi_fmul+0x32>
|
|
8000804: 0020 movs r0, r4
|
|
8000806: f000 fb7d bl 8000f04 <__clzsi2>
|
|
800080a: 2576 movs r5, #118 ; 0x76
|
|
800080c: 1f43 subs r3, r0, #5
|
|
800080e: 409c lsls r4, r3
|
|
8000810: 2300 movs r3, #0
|
|
8000812: 426d negs r5, r5
|
|
8000814: 4699 mov r9, r3
|
|
8000816: 469a mov sl, r3
|
|
8000818: 1a2d subs r5, r5, r0
|
|
800081a: e744 b.n 80006a6 <__aeabi_fmul+0x32>
|
|
800081c: 4640 mov r0, r8
|
|
800081e: f000 fb71 bl 8000f04 <__clzsi2>
|
|
8000822: 4642 mov r2, r8
|
|
8000824: 1f43 subs r3, r0, #5
|
|
8000826: 409a lsls r2, r3
|
|
8000828: 2300 movs r3, #0
|
|
800082a: 1a2d subs r5, r5, r0
|
|
800082c: 4690 mov r8, r2
|
|
800082e: 469c mov ip, r3
|
|
8000830: 3d76 subs r5, #118 ; 0x76
|
|
8000832: e74e b.n 80006d2 <__aeabi_fmul+0x5e>
|
|
8000834: 2480 movs r4, #128 ; 0x80
|
|
8000836: 2100 movs r1, #0
|
|
8000838: 20ff movs r0, #255 ; 0xff
|
|
800083a: 03e4 lsls r4, r4, #15
|
|
800083c: e760 b.n 8000700 <__aeabi_fmul+0x8c>
|
|
800083e: 2301 movs r3, #1
|
|
8000840: 1a9b subs r3, r3, r2
|
|
8000842: 2b1b cmp r3, #27
|
|
8000844: dd00 ble.n 8000848 <__aeabi_fmul+0x1d4>
|
|
8000846: e759 b.n 80006fc <__aeabi_fmul+0x88>
|
|
8000848: 0022 movs r2, r4
|
|
800084a: 309e adds r0, #158 ; 0x9e
|
|
800084c: 40da lsrs r2, r3
|
|
800084e: 4084 lsls r4, r0
|
|
8000850: 0013 movs r3, r2
|
|
8000852: 1e62 subs r2, r4, #1
|
|
8000854: 4194 sbcs r4, r2
|
|
8000856: 431c orrs r4, r3
|
|
8000858: 0763 lsls r3, r4, #29
|
|
800085a: d004 beq.n 8000866 <__aeabi_fmul+0x1f2>
|
|
800085c: 230f movs r3, #15
|
|
800085e: 4023 ands r3, r4
|
|
8000860: 2b04 cmp r3, #4
|
|
8000862: d000 beq.n 8000866 <__aeabi_fmul+0x1f2>
|
|
8000864: 3404 adds r4, #4
|
|
8000866: 0163 lsls r3, r4, #5
|
|
8000868: d51a bpl.n 80008a0 <__aeabi_fmul+0x22c>
|
|
800086a: 2001 movs r0, #1
|
|
800086c: 2400 movs r4, #0
|
|
800086e: e747 b.n 8000700 <__aeabi_fmul+0x8c>
|
|
8000870: 2080 movs r0, #128 ; 0x80
|
|
8000872: 03c0 lsls r0, r0, #15
|
|
8000874: 4204 tst r4, r0
|
|
8000876: d009 beq.n 800088c <__aeabi_fmul+0x218>
|
|
8000878: 4643 mov r3, r8
|
|
800087a: 4203 tst r3, r0
|
|
800087c: d106 bne.n 800088c <__aeabi_fmul+0x218>
|
|
800087e: 4644 mov r4, r8
|
|
8000880: 4304 orrs r4, r0
|
|
8000882: 0264 lsls r4, r4, #9
|
|
8000884: 0039 movs r1, r7
|
|
8000886: 20ff movs r0, #255 ; 0xff
|
|
8000888: 0a64 lsrs r4, r4, #9
|
|
800088a: e739 b.n 8000700 <__aeabi_fmul+0x8c>
|
|
800088c: 2080 movs r0, #128 ; 0x80
|
|
800088e: 03c0 lsls r0, r0, #15
|
|
8000890: 4304 orrs r4, r0
|
|
8000892: 0264 lsls r4, r4, #9
|
|
8000894: 0031 movs r1, r6
|
|
8000896: 20ff movs r0, #255 ; 0xff
|
|
8000898: 0a64 lsrs r4, r4, #9
|
|
800089a: e731 b.n 8000700 <__aeabi_fmul+0x8c>
|
|
800089c: 0028 movs r0, r5
|
|
800089e: e765 b.n 800076c <__aeabi_fmul+0xf8>
|
|
80008a0: 01a4 lsls r4, r4, #6
|
|
80008a2: 2000 movs r0, #0
|
|
80008a4: 0a64 lsrs r4, r4, #9
|
|
80008a6: e72b b.n 8000700 <__aeabi_fmul+0x8c>
|
|
80008a8: 2080 movs r0, #128 ; 0x80
|
|
80008aa: 03c0 lsls r0, r0, #15
|
|
80008ac: 4304 orrs r4, r0
|
|
80008ae: 0264 lsls r4, r4, #9
|
|
80008b0: 20ff movs r0, #255 ; 0xff
|
|
80008b2: 0a64 lsrs r4, r4, #9
|
|
80008b4: e724 b.n 8000700 <__aeabi_fmul+0x8c>
|
|
80008b6: 46c0 nop ; (mov r8, r8)
|
|
80008b8: 080067a8 .word 0x080067a8
|
|
80008bc: f7ffffff .word 0xf7ffffff
|
|
|
|
080008c0 <__aeabi_fsub>:
|
|
80008c0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80008c2: 46ce mov lr, r9
|
|
80008c4: 4647 mov r7, r8
|
|
80008c6: 0243 lsls r3, r0, #9
|
|
80008c8: 0a5b lsrs r3, r3, #9
|
|
80008ca: 024e lsls r6, r1, #9
|
|
80008cc: 00da lsls r2, r3, #3
|
|
80008ce: 4694 mov ip, r2
|
|
80008d0: 0a72 lsrs r2, r6, #9
|
|
80008d2: 4691 mov r9, r2
|
|
80008d4: 0045 lsls r5, r0, #1
|
|
80008d6: 004a lsls r2, r1, #1
|
|
80008d8: b580 push {r7, lr}
|
|
80008da: 0e2d lsrs r5, r5, #24
|
|
80008dc: 001f movs r7, r3
|
|
80008de: 0fc4 lsrs r4, r0, #31
|
|
80008e0: 0e12 lsrs r2, r2, #24
|
|
80008e2: 0fc9 lsrs r1, r1, #31
|
|
80008e4: 09b6 lsrs r6, r6, #6
|
|
80008e6: 2aff cmp r2, #255 ; 0xff
|
|
80008e8: d05b beq.n 80009a2 <__aeabi_fsub+0xe2>
|
|
80008ea: 2001 movs r0, #1
|
|
80008ec: 4041 eors r1, r0
|
|
80008ee: 428c cmp r4, r1
|
|
80008f0: d039 beq.n 8000966 <__aeabi_fsub+0xa6>
|
|
80008f2: 1aa8 subs r0, r5, r2
|
|
80008f4: 2800 cmp r0, #0
|
|
80008f6: dd5a ble.n 80009ae <__aeabi_fsub+0xee>
|
|
80008f8: 2a00 cmp r2, #0
|
|
80008fa: d06a beq.n 80009d2 <__aeabi_fsub+0x112>
|
|
80008fc: 2dff cmp r5, #255 ; 0xff
|
|
80008fe: d100 bne.n 8000902 <__aeabi_fsub+0x42>
|
|
8000900: e0d9 b.n 8000ab6 <__aeabi_fsub+0x1f6>
|
|
8000902: 2280 movs r2, #128 ; 0x80
|
|
8000904: 04d2 lsls r2, r2, #19
|
|
8000906: 4316 orrs r6, r2
|
|
8000908: 281b cmp r0, #27
|
|
800090a: dc00 bgt.n 800090e <__aeabi_fsub+0x4e>
|
|
800090c: e0e9 b.n 8000ae2 <__aeabi_fsub+0x222>
|
|
800090e: 2001 movs r0, #1
|
|
8000910: 4663 mov r3, ip
|
|
8000912: 1a18 subs r0, r3, r0
|
|
8000914: 0143 lsls r3, r0, #5
|
|
8000916: d400 bmi.n 800091a <__aeabi_fsub+0x5a>
|
|
8000918: e0b4 b.n 8000a84 <__aeabi_fsub+0x1c4>
|
|
800091a: 0180 lsls r0, r0, #6
|
|
800091c: 0987 lsrs r7, r0, #6
|
|
800091e: 0038 movs r0, r7
|
|
8000920: f000 faf0 bl 8000f04 <__clzsi2>
|
|
8000924: 3805 subs r0, #5
|
|
8000926: 4087 lsls r7, r0
|
|
8000928: 4285 cmp r5, r0
|
|
800092a: dc00 bgt.n 800092e <__aeabi_fsub+0x6e>
|
|
800092c: e0cc b.n 8000ac8 <__aeabi_fsub+0x208>
|
|
800092e: 1a2d subs r5, r5, r0
|
|
8000930: 48b5 ldr r0, [pc, #724] ; (8000c08 <__aeabi_fsub+0x348>)
|
|
8000932: 4038 ands r0, r7
|
|
8000934: 0743 lsls r3, r0, #29
|
|
8000936: d004 beq.n 8000942 <__aeabi_fsub+0x82>
|
|
8000938: 230f movs r3, #15
|
|
800093a: 4003 ands r3, r0
|
|
800093c: 2b04 cmp r3, #4
|
|
800093e: d000 beq.n 8000942 <__aeabi_fsub+0x82>
|
|
8000940: 3004 adds r0, #4
|
|
8000942: 0143 lsls r3, r0, #5
|
|
8000944: d400 bmi.n 8000948 <__aeabi_fsub+0x88>
|
|
8000946: e0a0 b.n 8000a8a <__aeabi_fsub+0x1ca>
|
|
8000948: 1c6a adds r2, r5, #1
|
|
800094a: 2dfe cmp r5, #254 ; 0xfe
|
|
800094c: d100 bne.n 8000950 <__aeabi_fsub+0x90>
|
|
800094e: e08d b.n 8000a6c <__aeabi_fsub+0x1ac>
|
|
8000950: 0180 lsls r0, r0, #6
|
|
8000952: 0a47 lsrs r7, r0, #9
|
|
8000954: b2d2 uxtb r2, r2
|
|
8000956: 05d0 lsls r0, r2, #23
|
|
8000958: 4338 orrs r0, r7
|
|
800095a: 07e4 lsls r4, r4, #31
|
|
800095c: 4320 orrs r0, r4
|
|
800095e: bcc0 pop {r6, r7}
|
|
8000960: 46b9 mov r9, r7
|
|
8000962: 46b0 mov r8, r6
|
|
8000964: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
8000966: 1aa8 subs r0, r5, r2
|
|
8000968: 4680 mov r8, r0
|
|
800096a: 2800 cmp r0, #0
|
|
800096c: dd45 ble.n 80009fa <__aeabi_fsub+0x13a>
|
|
800096e: 2a00 cmp r2, #0
|
|
8000970: d070 beq.n 8000a54 <__aeabi_fsub+0x194>
|
|
8000972: 2dff cmp r5, #255 ; 0xff
|
|
8000974: d100 bne.n 8000978 <__aeabi_fsub+0xb8>
|
|
8000976: e09e b.n 8000ab6 <__aeabi_fsub+0x1f6>
|
|
8000978: 2380 movs r3, #128 ; 0x80
|
|
800097a: 04db lsls r3, r3, #19
|
|
800097c: 431e orrs r6, r3
|
|
800097e: 4643 mov r3, r8
|
|
8000980: 2b1b cmp r3, #27
|
|
8000982: dc00 bgt.n 8000986 <__aeabi_fsub+0xc6>
|
|
8000984: e0d2 b.n 8000b2c <__aeabi_fsub+0x26c>
|
|
8000986: 2001 movs r0, #1
|
|
8000988: 4460 add r0, ip
|
|
800098a: 0143 lsls r3, r0, #5
|
|
800098c: d57a bpl.n 8000a84 <__aeabi_fsub+0x1c4>
|
|
800098e: 3501 adds r5, #1
|
|
8000990: 2dff cmp r5, #255 ; 0xff
|
|
8000992: d06b beq.n 8000a6c <__aeabi_fsub+0x1ac>
|
|
8000994: 2301 movs r3, #1
|
|
8000996: 4a9d ldr r2, [pc, #628] ; (8000c0c <__aeabi_fsub+0x34c>)
|
|
8000998: 4003 ands r3, r0
|
|
800099a: 0840 lsrs r0, r0, #1
|
|
800099c: 4010 ands r0, r2
|
|
800099e: 4318 orrs r0, r3
|
|
80009a0: e7c8 b.n 8000934 <__aeabi_fsub+0x74>
|
|
80009a2: 2e00 cmp r6, #0
|
|
80009a4: d020 beq.n 80009e8 <__aeabi_fsub+0x128>
|
|
80009a6: 428c cmp r4, r1
|
|
80009a8: d023 beq.n 80009f2 <__aeabi_fsub+0x132>
|
|
80009aa: 0028 movs r0, r5
|
|
80009ac: 38ff subs r0, #255 ; 0xff
|
|
80009ae: 2800 cmp r0, #0
|
|
80009b0: d039 beq.n 8000a26 <__aeabi_fsub+0x166>
|
|
80009b2: 1b57 subs r7, r2, r5
|
|
80009b4: 2d00 cmp r5, #0
|
|
80009b6: d000 beq.n 80009ba <__aeabi_fsub+0xfa>
|
|
80009b8: e09d b.n 8000af6 <__aeabi_fsub+0x236>
|
|
80009ba: 4663 mov r3, ip
|
|
80009bc: 2b00 cmp r3, #0
|
|
80009be: d100 bne.n 80009c2 <__aeabi_fsub+0x102>
|
|
80009c0: e0db b.n 8000b7a <__aeabi_fsub+0x2ba>
|
|
80009c2: 1e7b subs r3, r7, #1
|
|
80009c4: 2f01 cmp r7, #1
|
|
80009c6: d100 bne.n 80009ca <__aeabi_fsub+0x10a>
|
|
80009c8: e10d b.n 8000be6 <__aeabi_fsub+0x326>
|
|
80009ca: 2fff cmp r7, #255 ; 0xff
|
|
80009cc: d071 beq.n 8000ab2 <__aeabi_fsub+0x1f2>
|
|
80009ce: 001f movs r7, r3
|
|
80009d0: e098 b.n 8000b04 <__aeabi_fsub+0x244>
|
|
80009d2: 2e00 cmp r6, #0
|
|
80009d4: d100 bne.n 80009d8 <__aeabi_fsub+0x118>
|
|
80009d6: e0a7 b.n 8000b28 <__aeabi_fsub+0x268>
|
|
80009d8: 1e42 subs r2, r0, #1
|
|
80009da: 2801 cmp r0, #1
|
|
80009dc: d100 bne.n 80009e0 <__aeabi_fsub+0x120>
|
|
80009de: e0e6 b.n 8000bae <__aeabi_fsub+0x2ee>
|
|
80009e0: 28ff cmp r0, #255 ; 0xff
|
|
80009e2: d068 beq.n 8000ab6 <__aeabi_fsub+0x1f6>
|
|
80009e4: 0010 movs r0, r2
|
|
80009e6: e78f b.n 8000908 <__aeabi_fsub+0x48>
|
|
80009e8: 2001 movs r0, #1
|
|
80009ea: 4041 eors r1, r0
|
|
80009ec: 42a1 cmp r1, r4
|
|
80009ee: d000 beq.n 80009f2 <__aeabi_fsub+0x132>
|
|
80009f0: e77f b.n 80008f2 <__aeabi_fsub+0x32>
|
|
80009f2: 20ff movs r0, #255 ; 0xff
|
|
80009f4: 4240 negs r0, r0
|
|
80009f6: 4680 mov r8, r0
|
|
80009f8: 44a8 add r8, r5
|
|
80009fa: 4640 mov r0, r8
|
|
80009fc: 2800 cmp r0, #0
|
|
80009fe: d038 beq.n 8000a72 <__aeabi_fsub+0x1b2>
|
|
8000a00: 1b51 subs r1, r2, r5
|
|
8000a02: 2d00 cmp r5, #0
|
|
8000a04: d100 bne.n 8000a08 <__aeabi_fsub+0x148>
|
|
8000a06: e0ae b.n 8000b66 <__aeabi_fsub+0x2a6>
|
|
8000a08: 2aff cmp r2, #255 ; 0xff
|
|
8000a0a: d100 bne.n 8000a0e <__aeabi_fsub+0x14e>
|
|
8000a0c: e0df b.n 8000bce <__aeabi_fsub+0x30e>
|
|
8000a0e: 2380 movs r3, #128 ; 0x80
|
|
8000a10: 4660 mov r0, ip
|
|
8000a12: 04db lsls r3, r3, #19
|
|
8000a14: 4318 orrs r0, r3
|
|
8000a16: 4684 mov ip, r0
|
|
8000a18: 291b cmp r1, #27
|
|
8000a1a: dc00 bgt.n 8000a1e <__aeabi_fsub+0x15e>
|
|
8000a1c: e0d9 b.n 8000bd2 <__aeabi_fsub+0x312>
|
|
8000a1e: 2001 movs r0, #1
|
|
8000a20: 0015 movs r5, r2
|
|
8000a22: 1980 adds r0, r0, r6
|
|
8000a24: e7b1 b.n 800098a <__aeabi_fsub+0xca>
|
|
8000a26: 20fe movs r0, #254 ; 0xfe
|
|
8000a28: 1c6a adds r2, r5, #1
|
|
8000a2a: 4210 tst r0, r2
|
|
8000a2c: d171 bne.n 8000b12 <__aeabi_fsub+0x252>
|
|
8000a2e: 2d00 cmp r5, #0
|
|
8000a30: d000 beq.n 8000a34 <__aeabi_fsub+0x174>
|
|
8000a32: e0a6 b.n 8000b82 <__aeabi_fsub+0x2c2>
|
|
8000a34: 4663 mov r3, ip
|
|
8000a36: 2b00 cmp r3, #0
|
|
8000a38: d100 bne.n 8000a3c <__aeabi_fsub+0x17c>
|
|
8000a3a: e0d9 b.n 8000bf0 <__aeabi_fsub+0x330>
|
|
8000a3c: 2200 movs r2, #0
|
|
8000a3e: 2e00 cmp r6, #0
|
|
8000a40: d100 bne.n 8000a44 <__aeabi_fsub+0x184>
|
|
8000a42: e788 b.n 8000956 <__aeabi_fsub+0x96>
|
|
8000a44: 1b98 subs r0, r3, r6
|
|
8000a46: 0143 lsls r3, r0, #5
|
|
8000a48: d400 bmi.n 8000a4c <__aeabi_fsub+0x18c>
|
|
8000a4a: e0e1 b.n 8000c10 <__aeabi_fsub+0x350>
|
|
8000a4c: 4663 mov r3, ip
|
|
8000a4e: 000c movs r4, r1
|
|
8000a50: 1af0 subs r0, r6, r3
|
|
8000a52: e76f b.n 8000934 <__aeabi_fsub+0x74>
|
|
8000a54: 2e00 cmp r6, #0
|
|
8000a56: d100 bne.n 8000a5a <__aeabi_fsub+0x19a>
|
|
8000a58: e0b7 b.n 8000bca <__aeabi_fsub+0x30a>
|
|
8000a5a: 0002 movs r2, r0
|
|
8000a5c: 3a01 subs r2, #1
|
|
8000a5e: 2801 cmp r0, #1
|
|
8000a60: d100 bne.n 8000a64 <__aeabi_fsub+0x1a4>
|
|
8000a62: e09c b.n 8000b9e <__aeabi_fsub+0x2de>
|
|
8000a64: 28ff cmp r0, #255 ; 0xff
|
|
8000a66: d026 beq.n 8000ab6 <__aeabi_fsub+0x1f6>
|
|
8000a68: 4690 mov r8, r2
|
|
8000a6a: e788 b.n 800097e <__aeabi_fsub+0xbe>
|
|
8000a6c: 22ff movs r2, #255 ; 0xff
|
|
8000a6e: 2700 movs r7, #0
|
|
8000a70: e771 b.n 8000956 <__aeabi_fsub+0x96>
|
|
8000a72: 20fe movs r0, #254 ; 0xfe
|
|
8000a74: 1c6a adds r2, r5, #1
|
|
8000a76: 4210 tst r0, r2
|
|
8000a78: d064 beq.n 8000b44 <__aeabi_fsub+0x284>
|
|
8000a7a: 2aff cmp r2, #255 ; 0xff
|
|
8000a7c: d0f6 beq.n 8000a6c <__aeabi_fsub+0x1ac>
|
|
8000a7e: 0015 movs r5, r2
|
|
8000a80: 4466 add r6, ip
|
|
8000a82: 0870 lsrs r0, r6, #1
|
|
8000a84: 0743 lsls r3, r0, #29
|
|
8000a86: d000 beq.n 8000a8a <__aeabi_fsub+0x1ca>
|
|
8000a88: e756 b.n 8000938 <__aeabi_fsub+0x78>
|
|
8000a8a: 08c3 lsrs r3, r0, #3
|
|
8000a8c: 2dff cmp r5, #255 ; 0xff
|
|
8000a8e: d012 beq.n 8000ab6 <__aeabi_fsub+0x1f6>
|
|
8000a90: 025b lsls r3, r3, #9
|
|
8000a92: 0a5f lsrs r7, r3, #9
|
|
8000a94: b2ea uxtb r2, r5
|
|
8000a96: e75e b.n 8000956 <__aeabi_fsub+0x96>
|
|
8000a98: 4662 mov r2, ip
|
|
8000a9a: 2a00 cmp r2, #0
|
|
8000a9c: d100 bne.n 8000aa0 <__aeabi_fsub+0x1e0>
|
|
8000a9e: e096 b.n 8000bce <__aeabi_fsub+0x30e>
|
|
8000aa0: 2e00 cmp r6, #0
|
|
8000aa2: d008 beq.n 8000ab6 <__aeabi_fsub+0x1f6>
|
|
8000aa4: 2280 movs r2, #128 ; 0x80
|
|
8000aa6: 03d2 lsls r2, r2, #15
|
|
8000aa8: 4213 tst r3, r2
|
|
8000aaa: d004 beq.n 8000ab6 <__aeabi_fsub+0x1f6>
|
|
8000aac: 4648 mov r0, r9
|
|
8000aae: 4210 tst r0, r2
|
|
8000ab0: d101 bne.n 8000ab6 <__aeabi_fsub+0x1f6>
|
|
8000ab2: 000c movs r4, r1
|
|
8000ab4: 464b mov r3, r9
|
|
8000ab6: 2b00 cmp r3, #0
|
|
8000ab8: d0d8 beq.n 8000a6c <__aeabi_fsub+0x1ac>
|
|
8000aba: 2780 movs r7, #128 ; 0x80
|
|
8000abc: 03ff lsls r7, r7, #15
|
|
8000abe: 431f orrs r7, r3
|
|
8000ac0: 027f lsls r7, r7, #9
|
|
8000ac2: 22ff movs r2, #255 ; 0xff
|
|
8000ac4: 0a7f lsrs r7, r7, #9
|
|
8000ac6: e746 b.n 8000956 <__aeabi_fsub+0x96>
|
|
8000ac8: 2320 movs r3, #32
|
|
8000aca: 003a movs r2, r7
|
|
8000acc: 1b45 subs r5, r0, r5
|
|
8000ace: 0038 movs r0, r7
|
|
8000ad0: 3501 adds r5, #1
|
|
8000ad2: 40ea lsrs r2, r5
|
|
8000ad4: 1b5d subs r5, r3, r5
|
|
8000ad6: 40a8 lsls r0, r5
|
|
8000ad8: 1e43 subs r3, r0, #1
|
|
8000ada: 4198 sbcs r0, r3
|
|
8000adc: 2500 movs r5, #0
|
|
8000ade: 4310 orrs r0, r2
|
|
8000ae0: e728 b.n 8000934 <__aeabi_fsub+0x74>
|
|
8000ae2: 2320 movs r3, #32
|
|
8000ae4: 1a1b subs r3, r3, r0
|
|
8000ae6: 0032 movs r2, r6
|
|
8000ae8: 409e lsls r6, r3
|
|
8000aea: 40c2 lsrs r2, r0
|
|
8000aec: 0030 movs r0, r6
|
|
8000aee: 1e43 subs r3, r0, #1
|
|
8000af0: 4198 sbcs r0, r3
|
|
8000af2: 4310 orrs r0, r2
|
|
8000af4: e70c b.n 8000910 <__aeabi_fsub+0x50>
|
|
8000af6: 2aff cmp r2, #255 ; 0xff
|
|
8000af8: d0db beq.n 8000ab2 <__aeabi_fsub+0x1f2>
|
|
8000afa: 2380 movs r3, #128 ; 0x80
|
|
8000afc: 4660 mov r0, ip
|
|
8000afe: 04db lsls r3, r3, #19
|
|
8000b00: 4318 orrs r0, r3
|
|
8000b02: 4684 mov ip, r0
|
|
8000b04: 2f1b cmp r7, #27
|
|
8000b06: dd56 ble.n 8000bb6 <__aeabi_fsub+0x2f6>
|
|
8000b08: 2001 movs r0, #1
|
|
8000b0a: 000c movs r4, r1
|
|
8000b0c: 0015 movs r5, r2
|
|
8000b0e: 1a30 subs r0, r6, r0
|
|
8000b10: e700 b.n 8000914 <__aeabi_fsub+0x54>
|
|
8000b12: 4663 mov r3, ip
|
|
8000b14: 1b9f subs r7, r3, r6
|
|
8000b16: 017b lsls r3, r7, #5
|
|
8000b18: d43d bmi.n 8000b96 <__aeabi_fsub+0x2d6>
|
|
8000b1a: 2f00 cmp r7, #0
|
|
8000b1c: d000 beq.n 8000b20 <__aeabi_fsub+0x260>
|
|
8000b1e: e6fe b.n 800091e <__aeabi_fsub+0x5e>
|
|
8000b20: 2400 movs r4, #0
|
|
8000b22: 2200 movs r2, #0
|
|
8000b24: 2700 movs r7, #0
|
|
8000b26: e716 b.n 8000956 <__aeabi_fsub+0x96>
|
|
8000b28: 0005 movs r5, r0
|
|
8000b2a: e7af b.n 8000a8c <__aeabi_fsub+0x1cc>
|
|
8000b2c: 0032 movs r2, r6
|
|
8000b2e: 4643 mov r3, r8
|
|
8000b30: 4641 mov r1, r8
|
|
8000b32: 40da lsrs r2, r3
|
|
8000b34: 2320 movs r3, #32
|
|
8000b36: 1a5b subs r3, r3, r1
|
|
8000b38: 409e lsls r6, r3
|
|
8000b3a: 0030 movs r0, r6
|
|
8000b3c: 1e43 subs r3, r0, #1
|
|
8000b3e: 4198 sbcs r0, r3
|
|
8000b40: 4310 orrs r0, r2
|
|
8000b42: e721 b.n 8000988 <__aeabi_fsub+0xc8>
|
|
8000b44: 2d00 cmp r5, #0
|
|
8000b46: d1a7 bne.n 8000a98 <__aeabi_fsub+0x1d8>
|
|
8000b48: 4663 mov r3, ip
|
|
8000b4a: 2b00 cmp r3, #0
|
|
8000b4c: d059 beq.n 8000c02 <__aeabi_fsub+0x342>
|
|
8000b4e: 2200 movs r2, #0
|
|
8000b50: 2e00 cmp r6, #0
|
|
8000b52: d100 bne.n 8000b56 <__aeabi_fsub+0x296>
|
|
8000b54: e6ff b.n 8000956 <__aeabi_fsub+0x96>
|
|
8000b56: 0030 movs r0, r6
|
|
8000b58: 4460 add r0, ip
|
|
8000b5a: 0143 lsls r3, r0, #5
|
|
8000b5c: d592 bpl.n 8000a84 <__aeabi_fsub+0x1c4>
|
|
8000b5e: 4b2a ldr r3, [pc, #168] ; (8000c08 <__aeabi_fsub+0x348>)
|
|
8000b60: 3501 adds r5, #1
|
|
8000b62: 4018 ands r0, r3
|
|
8000b64: e78e b.n 8000a84 <__aeabi_fsub+0x1c4>
|
|
8000b66: 4663 mov r3, ip
|
|
8000b68: 2b00 cmp r3, #0
|
|
8000b6a: d047 beq.n 8000bfc <__aeabi_fsub+0x33c>
|
|
8000b6c: 1e4b subs r3, r1, #1
|
|
8000b6e: 2901 cmp r1, #1
|
|
8000b70: d015 beq.n 8000b9e <__aeabi_fsub+0x2de>
|
|
8000b72: 29ff cmp r1, #255 ; 0xff
|
|
8000b74: d02b beq.n 8000bce <__aeabi_fsub+0x30e>
|
|
8000b76: 0019 movs r1, r3
|
|
8000b78: e74e b.n 8000a18 <__aeabi_fsub+0x158>
|
|
8000b7a: 000c movs r4, r1
|
|
8000b7c: 464b mov r3, r9
|
|
8000b7e: 003d movs r5, r7
|
|
8000b80: e784 b.n 8000a8c <__aeabi_fsub+0x1cc>
|
|
8000b82: 4662 mov r2, ip
|
|
8000b84: 2a00 cmp r2, #0
|
|
8000b86: d18b bne.n 8000aa0 <__aeabi_fsub+0x1e0>
|
|
8000b88: 2e00 cmp r6, #0
|
|
8000b8a: d192 bne.n 8000ab2 <__aeabi_fsub+0x1f2>
|
|
8000b8c: 2780 movs r7, #128 ; 0x80
|
|
8000b8e: 2400 movs r4, #0
|
|
8000b90: 22ff movs r2, #255 ; 0xff
|
|
8000b92: 03ff lsls r7, r7, #15
|
|
8000b94: e6df b.n 8000956 <__aeabi_fsub+0x96>
|
|
8000b96: 4663 mov r3, ip
|
|
8000b98: 000c movs r4, r1
|
|
8000b9a: 1af7 subs r7, r6, r3
|
|
8000b9c: e6bf b.n 800091e <__aeabi_fsub+0x5e>
|
|
8000b9e: 0030 movs r0, r6
|
|
8000ba0: 4460 add r0, ip
|
|
8000ba2: 2501 movs r5, #1
|
|
8000ba4: 0143 lsls r3, r0, #5
|
|
8000ba6: d400 bmi.n 8000baa <__aeabi_fsub+0x2ea>
|
|
8000ba8: e76c b.n 8000a84 <__aeabi_fsub+0x1c4>
|
|
8000baa: 2502 movs r5, #2
|
|
8000bac: e6f2 b.n 8000994 <__aeabi_fsub+0xd4>
|
|
8000bae: 4663 mov r3, ip
|
|
8000bb0: 2501 movs r5, #1
|
|
8000bb2: 1b98 subs r0, r3, r6
|
|
8000bb4: e6ae b.n 8000914 <__aeabi_fsub+0x54>
|
|
8000bb6: 2320 movs r3, #32
|
|
8000bb8: 4664 mov r4, ip
|
|
8000bba: 4660 mov r0, ip
|
|
8000bbc: 40fc lsrs r4, r7
|
|
8000bbe: 1bdf subs r7, r3, r7
|
|
8000bc0: 40b8 lsls r0, r7
|
|
8000bc2: 1e43 subs r3, r0, #1
|
|
8000bc4: 4198 sbcs r0, r3
|
|
8000bc6: 4320 orrs r0, r4
|
|
8000bc8: e79f b.n 8000b0a <__aeabi_fsub+0x24a>
|
|
8000bca: 0005 movs r5, r0
|
|
8000bcc: e75e b.n 8000a8c <__aeabi_fsub+0x1cc>
|
|
8000bce: 464b mov r3, r9
|
|
8000bd0: e771 b.n 8000ab6 <__aeabi_fsub+0x1f6>
|
|
8000bd2: 2320 movs r3, #32
|
|
8000bd4: 4665 mov r5, ip
|
|
8000bd6: 4660 mov r0, ip
|
|
8000bd8: 40cd lsrs r5, r1
|
|
8000bda: 1a59 subs r1, r3, r1
|
|
8000bdc: 4088 lsls r0, r1
|
|
8000bde: 1e43 subs r3, r0, #1
|
|
8000be0: 4198 sbcs r0, r3
|
|
8000be2: 4328 orrs r0, r5
|
|
8000be4: e71c b.n 8000a20 <__aeabi_fsub+0x160>
|
|
8000be6: 4663 mov r3, ip
|
|
8000be8: 000c movs r4, r1
|
|
8000bea: 2501 movs r5, #1
|
|
8000bec: 1af0 subs r0, r6, r3
|
|
8000bee: e691 b.n 8000914 <__aeabi_fsub+0x54>
|
|
8000bf0: 2e00 cmp r6, #0
|
|
8000bf2: d095 beq.n 8000b20 <__aeabi_fsub+0x260>
|
|
8000bf4: 000c movs r4, r1
|
|
8000bf6: 464f mov r7, r9
|
|
8000bf8: 2200 movs r2, #0
|
|
8000bfa: e6ac b.n 8000956 <__aeabi_fsub+0x96>
|
|
8000bfc: 464b mov r3, r9
|
|
8000bfe: 000d movs r5, r1
|
|
8000c00: e744 b.n 8000a8c <__aeabi_fsub+0x1cc>
|
|
8000c02: 464f mov r7, r9
|
|
8000c04: 2200 movs r2, #0
|
|
8000c06: e6a6 b.n 8000956 <__aeabi_fsub+0x96>
|
|
8000c08: fbffffff .word 0xfbffffff
|
|
8000c0c: 7dffffff .word 0x7dffffff
|
|
8000c10: 2800 cmp r0, #0
|
|
8000c12: d000 beq.n 8000c16 <__aeabi_fsub+0x356>
|
|
8000c14: e736 b.n 8000a84 <__aeabi_fsub+0x1c4>
|
|
8000c16: 2400 movs r4, #0
|
|
8000c18: 2700 movs r7, #0
|
|
8000c1a: e69c b.n 8000956 <__aeabi_fsub+0x96>
|
|
|
|
08000c1c <__aeabi_f2iz>:
|
|
8000c1c: 0241 lsls r1, r0, #9
|
|
8000c1e: 0042 lsls r2, r0, #1
|
|
8000c20: 0fc3 lsrs r3, r0, #31
|
|
8000c22: 0a49 lsrs r1, r1, #9
|
|
8000c24: 2000 movs r0, #0
|
|
8000c26: 0e12 lsrs r2, r2, #24
|
|
8000c28: 2a7e cmp r2, #126 ; 0x7e
|
|
8000c2a: dd03 ble.n 8000c34 <__aeabi_f2iz+0x18>
|
|
8000c2c: 2a9d cmp r2, #157 ; 0x9d
|
|
8000c2e: dd02 ble.n 8000c36 <__aeabi_f2iz+0x1a>
|
|
8000c30: 4a09 ldr r2, [pc, #36] ; (8000c58 <__aeabi_f2iz+0x3c>)
|
|
8000c32: 1898 adds r0, r3, r2
|
|
8000c34: 4770 bx lr
|
|
8000c36: 2080 movs r0, #128 ; 0x80
|
|
8000c38: 0400 lsls r0, r0, #16
|
|
8000c3a: 4301 orrs r1, r0
|
|
8000c3c: 2a95 cmp r2, #149 ; 0x95
|
|
8000c3e: dc07 bgt.n 8000c50 <__aeabi_f2iz+0x34>
|
|
8000c40: 2096 movs r0, #150 ; 0x96
|
|
8000c42: 1a82 subs r2, r0, r2
|
|
8000c44: 40d1 lsrs r1, r2
|
|
8000c46: 4248 negs r0, r1
|
|
8000c48: 2b00 cmp r3, #0
|
|
8000c4a: d1f3 bne.n 8000c34 <__aeabi_f2iz+0x18>
|
|
8000c4c: 0008 movs r0, r1
|
|
8000c4e: e7f1 b.n 8000c34 <__aeabi_f2iz+0x18>
|
|
8000c50: 3a96 subs r2, #150 ; 0x96
|
|
8000c52: 4091 lsls r1, r2
|
|
8000c54: e7f7 b.n 8000c46 <__aeabi_f2iz+0x2a>
|
|
8000c56: 46c0 nop ; (mov r8, r8)
|
|
8000c58: 7fffffff .word 0x7fffffff
|
|
|
|
08000c5c <__eqdf2>:
|
|
8000c5c: b5f0 push {r4, r5, r6, r7, lr}
|
|
8000c5e: 464e mov r6, r9
|
|
8000c60: 4645 mov r5, r8
|
|
8000c62: 46de mov lr, fp
|
|
8000c64: 4657 mov r7, sl
|
|
8000c66: 4690 mov r8, r2
|
|
8000c68: b5e0 push {r5, r6, r7, lr}
|
|
8000c6a: 0017 movs r7, r2
|
|
8000c6c: 031a lsls r2, r3, #12
|
|
8000c6e: 0b12 lsrs r2, r2, #12
|
|
8000c70: 0005 movs r5, r0
|
|
8000c72: 4684 mov ip, r0
|
|
8000c74: 4819 ldr r0, [pc, #100] ; (8000cdc <__eqdf2+0x80>)
|
|
8000c76: 030e lsls r6, r1, #12
|
|
8000c78: 004c lsls r4, r1, #1
|
|
8000c7a: 4691 mov r9, r2
|
|
8000c7c: 005a lsls r2, r3, #1
|
|
8000c7e: 0fdb lsrs r3, r3, #31
|
|
8000c80: 469b mov fp, r3
|
|
8000c82: 0b36 lsrs r6, r6, #12
|
|
8000c84: 0d64 lsrs r4, r4, #21
|
|
8000c86: 0fc9 lsrs r1, r1, #31
|
|
8000c88: 0d52 lsrs r2, r2, #21
|
|
8000c8a: 4284 cmp r4, r0
|
|
8000c8c: d019 beq.n 8000cc2 <__eqdf2+0x66>
|
|
8000c8e: 4282 cmp r2, r0
|
|
8000c90: d010 beq.n 8000cb4 <__eqdf2+0x58>
|
|
8000c92: 2001 movs r0, #1
|
|
8000c94: 4294 cmp r4, r2
|
|
8000c96: d10e bne.n 8000cb6 <__eqdf2+0x5a>
|
|
8000c98: 454e cmp r6, r9
|
|
8000c9a: d10c bne.n 8000cb6 <__eqdf2+0x5a>
|
|
8000c9c: 2001 movs r0, #1
|
|
8000c9e: 45c4 cmp ip, r8
|
|
8000ca0: d109 bne.n 8000cb6 <__eqdf2+0x5a>
|
|
8000ca2: 4559 cmp r1, fp
|
|
8000ca4: d017 beq.n 8000cd6 <__eqdf2+0x7a>
|
|
8000ca6: 2c00 cmp r4, #0
|
|
8000ca8: d105 bne.n 8000cb6 <__eqdf2+0x5a>
|
|
8000caa: 0030 movs r0, r6
|
|
8000cac: 4328 orrs r0, r5
|
|
8000cae: 1e43 subs r3, r0, #1
|
|
8000cb0: 4198 sbcs r0, r3
|
|
8000cb2: e000 b.n 8000cb6 <__eqdf2+0x5a>
|
|
8000cb4: 2001 movs r0, #1
|
|
8000cb6: bcf0 pop {r4, r5, r6, r7}
|
|
8000cb8: 46bb mov fp, r7
|
|
8000cba: 46b2 mov sl, r6
|
|
8000cbc: 46a9 mov r9, r5
|
|
8000cbe: 46a0 mov r8, r4
|
|
8000cc0: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8000cc2: 0033 movs r3, r6
|
|
8000cc4: 2001 movs r0, #1
|
|
8000cc6: 432b orrs r3, r5
|
|
8000cc8: d1f5 bne.n 8000cb6 <__eqdf2+0x5a>
|
|
8000cca: 42a2 cmp r2, r4
|
|
8000ccc: d1f3 bne.n 8000cb6 <__eqdf2+0x5a>
|
|
8000cce: 464b mov r3, r9
|
|
8000cd0: 433b orrs r3, r7
|
|
8000cd2: d1f0 bne.n 8000cb6 <__eqdf2+0x5a>
|
|
8000cd4: e7e2 b.n 8000c9c <__eqdf2+0x40>
|
|
8000cd6: 2000 movs r0, #0
|
|
8000cd8: e7ed b.n 8000cb6 <__eqdf2+0x5a>
|
|
8000cda: 46c0 nop ; (mov r8, r8)
|
|
8000cdc: 000007ff .word 0x000007ff
|
|
|
|
08000ce0 <__gedf2>:
|
|
8000ce0: b5f0 push {r4, r5, r6, r7, lr}
|
|
8000ce2: 4647 mov r7, r8
|
|
8000ce4: 46ce mov lr, r9
|
|
8000ce6: 0004 movs r4, r0
|
|
8000ce8: 0018 movs r0, r3
|
|
8000cea: 0016 movs r6, r2
|
|
8000cec: 031b lsls r3, r3, #12
|
|
8000cee: 0b1b lsrs r3, r3, #12
|
|
8000cf0: 4d2d ldr r5, [pc, #180] ; (8000da8 <__gedf2+0xc8>)
|
|
8000cf2: 004a lsls r2, r1, #1
|
|
8000cf4: 4699 mov r9, r3
|
|
8000cf6: b580 push {r7, lr}
|
|
8000cf8: 0043 lsls r3, r0, #1
|
|
8000cfa: 030f lsls r7, r1, #12
|
|
8000cfc: 46a4 mov ip, r4
|
|
8000cfe: 46b0 mov r8, r6
|
|
8000d00: 0b3f lsrs r7, r7, #12
|
|
8000d02: 0d52 lsrs r2, r2, #21
|
|
8000d04: 0fc9 lsrs r1, r1, #31
|
|
8000d06: 0d5b lsrs r3, r3, #21
|
|
8000d08: 0fc0 lsrs r0, r0, #31
|
|
8000d0a: 42aa cmp r2, r5
|
|
8000d0c: d021 beq.n 8000d52 <__gedf2+0x72>
|
|
8000d0e: 42ab cmp r3, r5
|
|
8000d10: d013 beq.n 8000d3a <__gedf2+0x5a>
|
|
8000d12: 2a00 cmp r2, #0
|
|
8000d14: d122 bne.n 8000d5c <__gedf2+0x7c>
|
|
8000d16: 433c orrs r4, r7
|
|
8000d18: 2b00 cmp r3, #0
|
|
8000d1a: d102 bne.n 8000d22 <__gedf2+0x42>
|
|
8000d1c: 464d mov r5, r9
|
|
8000d1e: 432e orrs r6, r5
|
|
8000d20: d022 beq.n 8000d68 <__gedf2+0x88>
|
|
8000d22: 2c00 cmp r4, #0
|
|
8000d24: d010 beq.n 8000d48 <__gedf2+0x68>
|
|
8000d26: 4281 cmp r1, r0
|
|
8000d28: d022 beq.n 8000d70 <__gedf2+0x90>
|
|
8000d2a: 2002 movs r0, #2
|
|
8000d2c: 3901 subs r1, #1
|
|
8000d2e: 4008 ands r0, r1
|
|
8000d30: 3801 subs r0, #1
|
|
8000d32: bcc0 pop {r6, r7}
|
|
8000d34: 46b9 mov r9, r7
|
|
8000d36: 46b0 mov r8, r6
|
|
8000d38: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8000d3a: 464d mov r5, r9
|
|
8000d3c: 432e orrs r6, r5
|
|
8000d3e: d129 bne.n 8000d94 <__gedf2+0xb4>
|
|
8000d40: 2a00 cmp r2, #0
|
|
8000d42: d1f0 bne.n 8000d26 <__gedf2+0x46>
|
|
8000d44: 433c orrs r4, r7
|
|
8000d46: d1ee bne.n 8000d26 <__gedf2+0x46>
|
|
8000d48: 2800 cmp r0, #0
|
|
8000d4a: d1f2 bne.n 8000d32 <__gedf2+0x52>
|
|
8000d4c: 2001 movs r0, #1
|
|
8000d4e: 4240 negs r0, r0
|
|
8000d50: e7ef b.n 8000d32 <__gedf2+0x52>
|
|
8000d52: 003d movs r5, r7
|
|
8000d54: 4325 orrs r5, r4
|
|
8000d56: d11d bne.n 8000d94 <__gedf2+0xb4>
|
|
8000d58: 4293 cmp r3, r2
|
|
8000d5a: d0ee beq.n 8000d3a <__gedf2+0x5a>
|
|
8000d5c: 2b00 cmp r3, #0
|
|
8000d5e: d1e2 bne.n 8000d26 <__gedf2+0x46>
|
|
8000d60: 464c mov r4, r9
|
|
8000d62: 4326 orrs r6, r4
|
|
8000d64: d1df bne.n 8000d26 <__gedf2+0x46>
|
|
8000d66: e7e0 b.n 8000d2a <__gedf2+0x4a>
|
|
8000d68: 2000 movs r0, #0
|
|
8000d6a: 2c00 cmp r4, #0
|
|
8000d6c: d0e1 beq.n 8000d32 <__gedf2+0x52>
|
|
8000d6e: e7dc b.n 8000d2a <__gedf2+0x4a>
|
|
8000d70: 429a cmp r2, r3
|
|
8000d72: dc0a bgt.n 8000d8a <__gedf2+0xaa>
|
|
8000d74: dbe8 blt.n 8000d48 <__gedf2+0x68>
|
|
8000d76: 454f cmp r7, r9
|
|
8000d78: d8d7 bhi.n 8000d2a <__gedf2+0x4a>
|
|
8000d7a: d00e beq.n 8000d9a <__gedf2+0xba>
|
|
8000d7c: 2000 movs r0, #0
|
|
8000d7e: 454f cmp r7, r9
|
|
8000d80: d2d7 bcs.n 8000d32 <__gedf2+0x52>
|
|
8000d82: 2900 cmp r1, #0
|
|
8000d84: d0e2 beq.n 8000d4c <__gedf2+0x6c>
|
|
8000d86: 0008 movs r0, r1
|
|
8000d88: e7d3 b.n 8000d32 <__gedf2+0x52>
|
|
8000d8a: 4243 negs r3, r0
|
|
8000d8c: 4158 adcs r0, r3
|
|
8000d8e: 0040 lsls r0, r0, #1
|
|
8000d90: 3801 subs r0, #1
|
|
8000d92: e7ce b.n 8000d32 <__gedf2+0x52>
|
|
8000d94: 2002 movs r0, #2
|
|
8000d96: 4240 negs r0, r0
|
|
8000d98: e7cb b.n 8000d32 <__gedf2+0x52>
|
|
8000d9a: 45c4 cmp ip, r8
|
|
8000d9c: d8c5 bhi.n 8000d2a <__gedf2+0x4a>
|
|
8000d9e: 2000 movs r0, #0
|
|
8000da0: 45c4 cmp ip, r8
|
|
8000da2: d2c6 bcs.n 8000d32 <__gedf2+0x52>
|
|
8000da4: e7ed b.n 8000d82 <__gedf2+0xa2>
|
|
8000da6: 46c0 nop ; (mov r8, r8)
|
|
8000da8: 000007ff .word 0x000007ff
|
|
|
|
08000dac <__ledf2>:
|
|
8000dac: b5f0 push {r4, r5, r6, r7, lr}
|
|
8000dae: 4647 mov r7, r8
|
|
8000db0: 46ce mov lr, r9
|
|
8000db2: 0004 movs r4, r0
|
|
8000db4: 0018 movs r0, r3
|
|
8000db6: 0016 movs r6, r2
|
|
8000db8: 031b lsls r3, r3, #12
|
|
8000dba: 0b1b lsrs r3, r3, #12
|
|
8000dbc: 4d2c ldr r5, [pc, #176] ; (8000e70 <__ledf2+0xc4>)
|
|
8000dbe: 004a lsls r2, r1, #1
|
|
8000dc0: 4699 mov r9, r3
|
|
8000dc2: b580 push {r7, lr}
|
|
8000dc4: 0043 lsls r3, r0, #1
|
|
8000dc6: 030f lsls r7, r1, #12
|
|
8000dc8: 46a4 mov ip, r4
|
|
8000dca: 46b0 mov r8, r6
|
|
8000dcc: 0b3f lsrs r7, r7, #12
|
|
8000dce: 0d52 lsrs r2, r2, #21
|
|
8000dd0: 0fc9 lsrs r1, r1, #31
|
|
8000dd2: 0d5b lsrs r3, r3, #21
|
|
8000dd4: 0fc0 lsrs r0, r0, #31
|
|
8000dd6: 42aa cmp r2, r5
|
|
8000dd8: d00d beq.n 8000df6 <__ledf2+0x4a>
|
|
8000dda: 42ab cmp r3, r5
|
|
8000ddc: d010 beq.n 8000e00 <__ledf2+0x54>
|
|
8000dde: 2a00 cmp r2, #0
|
|
8000de0: d127 bne.n 8000e32 <__ledf2+0x86>
|
|
8000de2: 433c orrs r4, r7
|
|
8000de4: 2b00 cmp r3, #0
|
|
8000de6: d111 bne.n 8000e0c <__ledf2+0x60>
|
|
8000de8: 464d mov r5, r9
|
|
8000dea: 432e orrs r6, r5
|
|
8000dec: d10e bne.n 8000e0c <__ledf2+0x60>
|
|
8000dee: 2000 movs r0, #0
|
|
8000df0: 2c00 cmp r4, #0
|
|
8000df2: d015 beq.n 8000e20 <__ledf2+0x74>
|
|
8000df4: e00e b.n 8000e14 <__ledf2+0x68>
|
|
8000df6: 003d movs r5, r7
|
|
8000df8: 4325 orrs r5, r4
|
|
8000dfa: d110 bne.n 8000e1e <__ledf2+0x72>
|
|
8000dfc: 4293 cmp r3, r2
|
|
8000dfe: d118 bne.n 8000e32 <__ledf2+0x86>
|
|
8000e00: 464d mov r5, r9
|
|
8000e02: 432e orrs r6, r5
|
|
8000e04: d10b bne.n 8000e1e <__ledf2+0x72>
|
|
8000e06: 2a00 cmp r2, #0
|
|
8000e08: d102 bne.n 8000e10 <__ledf2+0x64>
|
|
8000e0a: 433c orrs r4, r7
|
|
8000e0c: 2c00 cmp r4, #0
|
|
8000e0e: d00b beq.n 8000e28 <__ledf2+0x7c>
|
|
8000e10: 4281 cmp r1, r0
|
|
8000e12: d014 beq.n 8000e3e <__ledf2+0x92>
|
|
8000e14: 2002 movs r0, #2
|
|
8000e16: 3901 subs r1, #1
|
|
8000e18: 4008 ands r0, r1
|
|
8000e1a: 3801 subs r0, #1
|
|
8000e1c: e000 b.n 8000e20 <__ledf2+0x74>
|
|
8000e1e: 2002 movs r0, #2
|
|
8000e20: bcc0 pop {r6, r7}
|
|
8000e22: 46b9 mov r9, r7
|
|
8000e24: 46b0 mov r8, r6
|
|
8000e26: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8000e28: 2800 cmp r0, #0
|
|
8000e2a: d1f9 bne.n 8000e20 <__ledf2+0x74>
|
|
8000e2c: 2001 movs r0, #1
|
|
8000e2e: 4240 negs r0, r0
|
|
8000e30: e7f6 b.n 8000e20 <__ledf2+0x74>
|
|
8000e32: 2b00 cmp r3, #0
|
|
8000e34: d1ec bne.n 8000e10 <__ledf2+0x64>
|
|
8000e36: 464c mov r4, r9
|
|
8000e38: 4326 orrs r6, r4
|
|
8000e3a: d1e9 bne.n 8000e10 <__ledf2+0x64>
|
|
8000e3c: e7ea b.n 8000e14 <__ledf2+0x68>
|
|
8000e3e: 429a cmp r2, r3
|
|
8000e40: dd04 ble.n 8000e4c <__ledf2+0xa0>
|
|
8000e42: 4243 negs r3, r0
|
|
8000e44: 4158 adcs r0, r3
|
|
8000e46: 0040 lsls r0, r0, #1
|
|
8000e48: 3801 subs r0, #1
|
|
8000e4a: e7e9 b.n 8000e20 <__ledf2+0x74>
|
|
8000e4c: 429a cmp r2, r3
|
|
8000e4e: dbeb blt.n 8000e28 <__ledf2+0x7c>
|
|
8000e50: 454f cmp r7, r9
|
|
8000e52: d8df bhi.n 8000e14 <__ledf2+0x68>
|
|
8000e54: d006 beq.n 8000e64 <__ledf2+0xb8>
|
|
8000e56: 2000 movs r0, #0
|
|
8000e58: 454f cmp r7, r9
|
|
8000e5a: d2e1 bcs.n 8000e20 <__ledf2+0x74>
|
|
8000e5c: 2900 cmp r1, #0
|
|
8000e5e: d0e5 beq.n 8000e2c <__ledf2+0x80>
|
|
8000e60: 0008 movs r0, r1
|
|
8000e62: e7dd b.n 8000e20 <__ledf2+0x74>
|
|
8000e64: 45c4 cmp ip, r8
|
|
8000e66: d8d5 bhi.n 8000e14 <__ledf2+0x68>
|
|
8000e68: 2000 movs r0, #0
|
|
8000e6a: 45c4 cmp ip, r8
|
|
8000e6c: d2d8 bcs.n 8000e20 <__ledf2+0x74>
|
|
8000e6e: e7f5 b.n 8000e5c <__ledf2+0xb0>
|
|
8000e70: 000007ff .word 0x000007ff
|
|
|
|
08000e74 <__aeabi_f2d>:
|
|
8000e74: b570 push {r4, r5, r6, lr}
|
|
8000e76: 0043 lsls r3, r0, #1
|
|
8000e78: 0246 lsls r6, r0, #9
|
|
8000e7a: 0fc4 lsrs r4, r0, #31
|
|
8000e7c: 20fe movs r0, #254 ; 0xfe
|
|
8000e7e: 0e1b lsrs r3, r3, #24
|
|
8000e80: 1c59 adds r1, r3, #1
|
|
8000e82: 0a75 lsrs r5, r6, #9
|
|
8000e84: 4208 tst r0, r1
|
|
8000e86: d00c beq.n 8000ea2 <__aeabi_f2d+0x2e>
|
|
8000e88: 22e0 movs r2, #224 ; 0xe0
|
|
8000e8a: 0092 lsls r2, r2, #2
|
|
8000e8c: 4694 mov ip, r2
|
|
8000e8e: 076d lsls r5, r5, #29
|
|
8000e90: 0b36 lsrs r6, r6, #12
|
|
8000e92: 4463 add r3, ip
|
|
8000e94: 051b lsls r3, r3, #20
|
|
8000e96: 4333 orrs r3, r6
|
|
8000e98: 07e4 lsls r4, r4, #31
|
|
8000e9a: 4323 orrs r3, r4
|
|
8000e9c: 0028 movs r0, r5
|
|
8000e9e: 0019 movs r1, r3
|
|
8000ea0: bd70 pop {r4, r5, r6, pc}
|
|
8000ea2: 2b00 cmp r3, #0
|
|
8000ea4: d114 bne.n 8000ed0 <__aeabi_f2d+0x5c>
|
|
8000ea6: 2d00 cmp r5, #0
|
|
8000ea8: d01b beq.n 8000ee2 <__aeabi_f2d+0x6e>
|
|
8000eaa: 0028 movs r0, r5
|
|
8000eac: f000 f82a bl 8000f04 <__clzsi2>
|
|
8000eb0: 280a cmp r0, #10
|
|
8000eb2: dc1c bgt.n 8000eee <__aeabi_f2d+0x7a>
|
|
8000eb4: 230b movs r3, #11
|
|
8000eb6: 002e movs r6, r5
|
|
8000eb8: 1a1b subs r3, r3, r0
|
|
8000eba: 40de lsrs r6, r3
|
|
8000ebc: 0003 movs r3, r0
|
|
8000ebe: 3315 adds r3, #21
|
|
8000ec0: 409d lsls r5, r3
|
|
8000ec2: 4a0e ldr r2, [pc, #56] ; (8000efc <__aeabi_f2d+0x88>)
|
|
8000ec4: 0336 lsls r6, r6, #12
|
|
8000ec6: 1a12 subs r2, r2, r0
|
|
8000ec8: 0552 lsls r2, r2, #21
|
|
8000eca: 0b36 lsrs r6, r6, #12
|
|
8000ecc: 0d53 lsrs r3, r2, #21
|
|
8000ece: e7e1 b.n 8000e94 <__aeabi_f2d+0x20>
|
|
8000ed0: 2d00 cmp r5, #0
|
|
8000ed2: d009 beq.n 8000ee8 <__aeabi_f2d+0x74>
|
|
8000ed4: 2280 movs r2, #128 ; 0x80
|
|
8000ed6: 0b36 lsrs r6, r6, #12
|
|
8000ed8: 0312 lsls r2, r2, #12
|
|
8000eda: 4b09 ldr r3, [pc, #36] ; (8000f00 <__aeabi_f2d+0x8c>)
|
|
8000edc: 076d lsls r5, r5, #29
|
|
8000ede: 4316 orrs r6, r2
|
|
8000ee0: e7d8 b.n 8000e94 <__aeabi_f2d+0x20>
|
|
8000ee2: 2300 movs r3, #0
|
|
8000ee4: 2600 movs r6, #0
|
|
8000ee6: e7d5 b.n 8000e94 <__aeabi_f2d+0x20>
|
|
8000ee8: 2600 movs r6, #0
|
|
8000eea: 4b05 ldr r3, [pc, #20] ; (8000f00 <__aeabi_f2d+0x8c>)
|
|
8000eec: e7d2 b.n 8000e94 <__aeabi_f2d+0x20>
|
|
8000eee: 0003 movs r3, r0
|
|
8000ef0: 3b0b subs r3, #11
|
|
8000ef2: 409d lsls r5, r3
|
|
8000ef4: 002e movs r6, r5
|
|
8000ef6: 2500 movs r5, #0
|
|
8000ef8: e7e3 b.n 8000ec2 <__aeabi_f2d+0x4e>
|
|
8000efa: 46c0 nop ; (mov r8, r8)
|
|
8000efc: 00000389 .word 0x00000389
|
|
8000f00: 000007ff .word 0x000007ff
|
|
|
|
08000f04 <__clzsi2>:
|
|
8000f04: 211c movs r1, #28
|
|
8000f06: 2301 movs r3, #1
|
|
8000f08: 041b lsls r3, r3, #16
|
|
8000f0a: 4298 cmp r0, r3
|
|
8000f0c: d301 bcc.n 8000f12 <__clzsi2+0xe>
|
|
8000f0e: 0c00 lsrs r0, r0, #16
|
|
8000f10: 3910 subs r1, #16
|
|
8000f12: 0a1b lsrs r3, r3, #8
|
|
8000f14: 4298 cmp r0, r3
|
|
8000f16: d301 bcc.n 8000f1c <__clzsi2+0x18>
|
|
8000f18: 0a00 lsrs r0, r0, #8
|
|
8000f1a: 3908 subs r1, #8
|
|
8000f1c: 091b lsrs r3, r3, #4
|
|
8000f1e: 4298 cmp r0, r3
|
|
8000f20: d301 bcc.n 8000f26 <__clzsi2+0x22>
|
|
8000f22: 0900 lsrs r0, r0, #4
|
|
8000f24: 3904 subs r1, #4
|
|
8000f26: a202 add r2, pc, #8 ; (adr r2, 8000f30 <__clzsi2+0x2c>)
|
|
8000f28: 5c10 ldrb r0, [r2, r0]
|
|
8000f2a: 1840 adds r0, r0, r1
|
|
8000f2c: 4770 bx lr
|
|
8000f2e: 46c0 nop ; (mov r8, r8)
|
|
8000f30: 02020304 .word 0x02020304
|
|
8000f34: 01010101 .word 0x01010101
|
|
...
|
|
|
|
08000f40 <loadConfig>:
|
|
|
|
/* Private user code ---------------------------------------------------------*/
|
|
/* USER CODE BEGIN 0 */
|
|
|
|
//load configuration from FLASH
|
|
volatile void loadConfig(void) {
|
|
8000f40: b580 push {r7, lr}
|
|
8000f42: b082 sub sp, #8
|
|
8000f44: af00 add r7, sp, #0
|
|
uint32_t l_Address = CONF_FLASH_ADDR;
|
|
8000f46: 4b18 ldr r3, [pc, #96] ; (8000fa8 <loadConfig+0x68>)
|
|
8000f48: 607b str r3, [r7, #4]
|
|
uint32_t l_Index = 0;
|
|
8000f4a: 2300 movs r3, #0
|
|
8000f4c: 603b str r3, [r7, #0]
|
|
|
|
//Reading from FLASH
|
|
while (l_Address < (CONF_FLASH_ADDR + FLASH_CONF_SIZE)) {
|
|
8000f4e: e00e b.n 8000f6e <loadConfig+0x2e>
|
|
configuration.data64[l_Index] = *(__IO uint64_t *)l_Address;
|
|
8000f50: 687b ldr r3, [r7, #4]
|
|
8000f52: 681a ldr r2, [r3, #0]
|
|
8000f54: 685b ldr r3, [r3, #4]
|
|
8000f56: 4815 ldr r0, [pc, #84] ; (8000fac <loadConfig+0x6c>)
|
|
8000f58: 6839 ldr r1, [r7, #0]
|
|
8000f5a: 00c9 lsls r1, r1, #3
|
|
8000f5c: 1841 adds r1, r0, r1
|
|
8000f5e: 600a str r2, [r1, #0]
|
|
8000f60: 604b str r3, [r1, #4]
|
|
l_Index += 1;
|
|
8000f62: 683b ldr r3, [r7, #0]
|
|
8000f64: 3301 adds r3, #1
|
|
8000f66: 603b str r3, [r7, #0]
|
|
l_Address += 8;
|
|
8000f68: 687b ldr r3, [r7, #4]
|
|
8000f6a: 3308 adds r3, #8
|
|
8000f6c: 607b str r3, [r7, #4]
|
|
while (l_Address < (CONF_FLASH_ADDR + FLASH_CONF_SIZE)) {
|
|
8000f6e: 687b ldr r3, [r7, #4]
|
|
8000f70: 4a0f ldr r2, [pc, #60] ; (8000fb0 <loadConfig+0x70>)
|
|
8000f72: 4293 cmp r3, r2
|
|
8000f74: d9ec bls.n 8000f50 <loadConfig+0x10>
|
|
}
|
|
|
|
//Calculate a hash from the configuration
|
|
if (HAL_CRC_Calculate(&hcrc, configuration.data32, 2) != configuration.sector.checksum
|
|
8000f76: 490d ldr r1, [pc, #52] ; (8000fac <loadConfig+0x6c>)
|
|
8000f78: 4b0e ldr r3, [pc, #56] ; (8000fb4 <loadConfig+0x74>)
|
|
8000f7a: 2202 movs r2, #2
|
|
8000f7c: 0018 movs r0, r3
|
|
8000f7e: f001 f867 bl 8002050 <HAL_CRC_Calculate>
|
|
8000f82: 0002 movs r2, r0
|
|
8000f84: 4b09 ldr r3, [pc, #36] ; (8000fac <loadConfig+0x6c>)
|
|
8000f86: 68db ldr r3, [r3, #12]
|
|
8000f88: 429a cmp r2, r3
|
|
8000f8a: d104 bne.n 8000f96 <loadConfig+0x56>
|
|
|| configuration.config.token != CONF_TOKEN) {
|
|
8000f8c: 4b07 ldr r3, [pc, #28] ; (8000fac <loadConfig+0x6c>)
|
|
8000f8e: 681b ldr r3, [r3, #0]
|
|
8000f90: 4a09 ldr r2, [pc, #36] ; (8000fb8 <loadConfig+0x78>)
|
|
8000f92: 4293 cmp r3, r2
|
|
8000f94: d001 beq.n 8000f9a <loadConfig+0x5a>
|
|
//First start or configuration is corrupted
|
|
|
|
saveConfig(); //Save dafault config
|
|
8000f96: f000 f813 bl 8000fc0 <saveConfig>
|
|
} // else successfully read the configuration
|
|
|
|
needConfig = 0;
|
|
8000f9a: 4b08 ldr r3, [pc, #32] ; (8000fbc <loadConfig+0x7c>)
|
|
8000f9c: 2200 movs r2, #0
|
|
8000f9e: 701a strb r2, [r3, #0]
|
|
}
|
|
8000fa0: 46c0 nop ; (mov r8, r8)
|
|
8000fa2: 46bd mov sp, r7
|
|
8000fa4: b002 add sp, #8
|
|
8000fa6: bd80 pop {r7, pc}
|
|
8000fa8: 0800f800 .word 0x0800f800
|
|
8000fac: 20000210 .word 0x20000210
|
|
8000fb0: 0800f80f .word 0x0800f80f
|
|
8000fb4: 200000b4 .word 0x200000b4
|
|
8000fb8: 000a0200 .word 0x000a0200
|
|
8000fbc: 20000000 .word 0x20000000
|
|
|
|
08000fc0 <saveConfig>:
|
|
|
|
//save configuration to FLASH
|
|
volatile void saveConfig(void) {
|
|
8000fc0: b580 push {r7, lr}
|
|
8000fc2: b084 sub sp, #16
|
|
8000fc4: af00 add r7, sp, #0
|
|
static FLASH_EraseInitTypeDef EraseInitStruct;
|
|
uint32_t l_Address = CONF_FLASH_ADDR;
|
|
8000fc6: 4b39 ldr r3, [pc, #228] ; (80010ac <saveConfig+0xec>)
|
|
8000fc8: 60fb str r3, [r7, #12]
|
|
uint32_t l_Index = 0;
|
|
8000fca: 2300 movs r3, #0
|
|
8000fcc: 60bb str r3, [r7, #8]
|
|
uint32_t l_Error = 0;
|
|
8000fce: 2300 movs r3, #0
|
|
8000fd0: 607b str r3, [r7, #4]
|
|
|
|
//We need it to erase a page
|
|
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
|
|
8000fd2: 4b37 ldr r3, [pc, #220] ; (80010b0 <saveConfig+0xf0>)
|
|
8000fd4: 2202 movs r2, #2
|
|
8000fd6: 601a str r2, [r3, #0]
|
|
EraseInitStruct.Page = CONF_FLASH_PAGE;
|
|
8000fd8: 4b35 ldr r3, [pc, #212] ; (80010b0 <saveConfig+0xf0>)
|
|
8000fda: 221f movs r2, #31
|
|
8000fdc: 609a str r2, [r3, #8]
|
|
EraseInitStruct.NbPages = 1;
|
|
8000fde: 4b34 ldr r3, [pc, #208] ; (80010b0 <saveConfig+0xf0>)
|
|
8000fe0: 2201 movs r2, #1
|
|
8000fe2: 60da str r2, [r3, #12]
|
|
|
|
if (configuration.config.token != CONF_TOKEN) {
|
|
8000fe4: 4b33 ldr r3, [pc, #204] ; (80010b4 <saveConfig+0xf4>)
|
|
8000fe6: 681b ldr r3, [r3, #0]
|
|
8000fe8: 4a33 ldr r2, [pc, #204] ; (80010b8 <saveConfig+0xf8>)
|
|
8000fea: 4293 cmp r3, r2
|
|
8000fec: d013 beq.n 8001016 <saveConfig+0x56>
|
|
//first start
|
|
//Nullify the struct
|
|
memset(configuration.data64, 0, sizeof(configuration.data64));
|
|
8000fee: 4b31 ldr r3, [pc, #196] ; (80010b4 <saveConfig+0xf4>)
|
|
8000ff0: 2210 movs r2, #16
|
|
8000ff2: 2100 movs r1, #0
|
|
8000ff4: 0018 movs r0, r3
|
|
8000ff6: f005 fbbb bl 8006770 <memset>
|
|
//set default values
|
|
configuration.config.token = CONF_TOKEN;
|
|
8000ffa: 4b2e ldr r3, [pc, #184] ; (80010b4 <saveConfig+0xf4>)
|
|
8000ffc: 4a2e ldr r2, [pc, #184] ; (80010b8 <saveConfig+0xf8>)
|
|
8000ffe: 601a str r2, [r3, #0]
|
|
configuration.config.dist_on = DEFAULT_DIST_ON;
|
|
8001000: 4b2c ldr r3, [pc, #176] ; (80010b4 <saveConfig+0xf4>)
|
|
8001002: 22fa movs r2, #250 ; 0xfa
|
|
8001004: 0052 lsls r2, r2, #1
|
|
8001006: 809a strh r2, [r3, #4]
|
|
configuration.config.dist_off = DEFAULT_DIST_OFF;
|
|
8001008: 4b2a ldr r3, [pc, #168] ; (80010b4 <saveConfig+0xf4>)
|
|
800100a: 22fa movs r2, #250 ; 0xfa
|
|
800100c: 0092 lsls r2, r2, #2
|
|
800100e: 80da strh r2, [r3, #6]
|
|
|
|
configuration.sector.counter = 0;
|
|
8001010: 4b28 ldr r3, [pc, #160] ; (80010b4 <saveConfig+0xf4>)
|
|
8001012: 2200 movs r2, #0
|
|
8001014: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
if (configuration.config.dist_off > 1400) configuration.config.dist_off = 1400;
|
|
8001016: 4b27 ldr r3, [pc, #156] ; (80010b4 <saveConfig+0xf4>)
|
|
8001018: 88da ldrh r2, [r3, #6]
|
|
800101a: 23af movs r3, #175 ; 0xaf
|
|
800101c: 00db lsls r3, r3, #3
|
|
800101e: 429a cmp r2, r3
|
|
8001020: d903 bls.n 800102a <saveConfig+0x6a>
|
|
8001022: 4b24 ldr r3, [pc, #144] ; (80010b4 <saveConfig+0xf4>)
|
|
8001024: 22af movs r2, #175 ; 0xaf
|
|
8001026: 00d2 lsls r2, r2, #3
|
|
8001028: 80da strh r2, [r3, #6]
|
|
if (configuration.config.dist_on > configuration.config.dist_off) configuration.config.dist_on = configuration.config.dist_off;
|
|
800102a: 4b22 ldr r3, [pc, #136] ; (80010b4 <saveConfig+0xf4>)
|
|
800102c: 889a ldrh r2, [r3, #4]
|
|
800102e: 4b21 ldr r3, [pc, #132] ; (80010b4 <saveConfig+0xf4>)
|
|
8001030: 88db ldrh r3, [r3, #6]
|
|
8001032: 429a cmp r2, r3
|
|
8001034: d903 bls.n 800103e <saveConfig+0x7e>
|
|
8001036: 4b1f ldr r3, [pc, #124] ; (80010b4 <saveConfig+0xf4>)
|
|
8001038: 88da ldrh r2, [r3, #6]
|
|
800103a: 4b1e ldr r3, [pc, #120] ; (80010b4 <saveConfig+0xf4>)
|
|
800103c: 809a strh r2, [r3, #4]
|
|
configuration.sector.counter += 1;
|
|
800103e: 4b1d ldr r3, [pc, #116] ; (80010b4 <saveConfig+0xf4>)
|
|
8001040: 689b ldr r3, [r3, #8]
|
|
8001042: 1c5a adds r2, r3, #1
|
|
8001044: 4b1b ldr r3, [pc, #108] ; (80010b4 <saveConfig+0xf4>)
|
|
8001046: 609a str r2, [r3, #8]
|
|
configuration.sector.checksum = HAL_CRC_Calculate(&hcrc, configuration.data32, 2);
|
|
8001048: 491a ldr r1, [pc, #104] ; (80010b4 <saveConfig+0xf4>)
|
|
800104a: 4b1c ldr r3, [pc, #112] ; (80010bc <saveConfig+0xfc>)
|
|
800104c: 2202 movs r2, #2
|
|
800104e: 0018 movs r0, r3
|
|
8001050: f000 fffe bl 8002050 <HAL_CRC_Calculate>
|
|
8001054: 0002 movs r2, r0
|
|
8001056: 4b17 ldr r3, [pc, #92] ; (80010b4 <saveConfig+0xf4>)
|
|
8001058: 60da str r2, [r3, #12]
|
|
|
|
HAL_FLASH_Unlock(); //Unlock the FLASH
|
|
800105a: f001 f9cb bl 80023f4 <HAL_FLASH_Unlock>
|
|
HAL_FLASHEx_Erase(&EraseInitStruct, &l_Error); //Erase the page
|
|
800105e: 1d3a adds r2, r7, #4
|
|
8001060: 4b13 ldr r3, [pc, #76] ; (80010b0 <saveConfig+0xf0>)
|
|
8001062: 0011 movs r1, r2
|
|
8001064: 0018 movs r0, r3
|
|
8001066: f001 fa73 bl 8002550 <HAL_FLASHEx_Erase>
|
|
|
|
// Programming the config
|
|
|
|
while (l_Address < (CONF_FLASH_ADDR + FLASH_CONF_SIZE)) {
|
|
800106a: e011 b.n 8001090 <saveConfig+0xd0>
|
|
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, l_Address, configuration.data64[l_Index]) == HAL_OK) {
|
|
800106c: 4a11 ldr r2, [pc, #68] ; (80010b4 <saveConfig+0xf4>)
|
|
800106e: 68bb ldr r3, [r7, #8]
|
|
8001070: 00db lsls r3, r3, #3
|
|
8001072: 18d3 adds r3, r2, r3
|
|
8001074: 681a ldr r2, [r3, #0]
|
|
8001076: 685b ldr r3, [r3, #4]
|
|
8001078: 68f9 ldr r1, [r7, #12]
|
|
800107a: 2001 movs r0, #1
|
|
800107c: f001 f96c bl 8002358 <HAL_FLASH_Program>
|
|
8001080: 1e03 subs r3, r0, #0
|
|
8001082: d105 bne.n 8001090 <saveConfig+0xd0>
|
|
l_Index += 1;
|
|
8001084: 68bb ldr r3, [r7, #8]
|
|
8001086: 3301 adds r3, #1
|
|
8001088: 60bb str r3, [r7, #8]
|
|
l_Address += 8;
|
|
800108a: 68fb ldr r3, [r7, #12]
|
|
800108c: 3308 adds r3, #8
|
|
800108e: 60fb str r3, [r7, #12]
|
|
while (l_Address < (CONF_FLASH_ADDR + FLASH_CONF_SIZE)) {
|
|
8001090: 68fb ldr r3, [r7, #12]
|
|
8001092: 4a0b ldr r2, [pc, #44] ; (80010c0 <saveConfig+0x100>)
|
|
8001094: 4293 cmp r3, r2
|
|
8001096: d9e9 bls.n 800106c <saveConfig+0xac>
|
|
}
|
|
}
|
|
HAL_FLASH_Lock();
|
|
8001098: f001 f9d0 bl 800243c <HAL_FLASH_Lock>
|
|
HAL_Delay(50);
|
|
800109c: 2032 movs r0, #50 ; 0x32
|
|
800109e: f000 fe6f bl 8001d80 <HAL_Delay>
|
|
}
|
|
80010a2: 46c0 nop ; (mov r8, r8)
|
|
80010a4: 46bd mov sp, r7
|
|
80010a6: b004 add sp, #16
|
|
80010a8: bd80 pop {r7, pc}
|
|
80010aa: 46c0 nop ; (mov r8, r8)
|
|
80010ac: 0800f800 .word 0x0800f800
|
|
80010b0: 20000228 .word 0x20000228
|
|
80010b4: 20000210 .word 0x20000210
|
|
80010b8: 000a0200 .word 0x000a0200
|
|
80010bc: 200000b4 .word 0x200000b4
|
|
80010c0: 0800f80f .word 0x0800f80f
|
|
|
|
080010c4 <fastBlink>:
|
|
|
|
// Fast blink LEDs `count` times
|
|
void fastBlink(uint8_t count) {
|
|
80010c4: b580 push {r7, lr}
|
|
80010c6: b084 sub sp, #16
|
|
80010c8: af00 add r7, sp, #0
|
|
80010ca: 0002 movs r2, r0
|
|
80010cc: 1dfb adds r3, r7, #7
|
|
80010ce: 701a strb r2, [r3, #0]
|
|
uint8_t i;
|
|
|
|
setLightLevel(0);
|
|
80010d0: 2000 movs r0, #0
|
|
80010d2: f000 faf9 bl 80016c8 <setLightLevel>
|
|
for (i = 0; i < count; i++) {
|
|
80010d6: 230f movs r3, #15
|
|
80010d8: 18fb adds r3, r7, r3
|
|
80010da: 2200 movs r2, #0
|
|
80010dc: 701a strb r2, [r3, #0]
|
|
80010de: e011 b.n 8001104 <fastBlink+0x40>
|
|
setLightLevel(99);
|
|
80010e0: 2063 movs r0, #99 ; 0x63
|
|
80010e2: f000 faf1 bl 80016c8 <setLightLevel>
|
|
HAL_Delay(80);
|
|
80010e6: 2050 movs r0, #80 ; 0x50
|
|
80010e8: f000 fe4a bl 8001d80 <HAL_Delay>
|
|
setLightLevel(0);
|
|
80010ec: 2000 movs r0, #0
|
|
80010ee: f000 faeb bl 80016c8 <setLightLevel>
|
|
HAL_Delay(80);
|
|
80010f2: 2050 movs r0, #80 ; 0x50
|
|
80010f4: f000 fe44 bl 8001d80 <HAL_Delay>
|
|
for (i = 0; i < count; i++) {
|
|
80010f8: 210f movs r1, #15
|
|
80010fa: 187b adds r3, r7, r1
|
|
80010fc: 781a ldrb r2, [r3, #0]
|
|
80010fe: 187b adds r3, r7, r1
|
|
8001100: 3201 adds r2, #1
|
|
8001102: 701a strb r2, [r3, #0]
|
|
8001104: 230f movs r3, #15
|
|
8001106: 18fa adds r2, r7, r3
|
|
8001108: 1dfb adds r3, r7, #7
|
|
800110a: 7812 ldrb r2, [r2, #0]
|
|
800110c: 781b ldrb r3, [r3, #0]
|
|
800110e: 429a cmp r2, r3
|
|
8001110: d3e6 bcc.n 80010e0 <fastBlink+0x1c>
|
|
}
|
|
}
|
|
8001112: 46c0 nop ; (mov r8, r8)
|
|
8001114: 46c0 nop ; (mov r8, r8)
|
|
8001116: 46bd mov sp, r7
|
|
8001118: b004 add sp, #16
|
|
800111a: bd80 pop {r7, pc}
|
|
|
|
0800111c <configure>:
|
|
|
|
// Range configuration procedure (set on and off ranges)
|
|
void configure(void) {
|
|
800111c: b580 push {r7, lr}
|
|
800111e: af00 add r7, sp, #0
|
|
startConfig = 0;
|
|
8001120: 4b35 ldr r3, [pc, #212] ; (80011f8 <configure+0xdc>)
|
|
8001122: 2200 movs r2, #0
|
|
8001124: 701a strb r2, [r3, #0]
|
|
|
|
//Fast blink 3 times
|
|
needConfig = 1;
|
|
8001126: 4b35 ldr r3, [pc, #212] ; (80011fc <configure+0xe0>)
|
|
8001128: 2201 movs r2, #1
|
|
800112a: 701a strb r2, [r3, #0]
|
|
fastBlink(3);
|
|
800112c: 2003 movs r0, #3
|
|
800112e: f7ff ffc9 bl 80010c4 <fastBlink>
|
|
|
|
//Configure ON distance
|
|
needConfig = 1; // in case the button was touched during fast blinks
|
|
8001132: 4b32 ldr r3, [pc, #200] ; (80011fc <configure+0xe0>)
|
|
8001134: 2201 movs r2, #1
|
|
8001136: 701a strb r2, [r3, #0]
|
|
while (needConfig) {
|
|
8001138: e01a b.n 8001170 <configure+0x54>
|
|
HAL_Delay(250);
|
|
800113a: 20fa movs r0, #250 ; 0xfa
|
|
800113c: f000 fe20 bl 8001d80 <HAL_Delay>
|
|
if (curDist > 1400) setLightLevel(0);
|
|
8001140: 4b2f ldr r3, [pc, #188] ; (8001200 <configure+0xe4>)
|
|
8001142: 881a ldrh r2, [r3, #0]
|
|
8001144: 23af movs r3, #175 ; 0xaf
|
|
8001146: 00db lsls r3, r3, #3
|
|
8001148: 429a cmp r2, r3
|
|
800114a: d903 bls.n 8001154 <configure+0x38>
|
|
800114c: 2000 movs r0, #0
|
|
800114e: f000 fabb bl 80016c8 <setLightLevel>
|
|
8001152: e00d b.n 8001170 <configure+0x54>
|
|
// (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min
|
|
// (x - 0) * (50 - 0) / (1400 - 0) + 0
|
|
// x * 50 / 1400
|
|
// (99 - curDist * 99 / 2000) //old version
|
|
else setLightLevel((uint8_t)(50 - curDist * 50 / 1400));
|
|
8001154: 4b2a ldr r3, [pc, #168] ; (8001200 <configure+0xe4>)
|
|
8001156: 881b ldrh r3, [r3, #0]
|
|
8001158: 211c movs r1, #28
|
|
800115a: 0018 movs r0, r3
|
|
800115c: f7ff f85e bl 800021c <__divsi3>
|
|
8001160: 0003 movs r3, r0
|
|
8001162: b2db uxtb r3, r3
|
|
8001164: 2232 movs r2, #50 ; 0x32
|
|
8001166: 1ad3 subs r3, r2, r3
|
|
8001168: b2db uxtb r3, r3
|
|
800116a: 0018 movs r0, r3
|
|
800116c: f000 faac bl 80016c8 <setLightLevel>
|
|
while (needConfig) {
|
|
8001170: 4b22 ldr r3, [pc, #136] ; (80011fc <configure+0xe0>)
|
|
8001172: 781b ldrb r3, [r3, #0]
|
|
8001174: 2b00 cmp r3, #0
|
|
8001176: d1e0 bne.n 800113a <configure+0x1e>
|
|
}
|
|
configuration.config.dist_on = curDist;
|
|
8001178: 4b21 ldr r3, [pc, #132] ; (8001200 <configure+0xe4>)
|
|
800117a: 881a ldrh r2, [r3, #0]
|
|
800117c: 4b21 ldr r3, [pc, #132] ; (8001204 <configure+0xe8>)
|
|
800117e: 809a strh r2, [r3, #4]
|
|
|
|
//Fast blink 2 times
|
|
needConfig = 1;
|
|
8001180: 4b1e ldr r3, [pc, #120] ; (80011fc <configure+0xe0>)
|
|
8001182: 2201 movs r2, #1
|
|
8001184: 701a strb r2, [r3, #0]
|
|
fastBlink(2);
|
|
8001186: 2002 movs r0, #2
|
|
8001188: f7ff ff9c bl 80010c4 <fastBlink>
|
|
|
|
//Configure OFF distance
|
|
needConfig = 1; // in case the button was touched during fast blinks
|
|
800118c: 4b1b ldr r3, [pc, #108] ; (80011fc <configure+0xe0>)
|
|
800118e: 2201 movs r2, #1
|
|
8001190: 701a strb r2, [r3, #0]
|
|
while (needConfig) {
|
|
8001192: e01a b.n 80011ca <configure+0xae>
|
|
HAL_Delay(250);
|
|
8001194: 20fa movs r0, #250 ; 0xfa
|
|
8001196: f000 fdf3 bl 8001d80 <HAL_Delay>
|
|
if (curDist > 1400) setLightLevel(0);
|
|
800119a: 4b19 ldr r3, [pc, #100] ; (8001200 <configure+0xe4>)
|
|
800119c: 881a ldrh r2, [r3, #0]
|
|
800119e: 23af movs r3, #175 ; 0xaf
|
|
80011a0: 00db lsls r3, r3, #3
|
|
80011a2: 429a cmp r2, r3
|
|
80011a4: d903 bls.n 80011ae <configure+0x92>
|
|
80011a6: 2000 movs r0, #0
|
|
80011a8: f000 fa8e bl 80016c8 <setLightLevel>
|
|
80011ac: e00d b.n 80011ca <configure+0xae>
|
|
else setLightLevel((uint8_t)(50 - curDist * 50 / 1400));
|
|
80011ae: 4b14 ldr r3, [pc, #80] ; (8001200 <configure+0xe4>)
|
|
80011b0: 881b ldrh r3, [r3, #0]
|
|
80011b2: 211c movs r1, #28
|
|
80011b4: 0018 movs r0, r3
|
|
80011b6: f7ff f831 bl 800021c <__divsi3>
|
|
80011ba: 0003 movs r3, r0
|
|
80011bc: b2db uxtb r3, r3
|
|
80011be: 2232 movs r2, #50 ; 0x32
|
|
80011c0: 1ad3 subs r3, r2, r3
|
|
80011c2: b2db uxtb r3, r3
|
|
80011c4: 0018 movs r0, r3
|
|
80011c6: f000 fa7f bl 80016c8 <setLightLevel>
|
|
while (needConfig) {
|
|
80011ca: 4b0c ldr r3, [pc, #48] ; (80011fc <configure+0xe0>)
|
|
80011cc: 781b ldrb r3, [r3, #0]
|
|
80011ce: 2b00 cmp r3, #0
|
|
80011d0: d1e0 bne.n 8001194 <configure+0x78>
|
|
}
|
|
configuration.config.dist_off = curDist;
|
|
80011d2: 4b0b ldr r3, [pc, #44] ; (8001200 <configure+0xe4>)
|
|
80011d4: 881a ldrh r2, [r3, #0]
|
|
80011d6: 4b0b ldr r3, [pc, #44] ; (8001204 <configure+0xe8>)
|
|
80011d8: 80da strh r2, [r3, #6]
|
|
|
|
saveConfig();
|
|
80011da: f7ff fef1 bl 8000fc0 <saveConfig>
|
|
|
|
//Fast blink 5 times
|
|
needConfig = 1;
|
|
80011de: 4b07 ldr r3, [pc, #28] ; (80011fc <configure+0xe0>)
|
|
80011e0: 2201 movs r2, #1
|
|
80011e2: 701a strb r2, [r3, #0]
|
|
fastBlink(5);
|
|
80011e4: 2005 movs r0, #5
|
|
80011e6: f7ff ff6d bl 80010c4 <fastBlink>
|
|
|
|
needConfig = 0;
|
|
80011ea: 4b04 ldr r3, [pc, #16] ; (80011fc <configure+0xe0>)
|
|
80011ec: 2200 movs r2, #0
|
|
80011ee: 701a strb r2, [r3, #0]
|
|
}
|
|
80011f0: 46c0 nop ; (mov r8, r8)
|
|
80011f2: 46bd mov sp, r7
|
|
80011f4: bd80 pop {r7, pc}
|
|
80011f6: 46c0 nop ; (mov r8, r8)
|
|
80011f8: 20000226 .word 0x20000226
|
|
80011fc: 20000000 .word 0x20000000
|
|
8001200: 20000222 .word 0x20000222
|
|
8001204: 20000210 .word 0x20000210
|
|
|
|
08001208 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8001208: b580 push {r7, lr}
|
|
800120a: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
800120c: f000 fd32 bl 8001c74 <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8001210: f000 f844 bl 800129c <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8001214: f000 f9d6 bl 80015c4 <MX_GPIO_Init>
|
|
MX_I2C1_Init();
|
|
8001218: f000 f8c2 bl 80013a0 <MX_I2C1_Init>
|
|
MX_TIM3_Init();
|
|
800121c: f000 f900 bl 8001420 <MX_TIM3_Init>
|
|
MX_TIM17_Init();
|
|
8001220: f000 f9a6 bl 8001570 <MX_TIM17_Init>
|
|
MX_CRC_Init();
|
|
8001224: f000 f898 bl 8001358 <MX_CRC_Init>
|
|
MX_TIM16_Init();
|
|
8001228: f000 f978 bl 800151c <MX_TIM16_Init>
|
|
|
|
// TIM3 - PWM timer
|
|
// TIM16 - ticks timer (10Hz - 100ms)
|
|
// TIM17 - timer for light fading
|
|
|
|
loadConfig();
|
|
800122c: f7ff fe88 bl 8000f40 <loadConfig>
|
|
|
|
// Set IO timeout for range sensor
|
|
setTimeout(250);
|
|
8001230: 20fa movs r0, #250 ; 0xfa
|
|
8001232: f005 f843 bl 80062bc <setTimeout>
|
|
|
|
TOF_Ready = initVL53L0X(1);
|
|
8001236: 2001 movs r0, #1
|
|
8001238: f004 fb60 bl 80058fc <initVL53L0X>
|
|
800123c: 0003 movs r3, r0
|
|
800123e: 001a movs r2, r3
|
|
8001240: 4b12 ldr r3, [pc, #72] ; (800128c <main+0x84>)
|
|
8001242: 701a strb r2, [r3, #0]
|
|
if (TOF_Ready) {
|
|
8001244: 4b11 ldr r3, [pc, #68] ; (800128c <main+0x84>)
|
|
8001246: 781b ldrb r3, [r3, #0]
|
|
8001248: 2b00 cmp r3, #0
|
|
800124a: d008 beq.n 800125e <main+0x56>
|
|
// lower the return signal rate limit (default is 0.25 MCPS)
|
|
// setSignalRateLimit(0.1);
|
|
// increase laser pulse periods (defaults are 14 and 10 PCLKs)
|
|
// setVcselPulsePeriod(VcselPeriodPreRange, 18);
|
|
// setVcselPulsePeriod(VcselPeriodFinalRange, 14);
|
|
setMeasurementTimingBudget( 500 * 1000UL ); // integrate over 500 ms per measurement
|
|
800124c: 4b10 ldr r3, [pc, #64] ; (8001290 <main+0x88>)
|
|
800124e: 0018 movs r0, r3
|
|
8001250: f004 fde8 bl 8005e24 <setMeasurementTimingBudget>
|
|
|
|
// Start measurements every second
|
|
startContinuous(1000);
|
|
8001254: 23fa movs r3, #250 ; 0xfa
|
|
8001256: 009b lsls r3, r3, #2
|
|
8001258: 0018 movs r0, r3
|
|
800125a: f004 ff5d bl 8006118 <startContinuous>
|
|
}
|
|
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1);
|
|
800125e: 4b0d ldr r3, [pc, #52] ; (8001294 <main+0x8c>)
|
|
8001260: 2100 movs r1, #0
|
|
8001262: 0018 movs r0, r3
|
|
8001264: f003 f9c8 bl 80045f8 <HAL_TIM_PWM_Start>
|
|
|
|
// Fast-blink 10 times to indicate range sensor error
|
|
if (!TOF_Ready) {
|
|
8001268: 4b08 ldr r3, [pc, #32] ; (800128c <main+0x84>)
|
|
800126a: 781b ldrb r3, [r3, #0]
|
|
800126c: 2b00 cmp r3, #0
|
|
800126e: d102 bne.n 8001276 <main+0x6e>
|
|
fastBlink(10);
|
|
8001270: 200a movs r0, #10
|
|
8001272: f7ff ff27 bl 80010c4 <fastBlink>
|
|
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
if (startConfig) {
|
|
8001276: 4b08 ldr r3, [pc, #32] ; (8001298 <main+0x90>)
|
|
8001278: 781b ldrb r3, [r3, #0]
|
|
800127a: 2b00 cmp r3, #0
|
|
800127c: d001 beq.n 8001282 <main+0x7a>
|
|
configure();
|
|
800127e: f7ff ff4d bl 800111c <configure>
|
|
}
|
|
|
|
HAL_Delay(100);
|
|
8001282: 2064 movs r0, #100 ; 0x64
|
|
8001284: f000 fd7c bl 8001d80 <HAL_Delay>
|
|
if (startConfig) {
|
|
8001288: e7f5 b.n 8001276 <main+0x6e>
|
|
800128a: 46c0 nop ; (mov r8, r8)
|
|
800128c: 20000220 .word 0x20000220
|
|
8001290: 0007a120 .word 0x0007a120
|
|
8001294: 2000012c .word 0x2000012c
|
|
8001298: 20000226 .word 0x20000226
|
|
|
|
0800129c <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
800129c: b590 push {r4, r7, lr}
|
|
800129e: b093 sub sp, #76 ; 0x4c
|
|
80012a0: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
80012a2: 2410 movs r4, #16
|
|
80012a4: 193b adds r3, r7, r4
|
|
80012a6: 0018 movs r0, r3
|
|
80012a8: 2338 movs r3, #56 ; 0x38
|
|
80012aa: 001a movs r2, r3
|
|
80012ac: 2100 movs r1, #0
|
|
80012ae: f005 fa5f bl 8006770 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
80012b2: 003b movs r3, r7
|
|
80012b4: 0018 movs r0, r3
|
|
80012b6: 2310 movs r3, #16
|
|
80012b8: 001a movs r2, r3
|
|
80012ba: 2100 movs r1, #0
|
|
80012bc: f005 fa58 bl 8006770 <memset>
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
80012c0: 2380 movs r3, #128 ; 0x80
|
|
80012c2: 009b lsls r3, r3, #2
|
|
80012c4: 0018 movs r0, r3
|
|
80012c6: f002 f9ff bl 80036c8 <HAL_PWREx_ControlVoltageScaling>
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
|
80012ca: 193b adds r3, r7, r4
|
|
80012cc: 2202 movs r2, #2
|
|
80012ce: 601a str r2, [r3, #0]
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
80012d0: 193b adds r3, r7, r4
|
|
80012d2: 2280 movs r2, #128 ; 0x80
|
|
80012d4: 0052 lsls r2, r2, #1
|
|
80012d6: 60da str r2, [r3, #12]
|
|
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
|
|
80012d8: 0021 movs r1, r4
|
|
80012da: 187b adds r3, r7, r1
|
|
80012dc: 2200 movs r2, #0
|
|
80012de: 611a str r2, [r3, #16]
|
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
|
80012e0: 187b adds r3, r7, r1
|
|
80012e2: 2240 movs r2, #64 ; 0x40
|
|
80012e4: 615a str r2, [r3, #20]
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
80012e6: 187b adds r3, r7, r1
|
|
80012e8: 2202 movs r2, #2
|
|
80012ea: 61da str r2, [r3, #28]
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
|
80012ec: 187b adds r3, r7, r1
|
|
80012ee: 2202 movs r2, #2
|
|
80012f0: 621a str r2, [r3, #32]
|
|
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
|
|
80012f2: 187b adds r3, r7, r1
|
|
80012f4: 2200 movs r2, #0
|
|
80012f6: 625a str r2, [r3, #36] ; 0x24
|
|
RCC_OscInitStruct.PLL.PLLN = 8;
|
|
80012f8: 187b adds r3, r7, r1
|
|
80012fa: 2208 movs r2, #8
|
|
80012fc: 629a str r2, [r3, #40] ; 0x28
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
80012fe: 187b adds r3, r7, r1
|
|
8001300: 2280 movs r2, #128 ; 0x80
|
|
8001302: 0292 lsls r2, r2, #10
|
|
8001304: 62da str r2, [r3, #44] ; 0x2c
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
|
8001306: 187b adds r3, r7, r1
|
|
8001308: 2280 movs r2, #128 ; 0x80
|
|
800130a: 0492 lsls r2, r2, #18
|
|
800130c: 631a str r2, [r3, #48] ; 0x30
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
|
800130e: 187b adds r3, r7, r1
|
|
8001310: 2280 movs r2, #128 ; 0x80
|
|
8001312: 0592 lsls r2, r2, #22
|
|
8001314: 635a str r2, [r3, #52] ; 0x34
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8001316: 187b adds r3, r7, r1
|
|
8001318: 0018 movs r0, r3
|
|
800131a: f002 fa15 bl 8003748 <HAL_RCC_OscConfig>
|
|
800131e: 1e03 subs r3, r0, #0
|
|
8001320: d001 beq.n 8001326 <SystemClock_Config+0x8a>
|
|
{
|
|
Error_Handler();
|
|
8001322: f000 faf3 bl 800190c <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
8001326: 003b movs r3, r7
|
|
8001328: 2207 movs r2, #7
|
|
800132a: 601a str r2, [r3, #0]
|
|
|RCC_CLOCKTYPE_PCLK1;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
800132c: 003b movs r3, r7
|
|
800132e: 2202 movs r2, #2
|
|
8001330: 605a str r2, [r3, #4]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8001332: 003b movs r3, r7
|
|
8001334: 2200 movs r2, #0
|
|
8001336: 609a str r2, [r3, #8]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
8001338: 003b movs r3, r7
|
|
800133a: 2200 movs r2, #0
|
|
800133c: 60da str r2, [r3, #12]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
|
|
800133e: 003b movs r3, r7
|
|
8001340: 2102 movs r1, #2
|
|
8001342: 0018 movs r0, r3
|
|
8001344: f002 fd1a bl 8003d7c <HAL_RCC_ClockConfig>
|
|
8001348: 1e03 subs r3, r0, #0
|
|
800134a: d001 beq.n 8001350 <SystemClock_Config+0xb4>
|
|
{
|
|
Error_Handler();
|
|
800134c: f000 fade bl 800190c <Error_Handler>
|
|
}
|
|
}
|
|
8001350: 46c0 nop ; (mov r8, r8)
|
|
8001352: 46bd mov sp, r7
|
|
8001354: b013 add sp, #76 ; 0x4c
|
|
8001356: bd90 pop {r4, r7, pc}
|
|
|
|
08001358 <MX_CRC_Init>:
|
|
* @brief CRC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_CRC_Init(void)
|
|
{
|
|
8001358: b580 push {r7, lr}
|
|
800135a: af00 add r7, sp, #0
|
|
/* USER CODE END CRC_Init 0 */
|
|
|
|
/* USER CODE BEGIN CRC_Init 1 */
|
|
|
|
/* USER CODE END CRC_Init 1 */
|
|
hcrc.Instance = CRC;
|
|
800135c: 4b0e ldr r3, [pc, #56] ; (8001398 <MX_CRC_Init+0x40>)
|
|
800135e: 4a0f ldr r2, [pc, #60] ; (800139c <MX_CRC_Init+0x44>)
|
|
8001360: 601a str r2, [r3, #0]
|
|
hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
|
|
8001362: 4b0d ldr r3, [pc, #52] ; (8001398 <MX_CRC_Init+0x40>)
|
|
8001364: 2200 movs r2, #0
|
|
8001366: 711a strb r2, [r3, #4]
|
|
hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE;
|
|
8001368: 4b0b ldr r3, [pc, #44] ; (8001398 <MX_CRC_Init+0x40>)
|
|
800136a: 2200 movs r2, #0
|
|
800136c: 715a strb r2, [r3, #5]
|
|
hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE;
|
|
800136e: 4b0a ldr r3, [pc, #40] ; (8001398 <MX_CRC_Init+0x40>)
|
|
8001370: 2200 movs r2, #0
|
|
8001372: 615a str r2, [r3, #20]
|
|
hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE;
|
|
8001374: 4b08 ldr r3, [pc, #32] ; (8001398 <MX_CRC_Init+0x40>)
|
|
8001376: 2200 movs r2, #0
|
|
8001378: 619a str r2, [r3, #24]
|
|
hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
|
|
800137a: 4b07 ldr r3, [pc, #28] ; (8001398 <MX_CRC_Init+0x40>)
|
|
800137c: 2201 movs r2, #1
|
|
800137e: 621a str r2, [r3, #32]
|
|
if (HAL_CRC_Init(&hcrc) != HAL_OK)
|
|
8001380: 4b05 ldr r3, [pc, #20] ; (8001398 <MX_CRC_Init+0x40>)
|
|
8001382: 0018 movs r0, r3
|
|
8001384: f000 fdfe bl 8001f84 <HAL_CRC_Init>
|
|
8001388: 1e03 subs r3, r0, #0
|
|
800138a: d001 beq.n 8001390 <MX_CRC_Init+0x38>
|
|
{
|
|
Error_Handler();
|
|
800138c: f000 fabe bl 800190c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN CRC_Init 2 */
|
|
|
|
/* USER CODE END CRC_Init 2 */
|
|
|
|
}
|
|
8001390: 46c0 nop ; (mov r8, r8)
|
|
8001392: 46bd mov sp, r7
|
|
8001394: bd80 pop {r7, pc}
|
|
8001396: 46c0 nop ; (mov r8, r8)
|
|
8001398: 200000b4 .word 0x200000b4
|
|
800139c: 40023000 .word 0x40023000
|
|
|
|
080013a0 <MX_I2C1_Init>:
|
|
* @brief I2C1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C1_Init(void)
|
|
{
|
|
80013a0: b580 push {r7, lr}
|
|
80013a2: af00 add r7, sp, #0
|
|
/* USER CODE END I2C1_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C1_Init 1 */
|
|
|
|
/* USER CODE END I2C1_Init 1 */
|
|
hi2c1.Instance = I2C1;
|
|
80013a4: 4b1b ldr r3, [pc, #108] ; (8001414 <MX_I2C1_Init+0x74>)
|
|
80013a6: 4a1c ldr r2, [pc, #112] ; (8001418 <MX_I2C1_Init+0x78>)
|
|
80013a8: 601a str r2, [r3, #0]
|
|
hi2c1.Init.Timing = 0x10707DBC;
|
|
80013aa: 4b1a ldr r3, [pc, #104] ; (8001414 <MX_I2C1_Init+0x74>)
|
|
80013ac: 4a1b ldr r2, [pc, #108] ; (800141c <MX_I2C1_Init+0x7c>)
|
|
80013ae: 605a str r2, [r3, #4]
|
|
hi2c1.Init.OwnAddress1 = 0;
|
|
80013b0: 4b18 ldr r3, [pc, #96] ; (8001414 <MX_I2C1_Init+0x74>)
|
|
80013b2: 2200 movs r2, #0
|
|
80013b4: 609a str r2, [r3, #8]
|
|
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
80013b6: 4b17 ldr r3, [pc, #92] ; (8001414 <MX_I2C1_Init+0x74>)
|
|
80013b8: 2201 movs r2, #1
|
|
80013ba: 60da str r2, [r3, #12]
|
|
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
80013bc: 4b15 ldr r3, [pc, #84] ; (8001414 <MX_I2C1_Init+0x74>)
|
|
80013be: 2200 movs r2, #0
|
|
80013c0: 611a str r2, [r3, #16]
|
|
hi2c1.Init.OwnAddress2 = 0;
|
|
80013c2: 4b14 ldr r3, [pc, #80] ; (8001414 <MX_I2C1_Init+0x74>)
|
|
80013c4: 2200 movs r2, #0
|
|
80013c6: 615a str r2, [r3, #20]
|
|
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
|
|
80013c8: 4b12 ldr r3, [pc, #72] ; (8001414 <MX_I2C1_Init+0x74>)
|
|
80013ca: 2200 movs r2, #0
|
|
80013cc: 619a str r2, [r3, #24]
|
|
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
80013ce: 4b11 ldr r3, [pc, #68] ; (8001414 <MX_I2C1_Init+0x74>)
|
|
80013d0: 2200 movs r2, #0
|
|
80013d2: 61da str r2, [r3, #28]
|
|
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
80013d4: 4b0f ldr r3, [pc, #60] ; (8001414 <MX_I2C1_Init+0x74>)
|
|
80013d6: 2200 movs r2, #0
|
|
80013d8: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
|
|
80013da: 4b0e ldr r3, [pc, #56] ; (8001414 <MX_I2C1_Init+0x74>)
|
|
80013dc: 0018 movs r0, r3
|
|
80013de: f001 fb07 bl 80029f0 <HAL_I2C_Init>
|
|
80013e2: 1e03 subs r3, r0, #0
|
|
80013e4: d001 beq.n 80013ea <MX_I2C1_Init+0x4a>
|
|
{
|
|
Error_Handler();
|
|
80013e6: f000 fa91 bl 800190c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Analogue filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
|
80013ea: 4b0a ldr r3, [pc, #40] ; (8001414 <MX_I2C1_Init+0x74>)
|
|
80013ec: 2100 movs r1, #0
|
|
80013ee: 0018 movs r0, r3
|
|
80013f0: f002 f8d2 bl 8003598 <HAL_I2CEx_ConfigAnalogFilter>
|
|
80013f4: 1e03 subs r3, r0, #0
|
|
80013f6: d001 beq.n 80013fc <MX_I2C1_Init+0x5c>
|
|
{
|
|
Error_Handler();
|
|
80013f8: f000 fa88 bl 800190c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Digital filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
|
|
80013fc: 4b05 ldr r3, [pc, #20] ; (8001414 <MX_I2C1_Init+0x74>)
|
|
80013fe: 2100 movs r1, #0
|
|
8001400: 0018 movs r0, r3
|
|
8001402: f002 f915 bl 8003630 <HAL_I2CEx_ConfigDigitalFilter>
|
|
8001406: 1e03 subs r3, r0, #0
|
|
8001408: d001 beq.n 800140e <MX_I2C1_Init+0x6e>
|
|
{
|
|
Error_Handler();
|
|
800140a: f000 fa7f bl 800190c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C1_Init 2 */
|
|
|
|
/* USER CODE END I2C1_Init 2 */
|
|
|
|
}
|
|
800140e: 46c0 nop ; (mov r8, r8)
|
|
8001410: 46bd mov sp, r7
|
|
8001412: bd80 pop {r7, pc}
|
|
8001414: 200000d8 .word 0x200000d8
|
|
8001418: 40005400 .word 0x40005400
|
|
800141c: 10707dbc .word 0x10707dbc
|
|
|
|
08001420 <MX_TIM3_Init>:
|
|
* @brief TIM3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM3_Init(void)
|
|
{
|
|
8001420: b580 push {r7, lr}
|
|
8001422: b08e sub sp, #56 ; 0x38
|
|
8001424: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM3_Init 0 */
|
|
|
|
/* USER CODE END TIM3_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
8001426: 2328 movs r3, #40 ; 0x28
|
|
8001428: 18fb adds r3, r7, r3
|
|
800142a: 0018 movs r0, r3
|
|
800142c: 2310 movs r3, #16
|
|
800142e: 001a movs r2, r3
|
|
8001430: 2100 movs r1, #0
|
|
8001432: f005 f99d bl 8006770 <memset>
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8001436: 231c movs r3, #28
|
|
8001438: 18fb adds r3, r7, r3
|
|
800143a: 0018 movs r0, r3
|
|
800143c: 230c movs r3, #12
|
|
800143e: 001a movs r2, r3
|
|
8001440: 2100 movs r1, #0
|
|
8001442: f005 f995 bl 8006770 <memset>
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
8001446: 003b movs r3, r7
|
|
8001448: 0018 movs r0, r3
|
|
800144a: 231c movs r3, #28
|
|
800144c: 001a movs r2, r3
|
|
800144e: 2100 movs r1, #0
|
|
8001450: f005 f98e bl 8006770 <memset>
|
|
|
|
/* USER CODE BEGIN TIM3_Init 1 */
|
|
|
|
/* USER CODE END TIM3_Init 1 */
|
|
htim3.Instance = TIM3;
|
|
8001454: 4b2f ldr r3, [pc, #188] ; (8001514 <MX_TIM3_Init+0xf4>)
|
|
8001456: 4a30 ldr r2, [pc, #192] ; (8001518 <MX_TIM3_Init+0xf8>)
|
|
8001458: 601a str r2, [r3, #0]
|
|
htim3.Init.Prescaler = 20-1;
|
|
800145a: 4b2e ldr r3, [pc, #184] ; (8001514 <MX_TIM3_Init+0xf4>)
|
|
800145c: 2213 movs r2, #19
|
|
800145e: 605a str r2, [r3, #4]
|
|
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8001460: 4b2c ldr r3, [pc, #176] ; (8001514 <MX_TIM3_Init+0xf4>)
|
|
8001462: 2200 movs r2, #0
|
|
8001464: 609a str r2, [r3, #8]
|
|
htim3.Init.Period = 100-1;
|
|
8001466: 4b2b ldr r3, [pc, #172] ; (8001514 <MX_TIM3_Init+0xf4>)
|
|
8001468: 2263 movs r2, #99 ; 0x63
|
|
800146a: 60da str r2, [r3, #12]
|
|
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
800146c: 4b29 ldr r3, [pc, #164] ; (8001514 <MX_TIM3_Init+0xf4>)
|
|
800146e: 2200 movs r2, #0
|
|
8001470: 611a str r2, [r3, #16]
|
|
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8001472: 4b28 ldr r3, [pc, #160] ; (8001514 <MX_TIM3_Init+0xf4>)
|
|
8001474: 2200 movs r2, #0
|
|
8001476: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
|
|
8001478: 4b26 ldr r3, [pc, #152] ; (8001514 <MX_TIM3_Init+0xf4>)
|
|
800147a: 0018 movs r0, r3
|
|
800147c: f002 ff82 bl 8004384 <HAL_TIM_Base_Init>
|
|
8001480: 1e03 subs r3, r0, #0
|
|
8001482: d001 beq.n 8001488 <MX_TIM3_Init+0x68>
|
|
{
|
|
Error_Handler();
|
|
8001484: f000 fa42 bl 800190c <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
8001488: 2128 movs r1, #40 ; 0x28
|
|
800148a: 187b adds r3, r7, r1
|
|
800148c: 2280 movs r2, #128 ; 0x80
|
|
800148e: 0152 lsls r2, r2, #5
|
|
8001490: 601a str r2, [r3, #0]
|
|
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
|
|
8001492: 187a adds r2, r7, r1
|
|
8001494: 4b1f ldr r3, [pc, #124] ; (8001514 <MX_TIM3_Init+0xf4>)
|
|
8001496: 0011 movs r1, r2
|
|
8001498: 0018 movs r0, r3
|
|
800149a: f003 fbbd bl 8004c18 <HAL_TIM_ConfigClockSource>
|
|
800149e: 1e03 subs r3, r0, #0
|
|
80014a0: d001 beq.n 80014a6 <MX_TIM3_Init+0x86>
|
|
{
|
|
Error_Handler();
|
|
80014a2: f000 fa33 bl 800190c <Error_Handler>
|
|
}
|
|
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
|
|
80014a6: 4b1b ldr r3, [pc, #108] ; (8001514 <MX_TIM3_Init+0xf4>)
|
|
80014a8: 0018 movs r0, r3
|
|
80014aa: f003 f845 bl 8004538 <HAL_TIM_PWM_Init>
|
|
80014ae: 1e03 subs r3, r0, #0
|
|
80014b0: d001 beq.n 80014b6 <MX_TIM3_Init+0x96>
|
|
{
|
|
Error_Handler();
|
|
80014b2: f000 fa2b bl 800190c <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
80014b6: 211c movs r1, #28
|
|
80014b8: 187b adds r3, r7, r1
|
|
80014ba: 2200 movs r2, #0
|
|
80014bc: 601a str r2, [r3, #0]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
80014be: 187b adds r3, r7, r1
|
|
80014c0: 2200 movs r2, #0
|
|
80014c2: 609a str r2, [r3, #8]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
|
80014c4: 187a adds r2, r7, r1
|
|
80014c6: 4b13 ldr r3, [pc, #76] ; (8001514 <MX_TIM3_Init+0xf4>)
|
|
80014c8: 0011 movs r1, r2
|
|
80014ca: 0018 movs r0, r3
|
|
80014cc: f004 f86c bl 80055a8 <HAL_TIMEx_MasterConfigSynchronization>
|
|
80014d0: 1e03 subs r3, r0, #0
|
|
80014d2: d001 beq.n 80014d8 <MX_TIM3_Init+0xb8>
|
|
{
|
|
Error_Handler();
|
|
80014d4: f000 fa1a bl 800190c <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
|
80014d8: 003b movs r3, r7
|
|
80014da: 2260 movs r2, #96 ; 0x60
|
|
80014dc: 601a str r2, [r3, #0]
|
|
sConfigOC.Pulse = 0;
|
|
80014de: 003b movs r3, r7
|
|
80014e0: 2200 movs r2, #0
|
|
80014e2: 605a str r2, [r3, #4]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
80014e4: 003b movs r3, r7
|
|
80014e6: 2200 movs r2, #0
|
|
80014e8: 609a str r2, [r3, #8]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
80014ea: 003b movs r3, r7
|
|
80014ec: 2200 movs r2, #0
|
|
80014ee: 611a str r2, [r3, #16]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
80014f0: 0039 movs r1, r7
|
|
80014f2: 4b08 ldr r3, [pc, #32] ; (8001514 <MX_TIM3_Init+0xf4>)
|
|
80014f4: 2200 movs r2, #0
|
|
80014f6: 0018 movs r0, r3
|
|
80014f8: f003 fa8e bl 8004a18 <HAL_TIM_PWM_ConfigChannel>
|
|
80014fc: 1e03 subs r3, r0, #0
|
|
80014fe: d001 beq.n 8001504 <MX_TIM3_Init+0xe4>
|
|
{
|
|
Error_Handler();
|
|
8001500: f000 fa04 bl 800190c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM3_Init 2 */
|
|
|
|
/* USER CODE END TIM3_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim3);
|
|
8001504: 4b03 ldr r3, [pc, #12] ; (8001514 <MX_TIM3_Init+0xf4>)
|
|
8001506: 0018 movs r0, r3
|
|
8001508: f000 fb06 bl 8001b18 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
800150c: 46c0 nop ; (mov r8, r8)
|
|
800150e: 46bd mov sp, r7
|
|
8001510: b00e add sp, #56 ; 0x38
|
|
8001512: bd80 pop {r7, pc}
|
|
8001514: 2000012c .word 0x2000012c
|
|
8001518: 40000400 .word 0x40000400
|
|
|
|
0800151c <MX_TIM16_Init>:
|
|
* @brief TIM16 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM16_Init(void)
|
|
{
|
|
800151c: b580 push {r7, lr}
|
|
800151e: af00 add r7, sp, #0
|
|
/* USER CODE END TIM16_Init 0 */
|
|
|
|
/* USER CODE BEGIN TIM16_Init 1 */
|
|
|
|
/* USER CODE END TIM16_Init 1 */
|
|
htim16.Instance = TIM16;
|
|
8001520: 4b0f ldr r3, [pc, #60] ; (8001560 <MX_TIM16_Init+0x44>)
|
|
8001522: 4a10 ldr r2, [pc, #64] ; (8001564 <MX_TIM16_Init+0x48>)
|
|
8001524: 601a str r2, [r3, #0]
|
|
htim16.Init.Prescaler = 640-1;
|
|
8001526: 4b0e ldr r3, [pc, #56] ; (8001560 <MX_TIM16_Init+0x44>)
|
|
8001528: 4a0f ldr r2, [pc, #60] ; (8001568 <MX_TIM16_Init+0x4c>)
|
|
800152a: 605a str r2, [r3, #4]
|
|
htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
800152c: 4b0c ldr r3, [pc, #48] ; (8001560 <MX_TIM16_Init+0x44>)
|
|
800152e: 2200 movs r2, #0
|
|
8001530: 609a str r2, [r3, #8]
|
|
htim16.Init.Period = 10000-1;
|
|
8001532: 4b0b ldr r3, [pc, #44] ; (8001560 <MX_TIM16_Init+0x44>)
|
|
8001534: 4a0d ldr r2, [pc, #52] ; (800156c <MX_TIM16_Init+0x50>)
|
|
8001536: 60da str r2, [r3, #12]
|
|
htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8001538: 4b09 ldr r3, [pc, #36] ; (8001560 <MX_TIM16_Init+0x44>)
|
|
800153a: 2200 movs r2, #0
|
|
800153c: 611a str r2, [r3, #16]
|
|
htim16.Init.RepetitionCounter = 0;
|
|
800153e: 4b08 ldr r3, [pc, #32] ; (8001560 <MX_TIM16_Init+0x44>)
|
|
8001540: 2200 movs r2, #0
|
|
8001542: 615a str r2, [r3, #20]
|
|
htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8001544: 4b06 ldr r3, [pc, #24] ; (8001560 <MX_TIM16_Init+0x44>)
|
|
8001546: 2200 movs r2, #0
|
|
8001548: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim16) != HAL_OK)
|
|
800154a: 4b05 ldr r3, [pc, #20] ; (8001560 <MX_TIM16_Init+0x44>)
|
|
800154c: 0018 movs r0, r3
|
|
800154e: f002 ff19 bl 8004384 <HAL_TIM_Base_Init>
|
|
8001552: 1e03 subs r3, r0, #0
|
|
8001554: d001 beq.n 800155a <MX_TIM16_Init+0x3e>
|
|
{
|
|
Error_Handler();
|
|
8001556: f000 f9d9 bl 800190c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM16_Init 2 */
|
|
|
|
/* USER CODE END TIM16_Init 2 */
|
|
|
|
}
|
|
800155a: 46c0 nop ; (mov r8, r8)
|
|
800155c: 46bd mov sp, r7
|
|
800155e: bd80 pop {r7, pc}
|
|
8001560: 20000178 .word 0x20000178
|
|
8001564: 40014400 .word 0x40014400
|
|
8001568: 0000027f .word 0x0000027f
|
|
800156c: 0000270f .word 0x0000270f
|
|
|
|
08001570 <MX_TIM17_Init>:
|
|
* @brief TIM17 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM17_Init(void)
|
|
{
|
|
8001570: b580 push {r7, lr}
|
|
8001572: af00 add r7, sp, #0
|
|
/* USER CODE END TIM17_Init 0 */
|
|
|
|
/* USER CODE BEGIN TIM17_Init 1 */
|
|
|
|
/* USER CODE END TIM17_Init 1 */
|
|
htim17.Instance = TIM17;
|
|
8001574: 4b10 ldr r3, [pc, #64] ; (80015b8 <MX_TIM17_Init+0x48>)
|
|
8001576: 4a11 ldr r2, [pc, #68] ; (80015bc <MX_TIM17_Init+0x4c>)
|
|
8001578: 601a str r2, [r3, #0]
|
|
htim17.Init.Prescaler = 320-1;
|
|
800157a: 4b0f ldr r3, [pc, #60] ; (80015b8 <MX_TIM17_Init+0x48>)
|
|
800157c: 2240 movs r2, #64 ; 0x40
|
|
800157e: 32ff adds r2, #255 ; 0xff
|
|
8001580: 605a str r2, [r3, #4]
|
|
htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8001582: 4b0d ldr r3, [pc, #52] ; (80015b8 <MX_TIM17_Init+0x48>)
|
|
8001584: 2200 movs r2, #0
|
|
8001586: 609a str r2, [r3, #8]
|
|
htim17.Init.Period = 3000-1;
|
|
8001588: 4b0b ldr r3, [pc, #44] ; (80015b8 <MX_TIM17_Init+0x48>)
|
|
800158a: 4a0d ldr r2, [pc, #52] ; (80015c0 <MX_TIM17_Init+0x50>)
|
|
800158c: 60da str r2, [r3, #12]
|
|
htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
800158e: 4b0a ldr r3, [pc, #40] ; (80015b8 <MX_TIM17_Init+0x48>)
|
|
8001590: 2200 movs r2, #0
|
|
8001592: 611a str r2, [r3, #16]
|
|
htim17.Init.RepetitionCounter = 0;
|
|
8001594: 4b08 ldr r3, [pc, #32] ; (80015b8 <MX_TIM17_Init+0x48>)
|
|
8001596: 2200 movs r2, #0
|
|
8001598: 615a str r2, [r3, #20]
|
|
htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
|
|
800159a: 4b07 ldr r3, [pc, #28] ; (80015b8 <MX_TIM17_Init+0x48>)
|
|
800159c: 2280 movs r2, #128 ; 0x80
|
|
800159e: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim17) != HAL_OK)
|
|
80015a0: 4b05 ldr r3, [pc, #20] ; (80015b8 <MX_TIM17_Init+0x48>)
|
|
80015a2: 0018 movs r0, r3
|
|
80015a4: f002 feee bl 8004384 <HAL_TIM_Base_Init>
|
|
80015a8: 1e03 subs r3, r0, #0
|
|
80015aa: d001 beq.n 80015b0 <MX_TIM17_Init+0x40>
|
|
{
|
|
Error_Handler();
|
|
80015ac: f000 f9ae bl 800190c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM17_Init 2 */
|
|
|
|
/* USER CODE END TIM17_Init 2 */
|
|
|
|
}
|
|
80015b0: 46c0 nop ; (mov r8, r8)
|
|
80015b2: 46bd mov sp, r7
|
|
80015b4: bd80 pop {r7, pc}
|
|
80015b6: 46c0 nop ; (mov r8, r8)
|
|
80015b8: 200001c4 .word 0x200001c4
|
|
80015bc: 40014800 .word 0x40014800
|
|
80015c0: 00000bb7 .word 0x00000bb7
|
|
|
|
080015c4 <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
80015c4: b590 push {r4, r7, lr}
|
|
80015c6: b089 sub sp, #36 ; 0x24
|
|
80015c8: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80015ca: 240c movs r4, #12
|
|
80015cc: 193b adds r3, r7, r4
|
|
80015ce: 0018 movs r0, r3
|
|
80015d0: 2314 movs r3, #20
|
|
80015d2: 001a movs r2, r3
|
|
80015d4: 2100 movs r1, #0
|
|
80015d6: f005 f8cb bl 8006770 <memset>
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80015da: 4b39 ldr r3, [pc, #228] ; (80016c0 <MX_GPIO_Init+0xfc>)
|
|
80015dc: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
80015de: 4b38 ldr r3, [pc, #224] ; (80016c0 <MX_GPIO_Init+0xfc>)
|
|
80015e0: 2101 movs r1, #1
|
|
80015e2: 430a orrs r2, r1
|
|
80015e4: 635a str r2, [r3, #52] ; 0x34
|
|
80015e6: 4b36 ldr r3, [pc, #216] ; (80016c0 <MX_GPIO_Init+0xfc>)
|
|
80015e8: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
80015ea: 2201 movs r2, #1
|
|
80015ec: 4013 ands r3, r2
|
|
80015ee: 60bb str r3, [r7, #8]
|
|
80015f0: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
80015f2: 4b33 ldr r3, [pc, #204] ; (80016c0 <MX_GPIO_Init+0xfc>)
|
|
80015f4: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
80015f6: 4b32 ldr r3, [pc, #200] ; (80016c0 <MX_GPIO_Init+0xfc>)
|
|
80015f8: 2104 movs r1, #4
|
|
80015fa: 430a orrs r2, r1
|
|
80015fc: 635a str r2, [r3, #52] ; 0x34
|
|
80015fe: 4b30 ldr r3, [pc, #192] ; (80016c0 <MX_GPIO_Init+0xfc>)
|
|
8001600: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8001602: 2204 movs r2, #4
|
|
8001604: 4013 ands r3, r2
|
|
8001606: 607b str r3, [r7, #4]
|
|
8001608: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
800160a: 4b2d ldr r3, [pc, #180] ; (80016c0 <MX_GPIO_Init+0xfc>)
|
|
800160c: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
800160e: 4b2c ldr r3, [pc, #176] ; (80016c0 <MX_GPIO_Init+0xfc>)
|
|
8001610: 2102 movs r1, #2
|
|
8001612: 430a orrs r2, r1
|
|
8001614: 635a str r2, [r3, #52] ; 0x34
|
|
8001616: 4b2a ldr r3, [pc, #168] ; (80016c0 <MX_GPIO_Init+0xfc>)
|
|
8001618: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
800161a: 2202 movs r2, #2
|
|
800161c: 4013 ands r3, r2
|
|
800161e: 603b str r3, [r7, #0]
|
|
8001620: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(Sens_SHUT_GPIO_Port, Sens_SHUT_Pin, GPIO_PIN_SET);
|
|
8001622: 4b28 ldr r3, [pc, #160] ; (80016c4 <MX_GPIO_Init+0x100>)
|
|
8001624: 2201 movs r2, #1
|
|
8001626: 2110 movs r1, #16
|
|
8001628: 0018 movs r0, r3
|
|
800162a: f001 f999 bl 8002960 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin : Btn_INT_Pin */
|
|
GPIO_InitStruct.Pin = Btn_INT_Pin;
|
|
800162e: 193b adds r3, r7, r4
|
|
8001630: 2201 movs r2, #1
|
|
8001632: 601a str r2, [r3, #0]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
|
|
8001634: 193b adds r3, r7, r4
|
|
8001636: 22c4 movs r2, #196 ; 0xc4
|
|
8001638: 0392 lsls r2, r2, #14
|
|
800163a: 605a str r2, [r3, #4]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800163c: 193b adds r3, r7, r4
|
|
800163e: 2200 movs r2, #0
|
|
8001640: 609a str r2, [r3, #8]
|
|
HAL_GPIO_Init(Btn_INT_GPIO_Port, &GPIO_InitStruct);
|
|
8001642: 193a adds r2, r7, r4
|
|
8001644: 23a0 movs r3, #160 ; 0xa0
|
|
8001646: 05db lsls r3, r3, #23
|
|
8001648: 0011 movs r1, r2
|
|
800164a: 0018 movs r0, r3
|
|
800164c: f001 f824 bl 8002698 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : Sens_SHUT_Pin */
|
|
GPIO_InitStruct.Pin = Sens_SHUT_Pin;
|
|
8001650: 193b adds r3, r7, r4
|
|
8001652: 2210 movs r2, #16
|
|
8001654: 601a str r2, [r3, #0]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001656: 193b adds r3, r7, r4
|
|
8001658: 2201 movs r2, #1
|
|
800165a: 605a str r2, [r3, #4]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
800165c: 193b adds r3, r7, r4
|
|
800165e: 2201 movs r2, #1
|
|
8001660: 609a str r2, [r3, #8]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
8001662: 193b adds r3, r7, r4
|
|
8001664: 2202 movs r2, #2
|
|
8001666: 60da str r2, [r3, #12]
|
|
HAL_GPIO_Init(Sens_SHUT_GPIO_Port, &GPIO_InitStruct);
|
|
8001668: 193b adds r3, r7, r4
|
|
800166a: 4a16 ldr r2, [pc, #88] ; (80016c4 <MX_GPIO_Init+0x100>)
|
|
800166c: 0019 movs r1, r3
|
|
800166e: 0010 movs r0, r2
|
|
8001670: f001 f812 bl 8002698 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : Sens_INT_Pin */
|
|
GPIO_InitStruct.Pin = Sens_INT_Pin;
|
|
8001674: 0021 movs r1, r4
|
|
8001676: 187b adds r3, r7, r1
|
|
8001678: 2220 movs r2, #32
|
|
800167a: 601a str r2, [r3, #0]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
|
|
800167c: 187b adds r3, r7, r1
|
|
800167e: 2284 movs r2, #132 ; 0x84
|
|
8001680: 0392 lsls r2, r2, #14
|
|
8001682: 605a str r2, [r3, #4]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001684: 187b adds r3, r7, r1
|
|
8001686: 2200 movs r2, #0
|
|
8001688: 609a str r2, [r3, #8]
|
|
HAL_GPIO_Init(Sens_INT_GPIO_Port, &GPIO_InitStruct);
|
|
800168a: 187b adds r3, r7, r1
|
|
800168c: 4a0d ldr r2, [pc, #52] ; (80016c4 <MX_GPIO_Init+0x100>)
|
|
800168e: 0019 movs r1, r3
|
|
8001690: 0010 movs r0, r2
|
|
8001692: f001 f801 bl 8002698 <HAL_GPIO_Init>
|
|
|
|
/* EXTI interrupt init*/
|
|
HAL_NVIC_SetPriority(EXTI0_1_IRQn, 0, 0);
|
|
8001696: 2200 movs r2, #0
|
|
8001698: 2100 movs r1, #0
|
|
800169a: 2005 movs r0, #5
|
|
800169c: f000 fc40 bl 8001f20 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(EXTI0_1_IRQn);
|
|
80016a0: 2005 movs r0, #5
|
|
80016a2: f000 fc52 bl 8001f4a <HAL_NVIC_EnableIRQ>
|
|
|
|
HAL_NVIC_SetPriority(EXTI4_15_IRQn, 0, 0);
|
|
80016a6: 2200 movs r2, #0
|
|
80016a8: 2100 movs r1, #0
|
|
80016aa: 2007 movs r0, #7
|
|
80016ac: f000 fc38 bl 8001f20 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(EXTI4_15_IRQn);
|
|
80016b0: 2007 movs r0, #7
|
|
80016b2: f000 fc4a bl 8001f4a <HAL_NVIC_EnableIRQ>
|
|
|
|
}
|
|
80016b6: 46c0 nop ; (mov r8, r8)
|
|
80016b8: 46bd mov sp, r7
|
|
80016ba: b009 add sp, #36 ; 0x24
|
|
80016bc: bd90 pop {r4, r7, pc}
|
|
80016be: 46c0 nop ; (mov r8, r8)
|
|
80016c0: 40021000 .word 0x40021000
|
|
80016c4: 50000400 .word 0x50000400
|
|
|
|
080016c8 <setLightLevel>:
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
|
|
volatile void setLightLevel(uint8_t level) {
|
|
80016c8: b580 push {r7, lr}
|
|
80016ca: b082 sub sp, #8
|
|
80016cc: af00 add r7, sp, #0
|
|
80016ce: 0002 movs r2, r0
|
|
80016d0: 1dfb adds r3, r7, #7
|
|
80016d2: 701a strb r2, [r3, #0]
|
|
if (level > 99) level = 99;
|
|
80016d4: 1dfb adds r3, r7, #7
|
|
80016d6: 781b ldrb r3, [r3, #0]
|
|
80016d8: 2b63 cmp r3, #99 ; 0x63
|
|
80016da: d902 bls.n 80016e2 <setLightLevel+0x1a>
|
|
80016dc: 1dfb adds r3, r7, #7
|
|
80016de: 2263 movs r2, #99 ; 0x63
|
|
80016e0: 701a strb r2, [r3, #0]
|
|
curLightLevel = level;
|
|
80016e2: 4b06 ldr r3, [pc, #24] ; (80016fc <setLightLevel+0x34>)
|
|
80016e4: 1dfa adds r2, r7, #7
|
|
80016e6: 7812 ldrb r2, [r2, #0]
|
|
80016e8: 701a strb r2, [r3, #0]
|
|
|
|
TIM3->CCR1 = curLightLevel;
|
|
80016ea: 4b04 ldr r3, [pc, #16] ; (80016fc <setLightLevel+0x34>)
|
|
80016ec: 781a ldrb r2, [r3, #0]
|
|
80016ee: 4b04 ldr r3, [pc, #16] ; (8001700 <setLightLevel+0x38>)
|
|
80016f0: 635a str r2, [r3, #52] ; 0x34
|
|
}
|
|
80016f2: 46c0 nop ; (mov r8, r8)
|
|
80016f4: 46bd mov sp, r7
|
|
80016f6: b002 add sp, #8
|
|
80016f8: bd80 pop {r7, pc}
|
|
80016fa: 46c0 nop ; (mov r8, r8)
|
|
80016fc: 20000221 .word 0x20000221
|
|
8001700: 40000400 .word 0x40000400
|
|
|
|
08001704 <HAL_GPIO_EXTI_Rising_Callback>:
|
|
|
|
void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) {
|
|
8001704: b580 push {r7, lr}
|
|
8001706: b082 sub sp, #8
|
|
8001708: af00 add r7, sp, #0
|
|
800170a: 0002 movs r2, r0
|
|
800170c: 1dbb adds r3, r7, #6
|
|
800170e: 801a strh r2, [r3, #0]
|
|
// Start counting "ticks" when the sense-button is pressed
|
|
if (GPIO_Pin == Btn_INT_Pin) {
|
|
8001710: 1dbb adds r3, r7, #6
|
|
8001712: 881b ldrh r3, [r3, #0]
|
|
8001714: 2b01 cmp r3, #1
|
|
8001716: d106 bne.n 8001726 <HAL_GPIO_EXTI_Rising_Callback+0x22>
|
|
btn_ticks = 0;
|
|
8001718: 4b05 ldr r3, [pc, #20] ; (8001730 <HAL_GPIO_EXTI_Rising_Callback+0x2c>)
|
|
800171a: 2200 movs r2, #0
|
|
800171c: 801a strh r2, [r3, #0]
|
|
HAL_TIM_Base_Start_IT(&htim16);
|
|
800171e: 4b05 ldr r3, [pc, #20] ; (8001734 <HAL_GPIO_EXTI_Rising_Callback+0x30>)
|
|
8001720: 0018 movs r0, r3
|
|
8001722: f002 fe87 bl 8004434 <HAL_TIM_Base_Start_IT>
|
|
}
|
|
}
|
|
8001726: 46c0 nop ; (mov r8, r8)
|
|
8001728: 46bd mov sp, r7
|
|
800172a: b002 add sp, #8
|
|
800172c: bd80 pop {r7, pc}
|
|
800172e: 46c0 nop ; (mov r8, r8)
|
|
8001730: 20000224 .word 0x20000224
|
|
8001734: 20000178 .word 0x20000178
|
|
|
|
08001738 <HAL_GPIO_EXTI_Falling_Callback>:
|
|
|
|
|
|
void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) {
|
|
8001738: b5b0 push {r4, r5, r7, lr}
|
|
800173a: b084 sub sp, #16
|
|
800173c: af00 add r7, sp, #0
|
|
800173e: 0002 movs r2, r0
|
|
8001740: 1dbb adds r3, r7, #6
|
|
8001742: 801a strh r2, [r3, #0]
|
|
uint16_t dist;
|
|
|
|
// Range sensor interrupt (measurement is done)
|
|
if (TOF_Ready && GPIO_Pin == Sens_INT_Pin) {
|
|
8001744: 4b3f ldr r3, [pc, #252] ; (8001844 <HAL_GPIO_EXTI_Falling_Callback+0x10c>)
|
|
8001746: 781b ldrb r3, [r3, #0]
|
|
8001748: 2b00 cmp r3, #0
|
|
800174a: d044 beq.n 80017d6 <HAL_GPIO_EXTI_Falling_Callback+0x9e>
|
|
800174c: 1dbb adds r3, r7, #6
|
|
800174e: 881b ldrh r3, [r3, #0]
|
|
8001750: 2b20 cmp r3, #32
|
|
8001752: d140 bne.n 80017d6 <HAL_GPIO_EXTI_Falling_Callback+0x9e>
|
|
dist = readRangeContinuousMillimeters(0);
|
|
8001754: 250e movs r5, #14
|
|
8001756: 197c adds r4, r7, r5
|
|
8001758: 2000 movs r0, #0
|
|
800175a: f004 fd27 bl 80061ac <readRangeContinuousMillimeters>
|
|
800175e: 0003 movs r3, r0
|
|
8001760: 8023 strh r3, [r4, #0]
|
|
if (dist < 1400) curDist = dist;
|
|
8001762: 0029 movs r1, r5
|
|
8001764: 187b adds r3, r7, r1
|
|
8001766: 881a ldrh r2, [r3, #0]
|
|
8001768: 23af movs r3, #175 ; 0xaf
|
|
800176a: 00db lsls r3, r3, #3
|
|
800176c: 429a cmp r2, r3
|
|
800176e: d204 bcs.n 800177a <HAL_GPIO_EXTI_Falling_Callback+0x42>
|
|
8001770: 4b35 ldr r3, [pc, #212] ; (8001848 <HAL_GPIO_EXTI_Falling_Callback+0x110>)
|
|
8001772: 187a adds r2, r7, r1
|
|
8001774: 8812 ldrh r2, [r2, #0]
|
|
8001776: 801a strh r2, [r3, #0]
|
|
8001778: e003 b.n 8001782 <HAL_GPIO_EXTI_Falling_Callback+0x4a>
|
|
else curDist = 1400;
|
|
800177a: 4b33 ldr r3, [pc, #204] ; (8001848 <HAL_GPIO_EXTI_Falling_Callback+0x110>)
|
|
800177c: 22af movs r2, #175 ; 0xaf
|
|
800177e: 00d2 lsls r2, r2, #3
|
|
8001780: 801a strh r2, [r3, #0]
|
|
if (!needConfig && !manualOn) {
|
|
8001782: 4b32 ldr r3, [pc, #200] ; (800184c <HAL_GPIO_EXTI_Falling_Callback+0x114>)
|
|
8001784: 781b ldrb r3, [r3, #0]
|
|
8001786: 2b00 cmp r3, #0
|
|
8001788: d125 bne.n 80017d6 <HAL_GPIO_EXTI_Falling_Callback+0x9e>
|
|
800178a: 4b31 ldr r3, [pc, #196] ; (8001850 <HAL_GPIO_EXTI_Falling_Callback+0x118>)
|
|
800178c: 781b ldrb r3, [r3, #0]
|
|
800178e: 2b00 cmp r3, #0
|
|
8001790: d121 bne.n 80017d6 <HAL_GPIO_EXTI_Falling_Callback+0x9e>
|
|
if (curDist <= configuration.config.dist_on && curLightLevel < 90) {
|
|
8001792: 4b30 ldr r3, [pc, #192] ; (8001854 <HAL_GPIO_EXTI_Falling_Callback+0x11c>)
|
|
8001794: 889a ldrh r2, [r3, #4]
|
|
8001796: 4b2c ldr r3, [pc, #176] ; (8001848 <HAL_GPIO_EXTI_Falling_Callback+0x110>)
|
|
8001798: 881b ldrh r3, [r3, #0]
|
|
800179a: 429a cmp r2, r3
|
|
800179c: d30a bcc.n 80017b4 <HAL_GPIO_EXTI_Falling_Callback+0x7c>
|
|
800179e: 4b2e ldr r3, [pc, #184] ; (8001858 <HAL_GPIO_EXTI_Falling_Callback+0x120>)
|
|
80017a0: 781b ldrb r3, [r3, #0]
|
|
80017a2: 2b59 cmp r3, #89 ; 0x59
|
|
80017a4: d806 bhi.n 80017b4 <HAL_GPIO_EXTI_Falling_Callback+0x7c>
|
|
//Turn on the lights
|
|
dLevel = 2;
|
|
80017a6: 4b2d ldr r3, [pc, #180] ; (800185c <HAL_GPIO_EXTI_Falling_Callback+0x124>)
|
|
80017a8: 2202 movs r2, #2
|
|
80017aa: 701a strb r2, [r3, #0]
|
|
HAL_TIM_Base_Start_IT(&htim17);
|
|
80017ac: 4b2c ldr r3, [pc, #176] ; (8001860 <HAL_GPIO_EXTI_Falling_Callback+0x128>)
|
|
80017ae: 0018 movs r0, r3
|
|
80017b0: f002 fe40 bl 8004434 <HAL_TIM_Base_Start_IT>
|
|
}
|
|
if (curDist >= configuration.config.dist_off && curLightLevel == 99) {
|
|
80017b4: 4b27 ldr r3, [pc, #156] ; (8001854 <HAL_GPIO_EXTI_Falling_Callback+0x11c>)
|
|
80017b6: 88da ldrh r2, [r3, #6]
|
|
80017b8: 4b23 ldr r3, [pc, #140] ; (8001848 <HAL_GPIO_EXTI_Falling_Callback+0x110>)
|
|
80017ba: 881b ldrh r3, [r3, #0]
|
|
80017bc: 429a cmp r2, r3
|
|
80017be: d80a bhi.n 80017d6 <HAL_GPIO_EXTI_Falling_Callback+0x9e>
|
|
80017c0: 4b25 ldr r3, [pc, #148] ; (8001858 <HAL_GPIO_EXTI_Falling_Callback+0x120>)
|
|
80017c2: 781b ldrb r3, [r3, #0]
|
|
80017c4: 2b63 cmp r3, #99 ; 0x63
|
|
80017c6: d106 bne.n 80017d6 <HAL_GPIO_EXTI_Falling_Callback+0x9e>
|
|
//Turn off the lights
|
|
dLevel = -1;
|
|
80017c8: 4b24 ldr r3, [pc, #144] ; (800185c <HAL_GPIO_EXTI_Falling_Callback+0x124>)
|
|
80017ca: 22ff movs r2, #255 ; 0xff
|
|
80017cc: 701a strb r2, [r3, #0]
|
|
HAL_TIM_Base_Start_IT(&htim17);
|
|
80017ce: 4b24 ldr r3, [pc, #144] ; (8001860 <HAL_GPIO_EXTI_Falling_Callback+0x128>)
|
|
80017d0: 0018 movs r0, r3
|
|
80017d2: f002 fe2f bl 8004434 <HAL_TIM_Base_Start_IT>
|
|
}
|
|
}
|
|
}
|
|
|
|
// The sense-button is released
|
|
if (GPIO_Pin == Btn_INT_Pin) {
|
|
80017d6: 1dbb adds r3, r7, #6
|
|
80017d8: 881b ldrh r3, [r3, #0]
|
|
80017da: 2b01 cmp r3, #1
|
|
80017dc: d12d bne.n 800183a <HAL_GPIO_EXTI_Falling_Callback+0x102>
|
|
HAL_TIM_Base_Stop_IT(&htim16);
|
|
80017de: 4b21 ldr r3, [pc, #132] ; (8001864 <HAL_GPIO_EXTI_Falling_Callback+0x12c>)
|
|
80017e0: 0018 movs r0, r3
|
|
80017e2: f002 fe7b bl 80044dc <HAL_TIM_Base_Stop_IT>
|
|
if (btn_ticks < 60) {
|
|
80017e6: 4b20 ldr r3, [pc, #128] ; (8001868 <HAL_GPIO_EXTI_Falling_Callback+0x130>)
|
|
80017e8: 881b ldrh r3, [r3, #0]
|
|
80017ea: 2b3b cmp r3, #59 ; 0x3b
|
|
80017ec: d825 bhi.n 800183a <HAL_GPIO_EXTI_Falling_Callback+0x102>
|
|
// Button was not held for more than 6 seconds
|
|
if (needConfig) {
|
|
80017ee: 4b17 ldr r3, [pc, #92] ; (800184c <HAL_GPIO_EXTI_Falling_Callback+0x114>)
|
|
80017f0: 781b ldrb r3, [r3, #0]
|
|
80017f2: 2b00 cmp r3, #0
|
|
80017f4: d003 beq.n 80017fe <HAL_GPIO_EXTI_Falling_Callback+0xc6>
|
|
needConfig = 0;
|
|
80017f6: 4b15 ldr r3, [pc, #84] ; (800184c <HAL_GPIO_EXTI_Falling_Callback+0x114>)
|
|
80017f8: 2200 movs r2, #0
|
|
80017fa: 701a strb r2, [r3, #0]
|
|
}
|
|
setLightLevel(curLightLevel);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
80017fc: e01d b.n 800183a <HAL_GPIO_EXTI_Falling_Callback+0x102>
|
|
if (curLightLevel < 90){
|
|
80017fe: 4b16 ldr r3, [pc, #88] ; (8001858 <HAL_GPIO_EXTI_Falling_Callback+0x120>)
|
|
8001800: 781b ldrb r3, [r3, #0]
|
|
8001802: 2b59 cmp r3, #89 ; 0x59
|
|
8001804: d80a bhi.n 800181c <HAL_GPIO_EXTI_Falling_Callback+0xe4>
|
|
manualOn = 1;
|
|
8001806: 4b12 ldr r3, [pc, #72] ; (8001850 <HAL_GPIO_EXTI_Falling_Callback+0x118>)
|
|
8001808: 2201 movs r2, #1
|
|
800180a: 701a strb r2, [r3, #0]
|
|
dLevel = 2;
|
|
800180c: 4b13 ldr r3, [pc, #76] ; (800185c <HAL_GPIO_EXTI_Falling_Callback+0x124>)
|
|
800180e: 2202 movs r2, #2
|
|
8001810: 701a strb r2, [r3, #0]
|
|
HAL_TIM_Base_Start_IT(&htim17);
|
|
8001812: 4b13 ldr r3, [pc, #76] ; (8001860 <HAL_GPIO_EXTI_Falling_Callback+0x128>)
|
|
8001814: 0018 movs r0, r3
|
|
8001816: f002 fe0d bl 8004434 <HAL_TIM_Base_Start_IT>
|
|
800181a: e009 b.n 8001830 <HAL_GPIO_EXTI_Falling_Callback+0xf8>
|
|
manualOn = 0;
|
|
800181c: 4b0c ldr r3, [pc, #48] ; (8001850 <HAL_GPIO_EXTI_Falling_Callback+0x118>)
|
|
800181e: 2200 movs r2, #0
|
|
8001820: 701a strb r2, [r3, #0]
|
|
dLevel = -1;
|
|
8001822: 4b0e ldr r3, [pc, #56] ; (800185c <HAL_GPIO_EXTI_Falling_Callback+0x124>)
|
|
8001824: 22ff movs r2, #255 ; 0xff
|
|
8001826: 701a strb r2, [r3, #0]
|
|
HAL_TIM_Base_Start_IT(&htim17);
|
|
8001828: 4b0d ldr r3, [pc, #52] ; (8001860 <HAL_GPIO_EXTI_Falling_Callback+0x128>)
|
|
800182a: 0018 movs r0, r3
|
|
800182c: f002 fe02 bl 8004434 <HAL_TIM_Base_Start_IT>
|
|
setLightLevel(curLightLevel);
|
|
8001830: 4b09 ldr r3, [pc, #36] ; (8001858 <HAL_GPIO_EXTI_Falling_Callback+0x120>)
|
|
8001832: 781b ldrb r3, [r3, #0]
|
|
8001834: 0018 movs r0, r3
|
|
8001836: f7ff ff47 bl 80016c8 <setLightLevel>
|
|
}
|
|
800183a: 46c0 nop ; (mov r8, r8)
|
|
800183c: 46bd mov sp, r7
|
|
800183e: b004 add sp, #16
|
|
8001840: bdb0 pop {r4, r5, r7, pc}
|
|
8001842: 46c0 nop ; (mov r8, r8)
|
|
8001844: 20000220 .word 0x20000220
|
|
8001848: 20000222 .word 0x20000222
|
|
800184c: 20000000 .word 0x20000000
|
|
8001850: 20000227 .word 0x20000227
|
|
8001854: 20000210 .word 0x20000210
|
|
8001858: 20000221 .word 0x20000221
|
|
800185c: 20000001 .word 0x20000001
|
|
8001860: 200001c4 .word 0x200001c4
|
|
8001864: 20000178 .word 0x20000178
|
|
8001868: 20000224 .word 0x20000224
|
|
|
|
0800186c <HAL_TIM_PeriodElapsedCallback>:
|
|
|
|
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
|
|
800186c: b580 push {r7, lr}
|
|
800186e: b082 sub sp, #8
|
|
8001870: af00 add r7, sp, #0
|
|
8001872: 6078 str r0, [r7, #4]
|
|
if(htim->Instance == TIM16) { //check if the interrupt comes from TIM16
|
|
8001874: 687b ldr r3, [r7, #4]
|
|
8001876: 681b ldr r3, [r3, #0]
|
|
8001878: 4a1c ldr r2, [pc, #112] ; (80018ec <HAL_TIM_PeriodElapsedCallback+0x80>)
|
|
800187a: 4293 cmp r3, r2
|
|
800187c: d111 bne.n 80018a2 <HAL_TIM_PeriodElapsedCallback+0x36>
|
|
if (btn_ticks < 60) {
|
|
800187e: 4b1c ldr r3, [pc, #112] ; (80018f0 <HAL_TIM_PeriodElapsedCallback+0x84>)
|
|
8001880: 881b ldrh r3, [r3, #0]
|
|
8001882: 2b3b cmp r3, #59 ; 0x3b
|
|
8001884: d806 bhi.n 8001894 <HAL_TIM_PeriodElapsedCallback+0x28>
|
|
btn_ticks++;
|
|
8001886: 4b1a ldr r3, [pc, #104] ; (80018f0 <HAL_TIM_PeriodElapsedCallback+0x84>)
|
|
8001888: 881b ldrh r3, [r3, #0]
|
|
800188a: 3301 adds r3, #1
|
|
800188c: b29a uxth r2, r3
|
|
800188e: 4b18 ldr r3, [pc, #96] ; (80018f0 <HAL_TIM_PeriodElapsedCallback+0x84>)
|
|
8001890: 801a strh r2, [r3, #0]
|
|
8001892: e006 b.n 80018a2 <HAL_TIM_PeriodElapsedCallback+0x36>
|
|
} else { // the button is held for more than 6 seconds
|
|
HAL_TIM_Base_Stop_IT(&htim16);
|
|
8001894: 4b17 ldr r3, [pc, #92] ; (80018f4 <HAL_TIM_PeriodElapsedCallback+0x88>)
|
|
8001896: 0018 movs r0, r3
|
|
8001898: f002 fe20 bl 80044dc <HAL_TIM_Base_Stop_IT>
|
|
startConfig = 1;
|
|
800189c: 4b16 ldr r3, [pc, #88] ; (80018f8 <HAL_TIM_PeriodElapsedCallback+0x8c>)
|
|
800189e: 2201 movs r2, #1
|
|
80018a0: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
|
|
// Fade-in / fade-out animation
|
|
if(htim->Instance == TIM17) { //check if the interrupt comes from TIM17
|
|
80018a2: 687b ldr r3, [r7, #4]
|
|
80018a4: 681b ldr r3, [r3, #0]
|
|
80018a6: 4a15 ldr r2, [pc, #84] ; (80018fc <HAL_TIM_PeriodElapsedCallback+0x90>)
|
|
80018a8: 4293 cmp r3, r2
|
|
80018aa: d11a bne.n 80018e2 <HAL_TIM_PeriodElapsedCallback+0x76>
|
|
curLightLevel += dLevel;
|
|
80018ac: 4b14 ldr r3, [pc, #80] ; (8001900 <HAL_TIM_PeriodElapsedCallback+0x94>)
|
|
80018ae: 781a ldrb r2, [r3, #0]
|
|
80018b0: 4b14 ldr r3, [pc, #80] ; (8001904 <HAL_TIM_PeriodElapsedCallback+0x98>)
|
|
80018b2: 781b ldrb r3, [r3, #0]
|
|
80018b4: b25b sxtb r3, r3
|
|
80018b6: b2db uxtb r3, r3
|
|
80018b8: 18d3 adds r3, r2, r3
|
|
80018ba: b2da uxtb r2, r3
|
|
80018bc: 4b10 ldr r3, [pc, #64] ; (8001900 <HAL_TIM_PeriodElapsedCallback+0x94>)
|
|
80018be: 701a strb r2, [r3, #0]
|
|
setLightLevel(curLightLevel);
|
|
80018c0: 4b0f ldr r3, [pc, #60] ; (8001900 <HAL_TIM_PeriodElapsedCallback+0x94>)
|
|
80018c2: 781b ldrb r3, [r3, #0]
|
|
80018c4: 0018 movs r0, r3
|
|
80018c6: f7ff feff bl 80016c8 <setLightLevel>
|
|
if (curLightLevel >= 99 || curLightLevel <= 0) {
|
|
80018ca: 4b0d ldr r3, [pc, #52] ; (8001900 <HAL_TIM_PeriodElapsedCallback+0x94>)
|
|
80018cc: 781b ldrb r3, [r3, #0]
|
|
80018ce: 2b62 cmp r3, #98 ; 0x62
|
|
80018d0: d803 bhi.n 80018da <HAL_TIM_PeriodElapsedCallback+0x6e>
|
|
80018d2: 4b0b ldr r3, [pc, #44] ; (8001900 <HAL_TIM_PeriodElapsedCallback+0x94>)
|
|
80018d4: 781b ldrb r3, [r3, #0]
|
|
80018d6: 2b00 cmp r3, #0
|
|
80018d8: d103 bne.n 80018e2 <HAL_TIM_PeriodElapsedCallback+0x76>
|
|
HAL_TIM_Base_Stop_IT(&htim17);
|
|
80018da: 4b0b ldr r3, [pc, #44] ; (8001908 <HAL_TIM_PeriodElapsedCallback+0x9c>)
|
|
80018dc: 0018 movs r0, r3
|
|
80018de: f002 fdfd bl 80044dc <HAL_TIM_Base_Stop_IT>
|
|
}
|
|
}
|
|
}
|
|
80018e2: 46c0 nop ; (mov r8, r8)
|
|
80018e4: 46bd mov sp, r7
|
|
80018e6: b002 add sp, #8
|
|
80018e8: bd80 pop {r7, pc}
|
|
80018ea: 46c0 nop ; (mov r8, r8)
|
|
80018ec: 40014400 .word 0x40014400
|
|
80018f0: 20000224 .word 0x20000224
|
|
80018f4: 20000178 .word 0x20000178
|
|
80018f8: 20000226 .word 0x20000226
|
|
80018fc: 40014800 .word 0x40014800
|
|
8001900: 20000221 .word 0x20000221
|
|
8001904: 20000001 .word 0x20000001
|
|
8001908: 200001c4 .word 0x200001c4
|
|
|
|
0800190c <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
800190c: b580 push {r7, lr}
|
|
800190e: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8001910: b672 cpsid i
|
|
}
|
|
8001912: 46c0 nop ; (mov r8, r8)
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8001914: e7fe b.n 8001914 <Error_Handler+0x8>
|
|
...
|
|
|
|
08001918 <HAL_MspInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8001918: b580 push {r7, lr}
|
|
800191a: b082 sub sp, #8
|
|
800191c: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
800191e: 4b0f ldr r3, [pc, #60] ; (800195c <HAL_MspInit+0x44>)
|
|
8001920: 6c1a ldr r2, [r3, #64] ; 0x40
|
|
8001922: 4b0e ldr r3, [pc, #56] ; (800195c <HAL_MspInit+0x44>)
|
|
8001924: 2101 movs r1, #1
|
|
8001926: 430a orrs r2, r1
|
|
8001928: 641a str r2, [r3, #64] ; 0x40
|
|
800192a: 4b0c ldr r3, [pc, #48] ; (800195c <HAL_MspInit+0x44>)
|
|
800192c: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800192e: 2201 movs r2, #1
|
|
8001930: 4013 ands r3, r2
|
|
8001932: 607b str r3, [r7, #4]
|
|
8001934: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8001936: 4b09 ldr r3, [pc, #36] ; (800195c <HAL_MspInit+0x44>)
|
|
8001938: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
800193a: 4b08 ldr r3, [pc, #32] ; (800195c <HAL_MspInit+0x44>)
|
|
800193c: 2180 movs r1, #128 ; 0x80
|
|
800193e: 0549 lsls r1, r1, #21
|
|
8001940: 430a orrs r2, r1
|
|
8001942: 63da str r2, [r3, #60] ; 0x3c
|
|
8001944: 4b05 ldr r3, [pc, #20] ; (800195c <HAL_MspInit+0x44>)
|
|
8001946: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
8001948: 2380 movs r3, #128 ; 0x80
|
|
800194a: 055b lsls r3, r3, #21
|
|
800194c: 4013 ands r3, r2
|
|
800194e: 603b str r3, [r7, #0]
|
|
8001950: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8001952: 46c0 nop ; (mov r8, r8)
|
|
8001954: 46bd mov sp, r7
|
|
8001956: b002 add sp, #8
|
|
8001958: bd80 pop {r7, pc}
|
|
800195a: 46c0 nop ; (mov r8, r8)
|
|
800195c: 40021000 .word 0x40021000
|
|
|
|
08001960 <HAL_CRC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hcrc: CRC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
|
|
{
|
|
8001960: b580 push {r7, lr}
|
|
8001962: b084 sub sp, #16
|
|
8001964: af00 add r7, sp, #0
|
|
8001966: 6078 str r0, [r7, #4]
|
|
if(hcrc->Instance==CRC)
|
|
8001968: 687b ldr r3, [r7, #4]
|
|
800196a: 681b ldr r3, [r3, #0]
|
|
800196c: 4a0a ldr r2, [pc, #40] ; (8001998 <HAL_CRC_MspInit+0x38>)
|
|
800196e: 4293 cmp r3, r2
|
|
8001970: d10d bne.n 800198e <HAL_CRC_MspInit+0x2e>
|
|
{
|
|
/* USER CODE BEGIN CRC_MspInit 0 */
|
|
|
|
/* USER CODE END CRC_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_CRC_CLK_ENABLE();
|
|
8001972: 4b0a ldr r3, [pc, #40] ; (800199c <HAL_CRC_MspInit+0x3c>)
|
|
8001974: 6b9a ldr r2, [r3, #56] ; 0x38
|
|
8001976: 4b09 ldr r3, [pc, #36] ; (800199c <HAL_CRC_MspInit+0x3c>)
|
|
8001978: 2180 movs r1, #128 ; 0x80
|
|
800197a: 0149 lsls r1, r1, #5
|
|
800197c: 430a orrs r2, r1
|
|
800197e: 639a str r2, [r3, #56] ; 0x38
|
|
8001980: 4b06 ldr r3, [pc, #24] ; (800199c <HAL_CRC_MspInit+0x3c>)
|
|
8001982: 6b9a ldr r2, [r3, #56] ; 0x38
|
|
8001984: 2380 movs r3, #128 ; 0x80
|
|
8001986: 015b lsls r3, r3, #5
|
|
8001988: 4013 ands r3, r2
|
|
800198a: 60fb str r3, [r7, #12]
|
|
800198c: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN CRC_MspInit 1 */
|
|
|
|
/* USER CODE END CRC_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
800198e: 46c0 nop ; (mov r8, r8)
|
|
8001990: 46bd mov sp, r7
|
|
8001992: b004 add sp, #16
|
|
8001994: bd80 pop {r7, pc}
|
|
8001996: 46c0 nop ; (mov r8, r8)
|
|
8001998: 40023000 .word 0x40023000
|
|
800199c: 40021000 .word 0x40021000
|
|
|
|
080019a0 <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
80019a0: b590 push {r4, r7, lr}
|
|
80019a2: b095 sub sp, #84 ; 0x54
|
|
80019a4: af00 add r7, sp, #0
|
|
80019a6: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80019a8: 233c movs r3, #60 ; 0x3c
|
|
80019aa: 18fb adds r3, r7, r3
|
|
80019ac: 0018 movs r0, r3
|
|
80019ae: 2314 movs r3, #20
|
|
80019b0: 001a movs r2, r3
|
|
80019b2: 2100 movs r1, #0
|
|
80019b4: f004 fedc bl 8006770 <memset>
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
80019b8: 2414 movs r4, #20
|
|
80019ba: 193b adds r3, r7, r4
|
|
80019bc: 0018 movs r0, r3
|
|
80019be: 2328 movs r3, #40 ; 0x28
|
|
80019c0: 001a movs r2, r3
|
|
80019c2: 2100 movs r1, #0
|
|
80019c4: f004 fed4 bl 8006770 <memset>
|
|
if(hi2c->Instance==I2C1)
|
|
80019c8: 687b ldr r3, [r7, #4]
|
|
80019ca: 681b ldr r3, [r3, #0]
|
|
80019cc: 4a22 ldr r2, [pc, #136] ; (8001a58 <HAL_I2C_MspInit+0xb8>)
|
|
80019ce: 4293 cmp r3, r2
|
|
80019d0: d13d bne.n 8001a4e <HAL_I2C_MspInit+0xae>
|
|
|
|
/* USER CODE END I2C1_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clocks
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
|
|
80019d2: 193b adds r3, r7, r4
|
|
80019d4: 2220 movs r2, #32
|
|
80019d6: 601a str r2, [r3, #0]
|
|
PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
|
|
80019d8: 193b adds r3, r7, r4
|
|
80019da: 2200 movs r2, #0
|
|
80019dc: 60da str r2, [r3, #12]
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
80019de: 193b adds r3, r7, r4
|
|
80019e0: 0018 movs r0, r3
|
|
80019e2: f002 fb55 bl 8004090 <HAL_RCCEx_PeriphCLKConfig>
|
|
80019e6: 1e03 subs r3, r0, #0
|
|
80019e8: d001 beq.n 80019ee <HAL_I2C_MspInit+0x4e>
|
|
{
|
|
Error_Handler();
|
|
80019ea: f7ff ff8f bl 800190c <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80019ee: 4b1b ldr r3, [pc, #108] ; (8001a5c <HAL_I2C_MspInit+0xbc>)
|
|
80019f0: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
80019f2: 4b1a ldr r3, [pc, #104] ; (8001a5c <HAL_I2C_MspInit+0xbc>)
|
|
80019f4: 2102 movs r1, #2
|
|
80019f6: 430a orrs r2, r1
|
|
80019f8: 635a str r2, [r3, #52] ; 0x34
|
|
80019fa: 4b18 ldr r3, [pc, #96] ; (8001a5c <HAL_I2C_MspInit+0xbc>)
|
|
80019fc: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
80019fe: 2202 movs r2, #2
|
|
8001a00: 4013 ands r3, r2
|
|
8001a02: 613b str r3, [r7, #16]
|
|
8001a04: 693b ldr r3, [r7, #16]
|
|
/**I2C1 GPIO Configuration
|
|
PB6 ------> I2C1_SCL
|
|
PB7 ------> I2C1_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = Sens_SCL_Pin|Sens_SDA_Pin;
|
|
8001a06: 213c movs r1, #60 ; 0x3c
|
|
8001a08: 187b adds r3, r7, r1
|
|
8001a0a: 22c0 movs r2, #192 ; 0xc0
|
|
8001a0c: 601a str r2, [r3, #0]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
8001a0e: 187b adds r3, r7, r1
|
|
8001a10: 2212 movs r2, #18
|
|
8001a12: 605a str r2, [r3, #4]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001a14: 187b adds r3, r7, r1
|
|
8001a16: 2200 movs r2, #0
|
|
8001a18: 609a str r2, [r3, #8]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001a1a: 187b adds r3, r7, r1
|
|
8001a1c: 2200 movs r2, #0
|
|
8001a1e: 60da str r2, [r3, #12]
|
|
GPIO_InitStruct.Alternate = GPIO_AF6_I2C1;
|
|
8001a20: 187b adds r3, r7, r1
|
|
8001a22: 2206 movs r2, #6
|
|
8001a24: 611a str r2, [r3, #16]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001a26: 187b adds r3, r7, r1
|
|
8001a28: 4a0d ldr r2, [pc, #52] ; (8001a60 <HAL_I2C_MspInit+0xc0>)
|
|
8001a2a: 0019 movs r1, r3
|
|
8001a2c: 0010 movs r0, r2
|
|
8001a2e: f000 fe33 bl 8002698 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C1_CLK_ENABLE();
|
|
8001a32: 4b0a ldr r3, [pc, #40] ; (8001a5c <HAL_I2C_MspInit+0xbc>)
|
|
8001a34: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
8001a36: 4b09 ldr r3, [pc, #36] ; (8001a5c <HAL_I2C_MspInit+0xbc>)
|
|
8001a38: 2180 movs r1, #128 ; 0x80
|
|
8001a3a: 0389 lsls r1, r1, #14
|
|
8001a3c: 430a orrs r2, r1
|
|
8001a3e: 63da str r2, [r3, #60] ; 0x3c
|
|
8001a40: 4b06 ldr r3, [pc, #24] ; (8001a5c <HAL_I2C_MspInit+0xbc>)
|
|
8001a42: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
8001a44: 2380 movs r3, #128 ; 0x80
|
|
8001a46: 039b lsls r3, r3, #14
|
|
8001a48: 4013 ands r3, r2
|
|
8001a4a: 60fb str r3, [r7, #12]
|
|
8001a4c: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN I2C1_MspInit 1 */
|
|
|
|
/* USER CODE END I2C1_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8001a4e: 46c0 nop ; (mov r8, r8)
|
|
8001a50: 46bd mov sp, r7
|
|
8001a52: b015 add sp, #84 ; 0x54
|
|
8001a54: bd90 pop {r4, r7, pc}
|
|
8001a56: 46c0 nop ; (mov r8, r8)
|
|
8001a58: 40005400 .word 0x40005400
|
|
8001a5c: 40021000 .word 0x40021000
|
|
8001a60: 50000400 .word 0x50000400
|
|
|
|
08001a64 <HAL_TIM_Base_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_base: TIM_Base handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
|
|
{
|
|
8001a64: b580 push {r7, lr}
|
|
8001a66: b086 sub sp, #24
|
|
8001a68: af00 add r7, sp, #0
|
|
8001a6a: 6078 str r0, [r7, #4]
|
|
if(htim_base->Instance==TIM3)
|
|
8001a6c: 687b ldr r3, [r7, #4]
|
|
8001a6e: 681b ldr r3, [r3, #0]
|
|
8001a70: 4a25 ldr r2, [pc, #148] ; (8001b08 <HAL_TIM_Base_MspInit+0xa4>)
|
|
8001a72: 4293 cmp r3, r2
|
|
8001a74: d10c bne.n 8001a90 <HAL_TIM_Base_MspInit+0x2c>
|
|
{
|
|
/* USER CODE BEGIN TIM3_MspInit 0 */
|
|
|
|
/* USER CODE END TIM3_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
8001a76: 4b25 ldr r3, [pc, #148] ; (8001b0c <HAL_TIM_Base_MspInit+0xa8>)
|
|
8001a78: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
8001a7a: 4b24 ldr r3, [pc, #144] ; (8001b0c <HAL_TIM_Base_MspInit+0xa8>)
|
|
8001a7c: 2102 movs r1, #2
|
|
8001a7e: 430a orrs r2, r1
|
|
8001a80: 63da str r2, [r3, #60] ; 0x3c
|
|
8001a82: 4b22 ldr r3, [pc, #136] ; (8001b0c <HAL_TIM_Base_MspInit+0xa8>)
|
|
8001a84: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
8001a86: 2202 movs r2, #2
|
|
8001a88: 4013 ands r3, r2
|
|
8001a8a: 617b str r3, [r7, #20]
|
|
8001a8c: 697b ldr r3, [r7, #20]
|
|
/* USER CODE BEGIN TIM17_MspInit 1 */
|
|
|
|
/* USER CODE END TIM17_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8001a8e: e036 b.n 8001afe <HAL_TIM_Base_MspInit+0x9a>
|
|
else if(htim_base->Instance==TIM16)
|
|
8001a90: 687b ldr r3, [r7, #4]
|
|
8001a92: 681b ldr r3, [r3, #0]
|
|
8001a94: 4a1e ldr r2, [pc, #120] ; (8001b10 <HAL_TIM_Base_MspInit+0xac>)
|
|
8001a96: 4293 cmp r3, r2
|
|
8001a98: d116 bne.n 8001ac8 <HAL_TIM_Base_MspInit+0x64>
|
|
__HAL_RCC_TIM16_CLK_ENABLE();
|
|
8001a9a: 4b1c ldr r3, [pc, #112] ; (8001b0c <HAL_TIM_Base_MspInit+0xa8>)
|
|
8001a9c: 6c1a ldr r2, [r3, #64] ; 0x40
|
|
8001a9e: 4b1b ldr r3, [pc, #108] ; (8001b0c <HAL_TIM_Base_MspInit+0xa8>)
|
|
8001aa0: 2180 movs r1, #128 ; 0x80
|
|
8001aa2: 0289 lsls r1, r1, #10
|
|
8001aa4: 430a orrs r2, r1
|
|
8001aa6: 641a str r2, [r3, #64] ; 0x40
|
|
8001aa8: 4b18 ldr r3, [pc, #96] ; (8001b0c <HAL_TIM_Base_MspInit+0xa8>)
|
|
8001aaa: 6c1a ldr r2, [r3, #64] ; 0x40
|
|
8001aac: 2380 movs r3, #128 ; 0x80
|
|
8001aae: 029b lsls r3, r3, #10
|
|
8001ab0: 4013 ands r3, r2
|
|
8001ab2: 613b str r3, [r7, #16]
|
|
8001ab4: 693b ldr r3, [r7, #16]
|
|
HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
|
|
8001ab6: 2200 movs r2, #0
|
|
8001ab8: 2100 movs r1, #0
|
|
8001aba: 2015 movs r0, #21
|
|
8001abc: f000 fa30 bl 8001f20 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(TIM16_IRQn);
|
|
8001ac0: 2015 movs r0, #21
|
|
8001ac2: f000 fa42 bl 8001f4a <HAL_NVIC_EnableIRQ>
|
|
}
|
|
8001ac6: e01a b.n 8001afe <HAL_TIM_Base_MspInit+0x9a>
|
|
else if(htim_base->Instance==TIM17)
|
|
8001ac8: 687b ldr r3, [r7, #4]
|
|
8001aca: 681b ldr r3, [r3, #0]
|
|
8001acc: 4a11 ldr r2, [pc, #68] ; (8001b14 <HAL_TIM_Base_MspInit+0xb0>)
|
|
8001ace: 4293 cmp r3, r2
|
|
8001ad0: d115 bne.n 8001afe <HAL_TIM_Base_MspInit+0x9a>
|
|
__HAL_RCC_TIM17_CLK_ENABLE();
|
|
8001ad2: 4b0e ldr r3, [pc, #56] ; (8001b0c <HAL_TIM_Base_MspInit+0xa8>)
|
|
8001ad4: 6c1a ldr r2, [r3, #64] ; 0x40
|
|
8001ad6: 4b0d ldr r3, [pc, #52] ; (8001b0c <HAL_TIM_Base_MspInit+0xa8>)
|
|
8001ad8: 2180 movs r1, #128 ; 0x80
|
|
8001ada: 02c9 lsls r1, r1, #11
|
|
8001adc: 430a orrs r2, r1
|
|
8001ade: 641a str r2, [r3, #64] ; 0x40
|
|
8001ae0: 4b0a ldr r3, [pc, #40] ; (8001b0c <HAL_TIM_Base_MspInit+0xa8>)
|
|
8001ae2: 6c1a ldr r2, [r3, #64] ; 0x40
|
|
8001ae4: 2380 movs r3, #128 ; 0x80
|
|
8001ae6: 02db lsls r3, r3, #11
|
|
8001ae8: 4013 ands r3, r2
|
|
8001aea: 60fb str r3, [r7, #12]
|
|
8001aec: 68fb ldr r3, [r7, #12]
|
|
HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
|
|
8001aee: 2200 movs r2, #0
|
|
8001af0: 2100 movs r1, #0
|
|
8001af2: 2016 movs r0, #22
|
|
8001af4: f000 fa14 bl 8001f20 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(TIM17_IRQn);
|
|
8001af8: 2016 movs r0, #22
|
|
8001afa: f000 fa26 bl 8001f4a <HAL_NVIC_EnableIRQ>
|
|
}
|
|
8001afe: 46c0 nop ; (mov r8, r8)
|
|
8001b00: 46bd mov sp, r7
|
|
8001b02: b006 add sp, #24
|
|
8001b04: bd80 pop {r7, pc}
|
|
8001b06: 46c0 nop ; (mov r8, r8)
|
|
8001b08: 40000400 .word 0x40000400
|
|
8001b0c: 40021000 .word 0x40021000
|
|
8001b10: 40014400 .word 0x40014400
|
|
8001b14: 40014800 .word 0x40014800
|
|
|
|
08001b18 <HAL_TIM_MspPostInit>:
|
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
|
{
|
|
8001b18: b590 push {r4, r7, lr}
|
|
8001b1a: b089 sub sp, #36 ; 0x24
|
|
8001b1c: af00 add r7, sp, #0
|
|
8001b1e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001b20: 240c movs r4, #12
|
|
8001b22: 193b adds r3, r7, r4
|
|
8001b24: 0018 movs r0, r3
|
|
8001b26: 2314 movs r3, #20
|
|
8001b28: 001a movs r2, r3
|
|
8001b2a: 2100 movs r1, #0
|
|
8001b2c: f004 fe20 bl 8006770 <memset>
|
|
if(htim->Instance==TIM3)
|
|
8001b30: 687b ldr r3, [r7, #4]
|
|
8001b32: 681b ldr r3, [r3, #0]
|
|
8001b34: 4a14 ldr r2, [pc, #80] ; (8001b88 <HAL_TIM_MspPostInit+0x70>)
|
|
8001b36: 4293 cmp r3, r2
|
|
8001b38: d121 bne.n 8001b7e <HAL_TIM_MspPostInit+0x66>
|
|
{
|
|
/* USER CODE BEGIN TIM3_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM3_MspPostInit 0 */
|
|
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8001b3a: 4b14 ldr r3, [pc, #80] ; (8001b8c <HAL_TIM_MspPostInit+0x74>)
|
|
8001b3c: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
8001b3e: 4b13 ldr r3, [pc, #76] ; (8001b8c <HAL_TIM_MspPostInit+0x74>)
|
|
8001b40: 2104 movs r1, #4
|
|
8001b42: 430a orrs r2, r1
|
|
8001b44: 635a str r2, [r3, #52] ; 0x34
|
|
8001b46: 4b11 ldr r3, [pc, #68] ; (8001b8c <HAL_TIM_MspPostInit+0x74>)
|
|
8001b48: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8001b4a: 2204 movs r2, #4
|
|
8001b4c: 4013 ands r3, r2
|
|
8001b4e: 60bb str r3, [r7, #8]
|
|
8001b50: 68bb ldr r3, [r7, #8]
|
|
/**TIM3 GPIO Configuration
|
|
PC6 ------> TIM3_CH1
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6;
|
|
8001b52: 0021 movs r1, r4
|
|
8001b54: 187b adds r3, r7, r1
|
|
8001b56: 2240 movs r2, #64 ; 0x40
|
|
8001b58: 601a str r2, [r3, #0]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001b5a: 187b adds r3, r7, r1
|
|
8001b5c: 2202 movs r2, #2
|
|
8001b5e: 605a str r2, [r3, #4]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001b60: 187b adds r3, r7, r1
|
|
8001b62: 2200 movs r2, #0
|
|
8001b64: 609a str r2, [r3, #8]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001b66: 187b adds r3, r7, r1
|
|
8001b68: 2200 movs r2, #0
|
|
8001b6a: 60da str r2, [r3, #12]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
|
|
8001b6c: 187b adds r3, r7, r1
|
|
8001b6e: 2201 movs r2, #1
|
|
8001b70: 611a str r2, [r3, #16]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8001b72: 187b adds r3, r7, r1
|
|
8001b74: 4a06 ldr r2, [pc, #24] ; (8001b90 <HAL_TIM_MspPostInit+0x78>)
|
|
8001b76: 0019 movs r1, r3
|
|
8001b78: 0010 movs r0, r2
|
|
8001b7a: f000 fd8d bl 8002698 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM3_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM3_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
8001b7e: 46c0 nop ; (mov r8, r8)
|
|
8001b80: 46bd mov sp, r7
|
|
8001b82: b009 add sp, #36 ; 0x24
|
|
8001b84: bd90 pop {r4, r7, pc}
|
|
8001b86: 46c0 nop ; (mov r8, r8)
|
|
8001b88: 40000400 .word 0x40000400
|
|
8001b8c: 40021000 .word 0x40021000
|
|
8001b90: 50000800 .word 0x50000800
|
|
|
|
08001b94 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8001b94: b580 push {r7, lr}
|
|
8001b96: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8001b98: e7fe b.n 8001b98 <NMI_Handler+0x4>
|
|
|
|
08001b9a <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8001b9a: b580 push {r7, lr}
|
|
8001b9c: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8001b9e: e7fe b.n 8001b9e <HardFault_Handler+0x4>
|
|
|
|
08001ba0 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8001ba0: b580 push {r7, lr}
|
|
8001ba2: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVC_IRQn 0 */
|
|
/* USER CODE BEGIN SVC_IRQn 1 */
|
|
|
|
/* USER CODE END SVC_IRQn 1 */
|
|
}
|
|
8001ba4: 46c0 nop ; (mov r8, r8)
|
|
8001ba6: 46bd mov sp, r7
|
|
8001ba8: bd80 pop {r7, pc}
|
|
|
|
08001baa <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8001baa: b580 push {r7, lr}
|
|
8001bac: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8001bae: 46c0 nop ; (mov r8, r8)
|
|
8001bb0: 46bd mov sp, r7
|
|
8001bb2: bd80 pop {r7, pc}
|
|
|
|
08001bb4 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8001bb4: b580 push {r7, lr}
|
|
8001bb6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
8001bb8: f000 f8c6 bl 8001d48 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8001bbc: 46c0 nop ; (mov r8, r8)
|
|
8001bbe: 46bd mov sp, r7
|
|
8001bc0: bd80 pop {r7, pc}
|
|
|
|
08001bc2 <EXTI0_1_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles EXTI line 0 and line 1 interrupts.
|
|
*/
|
|
void EXTI0_1_IRQHandler(void)
|
|
{
|
|
8001bc2: b580 push {r7, lr}
|
|
8001bc4: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EXTI0_1_IRQn 0 */
|
|
|
|
/* USER CODE END EXTI0_1_IRQn 0 */
|
|
HAL_GPIO_EXTI_IRQHandler(Btn_INT_Pin);
|
|
8001bc6: 2001 movs r0, #1
|
|
8001bc8: f000 fee8 bl 800299c <HAL_GPIO_EXTI_IRQHandler>
|
|
/* USER CODE BEGIN EXTI0_1_IRQn 1 */
|
|
|
|
/* USER CODE END EXTI0_1_IRQn 1 */
|
|
}
|
|
8001bcc: 46c0 nop ; (mov r8, r8)
|
|
8001bce: 46bd mov sp, r7
|
|
8001bd0: bd80 pop {r7, pc}
|
|
|
|
08001bd2 <EXTI4_15_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles EXTI line 4 to 15 interrupts.
|
|
*/
|
|
void EXTI4_15_IRQHandler(void)
|
|
{
|
|
8001bd2: b580 push {r7, lr}
|
|
8001bd4: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EXTI4_15_IRQn 0 */
|
|
|
|
/* USER CODE END EXTI4_15_IRQn 0 */
|
|
HAL_GPIO_EXTI_IRQHandler(Sens_INT_Pin);
|
|
8001bd6: 2020 movs r0, #32
|
|
8001bd8: f000 fee0 bl 800299c <HAL_GPIO_EXTI_IRQHandler>
|
|
/* USER CODE BEGIN EXTI4_15_IRQn 1 */
|
|
|
|
/* USER CODE END EXTI4_15_IRQn 1 */
|
|
}
|
|
8001bdc: 46c0 nop ; (mov r8, r8)
|
|
8001bde: 46bd mov sp, r7
|
|
8001be0: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001be4 <TIM16_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles TIM16 global interrupt.
|
|
*/
|
|
void TIM16_IRQHandler(void)
|
|
{
|
|
8001be4: b580 push {r7, lr}
|
|
8001be6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN TIM16_IRQn 0 */
|
|
|
|
/* USER CODE END TIM16_IRQn 0 */
|
|
HAL_TIM_IRQHandler(&htim16);
|
|
8001be8: 4b03 ldr r3, [pc, #12] ; (8001bf8 <TIM16_IRQHandler+0x14>)
|
|
8001bea: 0018 movs r0, r3
|
|
8001bec: f002 fde2 bl 80047b4 <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM16_IRQn 1 */
|
|
|
|
/* USER CODE END TIM16_IRQn 1 */
|
|
}
|
|
8001bf0: 46c0 nop ; (mov r8, r8)
|
|
8001bf2: 46bd mov sp, r7
|
|
8001bf4: bd80 pop {r7, pc}
|
|
8001bf6: 46c0 nop ; (mov r8, r8)
|
|
8001bf8: 20000178 .word 0x20000178
|
|
|
|
08001bfc <TIM17_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles TIM17 global interrupt.
|
|
*/
|
|
void TIM17_IRQHandler(void)
|
|
{
|
|
8001bfc: b580 push {r7, lr}
|
|
8001bfe: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN TIM17_IRQn 0 */
|
|
|
|
/* USER CODE END TIM17_IRQn 0 */
|
|
HAL_TIM_IRQHandler(&htim17);
|
|
8001c00: 4b03 ldr r3, [pc, #12] ; (8001c10 <TIM17_IRQHandler+0x14>)
|
|
8001c02: 0018 movs r0, r3
|
|
8001c04: f002 fdd6 bl 80047b4 <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM17_IRQn 1 */
|
|
|
|
/* USER CODE END TIM17_IRQn 1 */
|
|
}
|
|
8001c08: 46c0 nop ; (mov r8, r8)
|
|
8001c0a: 46bd mov sp, r7
|
|
8001c0c: bd80 pop {r7, pc}
|
|
8001c0e: 46c0 nop ; (mov r8, r8)
|
|
8001c10: 200001c4 .word 0x200001c4
|
|
|
|
08001c14 <SystemInit>:
|
|
* @brief Setup the microcontroller system.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
8001c14: b580 push {r7, lr}
|
|
8001c16: af00 add r7, sp, #0
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
8001c18: 46c0 nop ; (mov r8, r8)
|
|
8001c1a: 46bd mov sp, r7
|
|
8001c1c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001c20 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr r0, =_estack
|
|
8001c20: 480d ldr r0, [pc, #52] ; (8001c58 <LoopForever+0x2>)
|
|
mov sp, r0 /* set stack pointer */
|
|
8001c22: 4685 mov sp, r0
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8001c24: f7ff fff6 bl 8001c14 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8001c28: 480c ldr r0, [pc, #48] ; (8001c5c <LoopForever+0x6>)
|
|
ldr r1, =_edata
|
|
8001c2a: 490d ldr r1, [pc, #52] ; (8001c60 <LoopForever+0xa>)
|
|
ldr r2, =_sidata
|
|
8001c2c: 4a0d ldr r2, [pc, #52] ; (8001c64 <LoopForever+0xe>)
|
|
movs r3, #0
|
|
8001c2e: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
8001c30: e002 b.n 8001c38 <LoopCopyDataInit>
|
|
|
|
08001c32 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
8001c32: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8001c34: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8001c36: 3304 adds r3, #4
|
|
|
|
08001c38 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8001c38: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8001c3a: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8001c3c: d3f9 bcc.n 8001c32 <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
8001c3e: 4a0a ldr r2, [pc, #40] ; (8001c68 <LoopForever+0x12>)
|
|
ldr r4, =_ebss
|
|
8001c40: 4c0a ldr r4, [pc, #40] ; (8001c6c <LoopForever+0x16>)
|
|
movs r3, #0
|
|
8001c42: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8001c44: e001 b.n 8001c4a <LoopFillZerobss>
|
|
|
|
08001c46 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8001c46: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8001c48: 3204 adds r2, #4
|
|
|
|
08001c4a <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8001c4a: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8001c4c: d3fb bcc.n 8001c46 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8001c4e: f004 fd6b bl 8006728 <__libc_init_array>
|
|
/* Call the application s entry point.*/
|
|
bl main
|
|
8001c52: f7ff fad9 bl 8001208 <main>
|
|
|
|
08001c56 <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
8001c56: e7fe b.n 8001c56 <LoopForever>
|
|
ldr r0, =_estack
|
|
8001c58: 20002000 .word 0x20002000
|
|
ldr r0, =_sdata
|
|
8001c5c: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
8001c60: 20000098 .word 0x20000098
|
|
ldr r2, =_sidata
|
|
8001c64: 08006884 .word 0x08006884
|
|
ldr r2, =_sbss
|
|
8001c68: 20000098 .word 0x20000098
|
|
ldr r4, =_ebss
|
|
8001c6c: 20000264 .word 0x20000264
|
|
|
|
08001c70 <ADC1_IRQHandler>:
|
|
* @retval None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8001c70: e7fe b.n 8001c70 <ADC1_IRQHandler>
|
|
...
|
|
|
|
08001c74 <HAL_Init>:
|
|
* each 1ms in the SysTick_Handler() interrupt handler.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8001c74: b580 push {r7, lr}
|
|
8001c76: b082 sub sp, #8
|
|
8001c78: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8001c7a: 1dfb adds r3, r7, #7
|
|
8001c7c: 2200 movs r2, #0
|
|
8001c7e: 701a strb r2, [r3, #0]
|
|
#if (INSTRUCTION_CACHE_ENABLE == 0U)
|
|
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
|
|
#endif /* INSTRUCTION_CACHE_ENABLE */
|
|
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
8001c80: 4b0b ldr r3, [pc, #44] ; (8001cb0 <HAL_Init+0x3c>)
|
|
8001c82: 681a ldr r2, [r3, #0]
|
|
8001c84: 4b0a ldr r3, [pc, #40] ; (8001cb0 <HAL_Init+0x3c>)
|
|
8001c86: 2180 movs r1, #128 ; 0x80
|
|
8001c88: 0049 lsls r1, r1, #1
|
|
8001c8a: 430a orrs r2, r1
|
|
8001c8c: 601a str r2, [r3, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
8001c8e: 2003 movs r0, #3
|
|
8001c90: f000 f810 bl 8001cb4 <HAL_InitTick>
|
|
8001c94: 1e03 subs r3, r0, #0
|
|
8001c96: d003 beq.n 8001ca0 <HAL_Init+0x2c>
|
|
{
|
|
status = HAL_ERROR;
|
|
8001c98: 1dfb adds r3, r7, #7
|
|
8001c9a: 2201 movs r2, #1
|
|
8001c9c: 701a strb r2, [r3, #0]
|
|
8001c9e: e001 b.n 8001ca4 <HAL_Init+0x30>
|
|
}
|
|
else
|
|
{
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8001ca0: f7ff fe3a bl 8001918 <HAL_MspInit>
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8001ca4: 1dfb adds r3, r7, #7
|
|
8001ca6: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8001ca8: 0018 movs r0, r3
|
|
8001caa: 46bd mov sp, r7
|
|
8001cac: b002 add sp, #8
|
|
8001cae: bd80 pop {r7, pc}
|
|
8001cb0: 40022000 .word 0x40022000
|
|
|
|
08001cb4 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8001cb4: b590 push {r4, r7, lr}
|
|
8001cb6: b085 sub sp, #20
|
|
8001cb8: af00 add r7, sp, #0
|
|
8001cba: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8001cbc: 230f movs r3, #15
|
|
8001cbe: 18fb adds r3, r7, r3
|
|
8001cc0: 2200 movs r2, #0
|
|
8001cc2: 701a strb r2, [r3, #0]
|
|
|
|
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
|
|
if ((uint32_t)uwTickFreq != 0U)
|
|
8001cc4: 4b1d ldr r3, [pc, #116] ; (8001d3c <HAL_InitTick+0x88>)
|
|
8001cc6: 781b ldrb r3, [r3, #0]
|
|
8001cc8: 2b00 cmp r3, #0
|
|
8001cca: d02b beq.n 8001d24 <HAL_InitTick+0x70>
|
|
{
|
|
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U)
|
|
8001ccc: 4b1c ldr r3, [pc, #112] ; (8001d40 <HAL_InitTick+0x8c>)
|
|
8001cce: 681c ldr r4, [r3, #0]
|
|
8001cd0: 4b1a ldr r3, [pc, #104] ; (8001d3c <HAL_InitTick+0x88>)
|
|
8001cd2: 781b ldrb r3, [r3, #0]
|
|
8001cd4: 0019 movs r1, r3
|
|
8001cd6: 23fa movs r3, #250 ; 0xfa
|
|
8001cd8: 0098 lsls r0, r3, #2
|
|
8001cda: f7fe fa15 bl 8000108 <__udivsi3>
|
|
8001cde: 0003 movs r3, r0
|
|
8001ce0: 0019 movs r1, r3
|
|
8001ce2: 0020 movs r0, r4
|
|
8001ce4: f7fe fa10 bl 8000108 <__udivsi3>
|
|
8001ce8: 0003 movs r3, r0
|
|
8001cea: 0018 movs r0, r3
|
|
8001cec: f000 f93d bl 8001f6a <HAL_SYSTICK_Config>
|
|
8001cf0: 1e03 subs r3, r0, #0
|
|
8001cf2: d112 bne.n 8001d1a <HAL_InitTick+0x66>
|
|
{
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8001cf4: 687b ldr r3, [r7, #4]
|
|
8001cf6: 2b03 cmp r3, #3
|
|
8001cf8: d80a bhi.n 8001d10 <HAL_InitTick+0x5c>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
8001cfa: 6879 ldr r1, [r7, #4]
|
|
8001cfc: 2301 movs r3, #1
|
|
8001cfe: 425b negs r3, r3
|
|
8001d00: 2200 movs r2, #0
|
|
8001d02: 0018 movs r0, r3
|
|
8001d04: f000 f90c bl 8001f20 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8001d08: 4b0e ldr r3, [pc, #56] ; (8001d44 <HAL_InitTick+0x90>)
|
|
8001d0a: 687a ldr r2, [r7, #4]
|
|
8001d0c: 601a str r2, [r3, #0]
|
|
8001d0e: e00d b.n 8001d2c <HAL_InitTick+0x78>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8001d10: 230f movs r3, #15
|
|
8001d12: 18fb adds r3, r7, r3
|
|
8001d14: 2201 movs r2, #1
|
|
8001d16: 701a strb r2, [r3, #0]
|
|
8001d18: e008 b.n 8001d2c <HAL_InitTick+0x78>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8001d1a: 230f movs r3, #15
|
|
8001d1c: 18fb adds r3, r7, r3
|
|
8001d1e: 2201 movs r2, #1
|
|
8001d20: 701a strb r2, [r3, #0]
|
|
8001d22: e003 b.n 8001d2c <HAL_InitTick+0x78>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8001d24: 230f movs r3, #15
|
|
8001d26: 18fb adds r3, r7, r3
|
|
8001d28: 2201 movs r2, #1
|
|
8001d2a: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8001d2c: 230f movs r3, #15
|
|
8001d2e: 18fb adds r3, r7, r3
|
|
8001d30: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8001d32: 0018 movs r0, r3
|
|
8001d34: 46bd mov sp, r7
|
|
8001d36: b005 add sp, #20
|
|
8001d38: bd90 pop {r4, r7, pc}
|
|
8001d3a: 46c0 nop ; (mov r8, r8)
|
|
8001d3c: 2000000c .word 0x2000000c
|
|
8001d40: 20000004 .word 0x20000004
|
|
8001d44: 20000008 .word 0x20000008
|
|
|
|
08001d48 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8001d48: b580 push {r7, lr}
|
|
8001d4a: af00 add r7, sp, #0
|
|
uwTick += (uint32_t)uwTickFreq;
|
|
8001d4c: 4b05 ldr r3, [pc, #20] ; (8001d64 <HAL_IncTick+0x1c>)
|
|
8001d4e: 781b ldrb r3, [r3, #0]
|
|
8001d50: 001a movs r2, r3
|
|
8001d52: 4b05 ldr r3, [pc, #20] ; (8001d68 <HAL_IncTick+0x20>)
|
|
8001d54: 681b ldr r3, [r3, #0]
|
|
8001d56: 18d2 adds r2, r2, r3
|
|
8001d58: 4b03 ldr r3, [pc, #12] ; (8001d68 <HAL_IncTick+0x20>)
|
|
8001d5a: 601a str r2, [r3, #0]
|
|
}
|
|
8001d5c: 46c0 nop ; (mov r8, r8)
|
|
8001d5e: 46bd mov sp, r7
|
|
8001d60: bd80 pop {r7, pc}
|
|
8001d62: 46c0 nop ; (mov r8, r8)
|
|
8001d64: 2000000c .word 0x2000000c
|
|
8001d68: 20000238 .word 0x20000238
|
|
|
|
08001d6c <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8001d6c: b580 push {r7, lr}
|
|
8001d6e: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8001d70: 4b02 ldr r3, [pc, #8] ; (8001d7c <HAL_GetTick+0x10>)
|
|
8001d72: 681b ldr r3, [r3, #0]
|
|
}
|
|
8001d74: 0018 movs r0, r3
|
|
8001d76: 46bd mov sp, r7
|
|
8001d78: bd80 pop {r7, pc}
|
|
8001d7a: 46c0 nop ; (mov r8, r8)
|
|
8001d7c: 20000238 .word 0x20000238
|
|
|
|
08001d80 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8001d80: b580 push {r7, lr}
|
|
8001d82: b084 sub sp, #16
|
|
8001d84: af00 add r7, sp, #0
|
|
8001d86: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8001d88: f7ff fff0 bl 8001d6c <HAL_GetTick>
|
|
8001d8c: 0003 movs r3, r0
|
|
8001d8e: 60bb str r3, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8001d90: 687b ldr r3, [r7, #4]
|
|
8001d92: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8001d94: 68fb ldr r3, [r7, #12]
|
|
8001d96: 3301 adds r3, #1
|
|
8001d98: d005 beq.n 8001da6 <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
8001d9a: 4b0a ldr r3, [pc, #40] ; (8001dc4 <HAL_Delay+0x44>)
|
|
8001d9c: 781b ldrb r3, [r3, #0]
|
|
8001d9e: 001a movs r2, r3
|
|
8001da0: 68fb ldr r3, [r7, #12]
|
|
8001da2: 189b adds r3, r3, r2
|
|
8001da4: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
8001da6: 46c0 nop ; (mov r8, r8)
|
|
8001da8: f7ff ffe0 bl 8001d6c <HAL_GetTick>
|
|
8001dac: 0002 movs r2, r0
|
|
8001dae: 68bb ldr r3, [r7, #8]
|
|
8001db0: 1ad3 subs r3, r2, r3
|
|
8001db2: 68fa ldr r2, [r7, #12]
|
|
8001db4: 429a cmp r2, r3
|
|
8001db6: d8f7 bhi.n 8001da8 <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
8001db8: 46c0 nop ; (mov r8, r8)
|
|
8001dba: 46c0 nop ; (mov r8, r8)
|
|
8001dbc: 46bd mov sp, r7
|
|
8001dbe: b004 add sp, #16
|
|
8001dc0: bd80 pop {r7, pc}
|
|
8001dc2: 46c0 nop ; (mov r8, r8)
|
|
8001dc4: 2000000c .word 0x2000000c
|
|
|
|
08001dc8 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001dc8: b580 push {r7, lr}
|
|
8001dca: b082 sub sp, #8
|
|
8001dcc: af00 add r7, sp, #0
|
|
8001dce: 0002 movs r2, r0
|
|
8001dd0: 1dfb adds r3, r7, #7
|
|
8001dd2: 701a strb r2, [r3, #0]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001dd4: 1dfb adds r3, r7, #7
|
|
8001dd6: 781b ldrb r3, [r3, #0]
|
|
8001dd8: 2b7f cmp r3, #127 ; 0x7f
|
|
8001dda: d809 bhi.n 8001df0 <__NVIC_EnableIRQ+0x28>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8001ddc: 1dfb adds r3, r7, #7
|
|
8001dde: 781b ldrb r3, [r3, #0]
|
|
8001de0: 001a movs r2, r3
|
|
8001de2: 231f movs r3, #31
|
|
8001de4: 401a ands r2, r3
|
|
8001de6: 4b04 ldr r3, [pc, #16] ; (8001df8 <__NVIC_EnableIRQ+0x30>)
|
|
8001de8: 2101 movs r1, #1
|
|
8001dea: 4091 lsls r1, r2
|
|
8001dec: 000a movs r2, r1
|
|
8001dee: 601a str r2, [r3, #0]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
8001df0: 46c0 nop ; (mov r8, r8)
|
|
8001df2: 46bd mov sp, r7
|
|
8001df4: b002 add sp, #8
|
|
8001df6: bd80 pop {r7, pc}
|
|
8001df8: e000e100 .word 0xe000e100
|
|
|
|
08001dfc <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8001dfc: b590 push {r4, r7, lr}
|
|
8001dfe: b083 sub sp, #12
|
|
8001e00: af00 add r7, sp, #0
|
|
8001e02: 0002 movs r2, r0
|
|
8001e04: 6039 str r1, [r7, #0]
|
|
8001e06: 1dfb adds r3, r7, #7
|
|
8001e08: 701a strb r2, [r3, #0]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001e0a: 1dfb adds r3, r7, #7
|
|
8001e0c: 781b ldrb r3, [r3, #0]
|
|
8001e0e: 2b7f cmp r3, #127 ; 0x7f
|
|
8001e10: d828 bhi.n 8001e64 <__NVIC_SetPriority+0x68>
|
|
{
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8001e12: 4a2f ldr r2, [pc, #188] ; (8001ed0 <__NVIC_SetPriority+0xd4>)
|
|
8001e14: 1dfb adds r3, r7, #7
|
|
8001e16: 781b ldrb r3, [r3, #0]
|
|
8001e18: b25b sxtb r3, r3
|
|
8001e1a: 089b lsrs r3, r3, #2
|
|
8001e1c: 33c0 adds r3, #192 ; 0xc0
|
|
8001e1e: 009b lsls r3, r3, #2
|
|
8001e20: 589b ldr r3, [r3, r2]
|
|
8001e22: 1dfa adds r2, r7, #7
|
|
8001e24: 7812 ldrb r2, [r2, #0]
|
|
8001e26: 0011 movs r1, r2
|
|
8001e28: 2203 movs r2, #3
|
|
8001e2a: 400a ands r2, r1
|
|
8001e2c: 00d2 lsls r2, r2, #3
|
|
8001e2e: 21ff movs r1, #255 ; 0xff
|
|
8001e30: 4091 lsls r1, r2
|
|
8001e32: 000a movs r2, r1
|
|
8001e34: 43d2 mvns r2, r2
|
|
8001e36: 401a ands r2, r3
|
|
8001e38: 0011 movs r1, r2
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
8001e3a: 683b ldr r3, [r7, #0]
|
|
8001e3c: 019b lsls r3, r3, #6
|
|
8001e3e: 22ff movs r2, #255 ; 0xff
|
|
8001e40: 401a ands r2, r3
|
|
8001e42: 1dfb adds r3, r7, #7
|
|
8001e44: 781b ldrb r3, [r3, #0]
|
|
8001e46: 0018 movs r0, r3
|
|
8001e48: 2303 movs r3, #3
|
|
8001e4a: 4003 ands r3, r0
|
|
8001e4c: 00db lsls r3, r3, #3
|
|
8001e4e: 409a lsls r2, r3
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8001e50: 481f ldr r0, [pc, #124] ; (8001ed0 <__NVIC_SetPriority+0xd4>)
|
|
8001e52: 1dfb adds r3, r7, #7
|
|
8001e54: 781b ldrb r3, [r3, #0]
|
|
8001e56: b25b sxtb r3, r3
|
|
8001e58: 089b lsrs r3, r3, #2
|
|
8001e5a: 430a orrs r2, r1
|
|
8001e5c: 33c0 adds r3, #192 ; 0xc0
|
|
8001e5e: 009b lsls r3, r3, #2
|
|
8001e60: 501a str r2, [r3, r0]
|
|
else
|
|
{
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
}
|
|
}
|
|
8001e62: e031 b.n 8001ec8 <__NVIC_SetPriority+0xcc>
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8001e64: 4a1b ldr r2, [pc, #108] ; (8001ed4 <__NVIC_SetPriority+0xd8>)
|
|
8001e66: 1dfb adds r3, r7, #7
|
|
8001e68: 781b ldrb r3, [r3, #0]
|
|
8001e6a: 0019 movs r1, r3
|
|
8001e6c: 230f movs r3, #15
|
|
8001e6e: 400b ands r3, r1
|
|
8001e70: 3b08 subs r3, #8
|
|
8001e72: 089b lsrs r3, r3, #2
|
|
8001e74: 3306 adds r3, #6
|
|
8001e76: 009b lsls r3, r3, #2
|
|
8001e78: 18d3 adds r3, r2, r3
|
|
8001e7a: 3304 adds r3, #4
|
|
8001e7c: 681b ldr r3, [r3, #0]
|
|
8001e7e: 1dfa adds r2, r7, #7
|
|
8001e80: 7812 ldrb r2, [r2, #0]
|
|
8001e82: 0011 movs r1, r2
|
|
8001e84: 2203 movs r2, #3
|
|
8001e86: 400a ands r2, r1
|
|
8001e88: 00d2 lsls r2, r2, #3
|
|
8001e8a: 21ff movs r1, #255 ; 0xff
|
|
8001e8c: 4091 lsls r1, r2
|
|
8001e8e: 000a movs r2, r1
|
|
8001e90: 43d2 mvns r2, r2
|
|
8001e92: 401a ands r2, r3
|
|
8001e94: 0011 movs r1, r2
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
8001e96: 683b ldr r3, [r7, #0]
|
|
8001e98: 019b lsls r3, r3, #6
|
|
8001e9a: 22ff movs r2, #255 ; 0xff
|
|
8001e9c: 401a ands r2, r3
|
|
8001e9e: 1dfb adds r3, r7, #7
|
|
8001ea0: 781b ldrb r3, [r3, #0]
|
|
8001ea2: 0018 movs r0, r3
|
|
8001ea4: 2303 movs r3, #3
|
|
8001ea6: 4003 ands r3, r0
|
|
8001ea8: 00db lsls r3, r3, #3
|
|
8001eaa: 409a lsls r2, r3
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8001eac: 4809 ldr r0, [pc, #36] ; (8001ed4 <__NVIC_SetPriority+0xd8>)
|
|
8001eae: 1dfb adds r3, r7, #7
|
|
8001eb0: 781b ldrb r3, [r3, #0]
|
|
8001eb2: 001c movs r4, r3
|
|
8001eb4: 230f movs r3, #15
|
|
8001eb6: 4023 ands r3, r4
|
|
8001eb8: 3b08 subs r3, #8
|
|
8001eba: 089b lsrs r3, r3, #2
|
|
8001ebc: 430a orrs r2, r1
|
|
8001ebe: 3306 adds r3, #6
|
|
8001ec0: 009b lsls r3, r3, #2
|
|
8001ec2: 18c3 adds r3, r0, r3
|
|
8001ec4: 3304 adds r3, #4
|
|
8001ec6: 601a str r2, [r3, #0]
|
|
}
|
|
8001ec8: 46c0 nop ; (mov r8, r8)
|
|
8001eca: 46bd mov sp, r7
|
|
8001ecc: b003 add sp, #12
|
|
8001ece: bd90 pop {r4, r7, pc}
|
|
8001ed0: e000e100 .word 0xe000e100
|
|
8001ed4: e000ed00 .word 0xe000ed00
|
|
|
|
08001ed8 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
8001ed8: b580 push {r7, lr}
|
|
8001eda: b082 sub sp, #8
|
|
8001edc: af00 add r7, sp, #0
|
|
8001ede: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8001ee0: 687b ldr r3, [r7, #4]
|
|
8001ee2: 1e5a subs r2, r3, #1
|
|
8001ee4: 2380 movs r3, #128 ; 0x80
|
|
8001ee6: 045b lsls r3, r3, #17
|
|
8001ee8: 429a cmp r2, r3
|
|
8001eea: d301 bcc.n 8001ef0 <SysTick_Config+0x18>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
8001eec: 2301 movs r3, #1
|
|
8001eee: e010 b.n 8001f12 <SysTick_Config+0x3a>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8001ef0: 4b0a ldr r3, [pc, #40] ; (8001f1c <SysTick_Config+0x44>)
|
|
8001ef2: 687a ldr r2, [r7, #4]
|
|
8001ef4: 3a01 subs r2, #1
|
|
8001ef6: 605a str r2, [r3, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8001ef8: 2301 movs r3, #1
|
|
8001efa: 425b negs r3, r3
|
|
8001efc: 2103 movs r1, #3
|
|
8001efe: 0018 movs r0, r3
|
|
8001f00: f7ff ff7c bl 8001dfc <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8001f04: 4b05 ldr r3, [pc, #20] ; (8001f1c <SysTick_Config+0x44>)
|
|
8001f06: 2200 movs r2, #0
|
|
8001f08: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8001f0a: 4b04 ldr r3, [pc, #16] ; (8001f1c <SysTick_Config+0x44>)
|
|
8001f0c: 2207 movs r2, #7
|
|
8001f0e: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8001f10: 2300 movs r3, #0
|
|
}
|
|
8001f12: 0018 movs r0, r3
|
|
8001f14: 46bd mov sp, r7
|
|
8001f16: b002 add sp, #8
|
|
8001f18: bd80 pop {r7, pc}
|
|
8001f1a: 46c0 nop ; (mov r8, r8)
|
|
8001f1c: e000e010 .word 0xe000e010
|
|
|
|
08001f20 <HAL_NVIC_SetPriority>:
|
|
* with stm32g0xx devices, this parameter is a dummy value and it is ignored, because
|
|
* no subpriority supported in Cortex M0+ based products.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001f20: b580 push {r7, lr}
|
|
8001f22: b084 sub sp, #16
|
|
8001f24: af00 add r7, sp, #0
|
|
8001f26: 60b9 str r1, [r7, #8]
|
|
8001f28: 607a str r2, [r7, #4]
|
|
8001f2a: 210f movs r1, #15
|
|
8001f2c: 187b adds r3, r7, r1
|
|
8001f2e: 1c02 adds r2, r0, #0
|
|
8001f30: 701a strb r2, [r3, #0]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(SubPriority);
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
NVIC_SetPriority(IRQn, PreemptPriority);
|
|
8001f32: 68ba ldr r2, [r7, #8]
|
|
8001f34: 187b adds r3, r7, r1
|
|
8001f36: 781b ldrb r3, [r3, #0]
|
|
8001f38: b25b sxtb r3, r3
|
|
8001f3a: 0011 movs r1, r2
|
|
8001f3c: 0018 movs r0, r3
|
|
8001f3e: f7ff ff5d bl 8001dfc <__NVIC_SetPriority>
|
|
}
|
|
8001f42: 46c0 nop ; (mov r8, r8)
|
|
8001f44: 46bd mov sp, r7
|
|
8001f46: b004 add sp, #16
|
|
8001f48: bd80 pop {r7, pc}
|
|
|
|
08001f4a <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001f4a: b580 push {r7, lr}
|
|
8001f4c: b082 sub sp, #8
|
|
8001f4e: af00 add r7, sp, #0
|
|
8001f50: 0002 movs r2, r0
|
|
8001f52: 1dfb adds r3, r7, #7
|
|
8001f54: 701a strb r2, [r3, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8001f56: 1dfb adds r3, r7, #7
|
|
8001f58: 781b ldrb r3, [r3, #0]
|
|
8001f5a: b25b sxtb r3, r3
|
|
8001f5c: 0018 movs r0, r3
|
|
8001f5e: f7ff ff33 bl 8001dc8 <__NVIC_EnableIRQ>
|
|
}
|
|
8001f62: 46c0 nop ; (mov r8, r8)
|
|
8001f64: 46bd mov sp, r7
|
|
8001f66: b002 add sp, #8
|
|
8001f68: bd80 pop {r7, pc}
|
|
|
|
08001f6a <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
8001f6a: b580 push {r7, lr}
|
|
8001f6c: b082 sub sp, #8
|
|
8001f6e: af00 add r7, sp, #0
|
|
8001f70: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8001f72: 687b ldr r3, [r7, #4]
|
|
8001f74: 0018 movs r0, r3
|
|
8001f76: f7ff ffaf bl 8001ed8 <SysTick_Config>
|
|
8001f7a: 0003 movs r3, r0
|
|
}
|
|
8001f7c: 0018 movs r0, r3
|
|
8001f7e: 46bd mov sp, r7
|
|
8001f80: b002 add sp, #8
|
|
8001f82: bd80 pop {r7, pc}
|
|
|
|
08001f84 <HAL_CRC_Init>:
|
|
* parameters in the CRC_InitTypeDef and create the associated handle.
|
|
* @param hcrc CRC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
|
{
|
|
8001f84: b580 push {r7, lr}
|
|
8001f86: b082 sub sp, #8
|
|
8001f88: af00 add r7, sp, #0
|
|
8001f8a: 6078 str r0, [r7, #4]
|
|
/* Check the CRC handle allocation */
|
|
if (hcrc == NULL)
|
|
8001f8c: 687b ldr r3, [r7, #4]
|
|
8001f8e: 2b00 cmp r3, #0
|
|
8001f90: d101 bne.n 8001f96 <HAL_CRC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001f92: 2301 movs r3, #1
|
|
8001f94: e056 b.n 8002044 <HAL_CRC_Init+0xc0>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
|
|
|
if (hcrc->State == HAL_CRC_STATE_RESET)
|
|
8001f96: 687b ldr r3, [r7, #4]
|
|
8001f98: 7f5b ldrb r3, [r3, #29]
|
|
8001f9a: b2db uxtb r3, r3
|
|
8001f9c: 2b00 cmp r3, #0
|
|
8001f9e: d106 bne.n 8001fae <HAL_CRC_Init+0x2a>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hcrc->Lock = HAL_UNLOCKED;
|
|
8001fa0: 687b ldr r3, [r7, #4]
|
|
8001fa2: 2200 movs r2, #0
|
|
8001fa4: 771a strb r2, [r3, #28]
|
|
/* Init the low level hardware */
|
|
HAL_CRC_MspInit(hcrc);
|
|
8001fa6: 687b ldr r3, [r7, #4]
|
|
8001fa8: 0018 movs r0, r3
|
|
8001faa: f7ff fcd9 bl 8001960 <HAL_CRC_MspInit>
|
|
}
|
|
|
|
hcrc->State = HAL_CRC_STATE_BUSY;
|
|
8001fae: 687b ldr r3, [r7, #4]
|
|
8001fb0: 2202 movs r2, #2
|
|
8001fb2: 775a strb r2, [r3, #29]
|
|
|
|
/* check whether or not non-default generating polynomial has been
|
|
* picked up by user */
|
|
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
|
|
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
|
|
8001fb4: 687b ldr r3, [r7, #4]
|
|
8001fb6: 791b ldrb r3, [r3, #4]
|
|
8001fb8: 2b00 cmp r3, #0
|
|
8001fba: d10c bne.n 8001fd6 <HAL_CRC_Init+0x52>
|
|
{
|
|
/* initialize peripheral with default generating polynomial */
|
|
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
|
|
8001fbc: 687b ldr r3, [r7, #4]
|
|
8001fbe: 681b ldr r3, [r3, #0]
|
|
8001fc0: 4a22 ldr r2, [pc, #136] ; (800204c <HAL_CRC_Init+0xc8>)
|
|
8001fc2: 615a str r2, [r3, #20]
|
|
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
|
|
8001fc4: 687b ldr r3, [r7, #4]
|
|
8001fc6: 681b ldr r3, [r3, #0]
|
|
8001fc8: 689a ldr r2, [r3, #8]
|
|
8001fca: 687b ldr r3, [r7, #4]
|
|
8001fcc: 681b ldr r3, [r3, #0]
|
|
8001fce: 2118 movs r1, #24
|
|
8001fd0: 438a bics r2, r1
|
|
8001fd2: 609a str r2, [r3, #8]
|
|
8001fd4: e00b b.n 8001fee <HAL_CRC_Init+0x6a>
|
|
}
|
|
else
|
|
{
|
|
/* initialize CRC peripheral with generating polynomial defined by user */
|
|
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
|
|
8001fd6: 687b ldr r3, [r7, #4]
|
|
8001fd8: 6899 ldr r1, [r3, #8]
|
|
8001fda: 687b ldr r3, [r7, #4]
|
|
8001fdc: 68da ldr r2, [r3, #12]
|
|
8001fde: 687b ldr r3, [r7, #4]
|
|
8001fe0: 0018 movs r0, r3
|
|
8001fe2: f000 f94c bl 800227e <HAL_CRCEx_Polynomial_Set>
|
|
8001fe6: 1e03 subs r3, r0, #0
|
|
8001fe8: d001 beq.n 8001fee <HAL_CRC_Init+0x6a>
|
|
{
|
|
return HAL_ERROR;
|
|
8001fea: 2301 movs r3, #1
|
|
8001fec: e02a b.n 8002044 <HAL_CRC_Init+0xc0>
|
|
}
|
|
|
|
/* check whether or not non-default CRC initial value has been
|
|
* picked up by user */
|
|
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
|
|
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
|
|
8001fee: 687b ldr r3, [r7, #4]
|
|
8001ff0: 795b ldrb r3, [r3, #5]
|
|
8001ff2: 2b00 cmp r3, #0
|
|
8001ff4: d105 bne.n 8002002 <HAL_CRC_Init+0x7e>
|
|
{
|
|
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
|
|
8001ff6: 687b ldr r3, [r7, #4]
|
|
8001ff8: 681b ldr r3, [r3, #0]
|
|
8001ffa: 2201 movs r2, #1
|
|
8001ffc: 4252 negs r2, r2
|
|
8001ffe: 611a str r2, [r3, #16]
|
|
8002000: e004 b.n 800200c <HAL_CRC_Init+0x88>
|
|
}
|
|
else
|
|
{
|
|
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
|
|
8002002: 687b ldr r3, [r7, #4]
|
|
8002004: 681b ldr r3, [r3, #0]
|
|
8002006: 687a ldr r2, [r7, #4]
|
|
8002008: 6912 ldr r2, [r2, #16]
|
|
800200a: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
|
|
/* set input data inversion mode */
|
|
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
|
|
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
|
|
800200c: 687b ldr r3, [r7, #4]
|
|
800200e: 681b ldr r3, [r3, #0]
|
|
8002010: 689b ldr r3, [r3, #8]
|
|
8002012: 2260 movs r2, #96 ; 0x60
|
|
8002014: 4393 bics r3, r2
|
|
8002016: 0019 movs r1, r3
|
|
8002018: 687b ldr r3, [r7, #4]
|
|
800201a: 695a ldr r2, [r3, #20]
|
|
800201c: 687b ldr r3, [r7, #4]
|
|
800201e: 681b ldr r3, [r3, #0]
|
|
8002020: 430a orrs r2, r1
|
|
8002022: 609a str r2, [r3, #8]
|
|
|
|
/* set output data inversion mode */
|
|
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
|
|
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
|
|
8002024: 687b ldr r3, [r7, #4]
|
|
8002026: 681b ldr r3, [r3, #0]
|
|
8002028: 689b ldr r3, [r3, #8]
|
|
800202a: 2280 movs r2, #128 ; 0x80
|
|
800202c: 4393 bics r3, r2
|
|
800202e: 0019 movs r1, r3
|
|
8002030: 687b ldr r3, [r7, #4]
|
|
8002032: 699a ldr r2, [r3, #24]
|
|
8002034: 687b ldr r3, [r7, #4]
|
|
8002036: 681b ldr r3, [r3, #0]
|
|
8002038: 430a orrs r2, r1
|
|
800203a: 609a str r2, [r3, #8]
|
|
/* makes sure the input data format (bytes, halfwords or words stream)
|
|
* is properly specified by user */
|
|
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
|
|
|
|
/* Change CRC peripheral state */
|
|
hcrc->State = HAL_CRC_STATE_READY;
|
|
800203c: 687b ldr r3, [r7, #4]
|
|
800203e: 2201 movs r2, #1
|
|
8002040: 775a strb r2, [r3, #29]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8002042: 2300 movs r3, #0
|
|
}
|
|
8002044: 0018 movs r0, r3
|
|
8002046: 46bd mov sp, r7
|
|
8002048: b002 add sp, #8
|
|
800204a: bd80 pop {r7, pc}
|
|
800204c: 04c11db7 .word 0x04c11db7
|
|
|
|
08002050 <HAL_CRC_Calculate>:
|
|
* and the API will internally adjust its input data processing based on the
|
|
* handle field hcrc->InputDataFormat.
|
|
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
|
*/
|
|
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
|
{
|
|
8002050: b580 push {r7, lr}
|
|
8002052: b086 sub sp, #24
|
|
8002054: af00 add r7, sp, #0
|
|
8002056: 60f8 str r0, [r7, #12]
|
|
8002058: 60b9 str r1, [r7, #8]
|
|
800205a: 607a str r2, [r7, #4]
|
|
uint32_t index; /* CRC input data buffer index */
|
|
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
|
|
800205c: 2300 movs r3, #0
|
|
800205e: 613b str r3, [r7, #16]
|
|
|
|
/* Change CRC peripheral state */
|
|
hcrc->State = HAL_CRC_STATE_BUSY;
|
|
8002060: 68fb ldr r3, [r7, #12]
|
|
8002062: 2202 movs r2, #2
|
|
8002064: 775a strb r2, [r3, #29]
|
|
|
|
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
|
|
* written in hcrc->Instance->DR) */
|
|
__HAL_CRC_DR_RESET(hcrc);
|
|
8002066: 68fb ldr r3, [r7, #12]
|
|
8002068: 681b ldr r3, [r3, #0]
|
|
800206a: 689a ldr r2, [r3, #8]
|
|
800206c: 68fb ldr r3, [r7, #12]
|
|
800206e: 681b ldr r3, [r3, #0]
|
|
8002070: 2101 movs r1, #1
|
|
8002072: 430a orrs r2, r1
|
|
8002074: 609a str r2, [r3, #8]
|
|
|
|
switch (hcrc->InputDataFormat)
|
|
8002076: 68fb ldr r3, [r7, #12]
|
|
8002078: 6a1b ldr r3, [r3, #32]
|
|
800207a: 2b03 cmp r3, #3
|
|
800207c: d005 beq.n 800208a <HAL_CRC_Calculate+0x3a>
|
|
800207e: d82d bhi.n 80020dc <HAL_CRC_Calculate+0x8c>
|
|
8002080: 2b01 cmp r3, #1
|
|
8002082: d019 beq.n 80020b8 <HAL_CRC_Calculate+0x68>
|
|
8002084: 2b02 cmp r3, #2
|
|
8002086: d020 beq.n 80020ca <HAL_CRC_Calculate+0x7a>
|
|
/* Specific 16-bit input data handling */
|
|
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
8002088: e028 b.n 80020dc <HAL_CRC_Calculate+0x8c>
|
|
for (index = 0U; index < BufferLength; index++)
|
|
800208a: 2300 movs r3, #0
|
|
800208c: 617b str r3, [r7, #20]
|
|
800208e: e00a b.n 80020a6 <HAL_CRC_Calculate+0x56>
|
|
hcrc->Instance->DR = pBuffer[index];
|
|
8002090: 697b ldr r3, [r7, #20]
|
|
8002092: 009b lsls r3, r3, #2
|
|
8002094: 68ba ldr r2, [r7, #8]
|
|
8002096: 18d2 adds r2, r2, r3
|
|
8002098: 68fb ldr r3, [r7, #12]
|
|
800209a: 681b ldr r3, [r3, #0]
|
|
800209c: 6812 ldr r2, [r2, #0]
|
|
800209e: 601a str r2, [r3, #0]
|
|
for (index = 0U; index < BufferLength; index++)
|
|
80020a0: 697b ldr r3, [r7, #20]
|
|
80020a2: 3301 adds r3, #1
|
|
80020a4: 617b str r3, [r7, #20]
|
|
80020a6: 697a ldr r2, [r7, #20]
|
|
80020a8: 687b ldr r3, [r7, #4]
|
|
80020aa: 429a cmp r2, r3
|
|
80020ac: d3f0 bcc.n 8002090 <HAL_CRC_Calculate+0x40>
|
|
temp = hcrc->Instance->DR;
|
|
80020ae: 68fb ldr r3, [r7, #12]
|
|
80020b0: 681b ldr r3, [r3, #0]
|
|
80020b2: 681b ldr r3, [r3, #0]
|
|
80020b4: 613b str r3, [r7, #16]
|
|
break;
|
|
80020b6: e012 b.n 80020de <HAL_CRC_Calculate+0x8e>
|
|
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
|
|
80020b8: 687a ldr r2, [r7, #4]
|
|
80020ba: 68b9 ldr r1, [r7, #8]
|
|
80020bc: 68fb ldr r3, [r7, #12]
|
|
80020be: 0018 movs r0, r3
|
|
80020c0: f000 f815 bl 80020ee <CRC_Handle_8>
|
|
80020c4: 0003 movs r3, r0
|
|
80020c6: 613b str r3, [r7, #16]
|
|
break;
|
|
80020c8: e009 b.n 80020de <HAL_CRC_Calculate+0x8e>
|
|
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
|
|
80020ca: 687a ldr r2, [r7, #4]
|
|
80020cc: 68b9 ldr r1, [r7, #8]
|
|
80020ce: 68fb ldr r3, [r7, #12]
|
|
80020d0: 0018 movs r0, r3
|
|
80020d2: f000 f89d bl 8002210 <CRC_Handle_16>
|
|
80020d6: 0003 movs r3, r0
|
|
80020d8: 613b str r3, [r7, #16]
|
|
break;
|
|
80020da: e000 b.n 80020de <HAL_CRC_Calculate+0x8e>
|
|
break;
|
|
80020dc: 46c0 nop ; (mov r8, r8)
|
|
}
|
|
|
|
/* Change CRC peripheral state */
|
|
hcrc->State = HAL_CRC_STATE_READY;
|
|
80020de: 68fb ldr r3, [r7, #12]
|
|
80020e0: 2201 movs r2, #1
|
|
80020e2: 775a strb r2, [r3, #29]
|
|
|
|
/* Return the CRC computed value */
|
|
return temp;
|
|
80020e4: 693b ldr r3, [r7, #16]
|
|
}
|
|
80020e6: 0018 movs r0, r3
|
|
80020e8: 46bd mov sp, r7
|
|
80020ea: b006 add sp, #24
|
|
80020ec: bd80 pop {r7, pc}
|
|
|
|
080020ee <CRC_Handle_8>:
|
|
* @param pBuffer pointer to the input data buffer
|
|
* @param BufferLength input data buffer length
|
|
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
|
*/
|
|
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
|
|
{
|
|
80020ee: b580 push {r7, lr}
|
|
80020f0: b088 sub sp, #32
|
|
80020f2: af00 add r7, sp, #0
|
|
80020f4: 60f8 str r0, [r7, #12]
|
|
80020f6: 60b9 str r1, [r7, #8]
|
|
80020f8: 607a str r2, [r7, #4]
|
|
__IO uint16_t *pReg;
|
|
|
|
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
|
|
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
|
|
* handling by the peripheral */
|
|
for (i = 0U; i < (BufferLength / 4U); i++)
|
|
80020fa: 2300 movs r3, #0
|
|
80020fc: 61fb str r3, [r7, #28]
|
|
80020fe: e023 b.n 8002148 <CRC_Handle_8+0x5a>
|
|
{
|
|
hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
|
|
8002100: 69fb ldr r3, [r7, #28]
|
|
8002102: 009b lsls r3, r3, #2
|
|
8002104: 68ba ldr r2, [r7, #8]
|
|
8002106: 18d3 adds r3, r2, r3
|
|
8002108: 781b ldrb r3, [r3, #0]
|
|
800210a: 061a lsls r2, r3, #24
|
|
((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
|
|
800210c: 69fb ldr r3, [r7, #28]
|
|
800210e: 009b lsls r3, r3, #2
|
|
8002110: 3301 adds r3, #1
|
|
8002112: 68b9 ldr r1, [r7, #8]
|
|
8002114: 18cb adds r3, r1, r3
|
|
8002116: 781b ldrb r3, [r3, #0]
|
|
8002118: 041b lsls r3, r3, #16
|
|
hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
|
|
800211a: 431a orrs r2, r3
|
|
((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
|
|
800211c: 69fb ldr r3, [r7, #28]
|
|
800211e: 009b lsls r3, r3, #2
|
|
8002120: 3302 adds r3, #2
|
|
8002122: 68b9 ldr r1, [r7, #8]
|
|
8002124: 18cb adds r3, r1, r3
|
|
8002126: 781b ldrb r3, [r3, #0]
|
|
8002128: 021b lsls r3, r3, #8
|
|
((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
|
|
800212a: 431a orrs r2, r3
|
|
(uint32_t)pBuffer[(4U * i) + 3U];
|
|
800212c: 69fb ldr r3, [r7, #28]
|
|
800212e: 009b lsls r3, r3, #2
|
|
8002130: 3303 adds r3, #3
|
|
8002132: 68b9 ldr r1, [r7, #8]
|
|
8002134: 18cb adds r3, r1, r3
|
|
8002136: 781b ldrb r3, [r3, #0]
|
|
8002138: 0019 movs r1, r3
|
|
hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
|
|
800213a: 68fb ldr r3, [r7, #12]
|
|
800213c: 681b ldr r3, [r3, #0]
|
|
((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
|
|
800213e: 430a orrs r2, r1
|
|
hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
|
|
8002140: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < (BufferLength / 4U); i++)
|
|
8002142: 69fb ldr r3, [r7, #28]
|
|
8002144: 3301 adds r3, #1
|
|
8002146: 61fb str r3, [r7, #28]
|
|
8002148: 687b ldr r3, [r7, #4]
|
|
800214a: 089b lsrs r3, r3, #2
|
|
800214c: 69fa ldr r2, [r7, #28]
|
|
800214e: 429a cmp r2, r3
|
|
8002150: d3d6 bcc.n 8002100 <CRC_Handle_8+0x12>
|
|
}
|
|
/* last bytes specific handling */
|
|
if ((BufferLength % 4U) != 0U)
|
|
8002152: 687b ldr r3, [r7, #4]
|
|
8002154: 2203 movs r2, #3
|
|
8002156: 4013 ands r3, r2
|
|
8002158: d053 beq.n 8002202 <CRC_Handle_8+0x114>
|
|
{
|
|
if ((BufferLength % 4U) == 1U)
|
|
800215a: 687b ldr r3, [r7, #4]
|
|
800215c: 2203 movs r2, #3
|
|
800215e: 4013 ands r3, r2
|
|
8002160: 2b01 cmp r3, #1
|
|
8002162: d107 bne.n 8002174 <CRC_Handle_8+0x86>
|
|
{
|
|
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
|
|
8002164: 69fb ldr r3, [r7, #28]
|
|
8002166: 009b lsls r3, r3, #2
|
|
8002168: 68ba ldr r2, [r7, #8]
|
|
800216a: 18d2 adds r2, r2, r3
|
|
800216c: 68fb ldr r3, [r7, #12]
|
|
800216e: 681b ldr r3, [r3, #0]
|
|
8002170: 7812 ldrb r2, [r2, #0]
|
|
8002172: 701a strb r2, [r3, #0]
|
|
}
|
|
if ((BufferLength % 4U) == 2U)
|
|
8002174: 687b ldr r3, [r7, #4]
|
|
8002176: 2203 movs r2, #3
|
|
8002178: 4013 ands r3, r2
|
|
800217a: 2b02 cmp r3, #2
|
|
800217c: d119 bne.n 80021b2 <CRC_Handle_8+0xc4>
|
|
{
|
|
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
|
|
800217e: 69fb ldr r3, [r7, #28]
|
|
8002180: 009b lsls r3, r3, #2
|
|
8002182: 68ba ldr r2, [r7, #8]
|
|
8002184: 18d3 adds r3, r2, r3
|
|
8002186: 781b ldrb r3, [r3, #0]
|
|
8002188: 021b lsls r3, r3, #8
|
|
800218a: b21a sxth r2, r3
|
|
800218c: 69fb ldr r3, [r7, #28]
|
|
800218e: 009b lsls r3, r3, #2
|
|
8002190: 3301 adds r3, #1
|
|
8002192: 68b9 ldr r1, [r7, #8]
|
|
8002194: 18cb adds r3, r1, r3
|
|
8002196: 781b ldrb r3, [r3, #0]
|
|
8002198: b21b sxth r3, r3
|
|
800219a: 4313 orrs r3, r2
|
|
800219c: b21a sxth r2, r3
|
|
800219e: 211a movs r1, #26
|
|
80021a0: 187b adds r3, r7, r1
|
|
80021a2: 801a strh r2, [r3, #0]
|
|
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
|
|
80021a4: 68fb ldr r3, [r7, #12]
|
|
80021a6: 681b ldr r3, [r3, #0]
|
|
80021a8: 617b str r3, [r7, #20]
|
|
*pReg = data;
|
|
80021aa: 697b ldr r3, [r7, #20]
|
|
80021ac: 187a adds r2, r7, r1
|
|
80021ae: 8812 ldrh r2, [r2, #0]
|
|
80021b0: 801a strh r2, [r3, #0]
|
|
}
|
|
if ((BufferLength % 4U) == 3U)
|
|
80021b2: 687b ldr r3, [r7, #4]
|
|
80021b4: 2203 movs r2, #3
|
|
80021b6: 4013 ands r3, r2
|
|
80021b8: 2b03 cmp r3, #3
|
|
80021ba: d122 bne.n 8002202 <CRC_Handle_8+0x114>
|
|
{
|
|
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
|
|
80021bc: 69fb ldr r3, [r7, #28]
|
|
80021be: 009b lsls r3, r3, #2
|
|
80021c0: 68ba ldr r2, [r7, #8]
|
|
80021c2: 18d3 adds r3, r2, r3
|
|
80021c4: 781b ldrb r3, [r3, #0]
|
|
80021c6: 021b lsls r3, r3, #8
|
|
80021c8: b21a sxth r2, r3
|
|
80021ca: 69fb ldr r3, [r7, #28]
|
|
80021cc: 009b lsls r3, r3, #2
|
|
80021ce: 3301 adds r3, #1
|
|
80021d0: 68b9 ldr r1, [r7, #8]
|
|
80021d2: 18cb adds r3, r1, r3
|
|
80021d4: 781b ldrb r3, [r3, #0]
|
|
80021d6: b21b sxth r3, r3
|
|
80021d8: 4313 orrs r3, r2
|
|
80021da: b21a sxth r2, r3
|
|
80021dc: 211a movs r1, #26
|
|
80021de: 187b adds r3, r7, r1
|
|
80021e0: 801a strh r2, [r3, #0]
|
|
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
|
|
80021e2: 68fb ldr r3, [r7, #12]
|
|
80021e4: 681b ldr r3, [r3, #0]
|
|
80021e6: 617b str r3, [r7, #20]
|
|
*pReg = data;
|
|
80021e8: 697b ldr r3, [r7, #20]
|
|
80021ea: 187a adds r2, r7, r1
|
|
80021ec: 8812 ldrh r2, [r2, #0]
|
|
80021ee: 801a strh r2, [r3, #0]
|
|
|
|
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
|
|
80021f0: 69fb ldr r3, [r7, #28]
|
|
80021f2: 009b lsls r3, r3, #2
|
|
80021f4: 3302 adds r3, #2
|
|
80021f6: 68ba ldr r2, [r7, #8]
|
|
80021f8: 18d2 adds r2, r2, r3
|
|
80021fa: 68fb ldr r3, [r7, #12]
|
|
80021fc: 681b ldr r3, [r3, #0]
|
|
80021fe: 7812 ldrb r2, [r2, #0]
|
|
8002200: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
|
|
/* Return the CRC computed value */
|
|
return hcrc->Instance->DR;
|
|
8002202: 68fb ldr r3, [r7, #12]
|
|
8002204: 681b ldr r3, [r3, #0]
|
|
8002206: 681b ldr r3, [r3, #0]
|
|
}
|
|
8002208: 0018 movs r0, r3
|
|
800220a: 46bd mov sp, r7
|
|
800220c: b008 add sp, #32
|
|
800220e: bd80 pop {r7, pc}
|
|
|
|
08002210 <CRC_Handle_16>:
|
|
* @param pBuffer pointer to the input data buffer
|
|
* @param BufferLength input data buffer length
|
|
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
|
*/
|
|
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
|
|
{
|
|
8002210: b580 push {r7, lr}
|
|
8002212: b086 sub sp, #24
|
|
8002214: af00 add r7, sp, #0
|
|
8002216: 60f8 str r0, [r7, #12]
|
|
8002218: 60b9 str r1, [r7, #8]
|
|
800221a: 607a str r2, [r7, #4]
|
|
__IO uint16_t *pReg;
|
|
|
|
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
|
|
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
|
|
* a correct type handling by the peripheral */
|
|
for (i = 0U; i < (BufferLength / 2U); i++)
|
|
800221c: 2300 movs r3, #0
|
|
800221e: 617b str r3, [r7, #20]
|
|
8002220: e013 b.n 800224a <CRC_Handle_16+0x3a>
|
|
{
|
|
hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
|
|
8002222: 697b ldr r3, [r7, #20]
|
|
8002224: 009b lsls r3, r3, #2
|
|
8002226: 68ba ldr r2, [r7, #8]
|
|
8002228: 18d3 adds r3, r2, r3
|
|
800222a: 881b ldrh r3, [r3, #0]
|
|
800222c: 041a lsls r2, r3, #16
|
|
800222e: 697b ldr r3, [r7, #20]
|
|
8002230: 009b lsls r3, r3, #2
|
|
8002232: 3302 adds r3, #2
|
|
8002234: 68b9 ldr r1, [r7, #8]
|
|
8002236: 18cb adds r3, r1, r3
|
|
8002238: 881b ldrh r3, [r3, #0]
|
|
800223a: 0019 movs r1, r3
|
|
800223c: 68fb ldr r3, [r7, #12]
|
|
800223e: 681b ldr r3, [r3, #0]
|
|
8002240: 430a orrs r2, r1
|
|
8002242: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < (BufferLength / 2U); i++)
|
|
8002244: 697b ldr r3, [r7, #20]
|
|
8002246: 3301 adds r3, #1
|
|
8002248: 617b str r3, [r7, #20]
|
|
800224a: 687b ldr r3, [r7, #4]
|
|
800224c: 085b lsrs r3, r3, #1
|
|
800224e: 697a ldr r2, [r7, #20]
|
|
8002250: 429a cmp r2, r3
|
|
8002252: d3e6 bcc.n 8002222 <CRC_Handle_16+0x12>
|
|
}
|
|
if ((BufferLength % 2U) != 0U)
|
|
8002254: 687b ldr r3, [r7, #4]
|
|
8002256: 2201 movs r2, #1
|
|
8002258: 4013 ands r3, r2
|
|
800225a: d009 beq.n 8002270 <CRC_Handle_16+0x60>
|
|
{
|
|
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
|
|
800225c: 68fb ldr r3, [r7, #12]
|
|
800225e: 681b ldr r3, [r3, #0]
|
|
8002260: 613b str r3, [r7, #16]
|
|
*pReg = pBuffer[2U * i];
|
|
8002262: 697b ldr r3, [r7, #20]
|
|
8002264: 009b lsls r3, r3, #2
|
|
8002266: 68ba ldr r2, [r7, #8]
|
|
8002268: 18d3 adds r3, r2, r3
|
|
800226a: 881a ldrh r2, [r3, #0]
|
|
800226c: 693b ldr r3, [r7, #16]
|
|
800226e: 801a strh r2, [r3, #0]
|
|
}
|
|
|
|
/* Return the CRC computed value */
|
|
return hcrc->Instance->DR;
|
|
8002270: 68fb ldr r3, [r7, #12]
|
|
8002272: 681b ldr r3, [r3, #0]
|
|
8002274: 681b ldr r3, [r3, #0]
|
|
}
|
|
8002276: 0018 movs r0, r3
|
|
8002278: 46bd mov sp, r7
|
|
800227a: b006 add sp, #24
|
|
800227c: bd80 pop {r7, pc}
|
|
|
|
0800227e <HAL_CRCEx_Polynomial_Set>:
|
|
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
|
|
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
|
|
{
|
|
800227e: b580 push {r7, lr}
|
|
8002280: b086 sub sp, #24
|
|
8002282: af00 add r7, sp, #0
|
|
8002284: 60f8 str r0, [r7, #12]
|
|
8002286: 60b9 str r1, [r7, #8]
|
|
8002288: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800228a: 2317 movs r3, #23
|
|
800228c: 18fb adds r3, r7, r3
|
|
800228e: 2200 movs r2, #0
|
|
8002290: 701a strb r2, [r3, #0]
|
|
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
|
|
8002292: 231f movs r3, #31
|
|
8002294: 613b str r3, [r7, #16]
|
|
* definition. HAL_ERROR is reported if Pol degree is
|
|
* larger than that indicated by PolyLength.
|
|
* Look for MSB position: msb will contain the degree of
|
|
* the second to the largest polynomial member. E.g., for
|
|
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
|
|
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
|
|
8002296: 46c0 nop ; (mov r8, r8)
|
|
8002298: 693b ldr r3, [r7, #16]
|
|
800229a: 1e5a subs r2, r3, #1
|
|
800229c: 613a str r2, [r7, #16]
|
|
800229e: 2b00 cmp r3, #0
|
|
80022a0: d008 beq.n 80022b4 <HAL_CRCEx_Polynomial_Set+0x36>
|
|
80022a2: 693b ldr r3, [r7, #16]
|
|
80022a4: 221f movs r2, #31
|
|
80022a6: 4013 ands r3, r2
|
|
80022a8: 68ba ldr r2, [r7, #8]
|
|
80022aa: 40da lsrs r2, r3
|
|
80022ac: 0013 movs r3, r2
|
|
80022ae: 2201 movs r2, #1
|
|
80022b0: 4013 ands r3, r2
|
|
80022b2: d0f1 beq.n 8002298 <HAL_CRCEx_Polynomial_Set+0x1a>
|
|
{
|
|
}
|
|
|
|
switch (PolyLength)
|
|
80022b4: 687b ldr r3, [r7, #4]
|
|
80022b6: 2b18 cmp r3, #24
|
|
80022b8: d00f beq.n 80022da <HAL_CRCEx_Polynomial_Set+0x5c>
|
|
80022ba: 687b ldr r3, [r7, #4]
|
|
80022bc: 2b18 cmp r3, #24
|
|
80022be: d824 bhi.n 800230a <HAL_CRCEx_Polynomial_Set+0x8c>
|
|
80022c0: 687b ldr r3, [r7, #4]
|
|
80022c2: 2b10 cmp r3, #16
|
|
80022c4: d011 beq.n 80022ea <HAL_CRCEx_Polynomial_Set+0x6c>
|
|
80022c6: 687b ldr r3, [r7, #4]
|
|
80022c8: 2b10 cmp r3, #16
|
|
80022ca: d81e bhi.n 800230a <HAL_CRCEx_Polynomial_Set+0x8c>
|
|
80022cc: 687b ldr r3, [r7, #4]
|
|
80022ce: 2b00 cmp r3, #0
|
|
80022d0: d020 beq.n 8002314 <HAL_CRCEx_Polynomial_Set+0x96>
|
|
80022d2: 687b ldr r3, [r7, #4]
|
|
80022d4: 2b08 cmp r3, #8
|
|
80022d6: d010 beq.n 80022fa <HAL_CRCEx_Polynomial_Set+0x7c>
|
|
80022d8: e017 b.n 800230a <HAL_CRCEx_Polynomial_Set+0x8c>
|
|
{
|
|
case CRC_POLYLENGTH_7B:
|
|
if (msb >= HAL_CRC_LENGTH_7B)
|
|
80022da: 693b ldr r3, [r7, #16]
|
|
80022dc: 2b06 cmp r3, #6
|
|
80022de: d91b bls.n 8002318 <HAL_CRCEx_Polynomial_Set+0x9a>
|
|
{
|
|
status = HAL_ERROR;
|
|
80022e0: 2317 movs r3, #23
|
|
80022e2: 18fb adds r3, r7, r3
|
|
80022e4: 2201 movs r2, #1
|
|
80022e6: 701a strb r2, [r3, #0]
|
|
}
|
|
break;
|
|
80022e8: e016 b.n 8002318 <HAL_CRCEx_Polynomial_Set+0x9a>
|
|
case CRC_POLYLENGTH_8B:
|
|
if (msb >= HAL_CRC_LENGTH_8B)
|
|
80022ea: 693b ldr r3, [r7, #16]
|
|
80022ec: 2b07 cmp r3, #7
|
|
80022ee: d915 bls.n 800231c <HAL_CRCEx_Polynomial_Set+0x9e>
|
|
{
|
|
status = HAL_ERROR;
|
|
80022f0: 2317 movs r3, #23
|
|
80022f2: 18fb adds r3, r7, r3
|
|
80022f4: 2201 movs r2, #1
|
|
80022f6: 701a strb r2, [r3, #0]
|
|
}
|
|
break;
|
|
80022f8: e010 b.n 800231c <HAL_CRCEx_Polynomial_Set+0x9e>
|
|
case CRC_POLYLENGTH_16B:
|
|
if (msb >= HAL_CRC_LENGTH_16B)
|
|
80022fa: 693b ldr r3, [r7, #16]
|
|
80022fc: 2b0f cmp r3, #15
|
|
80022fe: d90f bls.n 8002320 <HAL_CRCEx_Polynomial_Set+0xa2>
|
|
{
|
|
status = HAL_ERROR;
|
|
8002300: 2317 movs r3, #23
|
|
8002302: 18fb adds r3, r7, r3
|
|
8002304: 2201 movs r2, #1
|
|
8002306: 701a strb r2, [r3, #0]
|
|
}
|
|
break;
|
|
8002308: e00a b.n 8002320 <HAL_CRCEx_Polynomial_Set+0xa2>
|
|
|
|
case CRC_POLYLENGTH_32B:
|
|
/* no polynomial definition vs. polynomial length issue possible */
|
|
break;
|
|
default:
|
|
status = HAL_ERROR;
|
|
800230a: 2317 movs r3, #23
|
|
800230c: 18fb adds r3, r7, r3
|
|
800230e: 2201 movs r2, #1
|
|
8002310: 701a strb r2, [r3, #0]
|
|
break;
|
|
8002312: e006 b.n 8002322 <HAL_CRCEx_Polynomial_Set+0xa4>
|
|
break;
|
|
8002314: 46c0 nop ; (mov r8, r8)
|
|
8002316: e004 b.n 8002322 <HAL_CRCEx_Polynomial_Set+0xa4>
|
|
break;
|
|
8002318: 46c0 nop ; (mov r8, r8)
|
|
800231a: e002 b.n 8002322 <HAL_CRCEx_Polynomial_Set+0xa4>
|
|
break;
|
|
800231c: 46c0 nop ; (mov r8, r8)
|
|
800231e: e000 b.n 8002322 <HAL_CRCEx_Polynomial_Set+0xa4>
|
|
break;
|
|
8002320: 46c0 nop ; (mov r8, r8)
|
|
}
|
|
if (status == HAL_OK)
|
|
8002322: 2317 movs r3, #23
|
|
8002324: 18fb adds r3, r7, r3
|
|
8002326: 781b ldrb r3, [r3, #0]
|
|
8002328: 2b00 cmp r3, #0
|
|
800232a: d10e bne.n 800234a <HAL_CRCEx_Polynomial_Set+0xcc>
|
|
{
|
|
/* set generating polynomial */
|
|
WRITE_REG(hcrc->Instance->POL, Pol);
|
|
800232c: 68fb ldr r3, [r7, #12]
|
|
800232e: 681b ldr r3, [r3, #0]
|
|
8002330: 68ba ldr r2, [r7, #8]
|
|
8002332: 615a str r2, [r3, #20]
|
|
|
|
/* set generating polynomial size */
|
|
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
|
|
8002334: 68fb ldr r3, [r7, #12]
|
|
8002336: 681b ldr r3, [r3, #0]
|
|
8002338: 689b ldr r3, [r3, #8]
|
|
800233a: 2218 movs r2, #24
|
|
800233c: 4393 bics r3, r2
|
|
800233e: 0019 movs r1, r3
|
|
8002340: 68fb ldr r3, [r7, #12]
|
|
8002342: 681b ldr r3, [r3, #0]
|
|
8002344: 687a ldr r2, [r7, #4]
|
|
8002346: 430a orrs r2, r1
|
|
8002348: 609a str r2, [r3, #8]
|
|
}
|
|
/* Return function status */
|
|
return status;
|
|
800234a: 2317 movs r3, #23
|
|
800234c: 18fb adds r3, r7, r3
|
|
800234e: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8002350: 0018 movs r0, r3
|
|
8002352: 46bd mov sp, r7
|
|
8002354: b006 add sp, #24
|
|
8002356: bd80 pop {r7, pc}
|
|
|
|
08002358 <HAL_FLASH_Program>:
|
|
* TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit).
|
|
*
|
|
* @retval HAL_StatusTypeDef HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
|
{
|
|
8002358: b5b0 push {r4, r5, r7, lr}
|
|
800235a: b086 sub sp, #24
|
|
800235c: af00 add r7, sp, #0
|
|
800235e: 60f8 str r0, [r7, #12]
|
|
8002360: 60b9 str r1, [r7, #8]
|
|
8002362: 603a str r2, [r7, #0]
|
|
8002364: 607b str r3, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(&pFlash);
|
|
8002366: 4b21 ldr r3, [pc, #132] ; (80023ec <HAL_FLASH_Program+0x94>)
|
|
8002368: 781b ldrb r3, [r3, #0]
|
|
800236a: 2b01 cmp r3, #1
|
|
800236c: d101 bne.n 8002372 <HAL_FLASH_Program+0x1a>
|
|
800236e: 2302 movs r3, #2
|
|
8002370: e038 b.n 80023e4 <HAL_FLASH_Program+0x8c>
|
|
8002372: 4b1e ldr r3, [pc, #120] ; (80023ec <HAL_FLASH_Program+0x94>)
|
|
8002374: 2201 movs r2, #1
|
|
8002376: 701a strb r2, [r3, #0]
|
|
|
|
/* Reset error code */
|
|
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
|
8002378: 4b1c ldr r3, [pc, #112] ; (80023ec <HAL_FLASH_Program+0x94>)
|
|
800237a: 2200 movs r2, #0
|
|
800237c: 605a str r2, [r3, #4]
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
|
800237e: 2517 movs r5, #23
|
|
8002380: 197c adds r4, r7, r5
|
|
8002382: 23fa movs r3, #250 ; 0xfa
|
|
8002384: 009b lsls r3, r3, #2
|
|
8002386: 0018 movs r0, r3
|
|
8002388: f000 f874 bl 8002474 <FLASH_WaitForLastOperation>
|
|
800238c: 0003 movs r3, r0
|
|
800238e: 7023 strb r3, [r4, #0]
|
|
|
|
if (status == HAL_OK)
|
|
8002390: 197b adds r3, r7, r5
|
|
8002392: 781b ldrb r3, [r3, #0]
|
|
8002394: 2b00 cmp r3, #0
|
|
8002396: d11f bne.n 80023d8 <HAL_FLASH_Program+0x80>
|
|
{
|
|
if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
|
|
8002398: 68fb ldr r3, [r7, #12]
|
|
800239a: 2b01 cmp r3, #1
|
|
800239c: d106 bne.n 80023ac <HAL_FLASH_Program+0x54>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
|
|
|
/* Program double-word (64-bit) at a specified address */
|
|
FLASH_Program_DoubleWord(Address, Data);
|
|
800239e: 683a ldr r2, [r7, #0]
|
|
80023a0: 687b ldr r3, [r7, #4]
|
|
80023a2: 68b9 ldr r1, [r7, #8]
|
|
80023a4: 0008 movs r0, r1
|
|
80023a6: f000 f8b3 bl 8002510 <FLASH_Program_DoubleWord>
|
|
80023aa: e005 b.n 80023b8 <HAL_FLASH_Program+0x60>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address));
|
|
|
|
/* Fast program a 32 row double-word (64-bit) at a specified address */
|
|
FLASH_Program_Fast(Address, (uint32_t)Data);
|
|
80023ac: 683a ldr r2, [r7, #0]
|
|
80023ae: 68bb ldr r3, [r7, #8]
|
|
80023b0: 0011 movs r1, r2
|
|
80023b2: 0018 movs r0, r3
|
|
80023b4: f004 f9f0 bl 8006798 <__FLASH_Program_Fast_veneer>
|
|
}
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
|
80023b8: 2317 movs r3, #23
|
|
80023ba: 18fc adds r4, r7, r3
|
|
80023bc: 23fa movs r3, #250 ; 0xfa
|
|
80023be: 009b lsls r3, r3, #2
|
|
80023c0: 0018 movs r0, r3
|
|
80023c2: f000 f857 bl 8002474 <FLASH_WaitForLastOperation>
|
|
80023c6: 0003 movs r3, r0
|
|
80023c8: 7023 strb r3, [r4, #0]
|
|
|
|
/* If the program operation is completed, disable the PG or FSTPG Bit */
|
|
CLEAR_BIT(FLASH->CR, TypeProgram);
|
|
80023ca: 4b09 ldr r3, [pc, #36] ; (80023f0 <HAL_FLASH_Program+0x98>)
|
|
80023cc: 695a ldr r2, [r3, #20]
|
|
80023ce: 68fb ldr r3, [r7, #12]
|
|
80023d0: 43d9 mvns r1, r3
|
|
80023d2: 4b07 ldr r3, [pc, #28] ; (80023f0 <HAL_FLASH_Program+0x98>)
|
|
80023d4: 400a ands r2, r1
|
|
80023d6: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(&pFlash);
|
|
80023d8: 4b04 ldr r3, [pc, #16] ; (80023ec <HAL_FLASH_Program+0x94>)
|
|
80023da: 2200 movs r2, #0
|
|
80023dc: 701a strb r2, [r3, #0]
|
|
|
|
/* return status */
|
|
return status;
|
|
80023de: 2317 movs r3, #23
|
|
80023e0: 18fb adds r3, r7, r3
|
|
80023e2: 781b ldrb r3, [r3, #0]
|
|
}
|
|
80023e4: 0018 movs r0, r3
|
|
80023e6: 46bd mov sp, r7
|
|
80023e8: b006 add sp, #24
|
|
80023ea: bdb0 pop {r4, r5, r7, pc}
|
|
80023ec: 2000023c .word 0x2000023c
|
|
80023f0: 40022000 .word 0x40022000
|
|
|
|
080023f4 <HAL_FLASH_Unlock>:
|
|
/**
|
|
* @brief Unlock the FLASH control register access.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
|
{
|
|
80023f4: b580 push {r7, lr}
|
|
80023f6: b082 sub sp, #8
|
|
80023f8: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80023fa: 1dfb adds r3, r7, #7
|
|
80023fc: 2200 movs r2, #0
|
|
80023fe: 701a strb r2, [r3, #0]
|
|
|
|
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U)
|
|
8002400: 4b0b ldr r3, [pc, #44] ; (8002430 <HAL_FLASH_Unlock+0x3c>)
|
|
8002402: 695b ldr r3, [r3, #20]
|
|
8002404: 2b00 cmp r3, #0
|
|
8002406: da0c bge.n 8002422 <HAL_FLASH_Unlock+0x2e>
|
|
{
|
|
/* Authorize the FLASH Registers access */
|
|
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
|
|
8002408: 4b09 ldr r3, [pc, #36] ; (8002430 <HAL_FLASH_Unlock+0x3c>)
|
|
800240a: 4a0a ldr r2, [pc, #40] ; (8002434 <HAL_FLASH_Unlock+0x40>)
|
|
800240c: 609a str r2, [r3, #8]
|
|
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
|
|
800240e: 4b08 ldr r3, [pc, #32] ; (8002430 <HAL_FLASH_Unlock+0x3c>)
|
|
8002410: 4a09 ldr r2, [pc, #36] ; (8002438 <HAL_FLASH_Unlock+0x44>)
|
|
8002412: 609a str r2, [r3, #8]
|
|
|
|
/* verify Flash is unlock */
|
|
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U)
|
|
8002414: 4b06 ldr r3, [pc, #24] ; (8002430 <HAL_FLASH_Unlock+0x3c>)
|
|
8002416: 695b ldr r3, [r3, #20]
|
|
8002418: 2b00 cmp r3, #0
|
|
800241a: da02 bge.n 8002422 <HAL_FLASH_Unlock+0x2e>
|
|
{
|
|
status = HAL_ERROR;
|
|
800241c: 1dfb adds r3, r7, #7
|
|
800241e: 2201 movs r2, #1
|
|
8002420: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8002422: 1dfb adds r3, r7, #7
|
|
8002424: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8002426: 0018 movs r0, r3
|
|
8002428: 46bd mov sp, r7
|
|
800242a: b002 add sp, #8
|
|
800242c: bd80 pop {r7, pc}
|
|
800242e: 46c0 nop ; (mov r8, r8)
|
|
8002430: 40022000 .word 0x40022000
|
|
8002434: 45670123 .word 0x45670123
|
|
8002438: cdef89ab .word 0xcdef89ab
|
|
|
|
0800243c <HAL_FLASH_Lock>:
|
|
/**
|
|
* @brief Lock the FLASH control register access.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
|
{
|
|
800243c: b580 push {r7, lr}
|
|
800243e: b082 sub sp, #8
|
|
8002440: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_ERROR;
|
|
8002442: 1dfb adds r3, r7, #7
|
|
8002444: 2201 movs r2, #1
|
|
8002446: 701a strb r2, [r3, #0]
|
|
|
|
/* Set the LOCK Bit to lock the FLASH Registers access */
|
|
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
|
|
8002448: 4b09 ldr r3, [pc, #36] ; (8002470 <HAL_FLASH_Lock+0x34>)
|
|
800244a: 695a ldr r2, [r3, #20]
|
|
800244c: 4b08 ldr r3, [pc, #32] ; (8002470 <HAL_FLASH_Lock+0x34>)
|
|
800244e: 2180 movs r1, #128 ; 0x80
|
|
8002450: 0609 lsls r1, r1, #24
|
|
8002452: 430a orrs r2, r1
|
|
8002454: 615a str r2, [r3, #20]
|
|
|
|
/* verify Flash is locked */
|
|
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00u)
|
|
8002456: 4b06 ldr r3, [pc, #24] ; (8002470 <HAL_FLASH_Lock+0x34>)
|
|
8002458: 695b ldr r3, [r3, #20]
|
|
800245a: 2b00 cmp r3, #0
|
|
800245c: da02 bge.n 8002464 <HAL_FLASH_Lock+0x28>
|
|
{
|
|
status = HAL_OK;
|
|
800245e: 1dfb adds r3, r7, #7
|
|
8002460: 2200 movs r2, #0
|
|
8002462: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
return status;
|
|
8002464: 1dfb adds r3, r7, #7
|
|
8002466: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8002468: 0018 movs r0, r3
|
|
800246a: 46bd mov sp, r7
|
|
800246c: b002 add sp, #8
|
|
800246e: bd80 pop {r7, pc}
|
|
8002470: 40022000 .word 0x40022000
|
|
|
|
08002474 <FLASH_WaitForLastOperation>:
|
|
* @brief Wait for a FLASH operation to complete.
|
|
* @param Timeout maximum flash operation timeout
|
|
* @retval HAL_StatusTypeDef HAL Status
|
|
*/
|
|
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
|
{
|
|
8002474: b580 push {r7, lr}
|
|
8002476: b084 sub sp, #16
|
|
8002478: af00 add r7, sp, #0
|
|
800247a: 6078 str r0, [r7, #4]
|
|
uint32_t error;
|
|
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
|
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
|
flag will be set */
|
|
uint32_t timeout = HAL_GetTick() + Timeout;
|
|
800247c: f7ff fc76 bl 8001d6c <HAL_GetTick>
|
|
8002480: 0002 movs r2, r0
|
|
8002482: 687b ldr r3, [r7, #4]
|
|
8002484: 189b adds r3, r3, r2
|
|
8002486: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait if any operation is ongoing */
|
|
#if defined(FLASH_DBANK_SUPPORT)
|
|
error = (FLASH_SR_BSY1 | FLASH_SR_BSY2);
|
|
#else
|
|
error = FLASH_SR_BSY1;
|
|
8002488: 2380 movs r3, #128 ; 0x80
|
|
800248a: 025b lsls r3, r3, #9
|
|
800248c: 60bb str r3, [r7, #8]
|
|
#endif /* FLASH_DBANK_SUPPORT */
|
|
|
|
while ((FLASH->SR & error) != 0x00U)
|
|
800248e: e007 b.n 80024a0 <FLASH_WaitForLastOperation+0x2c>
|
|
{
|
|
if (HAL_GetTick() >= timeout)
|
|
8002490: f7ff fc6c bl 8001d6c <HAL_GetTick>
|
|
8002494: 0002 movs r2, r0
|
|
8002496: 68fb ldr r3, [r7, #12]
|
|
8002498: 4293 cmp r3, r2
|
|
800249a: d801 bhi.n 80024a0 <FLASH_WaitForLastOperation+0x2c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800249c: 2303 movs r3, #3
|
|
800249e: e02a b.n 80024f6 <FLASH_WaitForLastOperation+0x82>
|
|
while ((FLASH->SR & error) != 0x00U)
|
|
80024a0: 4b17 ldr r3, [pc, #92] ; (8002500 <FLASH_WaitForLastOperation+0x8c>)
|
|
80024a2: 691b ldr r3, [r3, #16]
|
|
80024a4: 68ba ldr r2, [r7, #8]
|
|
80024a6: 4013 ands r3, r2
|
|
80024a8: d1f2 bne.n 8002490 <FLASH_WaitForLastOperation+0x1c>
|
|
}
|
|
}
|
|
|
|
/* check flash errors */
|
|
error = (FLASH->SR & FLASH_SR_ERRORS);
|
|
80024aa: 4b15 ldr r3, [pc, #84] ; (8002500 <FLASH_WaitForLastOperation+0x8c>)
|
|
80024ac: 691b ldr r3, [r3, #16]
|
|
80024ae: 4a15 ldr r2, [pc, #84] ; (8002504 <FLASH_WaitForLastOperation+0x90>)
|
|
80024b0: 4013 ands r3, r2
|
|
80024b2: 60bb str r3, [r7, #8]
|
|
|
|
/* Clear SR register */
|
|
FLASH->SR = FLASH_SR_CLEAR;
|
|
80024b4: 4b12 ldr r3, [pc, #72] ; (8002500 <FLASH_WaitForLastOperation+0x8c>)
|
|
80024b6: 4a14 ldr r2, [pc, #80] ; (8002508 <FLASH_WaitForLastOperation+0x94>)
|
|
80024b8: 611a str r2, [r3, #16]
|
|
|
|
if (error != 0x00U)
|
|
80024ba: 68bb ldr r3, [r7, #8]
|
|
80024bc: 2b00 cmp r3, #0
|
|
80024be: d004 beq.n 80024ca <FLASH_WaitForLastOperation+0x56>
|
|
{
|
|
/*Save the error code*/
|
|
pFlash.ErrorCode = error;
|
|
80024c0: 4b12 ldr r3, [pc, #72] ; (800250c <FLASH_WaitForLastOperation+0x98>)
|
|
80024c2: 68ba ldr r2, [r7, #8]
|
|
80024c4: 605a str r2, [r3, #4]
|
|
return HAL_ERROR;
|
|
80024c6: 2301 movs r3, #1
|
|
80024c8: e015 b.n 80024f6 <FLASH_WaitForLastOperation+0x82>
|
|
}
|
|
|
|
/* Wait for control register to be written */
|
|
timeout = HAL_GetTick() + Timeout;
|
|
80024ca: f7ff fc4f bl 8001d6c <HAL_GetTick>
|
|
80024ce: 0002 movs r2, r0
|
|
80024d0: 687b ldr r3, [r7, #4]
|
|
80024d2: 189b adds r3, r3, r2
|
|
80024d4: 60fb str r3, [r7, #12]
|
|
|
|
while ((FLASH->SR & FLASH_SR_CFGBSY) != 0x00U)
|
|
80024d6: e007 b.n 80024e8 <FLASH_WaitForLastOperation+0x74>
|
|
{
|
|
if (HAL_GetTick() >= timeout)
|
|
80024d8: f7ff fc48 bl 8001d6c <HAL_GetTick>
|
|
80024dc: 0002 movs r2, r0
|
|
80024de: 68fb ldr r3, [r7, #12]
|
|
80024e0: 4293 cmp r3, r2
|
|
80024e2: d801 bhi.n 80024e8 <FLASH_WaitForLastOperation+0x74>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80024e4: 2303 movs r3, #3
|
|
80024e6: e006 b.n 80024f6 <FLASH_WaitForLastOperation+0x82>
|
|
while ((FLASH->SR & FLASH_SR_CFGBSY) != 0x00U)
|
|
80024e8: 4b05 ldr r3, [pc, #20] ; (8002500 <FLASH_WaitForLastOperation+0x8c>)
|
|
80024ea: 691a ldr r2, [r3, #16]
|
|
80024ec: 2380 movs r3, #128 ; 0x80
|
|
80024ee: 02db lsls r3, r3, #11
|
|
80024f0: 4013 ands r3, r2
|
|
80024f2: d1f1 bne.n 80024d8 <FLASH_WaitForLastOperation+0x64>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
80024f4: 2300 movs r3, #0
|
|
}
|
|
80024f6: 0018 movs r0, r3
|
|
80024f8: 46bd mov sp, r7
|
|
80024fa: b004 add sp, #16
|
|
80024fc: bd80 pop {r7, pc}
|
|
80024fe: 46c0 nop ; (mov r8, r8)
|
|
8002500: 40022000 .word 0x40022000
|
|
8002504: 0000c3fa .word 0x0000c3fa
|
|
8002508: 0000c3fb .word 0x0000c3fb
|
|
800250c: 2000023c .word 0x2000023c
|
|
|
|
08002510 <FLASH_Program_DoubleWord>:
|
|
* @param Address Specifies the address to be programmed.
|
|
* @param Data Specifies the data to be programmed.
|
|
* @retval None
|
|
*/
|
|
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
|
|
{
|
|
8002510: b5b0 push {r4, r5, r7, lr}
|
|
8002512: b084 sub sp, #16
|
|
8002514: af00 add r7, sp, #0
|
|
8002516: 60f8 str r0, [r7, #12]
|
|
8002518: 603a str r2, [r7, #0]
|
|
800251a: 607b str r3, [r7, #4]
|
|
/* Set PG bit */
|
|
SET_BIT(FLASH->CR, FLASH_CR_PG);
|
|
800251c: 4b0b ldr r3, [pc, #44] ; (800254c <FLASH_Program_DoubleWord+0x3c>)
|
|
800251e: 695a ldr r2, [r3, #20]
|
|
8002520: 4b0a ldr r3, [pc, #40] ; (800254c <FLASH_Program_DoubleWord+0x3c>)
|
|
8002522: 2101 movs r1, #1
|
|
8002524: 430a orrs r2, r1
|
|
8002526: 615a str r2, [r3, #20]
|
|
|
|
/* Program first word */
|
|
*(uint32_t *)Address = (uint32_t)Data;
|
|
8002528: 68fb ldr r3, [r7, #12]
|
|
800252a: 683a ldr r2, [r7, #0]
|
|
800252c: 601a str r2, [r3, #0]
|
|
so that all instructions following the ISB are fetched from cache or memory,
|
|
after the instruction has been completed.
|
|
*/
|
|
__STATIC_FORCEINLINE void __ISB(void)
|
|
{
|
|
__ASM volatile ("isb 0xF":::"memory");
|
|
800252e: f3bf 8f6f isb sy
|
|
}
|
|
8002532: 46c0 nop ; (mov r8, r8)
|
|
/* Barrier to ensure programming is performed in 2 steps, in right order
|
|
(independently of compiler optimization behavior) */
|
|
__ISB();
|
|
|
|
/* Program second word */
|
|
*(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
|
|
8002534: 687b ldr r3, [r7, #4]
|
|
8002536: 001c movs r4, r3
|
|
8002538: 2300 movs r3, #0
|
|
800253a: 001d movs r5, r3
|
|
800253c: 68fb ldr r3, [r7, #12]
|
|
800253e: 3304 adds r3, #4
|
|
8002540: 0022 movs r2, r4
|
|
8002542: 601a str r2, [r3, #0]
|
|
}
|
|
8002544: 46c0 nop ; (mov r8, r8)
|
|
8002546: 46bd mov sp, r7
|
|
8002548: b004 add sp, #16
|
|
800254a: bdb0 pop {r4, r5, r7, pc}
|
|
800254c: 40022000 .word 0x40022000
|
|
|
|
08002550 <HAL_FLASHEx_Erase>:
|
|
* information on faulty page in case of error (0xFFFFFFFF means that all
|
|
* the pages have been correctly erased)
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
|
|
{
|
|
8002550: b5b0 push {r4, r5, r7, lr}
|
|
8002552: b084 sub sp, #16
|
|
8002554: af00 add r7, sp, #0
|
|
8002556: 6078 str r0, [r7, #4]
|
|
8002558: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(&pFlash);
|
|
800255a: 4b35 ldr r3, [pc, #212] ; (8002630 <HAL_FLASHEx_Erase+0xe0>)
|
|
800255c: 781b ldrb r3, [r3, #0]
|
|
800255e: 2b01 cmp r3, #1
|
|
8002560: d101 bne.n 8002566 <HAL_FLASHEx_Erase+0x16>
|
|
8002562: 2302 movs r3, #2
|
|
8002564: e05f b.n 8002626 <HAL_FLASHEx_Erase+0xd6>
|
|
8002566: 4b32 ldr r3, [pc, #200] ; (8002630 <HAL_FLASHEx_Erase+0xe0>)
|
|
8002568: 2201 movs r2, #1
|
|
800256a: 701a strb r2, [r3, #0]
|
|
|
|
/* Reset error code */
|
|
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
|
800256c: 4b30 ldr r3, [pc, #192] ; (8002630 <HAL_FLASHEx_Erase+0xe0>)
|
|
800256e: 2200 movs r2, #0
|
|
8002570: 605a str r2, [r3, #4]
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
|
8002572: 250f movs r5, #15
|
|
8002574: 197c adds r4, r7, r5
|
|
8002576: 23fa movs r3, #250 ; 0xfa
|
|
8002578: 009b lsls r3, r3, #2
|
|
800257a: 0018 movs r0, r3
|
|
800257c: f7ff ff7a bl 8002474 <FLASH_WaitForLastOperation>
|
|
8002580: 0003 movs r3, r0
|
|
8002582: 7023 strb r3, [r4, #0]
|
|
|
|
if (status == HAL_OK)
|
|
8002584: 002c movs r4, r5
|
|
8002586: 193b adds r3, r7, r4
|
|
8002588: 781b ldrb r3, [r3, #0]
|
|
800258a: 2b00 cmp r3, #0
|
|
800258c: d145 bne.n 800261a <HAL_FLASHEx_Erase+0xca>
|
|
{
|
|
#if !defined(FLASH_DBANK_SUPPORT)
|
|
/* For single bank product force Banks to Bank 1 */
|
|
pEraseInit->Banks = FLASH_BANK_1;
|
|
800258e: 687b ldr r3, [r7, #4]
|
|
8002590: 2204 movs r2, #4
|
|
8002592: 605a str r2, [r3, #4]
|
|
#endif /* FLASH_DBANK_SUPPORT */
|
|
|
|
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS)
|
|
8002594: 687b ldr r3, [r7, #4]
|
|
8002596: 681b ldr r3, [r3, #0]
|
|
8002598: 2b04 cmp r3, #4
|
|
800259a: d10d bne.n 80025b8 <HAL_FLASHEx_Erase+0x68>
|
|
{
|
|
/* Proceed to Mass Erase */
|
|
FLASH_MassErase(pEraseInit->Banks);
|
|
800259c: 687b ldr r3, [r7, #4]
|
|
800259e: 685b ldr r3, [r3, #4]
|
|
80025a0: 0018 movs r0, r3
|
|
80025a2: f000 f849 bl 8002638 <FLASH_MassErase>
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
|
80025a6: 193c adds r4, r7, r4
|
|
80025a8: 23fa movs r3, #250 ; 0xfa
|
|
80025aa: 009b lsls r3, r3, #2
|
|
80025ac: 0018 movs r0, r3
|
|
80025ae: f7ff ff61 bl 8002474 <FLASH_WaitForLastOperation>
|
|
80025b2: 0003 movs r3, r0
|
|
80025b4: 7023 strb r3, [r4, #0]
|
|
80025b6: e030 b.n 800261a <HAL_FLASHEx_Erase+0xca>
|
|
}
|
|
else
|
|
{
|
|
/*Initialization of PageError variable*/
|
|
*PageError = 0xFFFFFFFFU;
|
|
80025b8: 683b ldr r3, [r7, #0]
|
|
80025ba: 2201 movs r2, #1
|
|
80025bc: 4252 negs r2, r2
|
|
80025be: 601a str r2, [r3, #0]
|
|
|
|
for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++)
|
|
80025c0: 687b ldr r3, [r7, #4]
|
|
80025c2: 689b ldr r3, [r3, #8]
|
|
80025c4: 60bb str r3, [r7, #8]
|
|
80025c6: e01a b.n 80025fe <HAL_FLASHEx_Erase+0xae>
|
|
{
|
|
/* Start erase page */
|
|
FLASH_PageErase(pEraseInit->Banks, index);
|
|
80025c8: 687b ldr r3, [r7, #4]
|
|
80025ca: 685b ldr r3, [r3, #4]
|
|
80025cc: 68ba ldr r2, [r7, #8]
|
|
80025ce: 0011 movs r1, r2
|
|
80025d0: 0018 movs r0, r3
|
|
80025d2: f000 f845 bl 8002660 <FLASH_PageErase>
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
|
80025d6: 250f movs r5, #15
|
|
80025d8: 197c adds r4, r7, r5
|
|
80025da: 23fa movs r3, #250 ; 0xfa
|
|
80025dc: 009b lsls r3, r3, #2
|
|
80025de: 0018 movs r0, r3
|
|
80025e0: f7ff ff48 bl 8002474 <FLASH_WaitForLastOperation>
|
|
80025e4: 0003 movs r3, r0
|
|
80025e6: 7023 strb r3, [r4, #0]
|
|
|
|
if (status != HAL_OK)
|
|
80025e8: 197b adds r3, r7, r5
|
|
80025ea: 781b ldrb r3, [r3, #0]
|
|
80025ec: 2b00 cmp r3, #0
|
|
80025ee: d003 beq.n 80025f8 <HAL_FLASHEx_Erase+0xa8>
|
|
{
|
|
/* In case of error, stop erase procedure and return the faulty address */
|
|
*PageError = index;
|
|
80025f0: 683b ldr r3, [r7, #0]
|
|
80025f2: 68ba ldr r2, [r7, #8]
|
|
80025f4: 601a str r2, [r3, #0]
|
|
break;
|
|
80025f6: e00a b.n 800260e <HAL_FLASHEx_Erase+0xbe>
|
|
for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++)
|
|
80025f8: 68bb ldr r3, [r7, #8]
|
|
80025fa: 3301 adds r3, #1
|
|
80025fc: 60bb str r3, [r7, #8]
|
|
80025fe: 687b ldr r3, [r7, #4]
|
|
8002600: 689a ldr r2, [r3, #8]
|
|
8002602: 687b ldr r3, [r7, #4]
|
|
8002604: 68db ldr r3, [r3, #12]
|
|
8002606: 18d3 adds r3, r2, r3
|
|
8002608: 68ba ldr r2, [r7, #8]
|
|
800260a: 429a cmp r2, r3
|
|
800260c: d3dc bcc.n 80025c8 <HAL_FLASHEx_Erase+0x78>
|
|
}
|
|
}
|
|
|
|
/* If operation is completed or interrupted, disable the Page Erase Bit */
|
|
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
|
|
800260e: 4b09 ldr r3, [pc, #36] ; (8002634 <HAL_FLASHEx_Erase+0xe4>)
|
|
8002610: 695a ldr r2, [r3, #20]
|
|
8002612: 4b08 ldr r3, [pc, #32] ; (8002634 <HAL_FLASHEx_Erase+0xe4>)
|
|
8002614: 2102 movs r1, #2
|
|
8002616: 438a bics r2, r1
|
|
8002618: 615a str r2, [r3, #20]
|
|
}
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(&pFlash);
|
|
800261a: 4b05 ldr r3, [pc, #20] ; (8002630 <HAL_FLASHEx_Erase+0xe0>)
|
|
800261c: 2200 movs r2, #0
|
|
800261e: 701a strb r2, [r3, #0]
|
|
|
|
/* return status */
|
|
return status;
|
|
8002620: 230f movs r3, #15
|
|
8002622: 18fb adds r3, r7, r3
|
|
8002624: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8002626: 0018 movs r0, r3
|
|
8002628: 46bd mov sp, r7
|
|
800262a: b004 add sp, #16
|
|
800262c: bdb0 pop {r4, r5, r7, pc}
|
|
800262e: 46c0 nop ; (mov r8, r8)
|
|
8002630: 2000023c .word 0x2000023c
|
|
8002634: 40022000 .word 0x40022000
|
|
|
|
08002638 <FLASH_MassErase>:
|
|
* @arg FLASH_BANK_2: Bank2 to be erased*
|
|
* @note (*) availability depends on devices
|
|
* @retval None
|
|
*/
|
|
static void FLASH_MassErase(uint32_t Banks)
|
|
{
|
|
8002638: b580 push {r7, lr}
|
|
800263a: b082 sub sp, #8
|
|
800263c: af00 add r7, sp, #0
|
|
800263e: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_BANK(Banks));
|
|
|
|
/* Set the Mass Erase Bit and start bit */
|
|
FLASH->CR |= (FLASH_CR_STRT | Banks);
|
|
8002640: 4b06 ldr r3, [pc, #24] ; (800265c <FLASH_MassErase+0x24>)
|
|
8002642: 695a ldr r2, [r3, #20]
|
|
8002644: 687b ldr r3, [r7, #4]
|
|
8002646: 431a orrs r2, r3
|
|
8002648: 4b04 ldr r3, [pc, #16] ; (800265c <FLASH_MassErase+0x24>)
|
|
800264a: 2180 movs r1, #128 ; 0x80
|
|
800264c: 0249 lsls r1, r1, #9
|
|
800264e: 430a orrs r2, r1
|
|
8002650: 615a str r2, [r3, #20]
|
|
}
|
|
8002652: 46c0 nop ; (mov r8, r8)
|
|
8002654: 46bd mov sp, r7
|
|
8002656: b002 add sp, #8
|
|
8002658: bd80 pop {r7, pc}
|
|
800265a: 46c0 nop ; (mov r8, r8)
|
|
800265c: 40022000 .word 0x40022000
|
|
|
|
08002660 <FLASH_PageErase>:
|
|
* This parameter must be a value between 0 and (max number of pages in Flash - 1)
|
|
* @note (*) availability depends on devices
|
|
* @retval None
|
|
*/
|
|
void FLASH_PageErase(uint32_t Banks, uint32_t Page)
|
|
{
|
|
8002660: b580 push {r7, lr}
|
|
8002662: b084 sub sp, #16
|
|
8002664: af00 add r7, sp, #0
|
|
8002666: 6078 str r0, [r7, #4]
|
|
8002668: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_BANK(Banks));
|
|
assert_param(IS_FLASH_PAGE(Page));
|
|
|
|
/* Get configuration register, then clear page number */
|
|
tmp = (FLASH->CR & ~FLASH_CR_PNB);
|
|
800266a: 4b08 ldr r3, [pc, #32] ; (800268c <FLASH_PageErase+0x2c>)
|
|
800266c: 695b ldr r3, [r3, #20]
|
|
800266e: 4a08 ldr r2, [pc, #32] ; (8002690 <FLASH_PageErase+0x30>)
|
|
8002670: 4013 ands r3, r2
|
|
8002672: 60fb str r3, [r7, #12]
|
|
tmp &= ~FLASH_CR_BKER;
|
|
}
|
|
#endif /* FLASH_DBANK_SUPPORT */
|
|
|
|
/* Set page number, Page Erase bit & Start bit */
|
|
FLASH->CR = (tmp | (FLASH_CR_STRT | (Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER));
|
|
8002674: 683b ldr r3, [r7, #0]
|
|
8002676: 00da lsls r2, r3, #3
|
|
8002678: 68fb ldr r3, [r7, #12]
|
|
800267a: 431a orrs r2, r3
|
|
800267c: 4b03 ldr r3, [pc, #12] ; (800268c <FLASH_PageErase+0x2c>)
|
|
800267e: 4905 ldr r1, [pc, #20] ; (8002694 <FLASH_PageErase+0x34>)
|
|
8002680: 430a orrs r2, r1
|
|
8002682: 615a str r2, [r3, #20]
|
|
}
|
|
8002684: 46c0 nop ; (mov r8, r8)
|
|
8002686: 46bd mov sp, r7
|
|
8002688: b004 add sp, #16
|
|
800268a: bd80 pop {r7, pc}
|
|
800268c: 40022000 .word 0x40022000
|
|
8002690: ffffe007 .word 0xffffe007
|
|
8002694: 00010002 .word 0x00010002
|
|
|
|
08002698 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8002698: b580 push {r7, lr}
|
|
800269a: b086 sub sp, #24
|
|
800269c: af00 add r7, sp, #0
|
|
800269e: 6078 str r0, [r7, #4]
|
|
80026a0: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
80026a2: 2300 movs r3, #0
|
|
80026a4: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
80026a6: e147 b.n 8002938 <HAL_GPIO_Init+0x2a0>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
80026a8: 683b ldr r3, [r7, #0]
|
|
80026aa: 681b ldr r3, [r3, #0]
|
|
80026ac: 2101 movs r1, #1
|
|
80026ae: 697a ldr r2, [r7, #20]
|
|
80026b0: 4091 lsls r1, r2
|
|
80026b2: 000a movs r2, r1
|
|
80026b4: 4013 ands r3, r2
|
|
80026b6: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
80026b8: 68fb ldr r3, [r7, #12]
|
|
80026ba: 2b00 cmp r3, #0
|
|
80026bc: d100 bne.n 80026c0 <HAL_GPIO_Init+0x28>
|
|
80026be: e138 b.n 8002932 <HAL_GPIO_Init+0x29a>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
80026c0: 683b ldr r3, [r7, #0]
|
|
80026c2: 685b ldr r3, [r3, #4]
|
|
80026c4: 2203 movs r2, #3
|
|
80026c6: 4013 ands r3, r2
|
|
80026c8: 2b01 cmp r3, #1
|
|
80026ca: d005 beq.n 80026d8 <HAL_GPIO_Init+0x40>
|
|
80026cc: 683b ldr r3, [r7, #0]
|
|
80026ce: 685b ldr r3, [r3, #4]
|
|
80026d0: 2203 movs r2, #3
|
|
80026d2: 4013 ands r3, r2
|
|
80026d4: 2b02 cmp r3, #2
|
|
80026d6: d130 bne.n 800273a <HAL_GPIO_Init+0xa2>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
80026d8: 687b ldr r3, [r7, #4]
|
|
80026da: 689b ldr r3, [r3, #8]
|
|
80026dc: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
|
80026de: 697b ldr r3, [r7, #20]
|
|
80026e0: 005b lsls r3, r3, #1
|
|
80026e2: 2203 movs r2, #3
|
|
80026e4: 409a lsls r2, r3
|
|
80026e6: 0013 movs r3, r2
|
|
80026e8: 43da mvns r2, r3
|
|
80026ea: 693b ldr r3, [r7, #16]
|
|
80026ec: 4013 ands r3, r2
|
|
80026ee: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
|
80026f0: 683b ldr r3, [r7, #0]
|
|
80026f2: 68da ldr r2, [r3, #12]
|
|
80026f4: 697b ldr r3, [r7, #20]
|
|
80026f6: 005b lsls r3, r3, #1
|
|
80026f8: 409a lsls r2, r3
|
|
80026fa: 0013 movs r3, r2
|
|
80026fc: 693a ldr r2, [r7, #16]
|
|
80026fe: 4313 orrs r3, r2
|
|
8002700: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
8002702: 687b ldr r3, [r7, #4]
|
|
8002704: 693a ldr r2, [r7, #16]
|
|
8002706: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8002708: 687b ldr r3, [r7, #4]
|
|
800270a: 685b ldr r3, [r3, #4]
|
|
800270c: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
800270e: 2201 movs r2, #1
|
|
8002710: 697b ldr r3, [r7, #20]
|
|
8002712: 409a lsls r2, r3
|
|
8002714: 0013 movs r3, r2
|
|
8002716: 43da mvns r2, r3
|
|
8002718: 693b ldr r3, [r7, #16]
|
|
800271a: 4013 ands r3, r2
|
|
800271c: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
800271e: 683b ldr r3, [r7, #0]
|
|
8002720: 685b ldr r3, [r3, #4]
|
|
8002722: 091b lsrs r3, r3, #4
|
|
8002724: 2201 movs r2, #1
|
|
8002726: 401a ands r2, r3
|
|
8002728: 697b ldr r3, [r7, #20]
|
|
800272a: 409a lsls r2, r3
|
|
800272c: 0013 movs r3, r2
|
|
800272e: 693a ldr r2, [r7, #16]
|
|
8002730: 4313 orrs r3, r2
|
|
8002732: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
8002734: 687b ldr r3, [r7, #4]
|
|
8002736: 693a ldr r2, [r7, #16]
|
|
8002738: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
800273a: 683b ldr r3, [r7, #0]
|
|
800273c: 685b ldr r3, [r3, #4]
|
|
800273e: 2203 movs r2, #3
|
|
8002740: 4013 ands r3, r2
|
|
8002742: 2b03 cmp r3, #3
|
|
8002744: d017 beq.n 8002776 <HAL_GPIO_Init+0xde>
|
|
{
|
|
/* Check the Pull parameter */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
8002746: 687b ldr r3, [r7, #4]
|
|
8002748: 68db ldr r3, [r3, #12]
|
|
800274a: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
|
|
800274c: 697b ldr r3, [r7, #20]
|
|
800274e: 005b lsls r3, r3, #1
|
|
8002750: 2203 movs r2, #3
|
|
8002752: 409a lsls r2, r3
|
|
8002754: 0013 movs r3, r2
|
|
8002756: 43da mvns r2, r3
|
|
8002758: 693b ldr r3, [r7, #16]
|
|
800275a: 4013 ands r3, r2
|
|
800275c: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
|
800275e: 683b ldr r3, [r7, #0]
|
|
8002760: 689a ldr r2, [r3, #8]
|
|
8002762: 697b ldr r3, [r7, #20]
|
|
8002764: 005b lsls r3, r3, #1
|
|
8002766: 409a lsls r2, r3
|
|
8002768: 0013 movs r3, r2
|
|
800276a: 693a ldr r2, [r7, #16]
|
|
800276c: 4313 orrs r3, r2
|
|
800276e: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
8002770: 687b ldr r3, [r7, #4]
|
|
8002772: 693a ldr r2, [r7, #16]
|
|
8002774: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8002776: 683b ldr r3, [r7, #0]
|
|
8002778: 685b ldr r3, [r3, #4]
|
|
800277a: 2203 movs r2, #3
|
|
800277c: 4013 ands r3, r2
|
|
800277e: 2b02 cmp r3, #2
|
|
8002780: d123 bne.n 80027ca <HAL_GPIO_Init+0x132>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3u];
|
|
8002782: 697b ldr r3, [r7, #20]
|
|
8002784: 08da lsrs r2, r3, #3
|
|
8002786: 687b ldr r3, [r7, #4]
|
|
8002788: 3208 adds r2, #8
|
|
800278a: 0092 lsls r2, r2, #2
|
|
800278c: 58d3 ldr r3, [r2, r3]
|
|
800278e: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
|
8002790: 697b ldr r3, [r7, #20]
|
|
8002792: 2207 movs r2, #7
|
|
8002794: 4013 ands r3, r2
|
|
8002796: 009b lsls r3, r3, #2
|
|
8002798: 220f movs r2, #15
|
|
800279a: 409a lsls r2, r3
|
|
800279c: 0013 movs r3, r2
|
|
800279e: 43da mvns r2, r3
|
|
80027a0: 693b ldr r3, [r7, #16]
|
|
80027a2: 4013 ands r3, r2
|
|
80027a4: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
|
80027a6: 683b ldr r3, [r7, #0]
|
|
80027a8: 691a ldr r2, [r3, #16]
|
|
80027aa: 697b ldr r3, [r7, #20]
|
|
80027ac: 2107 movs r1, #7
|
|
80027ae: 400b ands r3, r1
|
|
80027b0: 009b lsls r3, r3, #2
|
|
80027b2: 409a lsls r2, r3
|
|
80027b4: 0013 movs r3, r2
|
|
80027b6: 693a ldr r2, [r7, #16]
|
|
80027b8: 4313 orrs r3, r2
|
|
80027ba: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
80027bc: 697b ldr r3, [r7, #20]
|
|
80027be: 08da lsrs r2, r3, #3
|
|
80027c0: 687b ldr r3, [r7, #4]
|
|
80027c2: 3208 adds r2, #8
|
|
80027c4: 0092 lsls r2, r2, #2
|
|
80027c6: 6939 ldr r1, [r7, #16]
|
|
80027c8: 50d1 str r1, [r2, r3]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
80027ca: 687b ldr r3, [r7, #4]
|
|
80027cc: 681b ldr r3, [r3, #0]
|
|
80027ce: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
|
|
80027d0: 697b ldr r3, [r7, #20]
|
|
80027d2: 005b lsls r3, r3, #1
|
|
80027d4: 2203 movs r2, #3
|
|
80027d6: 409a lsls r2, r3
|
|
80027d8: 0013 movs r3, r2
|
|
80027da: 43da mvns r2, r3
|
|
80027dc: 693b ldr r3, [r7, #16]
|
|
80027de: 4013 ands r3, r2
|
|
80027e0: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
|
80027e2: 683b ldr r3, [r7, #0]
|
|
80027e4: 685b ldr r3, [r3, #4]
|
|
80027e6: 2203 movs r2, #3
|
|
80027e8: 401a ands r2, r3
|
|
80027ea: 697b ldr r3, [r7, #20]
|
|
80027ec: 005b lsls r3, r3, #1
|
|
80027ee: 409a lsls r2, r3
|
|
80027f0: 0013 movs r3, r2
|
|
80027f2: 693a ldr r2, [r7, #16]
|
|
80027f4: 4313 orrs r3, r2
|
|
80027f6: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
80027f8: 687b ldr r3, [r7, #4]
|
|
80027fa: 693a ldr r2, [r7, #16]
|
|
80027fc: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
80027fe: 683b ldr r3, [r7, #0]
|
|
8002800: 685a ldr r2, [r3, #4]
|
|
8002802: 23c0 movs r3, #192 ; 0xc0
|
|
8002804: 029b lsls r3, r3, #10
|
|
8002806: 4013 ands r3, r2
|
|
8002808: d100 bne.n 800280c <HAL_GPIO_Init+0x174>
|
|
800280a: e092 b.n 8002932 <HAL_GPIO_Init+0x29a>
|
|
{
|
|
temp = EXTI->EXTICR[position >> 2u];
|
|
800280c: 4a50 ldr r2, [pc, #320] ; (8002950 <HAL_GPIO_Init+0x2b8>)
|
|
800280e: 697b ldr r3, [r7, #20]
|
|
8002810: 089b lsrs r3, r3, #2
|
|
8002812: 3318 adds r3, #24
|
|
8002814: 009b lsls r3, r3, #2
|
|
8002816: 589b ldr r3, [r3, r2]
|
|
8002818: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FuL << (8u * (position & 0x03u)));
|
|
800281a: 697b ldr r3, [r7, #20]
|
|
800281c: 2203 movs r2, #3
|
|
800281e: 4013 ands r3, r2
|
|
8002820: 00db lsls r3, r3, #3
|
|
8002822: 220f movs r2, #15
|
|
8002824: 409a lsls r2, r3
|
|
8002826: 0013 movs r3, r2
|
|
8002828: 43da mvns r2, r3
|
|
800282a: 693b ldr r3, [r7, #16]
|
|
800282c: 4013 ands r3, r2
|
|
800282e: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)));
|
|
8002830: 687a ldr r2, [r7, #4]
|
|
8002832: 23a0 movs r3, #160 ; 0xa0
|
|
8002834: 05db lsls r3, r3, #23
|
|
8002836: 429a cmp r2, r3
|
|
8002838: d013 beq.n 8002862 <HAL_GPIO_Init+0x1ca>
|
|
800283a: 687b ldr r3, [r7, #4]
|
|
800283c: 4a45 ldr r2, [pc, #276] ; (8002954 <HAL_GPIO_Init+0x2bc>)
|
|
800283e: 4293 cmp r3, r2
|
|
8002840: d00d beq.n 800285e <HAL_GPIO_Init+0x1c6>
|
|
8002842: 687b ldr r3, [r7, #4]
|
|
8002844: 4a44 ldr r2, [pc, #272] ; (8002958 <HAL_GPIO_Init+0x2c0>)
|
|
8002846: 4293 cmp r3, r2
|
|
8002848: d007 beq.n 800285a <HAL_GPIO_Init+0x1c2>
|
|
800284a: 687b ldr r3, [r7, #4]
|
|
800284c: 4a43 ldr r2, [pc, #268] ; (800295c <HAL_GPIO_Init+0x2c4>)
|
|
800284e: 4293 cmp r3, r2
|
|
8002850: d101 bne.n 8002856 <HAL_GPIO_Init+0x1be>
|
|
8002852: 2303 movs r3, #3
|
|
8002854: e006 b.n 8002864 <HAL_GPIO_Init+0x1cc>
|
|
8002856: 2305 movs r3, #5
|
|
8002858: e004 b.n 8002864 <HAL_GPIO_Init+0x1cc>
|
|
800285a: 2302 movs r3, #2
|
|
800285c: e002 b.n 8002864 <HAL_GPIO_Init+0x1cc>
|
|
800285e: 2301 movs r3, #1
|
|
8002860: e000 b.n 8002864 <HAL_GPIO_Init+0x1cc>
|
|
8002862: 2300 movs r3, #0
|
|
8002864: 697a ldr r2, [r7, #20]
|
|
8002866: 2103 movs r1, #3
|
|
8002868: 400a ands r2, r1
|
|
800286a: 00d2 lsls r2, r2, #3
|
|
800286c: 4093 lsls r3, r2
|
|
800286e: 693a ldr r2, [r7, #16]
|
|
8002870: 4313 orrs r3, r2
|
|
8002872: 613b str r3, [r7, #16]
|
|
EXTI->EXTICR[position >> 2u] = temp;
|
|
8002874: 4936 ldr r1, [pc, #216] ; (8002950 <HAL_GPIO_Init+0x2b8>)
|
|
8002876: 697b ldr r3, [r7, #20]
|
|
8002878: 089b lsrs r3, r3, #2
|
|
800287a: 3318 adds r3, #24
|
|
800287c: 009b lsls r3, r3, #2
|
|
800287e: 693a ldr r2, [r7, #16]
|
|
8002880: 505a str r2, [r3, r1]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR1;
|
|
8002882: 4b33 ldr r3, [pc, #204] ; (8002950 <HAL_GPIO_Init+0x2b8>)
|
|
8002884: 681b ldr r3, [r3, #0]
|
|
8002886: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8002888: 68fb ldr r3, [r7, #12]
|
|
800288a: 43da mvns r2, r3
|
|
800288c: 693b ldr r3, [r7, #16]
|
|
800288e: 4013 ands r3, r2
|
|
8002890: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
|
8002892: 683b ldr r3, [r7, #0]
|
|
8002894: 685a ldr r2, [r3, #4]
|
|
8002896: 2380 movs r3, #128 ; 0x80
|
|
8002898: 035b lsls r3, r3, #13
|
|
800289a: 4013 ands r3, r2
|
|
800289c: d003 beq.n 80028a6 <HAL_GPIO_Init+0x20e>
|
|
{
|
|
temp |= iocurrent;
|
|
800289e: 693a ldr r2, [r7, #16]
|
|
80028a0: 68fb ldr r3, [r7, #12]
|
|
80028a2: 4313 orrs r3, r2
|
|
80028a4: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR1 = temp;
|
|
80028a6: 4b2a ldr r3, [pc, #168] ; (8002950 <HAL_GPIO_Init+0x2b8>)
|
|
80028a8: 693a ldr r2, [r7, #16]
|
|
80028aa: 601a str r2, [r3, #0]
|
|
|
|
temp = EXTI->FTSR1;
|
|
80028ac: 4b28 ldr r3, [pc, #160] ; (8002950 <HAL_GPIO_Init+0x2b8>)
|
|
80028ae: 685b ldr r3, [r3, #4]
|
|
80028b0: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80028b2: 68fb ldr r3, [r7, #12]
|
|
80028b4: 43da mvns r2, r3
|
|
80028b6: 693b ldr r3, [r7, #16]
|
|
80028b8: 4013 ands r3, r2
|
|
80028ba: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
|
80028bc: 683b ldr r3, [r7, #0]
|
|
80028be: 685a ldr r2, [r3, #4]
|
|
80028c0: 2380 movs r3, #128 ; 0x80
|
|
80028c2: 039b lsls r3, r3, #14
|
|
80028c4: 4013 ands r3, r2
|
|
80028c6: d003 beq.n 80028d0 <HAL_GPIO_Init+0x238>
|
|
{
|
|
temp |= iocurrent;
|
|
80028c8: 693a ldr r2, [r7, #16]
|
|
80028ca: 68fb ldr r3, [r7, #12]
|
|
80028cc: 4313 orrs r3, r2
|
|
80028ce: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR1 = temp;
|
|
80028d0: 4b1f ldr r3, [pc, #124] ; (8002950 <HAL_GPIO_Init+0x2b8>)
|
|
80028d2: 693a ldr r2, [r7, #16]
|
|
80028d4: 605a str r2, [r3, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->EMR1;
|
|
80028d6: 4a1e ldr r2, [pc, #120] ; (8002950 <HAL_GPIO_Init+0x2b8>)
|
|
80028d8: 2384 movs r3, #132 ; 0x84
|
|
80028da: 58d3 ldr r3, [r2, r3]
|
|
80028dc: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80028de: 68fb ldr r3, [r7, #12]
|
|
80028e0: 43da mvns r2, r3
|
|
80028e2: 693b ldr r3, [r7, #16]
|
|
80028e4: 4013 ands r3, r2
|
|
80028e6: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
|
80028e8: 683b ldr r3, [r7, #0]
|
|
80028ea: 685a ldr r2, [r3, #4]
|
|
80028ec: 2380 movs r3, #128 ; 0x80
|
|
80028ee: 029b lsls r3, r3, #10
|
|
80028f0: 4013 ands r3, r2
|
|
80028f2: d003 beq.n 80028fc <HAL_GPIO_Init+0x264>
|
|
{
|
|
temp |= iocurrent;
|
|
80028f4: 693a ldr r2, [r7, #16]
|
|
80028f6: 68fb ldr r3, [r7, #12]
|
|
80028f8: 4313 orrs r3, r2
|
|
80028fa: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR1 = temp;
|
|
80028fc: 4914 ldr r1, [pc, #80] ; (8002950 <HAL_GPIO_Init+0x2b8>)
|
|
80028fe: 2284 movs r2, #132 ; 0x84
|
|
8002900: 693b ldr r3, [r7, #16]
|
|
8002902: 508b str r3, [r1, r2]
|
|
|
|
temp = EXTI->IMR1;
|
|
8002904: 4a12 ldr r2, [pc, #72] ; (8002950 <HAL_GPIO_Init+0x2b8>)
|
|
8002906: 2380 movs r3, #128 ; 0x80
|
|
8002908: 58d3 ldr r3, [r2, r3]
|
|
800290a: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
800290c: 68fb ldr r3, [r7, #12]
|
|
800290e: 43da mvns r2, r3
|
|
8002910: 693b ldr r3, [r7, #16]
|
|
8002912: 4013 ands r3, r2
|
|
8002914: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
|
8002916: 683b ldr r3, [r7, #0]
|
|
8002918: 685a ldr r2, [r3, #4]
|
|
800291a: 2380 movs r3, #128 ; 0x80
|
|
800291c: 025b lsls r3, r3, #9
|
|
800291e: 4013 ands r3, r2
|
|
8002920: d003 beq.n 800292a <HAL_GPIO_Init+0x292>
|
|
{
|
|
temp |= iocurrent;
|
|
8002922: 693a ldr r2, [r7, #16]
|
|
8002924: 68fb ldr r3, [r7, #12]
|
|
8002926: 4313 orrs r3, r2
|
|
8002928: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR1 = temp;
|
|
800292a: 4909 ldr r1, [pc, #36] ; (8002950 <HAL_GPIO_Init+0x2b8>)
|
|
800292c: 2280 movs r2, #128 ; 0x80
|
|
800292e: 693b ldr r3, [r7, #16]
|
|
8002930: 508b str r3, [r1, r2]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8002932: 697b ldr r3, [r7, #20]
|
|
8002934: 3301 adds r3, #1
|
|
8002936: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8002938: 683b ldr r3, [r7, #0]
|
|
800293a: 681a ldr r2, [r3, #0]
|
|
800293c: 697b ldr r3, [r7, #20]
|
|
800293e: 40da lsrs r2, r3
|
|
8002940: 1e13 subs r3, r2, #0
|
|
8002942: d000 beq.n 8002946 <HAL_GPIO_Init+0x2ae>
|
|
8002944: e6b0 b.n 80026a8 <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
8002946: 46c0 nop ; (mov r8, r8)
|
|
8002948: 46c0 nop ; (mov r8, r8)
|
|
800294a: 46bd mov sp, r7
|
|
800294c: b006 add sp, #24
|
|
800294e: bd80 pop {r7, pc}
|
|
8002950: 40021800 .word 0x40021800
|
|
8002954: 50000400 .word 0x50000400
|
|
8002958: 50000800 .word 0x50000800
|
|
800295c: 50000c00 .word 0x50000c00
|
|
|
|
08002960 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8002960: b580 push {r7, lr}
|
|
8002962: b082 sub sp, #8
|
|
8002964: af00 add r7, sp, #0
|
|
8002966: 6078 str r0, [r7, #4]
|
|
8002968: 0008 movs r0, r1
|
|
800296a: 0011 movs r1, r2
|
|
800296c: 1cbb adds r3, r7, #2
|
|
800296e: 1c02 adds r2, r0, #0
|
|
8002970: 801a strh r2, [r3, #0]
|
|
8002972: 1c7b adds r3, r7, #1
|
|
8002974: 1c0a adds r2, r1, #0
|
|
8002976: 701a strb r2, [r3, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if (PinState != GPIO_PIN_RESET)
|
|
8002978: 1c7b adds r3, r7, #1
|
|
800297a: 781b ldrb r3, [r3, #0]
|
|
800297c: 2b00 cmp r3, #0
|
|
800297e: d004 beq.n 800298a <HAL_GPIO_WritePin+0x2a>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
8002980: 1cbb adds r3, r7, #2
|
|
8002982: 881a ldrh r2, [r3, #0]
|
|
8002984: 687b ldr r3, [r7, #4]
|
|
8002986: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
8002988: e003 b.n 8002992 <HAL_GPIO_WritePin+0x32>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
800298a: 1cbb adds r3, r7, #2
|
|
800298c: 881a ldrh r2, [r3, #0]
|
|
800298e: 687b ldr r3, [r7, #4]
|
|
8002990: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
8002992: 46c0 nop ; (mov r8, r8)
|
|
8002994: 46bd mov sp, r7
|
|
8002996: b002 add sp, #8
|
|
8002998: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800299c <HAL_GPIO_EXTI_IRQHandler>:
|
|
* @brief Handle EXTI interrupt request.
|
|
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
|
{
|
|
800299c: b580 push {r7, lr}
|
|
800299e: b082 sub sp, #8
|
|
80029a0: af00 add r7, sp, #0
|
|
80029a2: 0002 movs r2, r0
|
|
80029a4: 1dbb adds r3, r7, #6
|
|
80029a6: 801a strh r2, [r3, #0]
|
|
/* EXTI line interrupt detected */
|
|
if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00u)
|
|
80029a8: 4b10 ldr r3, [pc, #64] ; (80029ec <HAL_GPIO_EXTI_IRQHandler+0x50>)
|
|
80029aa: 68db ldr r3, [r3, #12]
|
|
80029ac: 1dba adds r2, r7, #6
|
|
80029ae: 8812 ldrh r2, [r2, #0]
|
|
80029b0: 4013 ands r3, r2
|
|
80029b2: d008 beq.n 80029c6 <HAL_GPIO_EXTI_IRQHandler+0x2a>
|
|
{
|
|
__HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
|
|
80029b4: 4b0d ldr r3, [pc, #52] ; (80029ec <HAL_GPIO_EXTI_IRQHandler+0x50>)
|
|
80029b6: 1dba adds r2, r7, #6
|
|
80029b8: 8812 ldrh r2, [r2, #0]
|
|
80029ba: 60da str r2, [r3, #12]
|
|
HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
|
|
80029bc: 1dbb adds r3, r7, #6
|
|
80029be: 881b ldrh r3, [r3, #0]
|
|
80029c0: 0018 movs r0, r3
|
|
80029c2: f7fe fe9f bl 8001704 <HAL_GPIO_EXTI_Rising_Callback>
|
|
}
|
|
|
|
if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00u)
|
|
80029c6: 4b09 ldr r3, [pc, #36] ; (80029ec <HAL_GPIO_EXTI_IRQHandler+0x50>)
|
|
80029c8: 691b ldr r3, [r3, #16]
|
|
80029ca: 1dba adds r2, r7, #6
|
|
80029cc: 8812 ldrh r2, [r2, #0]
|
|
80029ce: 4013 ands r3, r2
|
|
80029d0: d008 beq.n 80029e4 <HAL_GPIO_EXTI_IRQHandler+0x48>
|
|
{
|
|
__HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
|
|
80029d2: 4b06 ldr r3, [pc, #24] ; (80029ec <HAL_GPIO_EXTI_IRQHandler+0x50>)
|
|
80029d4: 1dba adds r2, r7, #6
|
|
80029d6: 8812 ldrh r2, [r2, #0]
|
|
80029d8: 611a str r2, [r3, #16]
|
|
HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
|
|
80029da: 1dbb adds r3, r7, #6
|
|
80029dc: 881b ldrh r3, [r3, #0]
|
|
80029de: 0018 movs r0, r3
|
|
80029e0: f7fe feaa bl 8001738 <HAL_GPIO_EXTI_Falling_Callback>
|
|
}
|
|
}
|
|
80029e4: 46c0 nop ; (mov r8, r8)
|
|
80029e6: 46bd mov sp, r7
|
|
80029e8: b002 add sp, #8
|
|
80029ea: bd80 pop {r7, pc}
|
|
80029ec: 40021800 .word 0x40021800
|
|
|
|
080029f0 <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
80029f0: b580 push {r7, lr}
|
|
80029f2: b082 sub sp, #8
|
|
80029f4: af00 add r7, sp, #0
|
|
80029f6: 6078 str r0, [r7, #4]
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
80029f8: 687b ldr r3, [r7, #4]
|
|
80029fa: 2b00 cmp r3, #0
|
|
80029fc: d101 bne.n 8002a02 <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80029fe: 2301 movs r3, #1
|
|
8002a00: e082 b.n 8002b08 <HAL_I2C_Init+0x118>
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
8002a02: 687b ldr r3, [r7, #4]
|
|
8002a04: 2241 movs r2, #65 ; 0x41
|
|
8002a06: 5c9b ldrb r3, [r3, r2]
|
|
8002a08: b2db uxtb r3, r3
|
|
8002a0a: 2b00 cmp r3, #0
|
|
8002a0c: d107 bne.n 8002a1e <HAL_I2C_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
8002a0e: 687b ldr r3, [r7, #4]
|
|
8002a10: 2240 movs r2, #64 ; 0x40
|
|
8002a12: 2100 movs r1, #0
|
|
8002a14: 5499 strb r1, [r3, r2]
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
HAL_I2C_MspInit(hi2c);
|
|
8002a16: 687b ldr r3, [r7, #4]
|
|
8002a18: 0018 movs r0, r3
|
|
8002a1a: f7fe ffc1 bl 80019a0 <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8002a1e: 687b ldr r3, [r7, #4]
|
|
8002a20: 2241 movs r2, #65 ; 0x41
|
|
8002a22: 2124 movs r1, #36 ; 0x24
|
|
8002a24: 5499 strb r1, [r3, r2]
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8002a26: 687b ldr r3, [r7, #4]
|
|
8002a28: 681b ldr r3, [r3, #0]
|
|
8002a2a: 681a ldr r2, [r3, #0]
|
|
8002a2c: 687b ldr r3, [r7, #4]
|
|
8002a2e: 681b ldr r3, [r3, #0]
|
|
8002a30: 2101 movs r1, #1
|
|
8002a32: 438a bics r2, r1
|
|
8002a34: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
|
|
8002a36: 687b ldr r3, [r7, #4]
|
|
8002a38: 685a ldr r2, [r3, #4]
|
|
8002a3a: 687b ldr r3, [r7, #4]
|
|
8002a3c: 681b ldr r3, [r3, #0]
|
|
8002a3e: 4934 ldr r1, [pc, #208] ; (8002b10 <HAL_I2C_Init+0x120>)
|
|
8002a40: 400a ands r2, r1
|
|
8002a42: 611a str r2, [r3, #16]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Disable Own Address1 before set the Own Address1 configuration */
|
|
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
|
|
8002a44: 687b ldr r3, [r7, #4]
|
|
8002a46: 681b ldr r3, [r3, #0]
|
|
8002a48: 689a ldr r2, [r3, #8]
|
|
8002a4a: 687b ldr r3, [r7, #4]
|
|
8002a4c: 681b ldr r3, [r3, #0]
|
|
8002a4e: 4931 ldr r1, [pc, #196] ; (8002b14 <HAL_I2C_Init+0x124>)
|
|
8002a50: 400a ands r2, r1
|
|
8002a52: 609a str r2, [r3, #8]
|
|
|
|
/* Configure I2Cx: Own Address1 and ack own address1 mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
|
|
8002a54: 687b ldr r3, [r7, #4]
|
|
8002a56: 68db ldr r3, [r3, #12]
|
|
8002a58: 2b01 cmp r3, #1
|
|
8002a5a: d108 bne.n 8002a6e <HAL_I2C_Init+0x7e>
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
|
|
8002a5c: 687b ldr r3, [r7, #4]
|
|
8002a5e: 689a ldr r2, [r3, #8]
|
|
8002a60: 687b ldr r3, [r7, #4]
|
|
8002a62: 681b ldr r3, [r3, #0]
|
|
8002a64: 2180 movs r1, #128 ; 0x80
|
|
8002a66: 0209 lsls r1, r1, #8
|
|
8002a68: 430a orrs r2, r1
|
|
8002a6a: 609a str r2, [r3, #8]
|
|
8002a6c: e007 b.n 8002a7e <HAL_I2C_Init+0x8e>
|
|
}
|
|
else /* I2C_ADDRESSINGMODE_10BIT */
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
|
|
8002a6e: 687b ldr r3, [r7, #4]
|
|
8002a70: 689a ldr r2, [r3, #8]
|
|
8002a72: 687b ldr r3, [r7, #4]
|
|
8002a74: 681b ldr r3, [r3, #0]
|
|
8002a76: 2184 movs r1, #132 ; 0x84
|
|
8002a78: 0209 lsls r1, r1, #8
|
|
8002a7a: 430a orrs r2, r1
|
|
8002a7c: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Addressing Master mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
|
|
8002a7e: 687b ldr r3, [r7, #4]
|
|
8002a80: 68db ldr r3, [r3, #12]
|
|
8002a82: 2b02 cmp r3, #2
|
|
8002a84: d104 bne.n 8002a90 <HAL_I2C_Init+0xa0>
|
|
{
|
|
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
|
|
8002a86: 687b ldr r3, [r7, #4]
|
|
8002a88: 681b ldr r3, [r3, #0]
|
|
8002a8a: 2280 movs r2, #128 ; 0x80
|
|
8002a8c: 0112 lsls r2, r2, #4
|
|
8002a8e: 605a str r2, [r3, #4]
|
|
}
|
|
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
|
|
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
|
|
8002a90: 687b ldr r3, [r7, #4]
|
|
8002a92: 681b ldr r3, [r3, #0]
|
|
8002a94: 685a ldr r2, [r3, #4]
|
|
8002a96: 687b ldr r3, [r7, #4]
|
|
8002a98: 681b ldr r3, [r3, #0]
|
|
8002a9a: 491f ldr r1, [pc, #124] ; (8002b18 <HAL_I2C_Init+0x128>)
|
|
8002a9c: 430a orrs r2, r1
|
|
8002a9e: 605a str r2, [r3, #4]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Disable Own Address2 before set the Own Address2 configuration */
|
|
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
|
|
8002aa0: 687b ldr r3, [r7, #4]
|
|
8002aa2: 681b ldr r3, [r3, #0]
|
|
8002aa4: 68da ldr r2, [r3, #12]
|
|
8002aa6: 687b ldr r3, [r7, #4]
|
|
8002aa8: 681b ldr r3, [r3, #0]
|
|
8002aaa: 491a ldr r1, [pc, #104] ; (8002b14 <HAL_I2C_Init+0x124>)
|
|
8002aac: 400a ands r2, r1
|
|
8002aae: 60da str r2, [r3, #12]
|
|
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
|
|
8002ab0: 687b ldr r3, [r7, #4]
|
|
8002ab2: 691a ldr r2, [r3, #16]
|
|
8002ab4: 687b ldr r3, [r7, #4]
|
|
8002ab6: 695b ldr r3, [r3, #20]
|
|
8002ab8: 431a orrs r2, r3
|
|
8002aba: 0011 movs r1, r2
|
|
(hi2c->Init.OwnAddress2Masks << 8));
|
|
8002abc: 687b ldr r3, [r7, #4]
|
|
8002abe: 699b ldr r3, [r3, #24]
|
|
8002ac0: 021a lsls r2, r3, #8
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
|
|
8002ac2: 687b ldr r3, [r7, #4]
|
|
8002ac4: 681b ldr r3, [r3, #0]
|
|
8002ac6: 430a orrs r2, r1
|
|
8002ac8: 60da str r2, [r3, #12]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
|
|
8002aca: 687b ldr r3, [r7, #4]
|
|
8002acc: 69d9 ldr r1, [r3, #28]
|
|
8002ace: 687b ldr r3, [r7, #4]
|
|
8002ad0: 6a1a ldr r2, [r3, #32]
|
|
8002ad2: 687b ldr r3, [r7, #4]
|
|
8002ad4: 681b ldr r3, [r3, #0]
|
|
8002ad6: 430a orrs r2, r1
|
|
8002ad8: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8002ada: 687b ldr r3, [r7, #4]
|
|
8002adc: 681b ldr r3, [r3, #0]
|
|
8002ade: 681a ldr r2, [r3, #0]
|
|
8002ae0: 687b ldr r3, [r7, #4]
|
|
8002ae2: 681b ldr r3, [r3, #0]
|
|
8002ae4: 2101 movs r1, #1
|
|
8002ae6: 430a orrs r2, r1
|
|
8002ae8: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8002aea: 687b ldr r3, [r7, #4]
|
|
8002aec: 2200 movs r2, #0
|
|
8002aee: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8002af0: 687b ldr r3, [r7, #4]
|
|
8002af2: 2241 movs r2, #65 ; 0x41
|
|
8002af4: 2120 movs r1, #32
|
|
8002af6: 5499 strb r1, [r3, r2]
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8002af8: 687b ldr r3, [r7, #4]
|
|
8002afa: 2200 movs r2, #0
|
|
8002afc: 631a str r2, [r3, #48] ; 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8002afe: 687b ldr r3, [r7, #4]
|
|
8002b00: 2242 movs r2, #66 ; 0x42
|
|
8002b02: 2100 movs r1, #0
|
|
8002b04: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_OK;
|
|
8002b06: 2300 movs r3, #0
|
|
}
|
|
8002b08: 0018 movs r0, r3
|
|
8002b0a: 46bd mov sp, r7
|
|
8002b0c: b002 add sp, #8
|
|
8002b0e: bd80 pop {r7, pc}
|
|
8002b10: f0ffffff .word 0xf0ffffff
|
|
8002b14: ffff7fff .word 0xffff7fff
|
|
8002b18: 02008000 .word 0x02008000
|
|
|
|
08002b1c <HAL_I2C_Mem_Write>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8002b1c: b590 push {r4, r7, lr}
|
|
8002b1e: b089 sub sp, #36 ; 0x24
|
|
8002b20: af02 add r7, sp, #8
|
|
8002b22: 60f8 str r0, [r7, #12]
|
|
8002b24: 000c movs r4, r1
|
|
8002b26: 0010 movs r0, r2
|
|
8002b28: 0019 movs r1, r3
|
|
8002b2a: 230a movs r3, #10
|
|
8002b2c: 18fb adds r3, r7, r3
|
|
8002b2e: 1c22 adds r2, r4, #0
|
|
8002b30: 801a strh r2, [r3, #0]
|
|
8002b32: 2308 movs r3, #8
|
|
8002b34: 18fb adds r3, r7, r3
|
|
8002b36: 1c02 adds r2, r0, #0
|
|
8002b38: 801a strh r2, [r3, #0]
|
|
8002b3a: 1dbb adds r3, r7, #6
|
|
8002b3c: 1c0a adds r2, r1, #0
|
|
8002b3e: 801a strh r2, [r3, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8002b40: 68fb ldr r3, [r7, #12]
|
|
8002b42: 2241 movs r2, #65 ; 0x41
|
|
8002b44: 5c9b ldrb r3, [r3, r2]
|
|
8002b46: b2db uxtb r3, r3
|
|
8002b48: 2b20 cmp r3, #32
|
|
8002b4a: d000 beq.n 8002b4e <HAL_I2C_Mem_Write+0x32>
|
|
8002b4c: e10c b.n 8002d68 <HAL_I2C_Mem_Write+0x24c>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8002b4e: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8002b50: 2b00 cmp r3, #0
|
|
8002b52: d004 beq.n 8002b5e <HAL_I2C_Mem_Write+0x42>
|
|
8002b54: 232c movs r3, #44 ; 0x2c
|
|
8002b56: 18fb adds r3, r7, r3
|
|
8002b58: 881b ldrh r3, [r3, #0]
|
|
8002b5a: 2b00 cmp r3, #0
|
|
8002b5c: d105 bne.n 8002b6a <HAL_I2C_Mem_Write+0x4e>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
8002b5e: 68fb ldr r3, [r7, #12]
|
|
8002b60: 2280 movs r2, #128 ; 0x80
|
|
8002b62: 0092 lsls r2, r2, #2
|
|
8002b64: 645a str r2, [r3, #68] ; 0x44
|
|
return HAL_ERROR;
|
|
8002b66: 2301 movs r3, #1
|
|
8002b68: e0ff b.n 8002d6a <HAL_I2C_Mem_Write+0x24e>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8002b6a: 68fb ldr r3, [r7, #12]
|
|
8002b6c: 2240 movs r2, #64 ; 0x40
|
|
8002b6e: 5c9b ldrb r3, [r3, r2]
|
|
8002b70: 2b01 cmp r3, #1
|
|
8002b72: d101 bne.n 8002b78 <HAL_I2C_Mem_Write+0x5c>
|
|
8002b74: 2302 movs r3, #2
|
|
8002b76: e0f8 b.n 8002d6a <HAL_I2C_Mem_Write+0x24e>
|
|
8002b78: 68fb ldr r3, [r7, #12]
|
|
8002b7a: 2240 movs r2, #64 ; 0x40
|
|
8002b7c: 2101 movs r1, #1
|
|
8002b7e: 5499 strb r1, [r3, r2]
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
8002b80: f7ff f8f4 bl 8001d6c <HAL_GetTick>
|
|
8002b84: 0003 movs r3, r0
|
|
8002b86: 617b str r3, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
8002b88: 2380 movs r3, #128 ; 0x80
|
|
8002b8a: 0219 lsls r1, r3, #8
|
|
8002b8c: 68f8 ldr r0, [r7, #12]
|
|
8002b8e: 697b ldr r3, [r7, #20]
|
|
8002b90: 9300 str r3, [sp, #0]
|
|
8002b92: 2319 movs r3, #25
|
|
8002b94: 2201 movs r2, #1
|
|
8002b96: f000 fb0b bl 80031b0 <I2C_WaitOnFlagUntilTimeout>
|
|
8002b9a: 1e03 subs r3, r0, #0
|
|
8002b9c: d001 beq.n 8002ba2 <HAL_I2C_Mem_Write+0x86>
|
|
{
|
|
return HAL_ERROR;
|
|
8002b9e: 2301 movs r3, #1
|
|
8002ba0: e0e3 b.n 8002d6a <HAL_I2C_Mem_Write+0x24e>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_TX;
|
|
8002ba2: 68fb ldr r3, [r7, #12]
|
|
8002ba4: 2241 movs r2, #65 ; 0x41
|
|
8002ba6: 2121 movs r1, #33 ; 0x21
|
|
8002ba8: 5499 strb r1, [r3, r2]
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
8002baa: 68fb ldr r3, [r7, #12]
|
|
8002bac: 2242 movs r2, #66 ; 0x42
|
|
8002bae: 2140 movs r1, #64 ; 0x40
|
|
8002bb0: 5499 strb r1, [r3, r2]
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8002bb2: 68fb ldr r3, [r7, #12]
|
|
8002bb4: 2200 movs r2, #0
|
|
8002bb6: 645a str r2, [r3, #68] ; 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8002bb8: 68fb ldr r3, [r7, #12]
|
|
8002bba: 6aba ldr r2, [r7, #40] ; 0x28
|
|
8002bbc: 625a str r2, [r3, #36] ; 0x24
|
|
hi2c->XferCount = Size;
|
|
8002bbe: 68fb ldr r3, [r7, #12]
|
|
8002bc0: 222c movs r2, #44 ; 0x2c
|
|
8002bc2: 18ba adds r2, r7, r2
|
|
8002bc4: 8812 ldrh r2, [r2, #0]
|
|
8002bc6: 855a strh r2, [r3, #42] ; 0x2a
|
|
hi2c->XferISR = NULL;
|
|
8002bc8: 68fb ldr r3, [r7, #12]
|
|
8002bca: 2200 movs r2, #0
|
|
8002bcc: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
8002bce: 1dbb adds r3, r7, #6
|
|
8002bd0: 881c ldrh r4, [r3, #0]
|
|
8002bd2: 2308 movs r3, #8
|
|
8002bd4: 18fb adds r3, r7, r3
|
|
8002bd6: 881a ldrh r2, [r3, #0]
|
|
8002bd8: 230a movs r3, #10
|
|
8002bda: 18fb adds r3, r7, r3
|
|
8002bdc: 8819 ldrh r1, [r3, #0]
|
|
8002bde: 68f8 ldr r0, [r7, #12]
|
|
8002be0: 697b ldr r3, [r7, #20]
|
|
8002be2: 9301 str r3, [sp, #4]
|
|
8002be4: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8002be6: 9300 str r3, [sp, #0]
|
|
8002be8: 0023 movs r3, r4
|
|
8002bea: f000 f9f9 bl 8002fe0 <I2C_RequestMemoryWrite>
|
|
8002bee: 1e03 subs r3, r0, #0
|
|
8002bf0: d005 beq.n 8002bfe <HAL_I2C_Mem_Write+0xe2>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8002bf2: 68fb ldr r3, [r7, #12]
|
|
8002bf4: 2240 movs r2, #64 ; 0x40
|
|
8002bf6: 2100 movs r1, #0
|
|
8002bf8: 5499 strb r1, [r3, r2]
|
|
return HAL_ERROR;
|
|
8002bfa: 2301 movs r3, #1
|
|
8002bfc: e0b5 b.n 8002d6a <HAL_I2C_Mem_Write+0x24e>
|
|
}
|
|
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8002bfe: 68fb ldr r3, [r7, #12]
|
|
8002c00: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002c02: b29b uxth r3, r3
|
|
8002c04: 2bff cmp r3, #255 ; 0xff
|
|
8002c06: d911 bls.n 8002c2c <HAL_I2C_Mem_Write+0x110>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8002c08: 68fb ldr r3, [r7, #12]
|
|
8002c0a: 22ff movs r2, #255 ; 0xff
|
|
8002c0c: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
|
8002c0e: 68fb ldr r3, [r7, #12]
|
|
8002c10: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8002c12: b2da uxtb r2, r3
|
|
8002c14: 2380 movs r3, #128 ; 0x80
|
|
8002c16: 045c lsls r4, r3, #17
|
|
8002c18: 230a movs r3, #10
|
|
8002c1a: 18fb adds r3, r7, r3
|
|
8002c1c: 8819 ldrh r1, [r3, #0]
|
|
8002c1e: 68f8 ldr r0, [r7, #12]
|
|
8002c20: 2300 movs r3, #0
|
|
8002c22: 9300 str r3, [sp, #0]
|
|
8002c24: 0023 movs r3, r4
|
|
8002c26: f000 fc7d bl 8003524 <I2C_TransferConfig>
|
|
8002c2a: e012 b.n 8002c52 <HAL_I2C_Mem_Write+0x136>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8002c2c: 68fb ldr r3, [r7, #12]
|
|
8002c2e: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002c30: b29a uxth r2, r3
|
|
8002c32: 68fb ldr r3, [r7, #12]
|
|
8002c34: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
|
8002c36: 68fb ldr r3, [r7, #12]
|
|
8002c38: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8002c3a: b2da uxtb r2, r3
|
|
8002c3c: 2380 movs r3, #128 ; 0x80
|
|
8002c3e: 049c lsls r4, r3, #18
|
|
8002c40: 230a movs r3, #10
|
|
8002c42: 18fb adds r3, r7, r3
|
|
8002c44: 8819 ldrh r1, [r3, #0]
|
|
8002c46: 68f8 ldr r0, [r7, #12]
|
|
8002c48: 2300 movs r3, #0
|
|
8002c4a: 9300 str r3, [sp, #0]
|
|
8002c4c: 0023 movs r3, r4
|
|
8002c4e: f000 fc69 bl 8003524 <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8002c52: 697a ldr r2, [r7, #20]
|
|
8002c54: 6b39 ldr r1, [r7, #48] ; 0x30
|
|
8002c56: 68fb ldr r3, [r7, #12]
|
|
8002c58: 0018 movs r0, r3
|
|
8002c5a: f000 fae8 bl 800322e <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8002c5e: 1e03 subs r3, r0, #0
|
|
8002c60: d001 beq.n 8002c66 <HAL_I2C_Mem_Write+0x14a>
|
|
{
|
|
return HAL_ERROR;
|
|
8002c62: 2301 movs r3, #1
|
|
8002c64: e081 b.n 8002d6a <HAL_I2C_Mem_Write+0x24e>
|
|
}
|
|
|
|
/* Write data to TXDR */
|
|
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
|
8002c66: 68fb ldr r3, [r7, #12]
|
|
8002c68: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8002c6a: 781a ldrb r2, [r3, #0]
|
|
8002c6c: 68fb ldr r3, [r7, #12]
|
|
8002c6e: 681b ldr r3, [r3, #0]
|
|
8002c70: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8002c72: 68fb ldr r3, [r7, #12]
|
|
8002c74: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8002c76: 1c5a adds r2, r3, #1
|
|
8002c78: 68fb ldr r3, [r7, #12]
|
|
8002c7a: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hi2c->XferCount--;
|
|
8002c7c: 68fb ldr r3, [r7, #12]
|
|
8002c7e: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002c80: b29b uxth r3, r3
|
|
8002c82: 3b01 subs r3, #1
|
|
8002c84: b29a uxth r2, r3
|
|
8002c86: 68fb ldr r3, [r7, #12]
|
|
8002c88: 855a strh r2, [r3, #42] ; 0x2a
|
|
hi2c->XferSize--;
|
|
8002c8a: 68fb ldr r3, [r7, #12]
|
|
8002c8c: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8002c8e: 3b01 subs r3, #1
|
|
8002c90: b29a uxth r2, r3
|
|
8002c92: 68fb ldr r3, [r7, #12]
|
|
8002c94: 851a strh r2, [r3, #40] ; 0x28
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
8002c96: 68fb ldr r3, [r7, #12]
|
|
8002c98: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002c9a: b29b uxth r3, r3
|
|
8002c9c: 2b00 cmp r3, #0
|
|
8002c9e: d03a beq.n 8002d16 <HAL_I2C_Mem_Write+0x1fa>
|
|
8002ca0: 68fb ldr r3, [r7, #12]
|
|
8002ca2: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8002ca4: 2b00 cmp r3, #0
|
|
8002ca6: d136 bne.n 8002d16 <HAL_I2C_Mem_Write+0x1fa>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
8002ca8: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
8002caa: 68f8 ldr r0, [r7, #12]
|
|
8002cac: 697b ldr r3, [r7, #20]
|
|
8002cae: 9300 str r3, [sp, #0]
|
|
8002cb0: 0013 movs r3, r2
|
|
8002cb2: 2200 movs r2, #0
|
|
8002cb4: 2180 movs r1, #128 ; 0x80
|
|
8002cb6: f000 fa7b bl 80031b0 <I2C_WaitOnFlagUntilTimeout>
|
|
8002cba: 1e03 subs r3, r0, #0
|
|
8002cbc: d001 beq.n 8002cc2 <HAL_I2C_Mem_Write+0x1a6>
|
|
{
|
|
return HAL_ERROR;
|
|
8002cbe: 2301 movs r3, #1
|
|
8002cc0: e053 b.n 8002d6a <HAL_I2C_Mem_Write+0x24e>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8002cc2: 68fb ldr r3, [r7, #12]
|
|
8002cc4: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002cc6: b29b uxth r3, r3
|
|
8002cc8: 2bff cmp r3, #255 ; 0xff
|
|
8002cca: d911 bls.n 8002cf0 <HAL_I2C_Mem_Write+0x1d4>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8002ccc: 68fb ldr r3, [r7, #12]
|
|
8002cce: 22ff movs r2, #255 ; 0xff
|
|
8002cd0: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8002cd2: 68fb ldr r3, [r7, #12]
|
|
8002cd4: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8002cd6: b2da uxtb r2, r3
|
|
8002cd8: 2380 movs r3, #128 ; 0x80
|
|
8002cda: 045c lsls r4, r3, #17
|
|
8002cdc: 230a movs r3, #10
|
|
8002cde: 18fb adds r3, r7, r3
|
|
8002ce0: 8819 ldrh r1, [r3, #0]
|
|
8002ce2: 68f8 ldr r0, [r7, #12]
|
|
8002ce4: 2300 movs r3, #0
|
|
8002ce6: 9300 str r3, [sp, #0]
|
|
8002ce8: 0023 movs r3, r4
|
|
8002cea: f000 fc1b bl 8003524 <I2C_TransferConfig>
|
|
8002cee: e012 b.n 8002d16 <HAL_I2C_Mem_Write+0x1fa>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8002cf0: 68fb ldr r3, [r7, #12]
|
|
8002cf2: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002cf4: b29a uxth r2, r3
|
|
8002cf6: 68fb ldr r3, [r7, #12]
|
|
8002cf8: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8002cfa: 68fb ldr r3, [r7, #12]
|
|
8002cfc: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8002cfe: b2da uxtb r2, r3
|
|
8002d00: 2380 movs r3, #128 ; 0x80
|
|
8002d02: 049c lsls r4, r3, #18
|
|
8002d04: 230a movs r3, #10
|
|
8002d06: 18fb adds r3, r7, r3
|
|
8002d08: 8819 ldrh r1, [r3, #0]
|
|
8002d0a: 68f8 ldr r0, [r7, #12]
|
|
8002d0c: 2300 movs r3, #0
|
|
8002d0e: 9300 str r3, [sp, #0]
|
|
8002d10: 0023 movs r3, r4
|
|
8002d12: f000 fc07 bl 8003524 <I2C_TransferConfig>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
}
|
|
|
|
} while (hi2c->XferCount > 0U);
|
|
8002d16: 68fb ldr r3, [r7, #12]
|
|
8002d18: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002d1a: b29b uxth r3, r3
|
|
8002d1c: 2b00 cmp r3, #0
|
|
8002d1e: d198 bne.n 8002c52 <HAL_I2C_Mem_Write+0x136>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8002d20: 697a ldr r2, [r7, #20]
|
|
8002d22: 6b39 ldr r1, [r7, #48] ; 0x30
|
|
8002d24: 68fb ldr r3, [r7, #12]
|
|
8002d26: 0018 movs r0, r3
|
|
8002d28: f000 fac0 bl 80032ac <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
8002d2c: 1e03 subs r3, r0, #0
|
|
8002d2e: d001 beq.n 8002d34 <HAL_I2C_Mem_Write+0x218>
|
|
{
|
|
return HAL_ERROR;
|
|
8002d30: 2301 movs r3, #1
|
|
8002d32: e01a b.n 8002d6a <HAL_I2C_Mem_Write+0x24e>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8002d34: 68fb ldr r3, [r7, #12]
|
|
8002d36: 681b ldr r3, [r3, #0]
|
|
8002d38: 2220 movs r2, #32
|
|
8002d3a: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
8002d3c: 68fb ldr r3, [r7, #12]
|
|
8002d3e: 681b ldr r3, [r3, #0]
|
|
8002d40: 685a ldr r2, [r3, #4]
|
|
8002d42: 68fb ldr r3, [r7, #12]
|
|
8002d44: 681b ldr r3, [r3, #0]
|
|
8002d46: 490b ldr r1, [pc, #44] ; (8002d74 <HAL_I2C_Mem_Write+0x258>)
|
|
8002d48: 400a ands r2, r1
|
|
8002d4a: 605a str r2, [r3, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8002d4c: 68fb ldr r3, [r7, #12]
|
|
8002d4e: 2241 movs r2, #65 ; 0x41
|
|
8002d50: 2120 movs r1, #32
|
|
8002d52: 5499 strb r1, [r3, r2]
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8002d54: 68fb ldr r3, [r7, #12]
|
|
8002d56: 2242 movs r2, #66 ; 0x42
|
|
8002d58: 2100 movs r1, #0
|
|
8002d5a: 5499 strb r1, [r3, r2]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8002d5c: 68fb ldr r3, [r7, #12]
|
|
8002d5e: 2240 movs r2, #64 ; 0x40
|
|
8002d60: 2100 movs r1, #0
|
|
8002d62: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_OK;
|
|
8002d64: 2300 movs r3, #0
|
|
8002d66: e000 b.n 8002d6a <HAL_I2C_Mem_Write+0x24e>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8002d68: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8002d6a: 0018 movs r0, r3
|
|
8002d6c: 46bd mov sp, r7
|
|
8002d6e: b007 add sp, #28
|
|
8002d70: bd90 pop {r4, r7, pc}
|
|
8002d72: 46c0 nop ; (mov r8, r8)
|
|
8002d74: fe00e800 .word 0xfe00e800
|
|
|
|
08002d78 <HAL_I2C_Mem_Read>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8002d78: b590 push {r4, r7, lr}
|
|
8002d7a: b089 sub sp, #36 ; 0x24
|
|
8002d7c: af02 add r7, sp, #8
|
|
8002d7e: 60f8 str r0, [r7, #12]
|
|
8002d80: 000c movs r4, r1
|
|
8002d82: 0010 movs r0, r2
|
|
8002d84: 0019 movs r1, r3
|
|
8002d86: 230a movs r3, #10
|
|
8002d88: 18fb adds r3, r7, r3
|
|
8002d8a: 1c22 adds r2, r4, #0
|
|
8002d8c: 801a strh r2, [r3, #0]
|
|
8002d8e: 2308 movs r3, #8
|
|
8002d90: 18fb adds r3, r7, r3
|
|
8002d92: 1c02 adds r2, r0, #0
|
|
8002d94: 801a strh r2, [r3, #0]
|
|
8002d96: 1dbb adds r3, r7, #6
|
|
8002d98: 1c0a adds r2, r1, #0
|
|
8002d9a: 801a strh r2, [r3, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8002d9c: 68fb ldr r3, [r7, #12]
|
|
8002d9e: 2241 movs r2, #65 ; 0x41
|
|
8002da0: 5c9b ldrb r3, [r3, r2]
|
|
8002da2: b2db uxtb r3, r3
|
|
8002da4: 2b20 cmp r3, #32
|
|
8002da6: d000 beq.n 8002daa <HAL_I2C_Mem_Read+0x32>
|
|
8002da8: e110 b.n 8002fcc <HAL_I2C_Mem_Read+0x254>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8002daa: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8002dac: 2b00 cmp r3, #0
|
|
8002dae: d004 beq.n 8002dba <HAL_I2C_Mem_Read+0x42>
|
|
8002db0: 232c movs r3, #44 ; 0x2c
|
|
8002db2: 18fb adds r3, r7, r3
|
|
8002db4: 881b ldrh r3, [r3, #0]
|
|
8002db6: 2b00 cmp r3, #0
|
|
8002db8: d105 bne.n 8002dc6 <HAL_I2C_Mem_Read+0x4e>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
8002dba: 68fb ldr r3, [r7, #12]
|
|
8002dbc: 2280 movs r2, #128 ; 0x80
|
|
8002dbe: 0092 lsls r2, r2, #2
|
|
8002dc0: 645a str r2, [r3, #68] ; 0x44
|
|
return HAL_ERROR;
|
|
8002dc2: 2301 movs r3, #1
|
|
8002dc4: e103 b.n 8002fce <HAL_I2C_Mem_Read+0x256>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8002dc6: 68fb ldr r3, [r7, #12]
|
|
8002dc8: 2240 movs r2, #64 ; 0x40
|
|
8002dca: 5c9b ldrb r3, [r3, r2]
|
|
8002dcc: 2b01 cmp r3, #1
|
|
8002dce: d101 bne.n 8002dd4 <HAL_I2C_Mem_Read+0x5c>
|
|
8002dd0: 2302 movs r3, #2
|
|
8002dd2: e0fc b.n 8002fce <HAL_I2C_Mem_Read+0x256>
|
|
8002dd4: 68fb ldr r3, [r7, #12]
|
|
8002dd6: 2240 movs r2, #64 ; 0x40
|
|
8002dd8: 2101 movs r1, #1
|
|
8002dda: 5499 strb r1, [r3, r2]
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
8002ddc: f7fe ffc6 bl 8001d6c <HAL_GetTick>
|
|
8002de0: 0003 movs r3, r0
|
|
8002de2: 617b str r3, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
8002de4: 2380 movs r3, #128 ; 0x80
|
|
8002de6: 0219 lsls r1, r3, #8
|
|
8002de8: 68f8 ldr r0, [r7, #12]
|
|
8002dea: 697b ldr r3, [r7, #20]
|
|
8002dec: 9300 str r3, [sp, #0]
|
|
8002dee: 2319 movs r3, #25
|
|
8002df0: 2201 movs r2, #1
|
|
8002df2: f000 f9dd bl 80031b0 <I2C_WaitOnFlagUntilTimeout>
|
|
8002df6: 1e03 subs r3, r0, #0
|
|
8002df8: d001 beq.n 8002dfe <HAL_I2C_Mem_Read+0x86>
|
|
{
|
|
return HAL_ERROR;
|
|
8002dfa: 2301 movs r3, #1
|
|
8002dfc: e0e7 b.n 8002fce <HAL_I2C_Mem_Read+0x256>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_RX;
|
|
8002dfe: 68fb ldr r3, [r7, #12]
|
|
8002e00: 2241 movs r2, #65 ; 0x41
|
|
8002e02: 2122 movs r1, #34 ; 0x22
|
|
8002e04: 5499 strb r1, [r3, r2]
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
8002e06: 68fb ldr r3, [r7, #12]
|
|
8002e08: 2242 movs r2, #66 ; 0x42
|
|
8002e0a: 2140 movs r1, #64 ; 0x40
|
|
8002e0c: 5499 strb r1, [r3, r2]
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8002e0e: 68fb ldr r3, [r7, #12]
|
|
8002e10: 2200 movs r2, #0
|
|
8002e12: 645a str r2, [r3, #68] ; 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8002e14: 68fb ldr r3, [r7, #12]
|
|
8002e16: 6aba ldr r2, [r7, #40] ; 0x28
|
|
8002e18: 625a str r2, [r3, #36] ; 0x24
|
|
hi2c->XferCount = Size;
|
|
8002e1a: 68fb ldr r3, [r7, #12]
|
|
8002e1c: 222c movs r2, #44 ; 0x2c
|
|
8002e1e: 18ba adds r2, r7, r2
|
|
8002e20: 8812 ldrh r2, [r2, #0]
|
|
8002e22: 855a strh r2, [r3, #42] ; 0x2a
|
|
hi2c->XferISR = NULL;
|
|
8002e24: 68fb ldr r3, [r7, #12]
|
|
8002e26: 2200 movs r2, #0
|
|
8002e28: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
8002e2a: 1dbb adds r3, r7, #6
|
|
8002e2c: 881c ldrh r4, [r3, #0]
|
|
8002e2e: 2308 movs r3, #8
|
|
8002e30: 18fb adds r3, r7, r3
|
|
8002e32: 881a ldrh r2, [r3, #0]
|
|
8002e34: 230a movs r3, #10
|
|
8002e36: 18fb adds r3, r7, r3
|
|
8002e38: 8819 ldrh r1, [r3, #0]
|
|
8002e3a: 68f8 ldr r0, [r7, #12]
|
|
8002e3c: 697b ldr r3, [r7, #20]
|
|
8002e3e: 9301 str r3, [sp, #4]
|
|
8002e40: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8002e42: 9300 str r3, [sp, #0]
|
|
8002e44: 0023 movs r3, r4
|
|
8002e46: f000 f92f bl 80030a8 <I2C_RequestMemoryRead>
|
|
8002e4a: 1e03 subs r3, r0, #0
|
|
8002e4c: d005 beq.n 8002e5a <HAL_I2C_Mem_Read+0xe2>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8002e4e: 68fb ldr r3, [r7, #12]
|
|
8002e50: 2240 movs r2, #64 ; 0x40
|
|
8002e52: 2100 movs r1, #0
|
|
8002e54: 5499 strb r1, [r3, r2]
|
|
return HAL_ERROR;
|
|
8002e56: 2301 movs r3, #1
|
|
8002e58: e0b9 b.n 8002fce <HAL_I2C_Mem_Read+0x256>
|
|
}
|
|
|
|
/* Send Slave Address */
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8002e5a: 68fb ldr r3, [r7, #12]
|
|
8002e5c: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002e5e: b29b uxth r3, r3
|
|
8002e60: 2bff cmp r3, #255 ; 0xff
|
|
8002e62: d911 bls.n 8002e88 <HAL_I2C_Mem_Read+0x110>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8002e64: 68fb ldr r3, [r7, #12]
|
|
8002e66: 22ff movs r2, #255 ; 0xff
|
|
8002e68: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8002e6a: 68fb ldr r3, [r7, #12]
|
|
8002e6c: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8002e6e: b2da uxtb r2, r3
|
|
8002e70: 2380 movs r3, #128 ; 0x80
|
|
8002e72: 045c lsls r4, r3, #17
|
|
8002e74: 230a movs r3, #10
|
|
8002e76: 18fb adds r3, r7, r3
|
|
8002e78: 8819 ldrh r1, [r3, #0]
|
|
8002e7a: 68f8 ldr r0, [r7, #12]
|
|
8002e7c: 4b56 ldr r3, [pc, #344] ; (8002fd8 <HAL_I2C_Mem_Read+0x260>)
|
|
8002e7e: 9300 str r3, [sp, #0]
|
|
8002e80: 0023 movs r3, r4
|
|
8002e82: f000 fb4f bl 8003524 <I2C_TransferConfig>
|
|
8002e86: e012 b.n 8002eae <HAL_I2C_Mem_Read+0x136>
|
|
I2C_GENERATE_START_READ);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8002e88: 68fb ldr r3, [r7, #12]
|
|
8002e8a: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002e8c: b29a uxth r2, r3
|
|
8002e8e: 68fb ldr r3, [r7, #12]
|
|
8002e90: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8002e92: 68fb ldr r3, [r7, #12]
|
|
8002e94: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8002e96: b2da uxtb r2, r3
|
|
8002e98: 2380 movs r3, #128 ; 0x80
|
|
8002e9a: 049c lsls r4, r3, #18
|
|
8002e9c: 230a movs r3, #10
|
|
8002e9e: 18fb adds r3, r7, r3
|
|
8002ea0: 8819 ldrh r1, [r3, #0]
|
|
8002ea2: 68f8 ldr r0, [r7, #12]
|
|
8002ea4: 4b4c ldr r3, [pc, #304] ; (8002fd8 <HAL_I2C_Mem_Read+0x260>)
|
|
8002ea6: 9300 str r3, [sp, #0]
|
|
8002ea8: 0023 movs r3, r4
|
|
8002eaa: f000 fb3b bl 8003524 <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until RXNE flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
|
|
8002eae: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
8002eb0: 68f8 ldr r0, [r7, #12]
|
|
8002eb2: 697b ldr r3, [r7, #20]
|
|
8002eb4: 9300 str r3, [sp, #0]
|
|
8002eb6: 0013 movs r3, r2
|
|
8002eb8: 2200 movs r2, #0
|
|
8002eba: 2104 movs r1, #4
|
|
8002ebc: f000 f978 bl 80031b0 <I2C_WaitOnFlagUntilTimeout>
|
|
8002ec0: 1e03 subs r3, r0, #0
|
|
8002ec2: d001 beq.n 8002ec8 <HAL_I2C_Mem_Read+0x150>
|
|
{
|
|
return HAL_ERROR;
|
|
8002ec4: 2301 movs r3, #1
|
|
8002ec6: e082 b.n 8002fce <HAL_I2C_Mem_Read+0x256>
|
|
}
|
|
|
|
/* Read data from RXDR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
|
|
8002ec8: 68fb ldr r3, [r7, #12]
|
|
8002eca: 681b ldr r3, [r3, #0]
|
|
8002ecc: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
8002ece: 68fb ldr r3, [r7, #12]
|
|
8002ed0: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8002ed2: b2d2 uxtb r2, r2
|
|
8002ed4: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8002ed6: 68fb ldr r3, [r7, #12]
|
|
8002ed8: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8002eda: 1c5a adds r2, r3, #1
|
|
8002edc: 68fb ldr r3, [r7, #12]
|
|
8002ede: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hi2c->XferSize--;
|
|
8002ee0: 68fb ldr r3, [r7, #12]
|
|
8002ee2: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8002ee4: 3b01 subs r3, #1
|
|
8002ee6: b29a uxth r2, r3
|
|
8002ee8: 68fb ldr r3, [r7, #12]
|
|
8002eea: 851a strh r2, [r3, #40] ; 0x28
|
|
hi2c->XferCount--;
|
|
8002eec: 68fb ldr r3, [r7, #12]
|
|
8002eee: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002ef0: b29b uxth r3, r3
|
|
8002ef2: 3b01 subs r3, #1
|
|
8002ef4: b29a uxth r2, r3
|
|
8002ef6: 68fb ldr r3, [r7, #12]
|
|
8002ef8: 855a strh r2, [r3, #42] ; 0x2a
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
8002efa: 68fb ldr r3, [r7, #12]
|
|
8002efc: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002efe: b29b uxth r3, r3
|
|
8002f00: 2b00 cmp r3, #0
|
|
8002f02: d03a beq.n 8002f7a <HAL_I2C_Mem_Read+0x202>
|
|
8002f04: 68fb ldr r3, [r7, #12]
|
|
8002f06: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8002f08: 2b00 cmp r3, #0
|
|
8002f0a: d136 bne.n 8002f7a <HAL_I2C_Mem_Read+0x202>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
8002f0c: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
8002f0e: 68f8 ldr r0, [r7, #12]
|
|
8002f10: 697b ldr r3, [r7, #20]
|
|
8002f12: 9300 str r3, [sp, #0]
|
|
8002f14: 0013 movs r3, r2
|
|
8002f16: 2200 movs r2, #0
|
|
8002f18: 2180 movs r1, #128 ; 0x80
|
|
8002f1a: f000 f949 bl 80031b0 <I2C_WaitOnFlagUntilTimeout>
|
|
8002f1e: 1e03 subs r3, r0, #0
|
|
8002f20: d001 beq.n 8002f26 <HAL_I2C_Mem_Read+0x1ae>
|
|
{
|
|
return HAL_ERROR;
|
|
8002f22: 2301 movs r3, #1
|
|
8002f24: e053 b.n 8002fce <HAL_I2C_Mem_Read+0x256>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8002f26: 68fb ldr r3, [r7, #12]
|
|
8002f28: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002f2a: b29b uxth r3, r3
|
|
8002f2c: 2bff cmp r3, #255 ; 0xff
|
|
8002f2e: d911 bls.n 8002f54 <HAL_I2C_Mem_Read+0x1dc>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8002f30: 68fb ldr r3, [r7, #12]
|
|
8002f32: 22ff movs r2, #255 ; 0xff
|
|
8002f34: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8002f36: 68fb ldr r3, [r7, #12]
|
|
8002f38: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8002f3a: b2da uxtb r2, r3
|
|
8002f3c: 2380 movs r3, #128 ; 0x80
|
|
8002f3e: 045c lsls r4, r3, #17
|
|
8002f40: 230a movs r3, #10
|
|
8002f42: 18fb adds r3, r7, r3
|
|
8002f44: 8819 ldrh r1, [r3, #0]
|
|
8002f46: 68f8 ldr r0, [r7, #12]
|
|
8002f48: 2300 movs r3, #0
|
|
8002f4a: 9300 str r3, [sp, #0]
|
|
8002f4c: 0023 movs r3, r4
|
|
8002f4e: f000 fae9 bl 8003524 <I2C_TransferConfig>
|
|
8002f52: e012 b.n 8002f7a <HAL_I2C_Mem_Read+0x202>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8002f54: 68fb ldr r3, [r7, #12]
|
|
8002f56: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002f58: b29a uxth r2, r3
|
|
8002f5a: 68fb ldr r3, [r7, #12]
|
|
8002f5c: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8002f5e: 68fb ldr r3, [r7, #12]
|
|
8002f60: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8002f62: b2da uxtb r2, r3
|
|
8002f64: 2380 movs r3, #128 ; 0x80
|
|
8002f66: 049c lsls r4, r3, #18
|
|
8002f68: 230a movs r3, #10
|
|
8002f6a: 18fb adds r3, r7, r3
|
|
8002f6c: 8819 ldrh r1, [r3, #0]
|
|
8002f6e: 68f8 ldr r0, [r7, #12]
|
|
8002f70: 2300 movs r3, #0
|
|
8002f72: 9300 str r3, [sp, #0]
|
|
8002f74: 0023 movs r3, r4
|
|
8002f76: f000 fad5 bl 8003524 <I2C_TransferConfig>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
}
|
|
} while (hi2c->XferCount > 0U);
|
|
8002f7a: 68fb ldr r3, [r7, #12]
|
|
8002f7c: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8002f7e: b29b uxth r3, r3
|
|
8002f80: 2b00 cmp r3, #0
|
|
8002f82: d194 bne.n 8002eae <HAL_I2C_Mem_Read+0x136>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8002f84: 697a ldr r2, [r7, #20]
|
|
8002f86: 6b39 ldr r1, [r7, #48] ; 0x30
|
|
8002f88: 68fb ldr r3, [r7, #12]
|
|
8002f8a: 0018 movs r0, r3
|
|
8002f8c: f000 f98e bl 80032ac <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
8002f90: 1e03 subs r3, r0, #0
|
|
8002f92: d001 beq.n 8002f98 <HAL_I2C_Mem_Read+0x220>
|
|
{
|
|
return HAL_ERROR;
|
|
8002f94: 2301 movs r3, #1
|
|
8002f96: e01a b.n 8002fce <HAL_I2C_Mem_Read+0x256>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8002f98: 68fb ldr r3, [r7, #12]
|
|
8002f9a: 681b ldr r3, [r3, #0]
|
|
8002f9c: 2220 movs r2, #32
|
|
8002f9e: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
8002fa0: 68fb ldr r3, [r7, #12]
|
|
8002fa2: 681b ldr r3, [r3, #0]
|
|
8002fa4: 685a ldr r2, [r3, #4]
|
|
8002fa6: 68fb ldr r3, [r7, #12]
|
|
8002fa8: 681b ldr r3, [r3, #0]
|
|
8002faa: 490c ldr r1, [pc, #48] ; (8002fdc <HAL_I2C_Mem_Read+0x264>)
|
|
8002fac: 400a ands r2, r1
|
|
8002fae: 605a str r2, [r3, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8002fb0: 68fb ldr r3, [r7, #12]
|
|
8002fb2: 2241 movs r2, #65 ; 0x41
|
|
8002fb4: 2120 movs r1, #32
|
|
8002fb6: 5499 strb r1, [r3, r2]
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8002fb8: 68fb ldr r3, [r7, #12]
|
|
8002fba: 2242 movs r2, #66 ; 0x42
|
|
8002fbc: 2100 movs r1, #0
|
|
8002fbe: 5499 strb r1, [r3, r2]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8002fc0: 68fb ldr r3, [r7, #12]
|
|
8002fc2: 2240 movs r2, #64 ; 0x40
|
|
8002fc4: 2100 movs r1, #0
|
|
8002fc6: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_OK;
|
|
8002fc8: 2300 movs r3, #0
|
|
8002fca: e000 b.n 8002fce <HAL_I2C_Mem_Read+0x256>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8002fcc: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8002fce: 0018 movs r0, r3
|
|
8002fd0: 46bd mov sp, r7
|
|
8002fd2: b007 add sp, #28
|
|
8002fd4: bd90 pop {r4, r7, pc}
|
|
8002fd6: 46c0 nop ; (mov r8, r8)
|
|
8002fd8: 80002400 .word 0x80002400
|
|
8002fdc: fe00e800 .word 0xfe00e800
|
|
|
|
08002fe0 <I2C_RequestMemoryWrite>:
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
8002fe0: b5b0 push {r4, r5, r7, lr}
|
|
8002fe2: b086 sub sp, #24
|
|
8002fe4: af02 add r7, sp, #8
|
|
8002fe6: 60f8 str r0, [r7, #12]
|
|
8002fe8: 000c movs r4, r1
|
|
8002fea: 0010 movs r0, r2
|
|
8002fec: 0019 movs r1, r3
|
|
8002fee: 250a movs r5, #10
|
|
8002ff0: 197b adds r3, r7, r5
|
|
8002ff2: 1c22 adds r2, r4, #0
|
|
8002ff4: 801a strh r2, [r3, #0]
|
|
8002ff6: 2308 movs r3, #8
|
|
8002ff8: 18fb adds r3, r7, r3
|
|
8002ffa: 1c02 adds r2, r0, #0
|
|
8002ffc: 801a strh r2, [r3, #0]
|
|
8002ffe: 1dbb adds r3, r7, #6
|
|
8003000: 1c0a adds r2, r1, #0
|
|
8003002: 801a strh r2, [r3, #0]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
|
|
8003004: 1dbb adds r3, r7, #6
|
|
8003006: 881b ldrh r3, [r3, #0]
|
|
8003008: b2da uxtb r2, r3
|
|
800300a: 2380 movs r3, #128 ; 0x80
|
|
800300c: 045c lsls r4, r3, #17
|
|
800300e: 197b adds r3, r7, r5
|
|
8003010: 8819 ldrh r1, [r3, #0]
|
|
8003012: 68f8 ldr r0, [r7, #12]
|
|
8003014: 4b23 ldr r3, [pc, #140] ; (80030a4 <I2C_RequestMemoryWrite+0xc4>)
|
|
8003016: 9300 str r3, [sp, #0]
|
|
8003018: 0023 movs r3, r4
|
|
800301a: f000 fa83 bl 8003524 <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
800301e: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
8003020: 6a39 ldr r1, [r7, #32]
|
|
8003022: 68fb ldr r3, [r7, #12]
|
|
8003024: 0018 movs r0, r3
|
|
8003026: f000 f902 bl 800322e <I2C_WaitOnTXISFlagUntilTimeout>
|
|
800302a: 1e03 subs r3, r0, #0
|
|
800302c: d001 beq.n 8003032 <I2C_RequestMemoryWrite+0x52>
|
|
{
|
|
return HAL_ERROR;
|
|
800302e: 2301 movs r3, #1
|
|
8003030: e033 b.n 800309a <I2C_RequestMemoryWrite+0xba>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
8003032: 1dbb adds r3, r7, #6
|
|
8003034: 881b ldrh r3, [r3, #0]
|
|
8003036: 2b01 cmp r3, #1
|
|
8003038: d107 bne.n 800304a <I2C_RequestMemoryWrite+0x6a>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
800303a: 2308 movs r3, #8
|
|
800303c: 18fb adds r3, r7, r3
|
|
800303e: 881b ldrh r3, [r3, #0]
|
|
8003040: b2da uxtb r2, r3
|
|
8003042: 68fb ldr r3, [r7, #12]
|
|
8003044: 681b ldr r3, [r3, #0]
|
|
8003046: 629a str r2, [r3, #40] ; 0x28
|
|
8003048: e019 b.n 800307e <I2C_RequestMemoryWrite+0x9e>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
800304a: 2308 movs r3, #8
|
|
800304c: 18fb adds r3, r7, r3
|
|
800304e: 881b ldrh r3, [r3, #0]
|
|
8003050: 0a1b lsrs r3, r3, #8
|
|
8003052: b29b uxth r3, r3
|
|
8003054: b2da uxtb r2, r3
|
|
8003056: 68fb ldr r3, [r7, #12]
|
|
8003058: 681b ldr r3, [r3, #0]
|
|
800305a: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
800305c: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
800305e: 6a39 ldr r1, [r7, #32]
|
|
8003060: 68fb ldr r3, [r7, #12]
|
|
8003062: 0018 movs r0, r3
|
|
8003064: f000 f8e3 bl 800322e <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8003068: 1e03 subs r3, r0, #0
|
|
800306a: d001 beq.n 8003070 <I2C_RequestMemoryWrite+0x90>
|
|
{
|
|
return HAL_ERROR;
|
|
800306c: 2301 movs r3, #1
|
|
800306e: e014 b.n 800309a <I2C_RequestMemoryWrite+0xba>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8003070: 2308 movs r3, #8
|
|
8003072: 18fb adds r3, r7, r3
|
|
8003074: 881b ldrh r3, [r3, #0]
|
|
8003076: b2da uxtb r2, r3
|
|
8003078: 68fb ldr r3, [r7, #12]
|
|
800307a: 681b ldr r3, [r3, #0]
|
|
800307c: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
|
|
800307e: 6a3a ldr r2, [r7, #32]
|
|
8003080: 68f8 ldr r0, [r7, #12]
|
|
8003082: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8003084: 9300 str r3, [sp, #0]
|
|
8003086: 0013 movs r3, r2
|
|
8003088: 2200 movs r2, #0
|
|
800308a: 2180 movs r1, #128 ; 0x80
|
|
800308c: f000 f890 bl 80031b0 <I2C_WaitOnFlagUntilTimeout>
|
|
8003090: 1e03 subs r3, r0, #0
|
|
8003092: d001 beq.n 8003098 <I2C_RequestMemoryWrite+0xb8>
|
|
{
|
|
return HAL_ERROR;
|
|
8003094: 2301 movs r3, #1
|
|
8003096: e000 b.n 800309a <I2C_RequestMemoryWrite+0xba>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003098: 2300 movs r3, #0
|
|
}
|
|
800309a: 0018 movs r0, r3
|
|
800309c: 46bd mov sp, r7
|
|
800309e: b004 add sp, #16
|
|
80030a0: bdb0 pop {r4, r5, r7, pc}
|
|
80030a2: 46c0 nop ; (mov r8, r8)
|
|
80030a4: 80002000 .word 0x80002000
|
|
|
|
080030a8 <I2C_RequestMemoryRead>:
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
80030a8: b5b0 push {r4, r5, r7, lr}
|
|
80030aa: b086 sub sp, #24
|
|
80030ac: af02 add r7, sp, #8
|
|
80030ae: 60f8 str r0, [r7, #12]
|
|
80030b0: 000c movs r4, r1
|
|
80030b2: 0010 movs r0, r2
|
|
80030b4: 0019 movs r1, r3
|
|
80030b6: 250a movs r5, #10
|
|
80030b8: 197b adds r3, r7, r5
|
|
80030ba: 1c22 adds r2, r4, #0
|
|
80030bc: 801a strh r2, [r3, #0]
|
|
80030be: 2308 movs r3, #8
|
|
80030c0: 18fb adds r3, r7, r3
|
|
80030c2: 1c02 adds r2, r0, #0
|
|
80030c4: 801a strh r2, [r3, #0]
|
|
80030c6: 1dbb adds r3, r7, #6
|
|
80030c8: 1c0a adds r2, r1, #0
|
|
80030ca: 801a strh r2, [r3, #0]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
|
|
80030cc: 1dbb adds r3, r7, #6
|
|
80030ce: 881b ldrh r3, [r3, #0]
|
|
80030d0: b2da uxtb r2, r3
|
|
80030d2: 197b adds r3, r7, r5
|
|
80030d4: 8819 ldrh r1, [r3, #0]
|
|
80030d6: 68f8 ldr r0, [r7, #12]
|
|
80030d8: 4b23 ldr r3, [pc, #140] ; (8003168 <I2C_RequestMemoryRead+0xc0>)
|
|
80030da: 9300 str r3, [sp, #0]
|
|
80030dc: 2300 movs r3, #0
|
|
80030de: f000 fa21 bl 8003524 <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80030e2: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
80030e4: 6a39 ldr r1, [r7, #32]
|
|
80030e6: 68fb ldr r3, [r7, #12]
|
|
80030e8: 0018 movs r0, r3
|
|
80030ea: f000 f8a0 bl 800322e <I2C_WaitOnTXISFlagUntilTimeout>
|
|
80030ee: 1e03 subs r3, r0, #0
|
|
80030f0: d001 beq.n 80030f6 <I2C_RequestMemoryRead+0x4e>
|
|
{
|
|
return HAL_ERROR;
|
|
80030f2: 2301 movs r3, #1
|
|
80030f4: e033 b.n 800315e <I2C_RequestMemoryRead+0xb6>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
80030f6: 1dbb adds r3, r7, #6
|
|
80030f8: 881b ldrh r3, [r3, #0]
|
|
80030fa: 2b01 cmp r3, #1
|
|
80030fc: d107 bne.n 800310e <I2C_RequestMemoryRead+0x66>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
80030fe: 2308 movs r3, #8
|
|
8003100: 18fb adds r3, r7, r3
|
|
8003102: 881b ldrh r3, [r3, #0]
|
|
8003104: b2da uxtb r2, r3
|
|
8003106: 68fb ldr r3, [r7, #12]
|
|
8003108: 681b ldr r3, [r3, #0]
|
|
800310a: 629a str r2, [r3, #40] ; 0x28
|
|
800310c: e019 b.n 8003142 <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
800310e: 2308 movs r3, #8
|
|
8003110: 18fb adds r3, r7, r3
|
|
8003112: 881b ldrh r3, [r3, #0]
|
|
8003114: 0a1b lsrs r3, r3, #8
|
|
8003116: b29b uxth r3, r3
|
|
8003118: b2da uxtb r2, r3
|
|
800311a: 68fb ldr r3, [r7, #12]
|
|
800311c: 681b ldr r3, [r3, #0]
|
|
800311e: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8003120: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
8003122: 6a39 ldr r1, [r7, #32]
|
|
8003124: 68fb ldr r3, [r7, #12]
|
|
8003126: 0018 movs r0, r3
|
|
8003128: f000 f881 bl 800322e <I2C_WaitOnTXISFlagUntilTimeout>
|
|
800312c: 1e03 subs r3, r0, #0
|
|
800312e: d001 beq.n 8003134 <I2C_RequestMemoryRead+0x8c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003130: 2301 movs r3, #1
|
|
8003132: e014 b.n 800315e <I2C_RequestMemoryRead+0xb6>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8003134: 2308 movs r3, #8
|
|
8003136: 18fb adds r3, r7, r3
|
|
8003138: 881b ldrh r3, [r3, #0]
|
|
800313a: b2da uxtb r2, r3
|
|
800313c: 68fb ldr r3, [r7, #12]
|
|
800313e: 681b ldr r3, [r3, #0]
|
|
8003140: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
|
|
/* Wait until TC flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
|
|
8003142: 6a3a ldr r2, [r7, #32]
|
|
8003144: 68f8 ldr r0, [r7, #12]
|
|
8003146: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8003148: 9300 str r3, [sp, #0]
|
|
800314a: 0013 movs r3, r2
|
|
800314c: 2200 movs r2, #0
|
|
800314e: 2140 movs r1, #64 ; 0x40
|
|
8003150: f000 f82e bl 80031b0 <I2C_WaitOnFlagUntilTimeout>
|
|
8003154: 1e03 subs r3, r0, #0
|
|
8003156: d001 beq.n 800315c <I2C_RequestMemoryRead+0xb4>
|
|
{
|
|
return HAL_ERROR;
|
|
8003158: 2301 movs r3, #1
|
|
800315a: e000 b.n 800315e <I2C_RequestMemoryRead+0xb6>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800315c: 2300 movs r3, #0
|
|
}
|
|
800315e: 0018 movs r0, r3
|
|
8003160: 46bd mov sp, r7
|
|
8003162: b004 add sp, #16
|
|
8003164: bdb0 pop {r4, r5, r7, pc}
|
|
8003166: 46c0 nop ; (mov r8, r8)
|
|
8003168: 80002000 .word 0x80002000
|
|
|
|
0800316c <I2C_Flush_TXDR>:
|
|
* @brief I2C Tx data register flush process.
|
|
* @param hi2c I2C handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
800316c: b580 push {r7, lr}
|
|
800316e: b082 sub sp, #8
|
|
8003170: af00 add r7, sp, #0
|
|
8003172: 6078 str r0, [r7, #4]
|
|
/* If a pending TXIS flag is set */
|
|
/* Write a dummy data in TXDR to clear it */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
|
|
8003174: 687b ldr r3, [r7, #4]
|
|
8003176: 681b ldr r3, [r3, #0]
|
|
8003178: 699b ldr r3, [r3, #24]
|
|
800317a: 2202 movs r2, #2
|
|
800317c: 4013 ands r3, r2
|
|
800317e: 2b02 cmp r3, #2
|
|
8003180: d103 bne.n 800318a <I2C_Flush_TXDR+0x1e>
|
|
{
|
|
hi2c->Instance->TXDR = 0x00U;
|
|
8003182: 687b ldr r3, [r7, #4]
|
|
8003184: 681b ldr r3, [r3, #0]
|
|
8003186: 2200 movs r2, #0
|
|
8003188: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
|
|
/* Flush TX register if not empty */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
|
|
800318a: 687b ldr r3, [r7, #4]
|
|
800318c: 681b ldr r3, [r3, #0]
|
|
800318e: 699b ldr r3, [r3, #24]
|
|
8003190: 2201 movs r2, #1
|
|
8003192: 4013 ands r3, r2
|
|
8003194: 2b01 cmp r3, #1
|
|
8003196: d007 beq.n 80031a8 <I2C_Flush_TXDR+0x3c>
|
|
{
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
|
|
8003198: 687b ldr r3, [r7, #4]
|
|
800319a: 681b ldr r3, [r3, #0]
|
|
800319c: 699a ldr r2, [r3, #24]
|
|
800319e: 687b ldr r3, [r7, #4]
|
|
80031a0: 681b ldr r3, [r3, #0]
|
|
80031a2: 2101 movs r1, #1
|
|
80031a4: 430a orrs r2, r1
|
|
80031a6: 619a str r2, [r3, #24]
|
|
}
|
|
}
|
|
80031a8: 46c0 nop ; (mov r8, r8)
|
|
80031aa: 46bd mov sp, r7
|
|
80031ac: b002 add sp, #8
|
|
80031ae: bd80 pop {r7, pc}
|
|
|
|
080031b0 <I2C_WaitOnFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
80031b0: b580 push {r7, lr}
|
|
80031b2: b084 sub sp, #16
|
|
80031b4: af00 add r7, sp, #0
|
|
80031b6: 60f8 str r0, [r7, #12]
|
|
80031b8: 60b9 str r1, [r7, #8]
|
|
80031ba: 603b str r3, [r7, #0]
|
|
80031bc: 1dfb adds r3, r7, #7
|
|
80031be: 701a strb r2, [r3, #0]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
80031c0: e021 b.n 8003206 <I2C_WaitOnFlagUntilTimeout+0x56>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80031c2: 683b ldr r3, [r7, #0]
|
|
80031c4: 3301 adds r3, #1
|
|
80031c6: d01e beq.n 8003206 <I2C_WaitOnFlagUntilTimeout+0x56>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80031c8: f7fe fdd0 bl 8001d6c <HAL_GetTick>
|
|
80031cc: 0002 movs r2, r0
|
|
80031ce: 69bb ldr r3, [r7, #24]
|
|
80031d0: 1ad3 subs r3, r2, r3
|
|
80031d2: 683a ldr r2, [r7, #0]
|
|
80031d4: 429a cmp r2, r3
|
|
80031d6: d302 bcc.n 80031de <I2C_WaitOnFlagUntilTimeout+0x2e>
|
|
80031d8: 683b ldr r3, [r7, #0]
|
|
80031da: 2b00 cmp r3, #0
|
|
80031dc: d113 bne.n 8003206 <I2C_WaitOnFlagUntilTimeout+0x56>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
80031de: 68fb ldr r3, [r7, #12]
|
|
80031e0: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
80031e2: 2220 movs r2, #32
|
|
80031e4: 431a orrs r2, r3
|
|
80031e6: 68fb ldr r3, [r7, #12]
|
|
80031e8: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80031ea: 68fb ldr r3, [r7, #12]
|
|
80031ec: 2241 movs r2, #65 ; 0x41
|
|
80031ee: 2120 movs r1, #32
|
|
80031f0: 5499 strb r1, [r3, r2]
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80031f2: 68fb ldr r3, [r7, #12]
|
|
80031f4: 2242 movs r2, #66 ; 0x42
|
|
80031f6: 2100 movs r1, #0
|
|
80031f8: 5499 strb r1, [r3, r2]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80031fa: 68fb ldr r3, [r7, #12]
|
|
80031fc: 2240 movs r2, #64 ; 0x40
|
|
80031fe: 2100 movs r1, #0
|
|
8003200: 5499 strb r1, [r3, r2]
|
|
return HAL_ERROR;
|
|
8003202: 2301 movs r3, #1
|
|
8003204: e00f b.n 8003226 <I2C_WaitOnFlagUntilTimeout+0x76>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
8003206: 68fb ldr r3, [r7, #12]
|
|
8003208: 681b ldr r3, [r3, #0]
|
|
800320a: 699b ldr r3, [r3, #24]
|
|
800320c: 68ba ldr r2, [r7, #8]
|
|
800320e: 4013 ands r3, r2
|
|
8003210: 68ba ldr r2, [r7, #8]
|
|
8003212: 1ad3 subs r3, r2, r3
|
|
8003214: 425a negs r2, r3
|
|
8003216: 4153 adcs r3, r2
|
|
8003218: b2db uxtb r3, r3
|
|
800321a: 001a movs r2, r3
|
|
800321c: 1dfb adds r3, r7, #7
|
|
800321e: 781b ldrb r3, [r3, #0]
|
|
8003220: 429a cmp r2, r3
|
|
8003222: d0ce beq.n 80031c2 <I2C_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8003224: 2300 movs r3, #0
|
|
}
|
|
8003226: 0018 movs r0, r3
|
|
8003228: 46bd mov sp, r7
|
|
800322a: b004 add sp, #16
|
|
800322c: bd80 pop {r7, pc}
|
|
|
|
0800322e <I2C_WaitOnTXISFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
800322e: b580 push {r7, lr}
|
|
8003230: b084 sub sp, #16
|
|
8003232: af00 add r7, sp, #0
|
|
8003234: 60f8 str r0, [r7, #12]
|
|
8003236: 60b9 str r1, [r7, #8]
|
|
8003238: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
800323a: e02b b.n 8003294 <I2C_WaitOnTXISFlagUntilTimeout+0x66>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
800323c: 687a ldr r2, [r7, #4]
|
|
800323e: 68b9 ldr r1, [r7, #8]
|
|
8003240: 68fb ldr r3, [r7, #12]
|
|
8003242: 0018 movs r0, r3
|
|
8003244: f000 f86e bl 8003324 <I2C_IsErrorOccurred>
|
|
8003248: 1e03 subs r3, r0, #0
|
|
800324a: d001 beq.n 8003250 <I2C_WaitOnTXISFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
800324c: 2301 movs r3, #1
|
|
800324e: e029 b.n 80032a4 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8003250: 68bb ldr r3, [r7, #8]
|
|
8003252: 3301 adds r3, #1
|
|
8003254: d01e beq.n 8003294 <I2C_WaitOnTXISFlagUntilTimeout+0x66>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8003256: f7fe fd89 bl 8001d6c <HAL_GetTick>
|
|
800325a: 0002 movs r2, r0
|
|
800325c: 687b ldr r3, [r7, #4]
|
|
800325e: 1ad3 subs r3, r2, r3
|
|
8003260: 68ba ldr r2, [r7, #8]
|
|
8003262: 429a cmp r2, r3
|
|
8003264: d302 bcc.n 800326c <I2C_WaitOnTXISFlagUntilTimeout+0x3e>
|
|
8003266: 68bb ldr r3, [r7, #8]
|
|
8003268: 2b00 cmp r3, #0
|
|
800326a: d113 bne.n 8003294 <I2C_WaitOnTXISFlagUntilTimeout+0x66>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
800326c: 68fb ldr r3, [r7, #12]
|
|
800326e: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8003270: 2220 movs r2, #32
|
|
8003272: 431a orrs r2, r3
|
|
8003274: 68fb ldr r3, [r7, #12]
|
|
8003276: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8003278: 68fb ldr r3, [r7, #12]
|
|
800327a: 2241 movs r2, #65 ; 0x41
|
|
800327c: 2120 movs r1, #32
|
|
800327e: 5499 strb r1, [r3, r2]
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8003280: 68fb ldr r3, [r7, #12]
|
|
8003282: 2242 movs r2, #66 ; 0x42
|
|
8003284: 2100 movs r1, #0
|
|
8003286: 5499 strb r1, [r3, r2]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8003288: 68fb ldr r3, [r7, #12]
|
|
800328a: 2240 movs r2, #64 ; 0x40
|
|
800328c: 2100 movs r1, #0
|
|
800328e: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_ERROR;
|
|
8003290: 2301 movs r3, #1
|
|
8003292: e007 b.n 80032a4 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
8003294: 68fb ldr r3, [r7, #12]
|
|
8003296: 681b ldr r3, [r3, #0]
|
|
8003298: 699b ldr r3, [r3, #24]
|
|
800329a: 2202 movs r2, #2
|
|
800329c: 4013 ands r3, r2
|
|
800329e: 2b02 cmp r3, #2
|
|
80032a0: d1cc bne.n 800323c <I2C_WaitOnTXISFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80032a2: 2300 movs r3, #0
|
|
}
|
|
80032a4: 0018 movs r0, r3
|
|
80032a6: 46bd mov sp, r7
|
|
80032a8: b004 add sp, #16
|
|
80032aa: bd80 pop {r7, pc}
|
|
|
|
080032ac <I2C_WaitOnSTOPFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
80032ac: b580 push {r7, lr}
|
|
80032ae: b084 sub sp, #16
|
|
80032b0: af00 add r7, sp, #0
|
|
80032b2: 60f8 str r0, [r7, #12]
|
|
80032b4: 60b9 str r1, [r7, #8]
|
|
80032b6: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
80032b8: e028 b.n 800330c <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80032ba: 687a ldr r2, [r7, #4]
|
|
80032bc: 68b9 ldr r1, [r7, #8]
|
|
80032be: 68fb ldr r3, [r7, #12]
|
|
80032c0: 0018 movs r0, r3
|
|
80032c2: f000 f82f bl 8003324 <I2C_IsErrorOccurred>
|
|
80032c6: 1e03 subs r3, r0, #0
|
|
80032c8: d001 beq.n 80032ce <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
80032ca: 2301 movs r3, #1
|
|
80032cc: e026 b.n 800331c <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80032ce: f7fe fd4d bl 8001d6c <HAL_GetTick>
|
|
80032d2: 0002 movs r2, r0
|
|
80032d4: 687b ldr r3, [r7, #4]
|
|
80032d6: 1ad3 subs r3, r2, r3
|
|
80032d8: 68ba ldr r2, [r7, #8]
|
|
80032da: 429a cmp r2, r3
|
|
80032dc: d302 bcc.n 80032e4 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
|
|
80032de: 68bb ldr r3, [r7, #8]
|
|
80032e0: 2b00 cmp r3, #0
|
|
80032e2: d113 bne.n 800330c <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
80032e4: 68fb ldr r3, [r7, #12]
|
|
80032e6: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
80032e8: 2220 movs r2, #32
|
|
80032ea: 431a orrs r2, r3
|
|
80032ec: 68fb ldr r3, [r7, #12]
|
|
80032ee: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80032f0: 68fb ldr r3, [r7, #12]
|
|
80032f2: 2241 movs r2, #65 ; 0x41
|
|
80032f4: 2120 movs r1, #32
|
|
80032f6: 5499 strb r1, [r3, r2]
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80032f8: 68fb ldr r3, [r7, #12]
|
|
80032fa: 2242 movs r2, #66 ; 0x42
|
|
80032fc: 2100 movs r1, #0
|
|
80032fe: 5499 strb r1, [r3, r2]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8003300: 68fb ldr r3, [r7, #12]
|
|
8003302: 2240 movs r2, #64 ; 0x40
|
|
8003304: 2100 movs r1, #0
|
|
8003306: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_ERROR;
|
|
8003308: 2301 movs r3, #1
|
|
800330a: e007 b.n 800331c <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
800330c: 68fb ldr r3, [r7, #12]
|
|
800330e: 681b ldr r3, [r3, #0]
|
|
8003310: 699b ldr r3, [r3, #24]
|
|
8003312: 2220 movs r2, #32
|
|
8003314: 4013 ands r3, r2
|
|
8003316: 2b20 cmp r3, #32
|
|
8003318: d1cf bne.n 80032ba <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800331a: 2300 movs r3, #0
|
|
}
|
|
800331c: 0018 movs r0, r3
|
|
800331e: 46bd mov sp, r7
|
|
8003320: b004 add sp, #16
|
|
8003322: bd80 pop {r7, pc}
|
|
|
|
08003324 <I2C_IsErrorOccurred>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8003324: b590 push {r4, r7, lr}
|
|
8003326: b08b sub sp, #44 ; 0x2c
|
|
8003328: af00 add r7, sp, #0
|
|
800332a: 60f8 str r0, [r7, #12]
|
|
800332c: 60b9 str r1, [r7, #8]
|
|
800332e: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8003330: 2327 movs r3, #39 ; 0x27
|
|
8003332: 18fb adds r3, r7, r3
|
|
8003334: 2200 movs r2, #0
|
|
8003336: 701a strb r2, [r3, #0]
|
|
uint32_t itflag = hi2c->Instance->ISR;
|
|
8003338: 68fb ldr r3, [r7, #12]
|
|
800333a: 681b ldr r3, [r3, #0]
|
|
800333c: 699b ldr r3, [r3, #24]
|
|
800333e: 61bb str r3, [r7, #24]
|
|
uint32_t error_code = 0;
|
|
8003340: 2300 movs r3, #0
|
|
8003342: 623b str r3, [r7, #32]
|
|
uint32_t tickstart = Tickstart;
|
|
8003344: 687b ldr r3, [r7, #4]
|
|
8003346: 61fb str r3, [r7, #28]
|
|
uint32_t tmp1;
|
|
HAL_I2C_ModeTypeDef tmp2;
|
|
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
|
|
8003348: 69bb ldr r3, [r7, #24]
|
|
800334a: 2210 movs r2, #16
|
|
800334c: 4013 ands r3, r2
|
|
800334e: d100 bne.n 8003352 <I2C_IsErrorOccurred+0x2e>
|
|
8003350: e082 b.n 8003458 <I2C_IsErrorOccurred+0x134>
|
|
{
|
|
/* Clear NACKF Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8003352: 68fb ldr r3, [r7, #12]
|
|
8003354: 681b ldr r3, [r3, #0]
|
|
8003356: 2210 movs r2, #16
|
|
8003358: 61da str r2, [r3, #28]
|
|
|
|
/* Wait until STOP Flag is set or timeout occurred */
|
|
/* AutoEnd should be initiate after AF */
|
|
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
|
|
800335a: e060 b.n 800341e <I2C_IsErrorOccurred+0xfa>
|
|
800335c: 2427 movs r4, #39 ; 0x27
|
|
800335e: 193b adds r3, r7, r4
|
|
8003360: 193a adds r2, r7, r4
|
|
8003362: 7812 ldrb r2, [r2, #0]
|
|
8003364: 701a strb r2, [r3, #0]
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8003366: 68bb ldr r3, [r7, #8]
|
|
8003368: 3301 adds r3, #1
|
|
800336a: d058 beq.n 800341e <I2C_IsErrorOccurred+0xfa>
|
|
{
|
|
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
|
800336c: f7fe fcfe bl 8001d6c <HAL_GetTick>
|
|
8003370: 0002 movs r2, r0
|
|
8003372: 69fb ldr r3, [r7, #28]
|
|
8003374: 1ad3 subs r3, r2, r3
|
|
8003376: 68ba ldr r2, [r7, #8]
|
|
8003378: 429a cmp r2, r3
|
|
800337a: d306 bcc.n 800338a <I2C_IsErrorOccurred+0x66>
|
|
800337c: 193b adds r3, r7, r4
|
|
800337e: 193a adds r2, r7, r4
|
|
8003380: 7812 ldrb r2, [r2, #0]
|
|
8003382: 701a strb r2, [r3, #0]
|
|
8003384: 68bb ldr r3, [r7, #8]
|
|
8003386: 2b00 cmp r3, #0
|
|
8003388: d149 bne.n 800341e <I2C_IsErrorOccurred+0xfa>
|
|
{
|
|
tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
|
|
800338a: 68fb ldr r3, [r7, #12]
|
|
800338c: 681b ldr r3, [r3, #0]
|
|
800338e: 685a ldr r2, [r3, #4]
|
|
8003390: 2380 movs r3, #128 ; 0x80
|
|
8003392: 01db lsls r3, r3, #7
|
|
8003394: 4013 ands r3, r2
|
|
8003396: 617b str r3, [r7, #20]
|
|
tmp2 = hi2c->Mode;
|
|
8003398: 2013 movs r0, #19
|
|
800339a: 183b adds r3, r7, r0
|
|
800339c: 68fa ldr r2, [r7, #12]
|
|
800339e: 2142 movs r1, #66 ; 0x42
|
|
80033a0: 5c52 ldrb r2, [r2, r1]
|
|
80033a2: 701a strb r2, [r3, #0]
|
|
|
|
/* In case of I2C still busy, try to regenerate a STOP manually */
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
|
|
80033a4: 68fb ldr r3, [r7, #12]
|
|
80033a6: 681b ldr r3, [r3, #0]
|
|
80033a8: 699a ldr r2, [r3, #24]
|
|
80033aa: 2380 movs r3, #128 ; 0x80
|
|
80033ac: 021b lsls r3, r3, #8
|
|
80033ae: 401a ands r2, r3
|
|
80033b0: 2380 movs r3, #128 ; 0x80
|
|
80033b2: 021b lsls r3, r3, #8
|
|
80033b4: 429a cmp r2, r3
|
|
80033b6: d126 bne.n 8003406 <I2C_IsErrorOccurred+0xe2>
|
|
80033b8: 697a ldr r2, [r7, #20]
|
|
80033ba: 2380 movs r3, #128 ; 0x80
|
|
80033bc: 01db lsls r3, r3, #7
|
|
80033be: 429a cmp r2, r3
|
|
80033c0: d021 beq.n 8003406 <I2C_IsErrorOccurred+0xe2>
|
|
(tmp1 != I2C_CR2_STOP) && \
|
|
80033c2: 183b adds r3, r7, r0
|
|
80033c4: 781b ldrb r3, [r3, #0]
|
|
80033c6: 2b20 cmp r3, #32
|
|
80033c8: d01d beq.n 8003406 <I2C_IsErrorOccurred+0xe2>
|
|
(tmp2 != HAL_I2C_MODE_SLAVE))
|
|
{
|
|
/* Generate Stop */
|
|
hi2c->Instance->CR2 |= I2C_CR2_STOP;
|
|
80033ca: 68fb ldr r3, [r7, #12]
|
|
80033cc: 681b ldr r3, [r3, #0]
|
|
80033ce: 685a ldr r2, [r3, #4]
|
|
80033d0: 68fb ldr r3, [r7, #12]
|
|
80033d2: 681b ldr r3, [r3, #0]
|
|
80033d4: 2180 movs r1, #128 ; 0x80
|
|
80033d6: 01c9 lsls r1, r1, #7
|
|
80033d8: 430a orrs r2, r1
|
|
80033da: 605a str r2, [r3, #4]
|
|
|
|
/* Update Tick with new reference */
|
|
tickstart = HAL_GetTick();
|
|
80033dc: f7fe fcc6 bl 8001d6c <HAL_GetTick>
|
|
80033e0: 0003 movs r3, r0
|
|
80033e2: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
80033e4: e00f b.n 8003406 <I2C_IsErrorOccurred+0xe2>
|
|
{
|
|
/* Check for the Timeout */
|
|
if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
|
|
80033e6: f7fe fcc1 bl 8001d6c <HAL_GetTick>
|
|
80033ea: 0002 movs r2, r0
|
|
80033ec: 69fb ldr r3, [r7, #28]
|
|
80033ee: 1ad3 subs r3, r2, r3
|
|
80033f0: 2b19 cmp r3, #25
|
|
80033f2: d908 bls.n 8003406 <I2C_IsErrorOccurred+0xe2>
|
|
{
|
|
error_code |=HAL_I2C_ERROR_TIMEOUT;
|
|
80033f4: 6a3b ldr r3, [r7, #32]
|
|
80033f6: 2220 movs r2, #32
|
|
80033f8: 4313 orrs r3, r2
|
|
80033fa: 623b str r3, [r7, #32]
|
|
|
|
status = HAL_ERROR;
|
|
80033fc: 2327 movs r3, #39 ; 0x27
|
|
80033fe: 18fb adds r3, r7, r3
|
|
8003400: 2201 movs r2, #1
|
|
8003402: 701a strb r2, [r3, #0]
|
|
|
|
break;
|
|
8003404: e00b b.n 800341e <I2C_IsErrorOccurred+0xfa>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
8003406: 68fb ldr r3, [r7, #12]
|
|
8003408: 681b ldr r3, [r3, #0]
|
|
800340a: 699b ldr r3, [r3, #24]
|
|
800340c: 2220 movs r2, #32
|
|
800340e: 4013 ands r3, r2
|
|
8003410: 2127 movs r1, #39 ; 0x27
|
|
8003412: 187a adds r2, r7, r1
|
|
8003414: 1879 adds r1, r7, r1
|
|
8003416: 7809 ldrb r1, [r1, #0]
|
|
8003418: 7011 strb r1, [r2, #0]
|
|
800341a: 2b20 cmp r3, #32
|
|
800341c: d1e3 bne.n 80033e6 <I2C_IsErrorOccurred+0xc2>
|
|
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
|
|
800341e: 68fb ldr r3, [r7, #12]
|
|
8003420: 681b ldr r3, [r3, #0]
|
|
8003422: 699b ldr r3, [r3, #24]
|
|
8003424: 2220 movs r2, #32
|
|
8003426: 4013 ands r3, r2
|
|
8003428: 2b20 cmp r3, #32
|
|
800342a: d004 beq.n 8003436 <I2C_IsErrorOccurred+0x112>
|
|
800342c: 2327 movs r3, #39 ; 0x27
|
|
800342e: 18fb adds r3, r7, r3
|
|
8003430: 781b ldrb r3, [r3, #0]
|
|
8003432: 2b00 cmp r3, #0
|
|
8003434: d092 beq.n 800335c <I2C_IsErrorOccurred+0x38>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* In case STOP Flag is detected, clear it */
|
|
if (status == HAL_OK)
|
|
8003436: 2327 movs r3, #39 ; 0x27
|
|
8003438: 18fb adds r3, r7, r3
|
|
800343a: 781b ldrb r3, [r3, #0]
|
|
800343c: 2b00 cmp r3, #0
|
|
800343e: d103 bne.n 8003448 <I2C_IsErrorOccurred+0x124>
|
|
{
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8003440: 68fb ldr r3, [r7, #12]
|
|
8003442: 681b ldr r3, [r3, #0]
|
|
8003444: 2220 movs r2, #32
|
|
8003446: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
error_code |= HAL_I2C_ERROR_AF;
|
|
8003448: 6a3b ldr r3, [r7, #32]
|
|
800344a: 2204 movs r2, #4
|
|
800344c: 4313 orrs r3, r2
|
|
800344e: 623b str r3, [r7, #32]
|
|
|
|
status = HAL_ERROR;
|
|
8003450: 2327 movs r3, #39 ; 0x27
|
|
8003452: 18fb adds r3, r7, r3
|
|
8003454: 2201 movs r2, #1
|
|
8003456: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* Refresh Content of Status register */
|
|
itflag = hi2c->Instance->ISR;
|
|
8003458: 68fb ldr r3, [r7, #12]
|
|
800345a: 681b ldr r3, [r3, #0]
|
|
800345c: 699b ldr r3, [r3, #24]
|
|
800345e: 61bb str r3, [r7, #24]
|
|
|
|
/* Then verify if an additional errors occurs */
|
|
/* Check if a Bus error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
|
|
8003460: 69ba ldr r2, [r7, #24]
|
|
8003462: 2380 movs r3, #128 ; 0x80
|
|
8003464: 005b lsls r3, r3, #1
|
|
8003466: 4013 ands r3, r2
|
|
8003468: d00c beq.n 8003484 <I2C_IsErrorOccurred+0x160>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_BERR;
|
|
800346a: 6a3b ldr r3, [r7, #32]
|
|
800346c: 2201 movs r2, #1
|
|
800346e: 4313 orrs r3, r2
|
|
8003470: 623b str r3, [r7, #32]
|
|
|
|
/* Clear BERR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
|
|
8003472: 68fb ldr r3, [r7, #12]
|
|
8003474: 681b ldr r3, [r3, #0]
|
|
8003476: 2280 movs r2, #128 ; 0x80
|
|
8003478: 0052 lsls r2, r2, #1
|
|
800347a: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
800347c: 2327 movs r3, #39 ; 0x27
|
|
800347e: 18fb adds r3, r7, r3
|
|
8003480: 2201 movs r2, #1
|
|
8003482: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* Check if an Over-Run/Under-Run error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
|
|
8003484: 69ba ldr r2, [r7, #24]
|
|
8003486: 2380 movs r3, #128 ; 0x80
|
|
8003488: 00db lsls r3, r3, #3
|
|
800348a: 4013 ands r3, r2
|
|
800348c: d00c beq.n 80034a8 <I2C_IsErrorOccurred+0x184>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_OVR;
|
|
800348e: 6a3b ldr r3, [r7, #32]
|
|
8003490: 2208 movs r2, #8
|
|
8003492: 4313 orrs r3, r2
|
|
8003494: 623b str r3, [r7, #32]
|
|
|
|
/* Clear OVR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
|
|
8003496: 68fb ldr r3, [r7, #12]
|
|
8003498: 681b ldr r3, [r3, #0]
|
|
800349a: 2280 movs r2, #128 ; 0x80
|
|
800349c: 00d2 lsls r2, r2, #3
|
|
800349e: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
80034a0: 2327 movs r3, #39 ; 0x27
|
|
80034a2: 18fb adds r3, r7, r3
|
|
80034a4: 2201 movs r2, #1
|
|
80034a6: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* Check if an Arbitration Loss error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
|
|
80034a8: 69ba ldr r2, [r7, #24]
|
|
80034aa: 2380 movs r3, #128 ; 0x80
|
|
80034ac: 009b lsls r3, r3, #2
|
|
80034ae: 4013 ands r3, r2
|
|
80034b0: d00c beq.n 80034cc <I2C_IsErrorOccurred+0x1a8>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_ARLO;
|
|
80034b2: 6a3b ldr r3, [r7, #32]
|
|
80034b4: 2202 movs r2, #2
|
|
80034b6: 4313 orrs r3, r2
|
|
80034b8: 623b str r3, [r7, #32]
|
|
|
|
/* Clear ARLO flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
|
|
80034ba: 68fb ldr r3, [r7, #12]
|
|
80034bc: 681b ldr r3, [r3, #0]
|
|
80034be: 2280 movs r2, #128 ; 0x80
|
|
80034c0: 0092 lsls r2, r2, #2
|
|
80034c2: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
80034c4: 2327 movs r3, #39 ; 0x27
|
|
80034c6: 18fb adds r3, r7, r3
|
|
80034c8: 2201 movs r2, #1
|
|
80034ca: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
if (status != HAL_OK)
|
|
80034cc: 2327 movs r3, #39 ; 0x27
|
|
80034ce: 18fb adds r3, r7, r3
|
|
80034d0: 781b ldrb r3, [r3, #0]
|
|
80034d2: 2b00 cmp r3, #0
|
|
80034d4: d01d beq.n 8003512 <I2C_IsErrorOccurred+0x1ee>
|
|
{
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
80034d6: 68fb ldr r3, [r7, #12]
|
|
80034d8: 0018 movs r0, r3
|
|
80034da: f7ff fe47 bl 800316c <I2C_Flush_TXDR>
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
80034de: 68fb ldr r3, [r7, #12]
|
|
80034e0: 681b ldr r3, [r3, #0]
|
|
80034e2: 685a ldr r2, [r3, #4]
|
|
80034e4: 68fb ldr r3, [r7, #12]
|
|
80034e6: 681b ldr r3, [r3, #0]
|
|
80034e8: 490d ldr r1, [pc, #52] ; (8003520 <I2C_IsErrorOccurred+0x1fc>)
|
|
80034ea: 400a ands r2, r1
|
|
80034ec: 605a str r2, [r3, #4]
|
|
|
|
hi2c->ErrorCode |= error_code;
|
|
80034ee: 68fb ldr r3, [r7, #12]
|
|
80034f0: 6c5a ldr r2, [r3, #68] ; 0x44
|
|
80034f2: 6a3b ldr r3, [r7, #32]
|
|
80034f4: 431a orrs r2, r3
|
|
80034f6: 68fb ldr r3, [r7, #12]
|
|
80034f8: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80034fa: 68fb ldr r3, [r7, #12]
|
|
80034fc: 2241 movs r2, #65 ; 0x41
|
|
80034fe: 2120 movs r1, #32
|
|
8003500: 5499 strb r1, [r3, r2]
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8003502: 68fb ldr r3, [r7, #12]
|
|
8003504: 2242 movs r2, #66 ; 0x42
|
|
8003506: 2100 movs r1, #0
|
|
8003508: 5499 strb r1, [r3, r2]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800350a: 68fb ldr r3, [r7, #12]
|
|
800350c: 2240 movs r2, #64 ; 0x40
|
|
800350e: 2100 movs r1, #0
|
|
8003510: 5499 strb r1, [r3, r2]
|
|
}
|
|
|
|
return status;
|
|
8003512: 2327 movs r3, #39 ; 0x27
|
|
8003514: 18fb adds r3, r7, r3
|
|
8003516: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8003518: 0018 movs r0, r3
|
|
800351a: 46bd mov sp, r7
|
|
800351c: b00b add sp, #44 ; 0x2c
|
|
800351e: bd90 pop {r4, r7, pc}
|
|
8003520: fe00e800 .word 0xfe00e800
|
|
|
|
08003524 <I2C_TransferConfig>:
|
|
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
|
|
* @retval None
|
|
*/
|
|
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
|
uint32_t Request)
|
|
{
|
|
8003524: b590 push {r4, r7, lr}
|
|
8003526: b087 sub sp, #28
|
|
8003528: af00 add r7, sp, #0
|
|
800352a: 60f8 str r0, [r7, #12]
|
|
800352c: 0008 movs r0, r1
|
|
800352e: 0011 movs r1, r2
|
|
8003530: 607b str r3, [r7, #4]
|
|
8003532: 240a movs r4, #10
|
|
8003534: 193b adds r3, r7, r4
|
|
8003536: 1c02 adds r2, r0, #0
|
|
8003538: 801a strh r2, [r3, #0]
|
|
800353a: 2009 movs r0, #9
|
|
800353c: 183b adds r3, r7, r0
|
|
800353e: 1c0a adds r2, r1, #0
|
|
8003540: 701a strb r2, [r3, #0]
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_TRANSFER_MODE(Mode));
|
|
assert_param(IS_TRANSFER_REQUEST(Request));
|
|
|
|
/* Declaration of tmp to prevent undefined behavior of volatile usage */
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
8003542: 193b adds r3, r7, r4
|
|
8003544: 881b ldrh r3, [r3, #0]
|
|
8003546: 059b lsls r3, r3, #22
|
|
8003548: 0d9a lsrs r2, r3, #22
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
|
800354a: 183b adds r3, r7, r0
|
|
800354c: 781b ldrb r3, [r3, #0]
|
|
800354e: 0419 lsls r1, r3, #16
|
|
8003550: 23ff movs r3, #255 ; 0xff
|
|
8003552: 041b lsls r3, r3, #16
|
|
8003554: 400b ands r3, r1
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
8003556: 431a orrs r2, r3
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
|
8003558: 687b ldr r3, [r7, #4]
|
|
800355a: 431a orrs r2, r3
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
800355c: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800355e: 4313 orrs r3, r2
|
|
8003560: 005b lsls r3, r3, #1
|
|
8003562: 085b lsrs r3, r3, #1
|
|
8003564: 617b str r3, [r7, #20]
|
|
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
|
|
|
|
/* update CR2 register */
|
|
MODIFY_REG(hi2c->Instance->CR2, \
|
|
8003566: 68fb ldr r3, [r7, #12]
|
|
8003568: 681b ldr r3, [r3, #0]
|
|
800356a: 685b ldr r3, [r3, #4]
|
|
800356c: 6aba ldr r2, [r7, #40] ; 0x28
|
|
800356e: 0d51 lsrs r1, r2, #21
|
|
8003570: 2280 movs r2, #128 ; 0x80
|
|
8003572: 00d2 lsls r2, r2, #3
|
|
8003574: 400a ands r2, r1
|
|
8003576: 4907 ldr r1, [pc, #28] ; (8003594 <I2C_TransferConfig+0x70>)
|
|
8003578: 430a orrs r2, r1
|
|
800357a: 43d2 mvns r2, r2
|
|
800357c: 401a ands r2, r3
|
|
800357e: 0011 movs r1, r2
|
|
8003580: 68fb ldr r3, [r7, #12]
|
|
8003582: 681b ldr r3, [r3, #0]
|
|
8003584: 697a ldr r2, [r7, #20]
|
|
8003586: 430a orrs r2, r1
|
|
8003588: 605a str r2, [r3, #4]
|
|
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
|
|
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
|
|
I2C_CR2_START | I2C_CR2_STOP)), tmp);
|
|
}
|
|
800358a: 46c0 nop ; (mov r8, r8)
|
|
800358c: 46bd mov sp, r7
|
|
800358e: b007 add sp, #28
|
|
8003590: bd90 pop {r4, r7, pc}
|
|
8003592: 46c0 nop ; (mov r8, r8)
|
|
8003594: 03ff63ff .word 0x03ff63ff
|
|
|
|
08003598 <HAL_I2CEx_ConfigAnalogFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param AnalogFilter New state of the Analog filter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
|
{
|
|
8003598: b580 push {r7, lr}
|
|
800359a: b082 sub sp, #8
|
|
800359c: af00 add r7, sp, #0
|
|
800359e: 6078 str r0, [r7, #4]
|
|
80035a0: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
80035a2: 687b ldr r3, [r7, #4]
|
|
80035a4: 2241 movs r2, #65 ; 0x41
|
|
80035a6: 5c9b ldrb r3, [r3, r2]
|
|
80035a8: b2db uxtb r3, r3
|
|
80035aa: 2b20 cmp r3, #32
|
|
80035ac: d138 bne.n 8003620 <HAL_I2CEx_ConfigAnalogFilter+0x88>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
80035ae: 687b ldr r3, [r7, #4]
|
|
80035b0: 2240 movs r2, #64 ; 0x40
|
|
80035b2: 5c9b ldrb r3, [r3, r2]
|
|
80035b4: 2b01 cmp r3, #1
|
|
80035b6: d101 bne.n 80035bc <HAL_I2CEx_ConfigAnalogFilter+0x24>
|
|
80035b8: 2302 movs r3, #2
|
|
80035ba: e032 b.n 8003622 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
80035bc: 687b ldr r3, [r7, #4]
|
|
80035be: 2240 movs r2, #64 ; 0x40
|
|
80035c0: 2101 movs r1, #1
|
|
80035c2: 5499 strb r1, [r3, r2]
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
80035c4: 687b ldr r3, [r7, #4]
|
|
80035c6: 2241 movs r2, #65 ; 0x41
|
|
80035c8: 2124 movs r1, #36 ; 0x24
|
|
80035ca: 5499 strb r1, [r3, r2]
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
80035cc: 687b ldr r3, [r7, #4]
|
|
80035ce: 681b ldr r3, [r3, #0]
|
|
80035d0: 681a ldr r2, [r3, #0]
|
|
80035d2: 687b ldr r3, [r7, #4]
|
|
80035d4: 681b ldr r3, [r3, #0]
|
|
80035d6: 2101 movs r1, #1
|
|
80035d8: 438a bics r2, r1
|
|
80035da: 601a str r2, [r3, #0]
|
|
|
|
/* Reset I2Cx ANOFF bit */
|
|
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
|
80035dc: 687b ldr r3, [r7, #4]
|
|
80035de: 681b ldr r3, [r3, #0]
|
|
80035e0: 681a ldr r2, [r3, #0]
|
|
80035e2: 687b ldr r3, [r7, #4]
|
|
80035e4: 681b ldr r3, [r3, #0]
|
|
80035e6: 4911 ldr r1, [pc, #68] ; (800362c <HAL_I2CEx_ConfigAnalogFilter+0x94>)
|
|
80035e8: 400a ands r2, r1
|
|
80035ea: 601a str r2, [r3, #0]
|
|
|
|
/* Set analog filter bit*/
|
|
hi2c->Instance->CR1 |= AnalogFilter;
|
|
80035ec: 687b ldr r3, [r7, #4]
|
|
80035ee: 681b ldr r3, [r3, #0]
|
|
80035f0: 6819 ldr r1, [r3, #0]
|
|
80035f2: 687b ldr r3, [r7, #4]
|
|
80035f4: 681b ldr r3, [r3, #0]
|
|
80035f6: 683a ldr r2, [r7, #0]
|
|
80035f8: 430a orrs r2, r1
|
|
80035fa: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
80035fc: 687b ldr r3, [r7, #4]
|
|
80035fe: 681b ldr r3, [r3, #0]
|
|
8003600: 681a ldr r2, [r3, #0]
|
|
8003602: 687b ldr r3, [r7, #4]
|
|
8003604: 681b ldr r3, [r3, #0]
|
|
8003606: 2101 movs r1, #1
|
|
8003608: 430a orrs r2, r1
|
|
800360a: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800360c: 687b ldr r3, [r7, #4]
|
|
800360e: 2241 movs r2, #65 ; 0x41
|
|
8003610: 2120 movs r1, #32
|
|
8003612: 5499 strb r1, [r3, r2]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8003614: 687b ldr r3, [r7, #4]
|
|
8003616: 2240 movs r2, #64 ; 0x40
|
|
8003618: 2100 movs r1, #0
|
|
800361a: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_OK;
|
|
800361c: 2300 movs r3, #0
|
|
800361e: e000 b.n 8003622 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8003620: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8003622: 0018 movs r0, r3
|
|
8003624: 46bd mov sp, r7
|
|
8003626: b002 add sp, #8
|
|
8003628: bd80 pop {r7, pc}
|
|
800362a: 46c0 nop ; (mov r8, r8)
|
|
800362c: ffffefff .word 0xffffefff
|
|
|
|
08003630 <HAL_I2CEx_ConfigDigitalFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
|
{
|
|
8003630: b580 push {r7, lr}
|
|
8003632: b084 sub sp, #16
|
|
8003634: af00 add r7, sp, #0
|
|
8003636: 6078 str r0, [r7, #4]
|
|
8003638: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
800363a: 687b ldr r3, [r7, #4]
|
|
800363c: 2241 movs r2, #65 ; 0x41
|
|
800363e: 5c9b ldrb r3, [r3, r2]
|
|
8003640: b2db uxtb r3, r3
|
|
8003642: 2b20 cmp r3, #32
|
|
8003644: d139 bne.n 80036ba <HAL_I2CEx_ConfigDigitalFilter+0x8a>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8003646: 687b ldr r3, [r7, #4]
|
|
8003648: 2240 movs r2, #64 ; 0x40
|
|
800364a: 5c9b ldrb r3, [r3, r2]
|
|
800364c: 2b01 cmp r3, #1
|
|
800364e: d101 bne.n 8003654 <HAL_I2CEx_ConfigDigitalFilter+0x24>
|
|
8003650: 2302 movs r3, #2
|
|
8003652: e033 b.n 80036bc <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
8003654: 687b ldr r3, [r7, #4]
|
|
8003656: 2240 movs r2, #64 ; 0x40
|
|
8003658: 2101 movs r1, #1
|
|
800365a: 5499 strb r1, [r3, r2]
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
800365c: 687b ldr r3, [r7, #4]
|
|
800365e: 2241 movs r2, #65 ; 0x41
|
|
8003660: 2124 movs r1, #36 ; 0x24
|
|
8003662: 5499 strb r1, [r3, r2]
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8003664: 687b ldr r3, [r7, #4]
|
|
8003666: 681b ldr r3, [r3, #0]
|
|
8003668: 681a ldr r2, [r3, #0]
|
|
800366a: 687b ldr r3, [r7, #4]
|
|
800366c: 681b ldr r3, [r3, #0]
|
|
800366e: 2101 movs r1, #1
|
|
8003670: 438a bics r2, r1
|
|
8003672: 601a str r2, [r3, #0]
|
|
|
|
/* Get the old register value */
|
|
tmpreg = hi2c->Instance->CR1;
|
|
8003674: 687b ldr r3, [r7, #4]
|
|
8003676: 681b ldr r3, [r3, #0]
|
|
8003678: 681b ldr r3, [r3, #0]
|
|
800367a: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset I2Cx DNF bits [11:8] */
|
|
tmpreg &= ~(I2C_CR1_DNF);
|
|
800367c: 68fb ldr r3, [r7, #12]
|
|
800367e: 4a11 ldr r2, [pc, #68] ; (80036c4 <HAL_I2CEx_ConfigDigitalFilter+0x94>)
|
|
8003680: 4013 ands r3, r2
|
|
8003682: 60fb str r3, [r7, #12]
|
|
|
|
/* Set I2Cx DNF coefficient */
|
|
tmpreg |= DigitalFilter << 8U;
|
|
8003684: 683b ldr r3, [r7, #0]
|
|
8003686: 021b lsls r3, r3, #8
|
|
8003688: 68fa ldr r2, [r7, #12]
|
|
800368a: 4313 orrs r3, r2
|
|
800368c: 60fb str r3, [r7, #12]
|
|
|
|
/* Store the new register value */
|
|
hi2c->Instance->CR1 = tmpreg;
|
|
800368e: 687b ldr r3, [r7, #4]
|
|
8003690: 681b ldr r3, [r3, #0]
|
|
8003692: 68fa ldr r2, [r7, #12]
|
|
8003694: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8003696: 687b ldr r3, [r7, #4]
|
|
8003698: 681b ldr r3, [r3, #0]
|
|
800369a: 681a ldr r2, [r3, #0]
|
|
800369c: 687b ldr r3, [r7, #4]
|
|
800369e: 681b ldr r3, [r3, #0]
|
|
80036a0: 2101 movs r1, #1
|
|
80036a2: 430a orrs r2, r1
|
|
80036a4: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80036a6: 687b ldr r3, [r7, #4]
|
|
80036a8: 2241 movs r2, #65 ; 0x41
|
|
80036aa: 2120 movs r1, #32
|
|
80036ac: 5499 strb r1, [r3, r2]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80036ae: 687b ldr r3, [r7, #4]
|
|
80036b0: 2240 movs r2, #64 ; 0x40
|
|
80036b2: 2100 movs r1, #0
|
|
80036b4: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_OK;
|
|
80036b6: 2300 movs r3, #0
|
|
80036b8: e000 b.n 80036bc <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
80036ba: 2302 movs r3, #2
|
|
}
|
|
}
|
|
80036bc: 0018 movs r0, r3
|
|
80036be: 46bd mov sp, r7
|
|
80036c0: b004 add sp, #16
|
|
80036c2: bd80 pop {r7, pc}
|
|
80036c4: fffff0ff .word 0xfffff0ff
|
|
|
|
080036c8 <HAL_PWREx_ControlVoltageScaling>:
|
|
* cleared before returning the status. If the flag is not cleared within
|
|
* 6 microseconds, HAL_TIMEOUT status is reported.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
|
{
|
|
80036c8: b580 push {r7, lr}
|
|
80036ca: b084 sub sp, #16
|
|
80036cc: af00 add r7, sp, #0
|
|
80036ce: 6078 str r0, [r7, #4]
|
|
uint32_t wait_loop_index;
|
|
|
|
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
|
|
|
|
/* Modify voltage scaling range */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
|
|
80036d0: 4b19 ldr r3, [pc, #100] ; (8003738 <HAL_PWREx_ControlVoltageScaling+0x70>)
|
|
80036d2: 681b ldr r3, [r3, #0]
|
|
80036d4: 4a19 ldr r2, [pc, #100] ; (800373c <HAL_PWREx_ControlVoltageScaling+0x74>)
|
|
80036d6: 4013 ands r3, r2
|
|
80036d8: 0019 movs r1, r3
|
|
80036da: 4b17 ldr r3, [pc, #92] ; (8003738 <HAL_PWREx_ControlVoltageScaling+0x70>)
|
|
80036dc: 687a ldr r2, [r7, #4]
|
|
80036de: 430a orrs r2, r1
|
|
80036e0: 601a str r2, [r3, #0]
|
|
|
|
/* In case of Range 1 selected, we need to ensure that main regulator reaches new value */
|
|
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
80036e2: 687a ldr r2, [r7, #4]
|
|
80036e4: 2380 movs r3, #128 ; 0x80
|
|
80036e6: 009b lsls r3, r3, #2
|
|
80036e8: 429a cmp r2, r3
|
|
80036ea: d11f bne.n 800372c <HAL_PWREx_ControlVoltageScaling+0x64>
|
|
{
|
|
/* Set timeout value */
|
|
wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U;
|
|
80036ec: 4b14 ldr r3, [pc, #80] ; (8003740 <HAL_PWREx_ControlVoltageScaling+0x78>)
|
|
80036ee: 681a ldr r2, [r3, #0]
|
|
80036f0: 0013 movs r3, r2
|
|
80036f2: 005b lsls r3, r3, #1
|
|
80036f4: 189b adds r3, r3, r2
|
|
80036f6: 005b lsls r3, r3, #1
|
|
80036f8: 4912 ldr r1, [pc, #72] ; (8003744 <HAL_PWREx_ControlVoltageScaling+0x7c>)
|
|
80036fa: 0018 movs r0, r3
|
|
80036fc: f7fc fd04 bl 8000108 <__udivsi3>
|
|
8003700: 0003 movs r3, r0
|
|
8003702: 3301 adds r3, #1
|
|
8003704: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait until VOSF is reset */
|
|
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
8003706: e008 b.n 800371a <HAL_PWREx_ControlVoltageScaling+0x52>
|
|
{
|
|
if (wait_loop_index != 0U)
|
|
8003708: 68fb ldr r3, [r7, #12]
|
|
800370a: 2b00 cmp r3, #0
|
|
800370c: d003 beq.n 8003716 <HAL_PWREx_ControlVoltageScaling+0x4e>
|
|
{
|
|
wait_loop_index--;
|
|
800370e: 68fb ldr r3, [r7, #12]
|
|
8003710: 3b01 subs r3, #1
|
|
8003712: 60fb str r3, [r7, #12]
|
|
8003714: e001 b.n 800371a <HAL_PWREx_ControlVoltageScaling+0x52>
|
|
}
|
|
else
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003716: 2303 movs r3, #3
|
|
8003718: e009 b.n 800372e <HAL_PWREx_ControlVoltageScaling+0x66>
|
|
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
800371a: 4b07 ldr r3, [pc, #28] ; (8003738 <HAL_PWREx_ControlVoltageScaling+0x70>)
|
|
800371c: 695a ldr r2, [r3, #20]
|
|
800371e: 2380 movs r3, #128 ; 0x80
|
|
8003720: 00db lsls r3, r3, #3
|
|
8003722: 401a ands r2, r3
|
|
8003724: 2380 movs r3, #128 ; 0x80
|
|
8003726: 00db lsls r3, r3, #3
|
|
8003728: 429a cmp r2, r3
|
|
800372a: d0ed beq.n 8003708 <HAL_PWREx_ControlVoltageScaling+0x40>
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
800372c: 2300 movs r3, #0
|
|
}
|
|
800372e: 0018 movs r0, r3
|
|
8003730: 46bd mov sp, r7
|
|
8003732: b004 add sp, #16
|
|
8003734: bd80 pop {r7, pc}
|
|
8003736: 46c0 nop ; (mov r8, r8)
|
|
8003738: 40007000 .word 0x40007000
|
|
800373c: fffff9ff .word 0xfffff9ff
|
|
8003740: 20000004 .word 0x20000004
|
|
8003744: 000f4240 .word 0x000f4240
|
|
|
|
08003748 <HAL_RCC_OscConfig>:
|
|
* supported by this function. User should request a transition to LSE Off
|
|
* first and then to LSE On or LSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8003748: b580 push {r7, lr}
|
|
800374a: b088 sub sp, #32
|
|
800374c: af00 add r7, sp, #0
|
|
800374e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t temp_sysclksrc;
|
|
uint32_t temp_pllckcfg;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8003750: 687b ldr r3, [r7, #4]
|
|
8003752: 2b00 cmp r3, #0
|
|
8003754: d101 bne.n 800375a <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8003756: 2301 movs r3, #1
|
|
8003758: e2fe b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
800375a: 687b ldr r3, [r7, #4]
|
|
800375c: 681b ldr r3, [r3, #0]
|
|
800375e: 2201 movs r2, #1
|
|
8003760: 4013 ands r3, r2
|
|
8003762: d100 bne.n 8003766 <HAL_RCC_OscConfig+0x1e>
|
|
8003764: e07c b.n 8003860 <HAL_RCC_OscConfig+0x118>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8003766: 4bc3 ldr r3, [pc, #780] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003768: 689b ldr r3, [r3, #8]
|
|
800376a: 2238 movs r2, #56 ; 0x38
|
|
800376c: 4013 ands r3, r2
|
|
800376e: 61bb str r3, [r7, #24]
|
|
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8003770: 4bc0 ldr r3, [pc, #768] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003772: 68db ldr r3, [r3, #12]
|
|
8003774: 2203 movs r2, #3
|
|
8003776: 4013 ands r3, r2
|
|
8003778: 617b str r3, [r7, #20]
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE))
|
|
800377a: 69bb ldr r3, [r7, #24]
|
|
800377c: 2b10 cmp r3, #16
|
|
800377e: d102 bne.n 8003786 <HAL_RCC_OscConfig+0x3e>
|
|
8003780: 697b ldr r3, [r7, #20]
|
|
8003782: 2b03 cmp r3, #3
|
|
8003784: d002 beq.n 800378c <HAL_RCC_OscConfig+0x44>
|
|
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE))
|
|
8003786: 69bb ldr r3, [r7, #24]
|
|
8003788: 2b08 cmp r3, #8
|
|
800378a: d10b bne.n 80037a4 <HAL_RCC_OscConfig+0x5c>
|
|
{
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
800378c: 4bb9 ldr r3, [pc, #740] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
800378e: 681a ldr r2, [r3, #0]
|
|
8003790: 2380 movs r3, #128 ; 0x80
|
|
8003792: 029b lsls r3, r3, #10
|
|
8003794: 4013 ands r3, r2
|
|
8003796: d062 beq.n 800385e <HAL_RCC_OscConfig+0x116>
|
|
8003798: 687b ldr r3, [r7, #4]
|
|
800379a: 685b ldr r3, [r3, #4]
|
|
800379c: 2b00 cmp r3, #0
|
|
800379e: d15e bne.n 800385e <HAL_RCC_OscConfig+0x116>
|
|
{
|
|
return HAL_ERROR;
|
|
80037a0: 2301 movs r3, #1
|
|
80037a2: e2d9 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
80037a4: 687b ldr r3, [r7, #4]
|
|
80037a6: 685a ldr r2, [r3, #4]
|
|
80037a8: 2380 movs r3, #128 ; 0x80
|
|
80037aa: 025b lsls r3, r3, #9
|
|
80037ac: 429a cmp r2, r3
|
|
80037ae: d107 bne.n 80037c0 <HAL_RCC_OscConfig+0x78>
|
|
80037b0: 4bb0 ldr r3, [pc, #704] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80037b2: 681a ldr r2, [r3, #0]
|
|
80037b4: 4baf ldr r3, [pc, #700] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80037b6: 2180 movs r1, #128 ; 0x80
|
|
80037b8: 0249 lsls r1, r1, #9
|
|
80037ba: 430a orrs r2, r1
|
|
80037bc: 601a str r2, [r3, #0]
|
|
80037be: e020 b.n 8003802 <HAL_RCC_OscConfig+0xba>
|
|
80037c0: 687b ldr r3, [r7, #4]
|
|
80037c2: 685a ldr r2, [r3, #4]
|
|
80037c4: 23a0 movs r3, #160 ; 0xa0
|
|
80037c6: 02db lsls r3, r3, #11
|
|
80037c8: 429a cmp r2, r3
|
|
80037ca: d10e bne.n 80037ea <HAL_RCC_OscConfig+0xa2>
|
|
80037cc: 4ba9 ldr r3, [pc, #676] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80037ce: 681a ldr r2, [r3, #0]
|
|
80037d0: 4ba8 ldr r3, [pc, #672] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80037d2: 2180 movs r1, #128 ; 0x80
|
|
80037d4: 02c9 lsls r1, r1, #11
|
|
80037d6: 430a orrs r2, r1
|
|
80037d8: 601a str r2, [r3, #0]
|
|
80037da: 4ba6 ldr r3, [pc, #664] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80037dc: 681a ldr r2, [r3, #0]
|
|
80037de: 4ba5 ldr r3, [pc, #660] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80037e0: 2180 movs r1, #128 ; 0x80
|
|
80037e2: 0249 lsls r1, r1, #9
|
|
80037e4: 430a orrs r2, r1
|
|
80037e6: 601a str r2, [r3, #0]
|
|
80037e8: e00b b.n 8003802 <HAL_RCC_OscConfig+0xba>
|
|
80037ea: 4ba2 ldr r3, [pc, #648] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80037ec: 681a ldr r2, [r3, #0]
|
|
80037ee: 4ba1 ldr r3, [pc, #644] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80037f0: 49a1 ldr r1, [pc, #644] ; (8003a78 <HAL_RCC_OscConfig+0x330>)
|
|
80037f2: 400a ands r2, r1
|
|
80037f4: 601a str r2, [r3, #0]
|
|
80037f6: 4b9f ldr r3, [pc, #636] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80037f8: 681a ldr r2, [r3, #0]
|
|
80037fa: 4b9e ldr r3, [pc, #632] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80037fc: 499f ldr r1, [pc, #636] ; (8003a7c <HAL_RCC_OscConfig+0x334>)
|
|
80037fe: 400a ands r2, r1
|
|
8003800: 601a str r2, [r3, #0]
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8003802: 687b ldr r3, [r7, #4]
|
|
8003804: 685b ldr r3, [r3, #4]
|
|
8003806: 2b00 cmp r3, #0
|
|
8003808: d014 beq.n 8003834 <HAL_RCC_OscConfig+0xec>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800380a: f7fe faaf bl 8001d6c <HAL_GetTick>
|
|
800380e: 0003 movs r3, r0
|
|
8003810: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8003812: e008 b.n 8003826 <HAL_RCC_OscConfig+0xde>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8003814: f7fe faaa bl 8001d6c <HAL_GetTick>
|
|
8003818: 0002 movs r2, r0
|
|
800381a: 693b ldr r3, [r7, #16]
|
|
800381c: 1ad3 subs r3, r2, r3
|
|
800381e: 2b64 cmp r3, #100 ; 0x64
|
|
8003820: d901 bls.n 8003826 <HAL_RCC_OscConfig+0xde>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003822: 2303 movs r3, #3
|
|
8003824: e298 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8003826: 4b93 ldr r3, [pc, #588] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003828: 681a ldr r2, [r3, #0]
|
|
800382a: 2380 movs r3, #128 ; 0x80
|
|
800382c: 029b lsls r3, r3, #10
|
|
800382e: 4013 ands r3, r2
|
|
8003830: d0f0 beq.n 8003814 <HAL_RCC_OscConfig+0xcc>
|
|
8003832: e015 b.n 8003860 <HAL_RCC_OscConfig+0x118>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003834: f7fe fa9a bl 8001d6c <HAL_GetTick>
|
|
8003838: 0003 movs r3, r0
|
|
800383a: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
800383c: e008 b.n 8003850 <HAL_RCC_OscConfig+0x108>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
800383e: f7fe fa95 bl 8001d6c <HAL_GetTick>
|
|
8003842: 0002 movs r2, r0
|
|
8003844: 693b ldr r3, [r7, #16]
|
|
8003846: 1ad3 subs r3, r2, r3
|
|
8003848: 2b64 cmp r3, #100 ; 0x64
|
|
800384a: d901 bls.n 8003850 <HAL_RCC_OscConfig+0x108>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800384c: 2303 movs r3, #3
|
|
800384e: e283 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8003850: 4b88 ldr r3, [pc, #544] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003852: 681a ldr r2, [r3, #0]
|
|
8003854: 2380 movs r3, #128 ; 0x80
|
|
8003856: 029b lsls r3, r3, #10
|
|
8003858: 4013 ands r3, r2
|
|
800385a: d1f0 bne.n 800383e <HAL_RCC_OscConfig+0xf6>
|
|
800385c: e000 b.n 8003860 <HAL_RCC_OscConfig+0x118>
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
800385e: 46c0 nop ; (mov r8, r8)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8003860: 687b ldr r3, [r7, #4]
|
|
8003862: 681b ldr r3, [r3, #0]
|
|
8003864: 2202 movs r2, #2
|
|
8003866: 4013 ands r3, r2
|
|
8003868: d100 bne.n 800386c <HAL_RCC_OscConfig+0x124>
|
|
800386a: e099 b.n 80039a0 <HAL_RCC_OscConfig+0x258>
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv));
|
|
|
|
/* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */
|
|
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
800386c: 4b81 ldr r3, [pc, #516] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
800386e: 689b ldr r3, [r3, #8]
|
|
8003870: 2238 movs r2, #56 ; 0x38
|
|
8003872: 4013 ands r3, r2
|
|
8003874: 61bb str r3, [r7, #24]
|
|
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8003876: 4b7f ldr r3, [pc, #508] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003878: 68db ldr r3, [r3, #12]
|
|
800387a: 2203 movs r2, #3
|
|
800387c: 4013 ands r3, r2
|
|
800387e: 617b str r3, [r7, #20]
|
|
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI))
|
|
8003880: 69bb ldr r3, [r7, #24]
|
|
8003882: 2b10 cmp r3, #16
|
|
8003884: d102 bne.n 800388c <HAL_RCC_OscConfig+0x144>
|
|
8003886: 697b ldr r3, [r7, #20]
|
|
8003888: 2b02 cmp r3, #2
|
|
800388a: d002 beq.n 8003892 <HAL_RCC_OscConfig+0x14a>
|
|
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI))
|
|
800388c: 69bb ldr r3, [r7, #24]
|
|
800388e: 2b00 cmp r3, #0
|
|
8003890: d135 bne.n 80038fe <HAL_RCC_OscConfig+0x1b6>
|
|
{
|
|
/* When HSI is used as system clock or as PLL input clock it can not be disabled */
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8003892: 4b78 ldr r3, [pc, #480] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003894: 681a ldr r2, [r3, #0]
|
|
8003896: 2380 movs r3, #128 ; 0x80
|
|
8003898: 00db lsls r3, r3, #3
|
|
800389a: 4013 ands r3, r2
|
|
800389c: d005 beq.n 80038aa <HAL_RCC_OscConfig+0x162>
|
|
800389e: 687b ldr r3, [r7, #4]
|
|
80038a0: 68db ldr r3, [r3, #12]
|
|
80038a2: 2b00 cmp r3, #0
|
|
80038a4: d101 bne.n 80038aa <HAL_RCC_OscConfig+0x162>
|
|
{
|
|
return HAL_ERROR;
|
|
80038a6: 2301 movs r3, #1
|
|
80038a8: e256 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
80038aa: 4b72 ldr r3, [pc, #456] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80038ac: 685b ldr r3, [r3, #4]
|
|
80038ae: 4a74 ldr r2, [pc, #464] ; (8003a80 <HAL_RCC_OscConfig+0x338>)
|
|
80038b0: 4013 ands r3, r2
|
|
80038b2: 0019 movs r1, r3
|
|
80038b4: 687b ldr r3, [r7, #4]
|
|
80038b6: 695b ldr r3, [r3, #20]
|
|
80038b8: 021a lsls r2, r3, #8
|
|
80038ba: 4b6e ldr r3, [pc, #440] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80038bc: 430a orrs r2, r1
|
|
80038be: 605a str r2, [r3, #4]
|
|
|
|
if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
80038c0: 69bb ldr r3, [r7, #24]
|
|
80038c2: 2b00 cmp r3, #0
|
|
80038c4: d112 bne.n 80038ec <HAL_RCC_OscConfig+0x1a4>
|
|
{
|
|
/* Adjust the HSI16 division factor */
|
|
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
|
|
80038c6: 4b6b ldr r3, [pc, #428] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80038c8: 681b ldr r3, [r3, #0]
|
|
80038ca: 4a6e ldr r2, [pc, #440] ; (8003a84 <HAL_RCC_OscConfig+0x33c>)
|
|
80038cc: 4013 ands r3, r2
|
|
80038ce: 0019 movs r1, r3
|
|
80038d0: 687b ldr r3, [r7, #4]
|
|
80038d2: 691a ldr r2, [r3, #16]
|
|
80038d4: 4b67 ldr r3, [pc, #412] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80038d6: 430a orrs r2, r1
|
|
80038d8: 601a str r2, [r3, #0]
|
|
|
|
/* Update the SystemCoreClock global variable with HSISYS value */
|
|
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
|
|
80038da: 4b66 ldr r3, [pc, #408] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80038dc: 681b ldr r3, [r3, #0]
|
|
80038de: 0adb lsrs r3, r3, #11
|
|
80038e0: 2207 movs r2, #7
|
|
80038e2: 4013 ands r3, r2
|
|
80038e4: 4a68 ldr r2, [pc, #416] ; (8003a88 <HAL_RCC_OscConfig+0x340>)
|
|
80038e6: 40da lsrs r2, r3
|
|
80038e8: 4b68 ldr r3, [pc, #416] ; (8003a8c <HAL_RCC_OscConfig+0x344>)
|
|
80038ea: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Adapt Systick interrupt period */
|
|
if (HAL_InitTick(uwTickPrio) != HAL_OK)
|
|
80038ec: 4b68 ldr r3, [pc, #416] ; (8003a90 <HAL_RCC_OscConfig+0x348>)
|
|
80038ee: 681b ldr r3, [r3, #0]
|
|
80038f0: 0018 movs r0, r3
|
|
80038f2: f7fe f9df bl 8001cb4 <HAL_InitTick>
|
|
80038f6: 1e03 subs r3, r0, #0
|
|
80038f8: d051 beq.n 800399e <HAL_RCC_OscConfig+0x256>
|
|
{
|
|
return HAL_ERROR;
|
|
80038fa: 2301 movs r3, #1
|
|
80038fc: e22c b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
80038fe: 687b ldr r3, [r7, #4]
|
|
8003900: 68db ldr r3, [r3, #12]
|
|
8003902: 2b00 cmp r3, #0
|
|
8003904: d030 beq.n 8003968 <HAL_RCC_OscConfig+0x220>
|
|
{
|
|
/* Configure the HSI16 division factor */
|
|
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
|
|
8003906: 4b5b ldr r3, [pc, #364] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003908: 681b ldr r3, [r3, #0]
|
|
800390a: 4a5e ldr r2, [pc, #376] ; (8003a84 <HAL_RCC_OscConfig+0x33c>)
|
|
800390c: 4013 ands r3, r2
|
|
800390e: 0019 movs r1, r3
|
|
8003910: 687b ldr r3, [r7, #4]
|
|
8003912: 691a ldr r2, [r3, #16]
|
|
8003914: 4b57 ldr r3, [pc, #348] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003916: 430a orrs r2, r1
|
|
8003918: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the Internal High Speed oscillator (HSI16). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
800391a: 4b56 ldr r3, [pc, #344] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
800391c: 681a ldr r2, [r3, #0]
|
|
800391e: 4b55 ldr r3, [pc, #340] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003920: 2180 movs r1, #128 ; 0x80
|
|
8003922: 0049 lsls r1, r1, #1
|
|
8003924: 430a orrs r2, r1
|
|
8003926: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003928: f7fe fa20 bl 8001d6c <HAL_GetTick>
|
|
800392c: 0003 movs r3, r0
|
|
800392e: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8003930: e008 b.n 8003944 <HAL_RCC_OscConfig+0x1fc>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8003932: f7fe fa1b bl 8001d6c <HAL_GetTick>
|
|
8003936: 0002 movs r2, r0
|
|
8003938: 693b ldr r3, [r7, #16]
|
|
800393a: 1ad3 subs r3, r2, r3
|
|
800393c: 2b02 cmp r3, #2
|
|
800393e: d901 bls.n 8003944 <HAL_RCC_OscConfig+0x1fc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003940: 2303 movs r3, #3
|
|
8003942: e209 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8003944: 4b4b ldr r3, [pc, #300] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003946: 681a ldr r2, [r3, #0]
|
|
8003948: 2380 movs r3, #128 ; 0x80
|
|
800394a: 00db lsls r3, r3, #3
|
|
800394c: 4013 ands r3, r2
|
|
800394e: d0f0 beq.n 8003932 <HAL_RCC_OscConfig+0x1ea>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8003950: 4b48 ldr r3, [pc, #288] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003952: 685b ldr r3, [r3, #4]
|
|
8003954: 4a4a ldr r2, [pc, #296] ; (8003a80 <HAL_RCC_OscConfig+0x338>)
|
|
8003956: 4013 ands r3, r2
|
|
8003958: 0019 movs r1, r3
|
|
800395a: 687b ldr r3, [r7, #4]
|
|
800395c: 695b ldr r3, [r3, #20]
|
|
800395e: 021a lsls r2, r3, #8
|
|
8003960: 4b44 ldr r3, [pc, #272] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003962: 430a orrs r2, r1
|
|
8003964: 605a str r2, [r3, #4]
|
|
8003966: e01b b.n 80039a0 <HAL_RCC_OscConfig+0x258>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI16). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8003968: 4b42 ldr r3, [pc, #264] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
800396a: 681a ldr r2, [r3, #0]
|
|
800396c: 4b41 ldr r3, [pc, #260] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
800396e: 4949 ldr r1, [pc, #292] ; (8003a94 <HAL_RCC_OscConfig+0x34c>)
|
|
8003970: 400a ands r2, r1
|
|
8003972: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003974: f7fe f9fa bl 8001d6c <HAL_GetTick>
|
|
8003978: 0003 movs r3, r0
|
|
800397a: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
800397c: e008 b.n 8003990 <HAL_RCC_OscConfig+0x248>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
800397e: f7fe f9f5 bl 8001d6c <HAL_GetTick>
|
|
8003982: 0002 movs r2, r0
|
|
8003984: 693b ldr r3, [r7, #16]
|
|
8003986: 1ad3 subs r3, r2, r3
|
|
8003988: 2b02 cmp r3, #2
|
|
800398a: d901 bls.n 8003990 <HAL_RCC_OscConfig+0x248>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800398c: 2303 movs r3, #3
|
|
800398e: e1e3 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8003990: 4b38 ldr r3, [pc, #224] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003992: 681a ldr r2, [r3, #0]
|
|
8003994: 2380 movs r3, #128 ; 0x80
|
|
8003996: 00db lsls r3, r3, #3
|
|
8003998: 4013 ands r3, r2
|
|
800399a: d1f0 bne.n 800397e <HAL_RCC_OscConfig+0x236>
|
|
800399c: e000 b.n 80039a0 <HAL_RCC_OscConfig+0x258>
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
800399e: 46c0 nop ; (mov r8, r8)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
80039a0: 687b ldr r3, [r7, #4]
|
|
80039a2: 681b ldr r3, [r3, #0]
|
|
80039a4: 2208 movs r2, #8
|
|
80039a6: 4013 ands r3, r2
|
|
80039a8: d047 beq.n 8003a3a <HAL_RCC_OscConfig+0x2f2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check if LSI is used as system clock */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
|
|
80039aa: 4b32 ldr r3, [pc, #200] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80039ac: 689b ldr r3, [r3, #8]
|
|
80039ae: 2238 movs r2, #56 ; 0x38
|
|
80039b0: 4013 ands r3, r2
|
|
80039b2: 2b18 cmp r3, #24
|
|
80039b4: d10a bne.n 80039cc <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
/* When LSI is used as system clock it will not be disabled */
|
|
if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF))
|
|
80039b6: 4b2f ldr r3, [pc, #188] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80039b8: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
80039ba: 2202 movs r2, #2
|
|
80039bc: 4013 ands r3, r2
|
|
80039be: d03c beq.n 8003a3a <HAL_RCC_OscConfig+0x2f2>
|
|
80039c0: 687b ldr r3, [r7, #4]
|
|
80039c2: 699b ldr r3, [r3, #24]
|
|
80039c4: 2b00 cmp r3, #0
|
|
80039c6: d138 bne.n 8003a3a <HAL_RCC_OscConfig+0x2f2>
|
|
{
|
|
return HAL_ERROR;
|
|
80039c8: 2301 movs r3, #1
|
|
80039ca: e1c5 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the LSI State */
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
80039cc: 687b ldr r3, [r7, #4]
|
|
80039ce: 699b ldr r3, [r3, #24]
|
|
80039d0: 2b00 cmp r3, #0
|
|
80039d2: d019 beq.n 8003a08 <HAL_RCC_OscConfig+0x2c0>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
80039d4: 4b27 ldr r3, [pc, #156] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80039d6: 6e1a ldr r2, [r3, #96] ; 0x60
|
|
80039d8: 4b26 ldr r3, [pc, #152] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80039da: 2101 movs r1, #1
|
|
80039dc: 430a orrs r2, r1
|
|
80039de: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80039e0: f7fe f9c4 bl 8001d6c <HAL_GetTick>
|
|
80039e4: 0003 movs r3, r0
|
|
80039e6: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
80039e8: e008 b.n 80039fc <HAL_RCC_OscConfig+0x2b4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
80039ea: f7fe f9bf bl 8001d6c <HAL_GetTick>
|
|
80039ee: 0002 movs r2, r0
|
|
80039f0: 693b ldr r3, [r7, #16]
|
|
80039f2: 1ad3 subs r3, r2, r3
|
|
80039f4: 2b02 cmp r3, #2
|
|
80039f6: d901 bls.n 80039fc <HAL_RCC_OscConfig+0x2b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80039f8: 2303 movs r3, #3
|
|
80039fa: e1ad b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
80039fc: 4b1d ldr r3, [pc, #116] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
80039fe: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
8003a00: 2202 movs r2, #2
|
|
8003a02: 4013 ands r3, r2
|
|
8003a04: d0f1 beq.n 80039ea <HAL_RCC_OscConfig+0x2a2>
|
|
8003a06: e018 b.n 8003a3a <HAL_RCC_OscConfig+0x2f2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8003a08: 4b1a ldr r3, [pc, #104] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003a0a: 6e1a ldr r2, [r3, #96] ; 0x60
|
|
8003a0c: 4b19 ldr r3, [pc, #100] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003a0e: 2101 movs r1, #1
|
|
8003a10: 438a bics r2, r1
|
|
8003a12: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003a14: f7fe f9aa bl 8001d6c <HAL_GetTick>
|
|
8003a18: 0003 movs r3, r0
|
|
8003a1a: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8003a1c: e008 b.n 8003a30 <HAL_RCC_OscConfig+0x2e8>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8003a1e: f7fe f9a5 bl 8001d6c <HAL_GetTick>
|
|
8003a22: 0002 movs r2, r0
|
|
8003a24: 693b ldr r3, [r7, #16]
|
|
8003a26: 1ad3 subs r3, r2, r3
|
|
8003a28: 2b02 cmp r3, #2
|
|
8003a2a: d901 bls.n 8003a30 <HAL_RCC_OscConfig+0x2e8>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003a2c: 2303 movs r3, #3
|
|
8003a2e: e193 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8003a30: 4b10 ldr r3, [pc, #64] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003a32: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
8003a34: 2202 movs r2, #2
|
|
8003a36: 4013 ands r3, r2
|
|
8003a38: d1f1 bne.n 8003a1e <HAL_RCC_OscConfig+0x2d6>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8003a3a: 687b ldr r3, [r7, #4]
|
|
8003a3c: 681b ldr r3, [r3, #0]
|
|
8003a3e: 2204 movs r2, #4
|
|
8003a40: 4013 ands r3, r2
|
|
8003a42: d100 bne.n 8003a46 <HAL_RCC_OscConfig+0x2fe>
|
|
8003a44: e0c6 b.n 8003bd4 <HAL_RCC_OscConfig+0x48c>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8003a46: 231f movs r3, #31
|
|
8003a48: 18fb adds r3, r7, r3
|
|
8003a4a: 2200 movs r2, #0
|
|
8003a4c: 701a strb r2, [r3, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* When the LSE is used as system clock, it is not allowed disable it */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
|
|
8003a4e: 4b09 ldr r3, [pc, #36] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003a50: 689b ldr r3, [r3, #8]
|
|
8003a52: 2238 movs r2, #56 ; 0x38
|
|
8003a54: 4013 ands r3, r2
|
|
8003a56: 2b20 cmp r3, #32
|
|
8003a58: d11e bne.n 8003a98 <HAL_RCC_OscConfig+0x350>
|
|
{
|
|
if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF))
|
|
8003a5a: 4b06 ldr r3, [pc, #24] ; (8003a74 <HAL_RCC_OscConfig+0x32c>)
|
|
8003a5c: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
8003a5e: 2202 movs r2, #2
|
|
8003a60: 4013 ands r3, r2
|
|
8003a62: d100 bne.n 8003a66 <HAL_RCC_OscConfig+0x31e>
|
|
8003a64: e0b6 b.n 8003bd4 <HAL_RCC_OscConfig+0x48c>
|
|
8003a66: 687b ldr r3, [r7, #4]
|
|
8003a68: 689b ldr r3, [r3, #8]
|
|
8003a6a: 2b00 cmp r3, #0
|
|
8003a6c: d000 beq.n 8003a70 <HAL_RCC_OscConfig+0x328>
|
|
8003a6e: e0b1 b.n 8003bd4 <HAL_RCC_OscConfig+0x48c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003a70: 2301 movs r3, #1
|
|
8003a72: e171 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
8003a74: 40021000 .word 0x40021000
|
|
8003a78: fffeffff .word 0xfffeffff
|
|
8003a7c: fffbffff .word 0xfffbffff
|
|
8003a80: ffff80ff .word 0xffff80ff
|
|
8003a84: ffffc7ff .word 0xffffc7ff
|
|
8003a88: 00f42400 .word 0x00f42400
|
|
8003a8c: 20000004 .word 0x20000004
|
|
8003a90: 20000008 .word 0x20000008
|
|
8003a94: fffffeff .word 0xfffffeff
|
|
}
|
|
else
|
|
{
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
|
|
8003a98: 4bb1 ldr r3, [pc, #708] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003a9a: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
8003a9c: 2380 movs r3, #128 ; 0x80
|
|
8003a9e: 055b lsls r3, r3, #21
|
|
8003aa0: 4013 ands r3, r2
|
|
8003aa2: d101 bne.n 8003aa8 <HAL_RCC_OscConfig+0x360>
|
|
8003aa4: 2301 movs r3, #1
|
|
8003aa6: e000 b.n 8003aaa <HAL_RCC_OscConfig+0x362>
|
|
8003aa8: 2300 movs r3, #0
|
|
8003aaa: 2b00 cmp r3, #0
|
|
8003aac: d011 beq.n 8003ad2 <HAL_RCC_OscConfig+0x38a>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8003aae: 4bac ldr r3, [pc, #688] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003ab0: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
8003ab2: 4bab ldr r3, [pc, #684] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003ab4: 2180 movs r1, #128 ; 0x80
|
|
8003ab6: 0549 lsls r1, r1, #21
|
|
8003ab8: 430a orrs r2, r1
|
|
8003aba: 63da str r2, [r3, #60] ; 0x3c
|
|
8003abc: 4ba8 ldr r3, [pc, #672] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003abe: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
8003ac0: 2380 movs r3, #128 ; 0x80
|
|
8003ac2: 055b lsls r3, r3, #21
|
|
8003ac4: 4013 ands r3, r2
|
|
8003ac6: 60fb str r3, [r7, #12]
|
|
8003ac8: 68fb ldr r3, [r7, #12]
|
|
pwrclkchanged = SET;
|
|
8003aca: 231f movs r3, #31
|
|
8003acc: 18fb adds r3, r7, r3
|
|
8003ace: 2201 movs r2, #1
|
|
8003ad0: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8003ad2: 4ba4 ldr r3, [pc, #656] ; (8003d64 <HAL_RCC_OscConfig+0x61c>)
|
|
8003ad4: 681a ldr r2, [r3, #0]
|
|
8003ad6: 2380 movs r3, #128 ; 0x80
|
|
8003ad8: 005b lsls r3, r3, #1
|
|
8003ada: 4013 ands r3, r2
|
|
8003adc: d11a bne.n 8003b14 <HAL_RCC_OscConfig+0x3cc>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8003ade: 4ba1 ldr r3, [pc, #644] ; (8003d64 <HAL_RCC_OscConfig+0x61c>)
|
|
8003ae0: 681a ldr r2, [r3, #0]
|
|
8003ae2: 4ba0 ldr r3, [pc, #640] ; (8003d64 <HAL_RCC_OscConfig+0x61c>)
|
|
8003ae4: 2180 movs r1, #128 ; 0x80
|
|
8003ae6: 0049 lsls r1, r1, #1
|
|
8003ae8: 430a orrs r2, r1
|
|
8003aea: 601a str r2, [r3, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8003aec: f7fe f93e bl 8001d6c <HAL_GetTick>
|
|
8003af0: 0003 movs r3, r0
|
|
8003af2: 613b str r3, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8003af4: e008 b.n 8003b08 <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8003af6: f7fe f939 bl 8001d6c <HAL_GetTick>
|
|
8003afa: 0002 movs r2, r0
|
|
8003afc: 693b ldr r3, [r7, #16]
|
|
8003afe: 1ad3 subs r3, r2, r3
|
|
8003b00: 2b02 cmp r3, #2
|
|
8003b02: d901 bls.n 8003b08 <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003b04: 2303 movs r3, #3
|
|
8003b06: e127 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8003b08: 4b96 ldr r3, [pc, #600] ; (8003d64 <HAL_RCC_OscConfig+0x61c>)
|
|
8003b0a: 681a ldr r2, [r3, #0]
|
|
8003b0c: 2380 movs r3, #128 ; 0x80
|
|
8003b0e: 005b lsls r3, r3, #1
|
|
8003b10: 4013 ands r3, r2
|
|
8003b12: d0f0 beq.n 8003af6 <HAL_RCC_OscConfig+0x3ae>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8003b14: 687b ldr r3, [r7, #4]
|
|
8003b16: 689b ldr r3, [r3, #8]
|
|
8003b18: 2b01 cmp r3, #1
|
|
8003b1a: d106 bne.n 8003b2a <HAL_RCC_OscConfig+0x3e2>
|
|
8003b1c: 4b90 ldr r3, [pc, #576] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003b1e: 6dda ldr r2, [r3, #92] ; 0x5c
|
|
8003b20: 4b8f ldr r3, [pc, #572] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003b22: 2101 movs r1, #1
|
|
8003b24: 430a orrs r2, r1
|
|
8003b26: 65da str r2, [r3, #92] ; 0x5c
|
|
8003b28: e01c b.n 8003b64 <HAL_RCC_OscConfig+0x41c>
|
|
8003b2a: 687b ldr r3, [r7, #4]
|
|
8003b2c: 689b ldr r3, [r3, #8]
|
|
8003b2e: 2b05 cmp r3, #5
|
|
8003b30: d10c bne.n 8003b4c <HAL_RCC_OscConfig+0x404>
|
|
8003b32: 4b8b ldr r3, [pc, #556] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003b34: 6dda ldr r2, [r3, #92] ; 0x5c
|
|
8003b36: 4b8a ldr r3, [pc, #552] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003b38: 2104 movs r1, #4
|
|
8003b3a: 430a orrs r2, r1
|
|
8003b3c: 65da str r2, [r3, #92] ; 0x5c
|
|
8003b3e: 4b88 ldr r3, [pc, #544] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003b40: 6dda ldr r2, [r3, #92] ; 0x5c
|
|
8003b42: 4b87 ldr r3, [pc, #540] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003b44: 2101 movs r1, #1
|
|
8003b46: 430a orrs r2, r1
|
|
8003b48: 65da str r2, [r3, #92] ; 0x5c
|
|
8003b4a: e00b b.n 8003b64 <HAL_RCC_OscConfig+0x41c>
|
|
8003b4c: 4b84 ldr r3, [pc, #528] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003b4e: 6dda ldr r2, [r3, #92] ; 0x5c
|
|
8003b50: 4b83 ldr r3, [pc, #524] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003b52: 2101 movs r1, #1
|
|
8003b54: 438a bics r2, r1
|
|
8003b56: 65da str r2, [r3, #92] ; 0x5c
|
|
8003b58: 4b81 ldr r3, [pc, #516] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003b5a: 6dda ldr r2, [r3, #92] ; 0x5c
|
|
8003b5c: 4b80 ldr r3, [pc, #512] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003b5e: 2104 movs r1, #4
|
|
8003b60: 438a bics r2, r1
|
|
8003b62: 65da str r2, [r3, #92] ; 0x5c
|
|
|
|
/* Check the LSE State */
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8003b64: 687b ldr r3, [r7, #4]
|
|
8003b66: 689b ldr r3, [r3, #8]
|
|
8003b68: 2b00 cmp r3, #0
|
|
8003b6a: d014 beq.n 8003b96 <HAL_RCC_OscConfig+0x44e>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003b6c: f7fe f8fe bl 8001d6c <HAL_GetTick>
|
|
8003b70: 0003 movs r3, r0
|
|
8003b72: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8003b74: e009 b.n 8003b8a <HAL_RCC_OscConfig+0x442>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003b76: f7fe f8f9 bl 8001d6c <HAL_GetTick>
|
|
8003b7a: 0002 movs r2, r0
|
|
8003b7c: 693b ldr r3, [r7, #16]
|
|
8003b7e: 1ad3 subs r3, r2, r3
|
|
8003b80: 4a79 ldr r2, [pc, #484] ; (8003d68 <HAL_RCC_OscConfig+0x620>)
|
|
8003b82: 4293 cmp r3, r2
|
|
8003b84: d901 bls.n 8003b8a <HAL_RCC_OscConfig+0x442>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003b86: 2303 movs r3, #3
|
|
8003b88: e0e6 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8003b8a: 4b75 ldr r3, [pc, #468] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003b8c: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
8003b8e: 2202 movs r2, #2
|
|
8003b90: 4013 ands r3, r2
|
|
8003b92: d0f0 beq.n 8003b76 <HAL_RCC_OscConfig+0x42e>
|
|
8003b94: e013 b.n 8003bbe <HAL_RCC_OscConfig+0x476>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003b96: f7fe f8e9 bl 8001d6c <HAL_GetTick>
|
|
8003b9a: 0003 movs r3, r0
|
|
8003b9c: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8003b9e: e009 b.n 8003bb4 <HAL_RCC_OscConfig+0x46c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003ba0: f7fe f8e4 bl 8001d6c <HAL_GetTick>
|
|
8003ba4: 0002 movs r2, r0
|
|
8003ba6: 693b ldr r3, [r7, #16]
|
|
8003ba8: 1ad3 subs r3, r2, r3
|
|
8003baa: 4a6f ldr r2, [pc, #444] ; (8003d68 <HAL_RCC_OscConfig+0x620>)
|
|
8003bac: 4293 cmp r3, r2
|
|
8003bae: d901 bls.n 8003bb4 <HAL_RCC_OscConfig+0x46c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003bb0: 2303 movs r3, #3
|
|
8003bb2: e0d1 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8003bb4: 4b6a ldr r3, [pc, #424] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003bb6: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
8003bb8: 2202 movs r2, #2
|
|
8003bba: 4013 ands r3, r2
|
|
8003bbc: d1f0 bne.n 8003ba0 <HAL_RCC_OscConfig+0x458>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
8003bbe: 231f movs r3, #31
|
|
8003bc0: 18fb adds r3, r7, r3
|
|
8003bc2: 781b ldrb r3, [r3, #0]
|
|
8003bc4: 2b01 cmp r3, #1
|
|
8003bc6: d105 bne.n 8003bd4 <HAL_RCC_OscConfig+0x48c>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8003bc8: 4b65 ldr r3, [pc, #404] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003bca: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
8003bcc: 4b64 ldr r3, [pc, #400] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003bce: 4967 ldr r1, [pc, #412] ; (8003d6c <HAL_RCC_OscConfig+0x624>)
|
|
8003bd0: 400a ands r2, r1
|
|
8003bd2: 63da str r2, [r3, #60] ; 0x3c
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
8003bd4: 687b ldr r3, [r7, #4]
|
|
8003bd6: 69db ldr r3, [r3, #28]
|
|
8003bd8: 2b00 cmp r3, #0
|
|
8003bda: d100 bne.n 8003bde <HAL_RCC_OscConfig+0x496>
|
|
8003bdc: e0bb b.n 8003d56 <HAL_RCC_OscConfig+0x60e>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
8003bde: 4b60 ldr r3, [pc, #384] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003be0: 689b ldr r3, [r3, #8]
|
|
8003be2: 2238 movs r2, #56 ; 0x38
|
|
8003be4: 4013 ands r3, r2
|
|
8003be6: 2b10 cmp r3, #16
|
|
8003be8: d100 bne.n 8003bec <HAL_RCC_OscConfig+0x4a4>
|
|
8003bea: e07b b.n 8003ce4 <HAL_RCC_OscConfig+0x59c>
|
|
{
|
|
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
8003bec: 687b ldr r3, [r7, #4]
|
|
8003bee: 69db ldr r3, [r3, #28]
|
|
8003bf0: 2b02 cmp r3, #2
|
|
8003bf2: d156 bne.n 8003ca2 <HAL_RCC_OscConfig+0x55a>
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
#endif /* RCC_PLLQ_SUPPORT */
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8003bf4: 4b5a ldr r3, [pc, #360] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003bf6: 681a ldr r2, [r3, #0]
|
|
8003bf8: 4b59 ldr r3, [pc, #356] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003bfa: 495d ldr r1, [pc, #372] ; (8003d70 <HAL_RCC_OscConfig+0x628>)
|
|
8003bfc: 400a ands r2, r1
|
|
8003bfe: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003c00: f7fe f8b4 bl 8001d6c <HAL_GetTick>
|
|
8003c04: 0003 movs r3, r0
|
|
8003c06: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003c08: e008 b.n 8003c1c <HAL_RCC_OscConfig+0x4d4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003c0a: f7fe f8af bl 8001d6c <HAL_GetTick>
|
|
8003c0e: 0002 movs r2, r0
|
|
8003c10: 693b ldr r3, [r7, #16]
|
|
8003c12: 1ad3 subs r3, r2, r3
|
|
8003c14: 2b02 cmp r3, #2
|
|
8003c16: d901 bls.n 8003c1c <HAL_RCC_OscConfig+0x4d4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003c18: 2303 movs r3, #3
|
|
8003c1a: e09d b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003c1c: 4b50 ldr r3, [pc, #320] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003c1e: 681a ldr r2, [r3, #0]
|
|
8003c20: 2380 movs r3, #128 ; 0x80
|
|
8003c22: 049b lsls r3, r3, #18
|
|
8003c24: 4013 ands r3, r2
|
|
8003c26: d1f0 bne.n 8003c0a <HAL_RCC_OscConfig+0x4c2>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
#if defined(RCC_PLLQ_SUPPORT)
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
8003c28: 4b4d ldr r3, [pc, #308] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003c2a: 68db ldr r3, [r3, #12]
|
|
8003c2c: 4a51 ldr r2, [pc, #324] ; (8003d74 <HAL_RCC_OscConfig+0x62c>)
|
|
8003c2e: 4013 ands r3, r2
|
|
8003c30: 0019 movs r1, r3
|
|
8003c32: 687b ldr r3, [r7, #4]
|
|
8003c34: 6a1a ldr r2, [r3, #32]
|
|
8003c36: 687b ldr r3, [r7, #4]
|
|
8003c38: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8003c3a: 431a orrs r2, r3
|
|
8003c3c: 687b ldr r3, [r7, #4]
|
|
8003c3e: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
8003c40: 021b lsls r3, r3, #8
|
|
8003c42: 431a orrs r2, r3
|
|
8003c44: 687b ldr r3, [r7, #4]
|
|
8003c46: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8003c48: 431a orrs r2, r3
|
|
8003c4a: 687b ldr r3, [r7, #4]
|
|
8003c4c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003c4e: 431a orrs r2, r3
|
|
8003c50: 687b ldr r3, [r7, #4]
|
|
8003c52: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8003c54: 431a orrs r2, r3
|
|
8003c56: 4b42 ldr r3, [pc, #264] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003c58: 430a orrs r2, r1
|
|
8003c5a: 60da str r2, [r3, #12]
|
|
RCC_OscInitStruct->PLL.PLLP,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
#endif /* RCC_PLLQ_SUPPORT */
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8003c5c: 4b40 ldr r3, [pc, #256] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003c5e: 681a ldr r2, [r3, #0]
|
|
8003c60: 4b3f ldr r3, [pc, #252] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003c62: 2180 movs r1, #128 ; 0x80
|
|
8003c64: 0449 lsls r1, r1, #17
|
|
8003c66: 430a orrs r2, r1
|
|
8003c68: 601a str r2, [r3, #0]
|
|
|
|
/* Enable PLLR Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK);
|
|
8003c6a: 4b3d ldr r3, [pc, #244] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003c6c: 68da ldr r2, [r3, #12]
|
|
8003c6e: 4b3c ldr r3, [pc, #240] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003c70: 2180 movs r1, #128 ; 0x80
|
|
8003c72: 0549 lsls r1, r1, #21
|
|
8003c74: 430a orrs r2, r1
|
|
8003c76: 60da str r2, [r3, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003c78: f7fe f878 bl 8001d6c <HAL_GetTick>
|
|
8003c7c: 0003 movs r3, r0
|
|
8003c7e: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003c80: e008 b.n 8003c94 <HAL_RCC_OscConfig+0x54c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003c82: f7fe f873 bl 8001d6c <HAL_GetTick>
|
|
8003c86: 0002 movs r2, r0
|
|
8003c88: 693b ldr r3, [r7, #16]
|
|
8003c8a: 1ad3 subs r3, r2, r3
|
|
8003c8c: 2b02 cmp r3, #2
|
|
8003c8e: d901 bls.n 8003c94 <HAL_RCC_OscConfig+0x54c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003c90: 2303 movs r3, #3
|
|
8003c92: e061 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003c94: 4b32 ldr r3, [pc, #200] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003c96: 681a ldr r2, [r3, #0]
|
|
8003c98: 2380 movs r3, #128 ; 0x80
|
|
8003c9a: 049b lsls r3, r3, #18
|
|
8003c9c: 4013 ands r3, r2
|
|
8003c9e: d0f0 beq.n 8003c82 <HAL_RCC_OscConfig+0x53a>
|
|
8003ca0: e059 b.n 8003d56 <HAL_RCC_OscConfig+0x60e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8003ca2: 4b2f ldr r3, [pc, #188] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003ca4: 681a ldr r2, [r3, #0]
|
|
8003ca6: 4b2e ldr r3, [pc, #184] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003ca8: 4931 ldr r1, [pc, #196] ; (8003d70 <HAL_RCC_OscConfig+0x628>)
|
|
8003caa: 400a ands r2, r1
|
|
8003cac: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003cae: f7fe f85d bl 8001d6c <HAL_GetTick>
|
|
8003cb2: 0003 movs r3, r0
|
|
8003cb4: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003cb6: e008 b.n 8003cca <HAL_RCC_OscConfig+0x582>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003cb8: f7fe f858 bl 8001d6c <HAL_GetTick>
|
|
8003cbc: 0002 movs r2, r0
|
|
8003cbe: 693b ldr r3, [r7, #16]
|
|
8003cc0: 1ad3 subs r3, r2, r3
|
|
8003cc2: 2b02 cmp r3, #2
|
|
8003cc4: d901 bls.n 8003cca <HAL_RCC_OscConfig+0x582>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003cc6: 2303 movs r3, #3
|
|
8003cc8: e046 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003cca: 4b25 ldr r3, [pc, #148] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003ccc: 681a ldr r2, [r3, #0]
|
|
8003cce: 2380 movs r3, #128 ; 0x80
|
|
8003cd0: 049b lsls r3, r3, #18
|
|
8003cd2: 4013 ands r3, r2
|
|
8003cd4: d1f0 bne.n 8003cb8 <HAL_RCC_OscConfig+0x570>
|
|
}
|
|
}
|
|
/* Unselect main PLL clock source and disable main PLL outputs to save power */
|
|
#if defined(RCC_PLLQ_SUPPORT)
|
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN);
|
|
8003cd6: 4b22 ldr r3, [pc, #136] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003cd8: 68da ldr r2, [r3, #12]
|
|
8003cda: 4b21 ldr r3, [pc, #132] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003cdc: 4926 ldr r1, [pc, #152] ; (8003d78 <HAL_RCC_OscConfig+0x630>)
|
|
8003cde: 400a ands r2, r1
|
|
8003ce0: 60da str r2, [r3, #12]
|
|
8003ce2: e038 b.n 8003d56 <HAL_RCC_OscConfig+0x60e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8003ce4: 687b ldr r3, [r7, #4]
|
|
8003ce6: 69db ldr r3, [r3, #28]
|
|
8003ce8: 2b01 cmp r3, #1
|
|
8003cea: d101 bne.n 8003cf0 <HAL_RCC_OscConfig+0x5a8>
|
|
{
|
|
return HAL_ERROR;
|
|
8003cec: 2301 movs r3, #1
|
|
8003cee: e033 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
temp_pllckcfg = RCC->PLLCFGR;
|
|
8003cf0: 4b1b ldr r3, [pc, #108] ; (8003d60 <HAL_RCC_OscConfig+0x618>)
|
|
8003cf2: 68db ldr r3, [r3, #12]
|
|
8003cf4: 617b str r3, [r7, #20]
|
|
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8003cf6: 697b ldr r3, [r7, #20]
|
|
8003cf8: 2203 movs r2, #3
|
|
8003cfa: 401a ands r2, r3
|
|
8003cfc: 687b ldr r3, [r7, #4]
|
|
8003cfe: 6a1b ldr r3, [r3, #32]
|
|
8003d00: 429a cmp r2, r3
|
|
8003d02: d126 bne.n 8003d52 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
|
|
8003d04: 697b ldr r3, [r7, #20]
|
|
8003d06: 2270 movs r2, #112 ; 0x70
|
|
8003d08: 401a ands r2, r3
|
|
8003d0a: 687b ldr r3, [r7, #4]
|
|
8003d0c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8003d0e: 429a cmp r2, r3
|
|
8003d10: d11f bne.n 8003d52 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8003d12: 697a ldr r2, [r7, #20]
|
|
8003d14: 23fe movs r3, #254 ; 0xfe
|
|
8003d16: 01db lsls r3, r3, #7
|
|
8003d18: 401a ands r2, r3
|
|
8003d1a: 687b ldr r3, [r7, #4]
|
|
8003d1c: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
8003d1e: 021b lsls r3, r3, #8
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
|
|
8003d20: 429a cmp r2, r3
|
|
8003d22: d116 bne.n 8003d52 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
|
|
8003d24: 697a ldr r2, [r7, #20]
|
|
8003d26: 23f8 movs r3, #248 ; 0xf8
|
|
8003d28: 039b lsls r3, r3, #14
|
|
8003d2a: 401a ands r2, r3
|
|
8003d2c: 687b ldr r3, [r7, #4]
|
|
8003d2e: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8003d30: 429a cmp r2, r3
|
|
8003d32: d10e bne.n 8003d52 <HAL_RCC_OscConfig+0x60a>
|
|
#if defined (RCC_PLLQ_SUPPORT)
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
|
|
8003d34: 697a ldr r2, [r7, #20]
|
|
8003d36: 23e0 movs r3, #224 ; 0xe0
|
|
8003d38: 051b lsls r3, r3, #20
|
|
8003d3a: 401a ands r2, r3
|
|
8003d3c: 687b ldr r3, [r7, #4]
|
|
8003d3e: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
|
|
8003d40: 429a cmp r2, r3
|
|
8003d42: d106 bne.n 8003d52 <HAL_RCC_OscConfig+0x60a>
|
|
#endif /* RCC_PLLQ_SUPPORT */
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
|
|
8003d44: 697b ldr r3, [r7, #20]
|
|
8003d46: 0f5b lsrs r3, r3, #29
|
|
8003d48: 075a lsls r2, r3, #29
|
|
8003d4a: 687b ldr r3, [r7, #4]
|
|
8003d4c: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
|
|
8003d4e: 429a cmp r2, r3
|
|
8003d50: d001 beq.n 8003d56 <HAL_RCC_OscConfig+0x60e>
|
|
{
|
|
return HAL_ERROR;
|
|
8003d52: 2301 movs r3, #1
|
|
8003d54: e000 b.n 8003d58 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8003d56: 2300 movs r3, #0
|
|
}
|
|
8003d58: 0018 movs r0, r3
|
|
8003d5a: 46bd mov sp, r7
|
|
8003d5c: b008 add sp, #32
|
|
8003d5e: bd80 pop {r7, pc}
|
|
8003d60: 40021000 .word 0x40021000
|
|
8003d64: 40007000 .word 0x40007000
|
|
8003d68: 00001388 .word 0x00001388
|
|
8003d6c: efffffff .word 0xefffffff
|
|
8003d70: feffffff .word 0xfeffffff
|
|
8003d74: 11c1808c .word 0x11c1808c
|
|
8003d78: eefefffc .word 0xeefefffc
|
|
|
|
08003d7c <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8003d7c: b580 push {r7, lr}
|
|
8003d7e: b084 sub sp, #16
|
|
8003d80: af00 add r7, sp, #0
|
|
8003d82: 6078 str r0, [r7, #4]
|
|
8003d84: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
8003d86: 687b ldr r3, [r7, #4]
|
|
8003d88: 2b00 cmp r3, #0
|
|
8003d8a: d101 bne.n 8003d90 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8003d8c: 2301 movs r3, #1
|
|
8003d8e: e0e9 b.n 8003f64 <HAL_RCC_ClockConfig+0x1e8>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the FLASH clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8003d90: 4b76 ldr r3, [pc, #472] ; (8003f6c <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003d92: 681b ldr r3, [r3, #0]
|
|
8003d94: 2207 movs r2, #7
|
|
8003d96: 4013 ands r3, r2
|
|
8003d98: 683a ldr r2, [r7, #0]
|
|
8003d9a: 429a cmp r2, r3
|
|
8003d9c: d91e bls.n 8003ddc <HAL_RCC_ClockConfig+0x60>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8003d9e: 4b73 ldr r3, [pc, #460] ; (8003f6c <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003da0: 681b ldr r3, [r3, #0]
|
|
8003da2: 2207 movs r2, #7
|
|
8003da4: 4393 bics r3, r2
|
|
8003da6: 0019 movs r1, r3
|
|
8003da8: 4b70 ldr r3, [pc, #448] ; (8003f6c <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003daa: 683a ldr r2, [r7, #0]
|
|
8003dac: 430a orrs r2, r1
|
|
8003dae: 601a str r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by polling the FLASH_ACR register */
|
|
tickstart = HAL_GetTick();
|
|
8003db0: f7fd ffdc bl 8001d6c <HAL_GetTick>
|
|
8003db4: 0003 movs r3, r0
|
|
8003db6: 60fb str r3, [r7, #12]
|
|
|
|
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
8003db8: e009 b.n 8003dce <HAL_RCC_ClockConfig+0x52>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8003dba: f7fd ffd7 bl 8001d6c <HAL_GetTick>
|
|
8003dbe: 0002 movs r2, r0
|
|
8003dc0: 68fb ldr r3, [r7, #12]
|
|
8003dc2: 1ad3 subs r3, r2, r3
|
|
8003dc4: 4a6a ldr r2, [pc, #424] ; (8003f70 <HAL_RCC_ClockConfig+0x1f4>)
|
|
8003dc6: 4293 cmp r3, r2
|
|
8003dc8: d901 bls.n 8003dce <HAL_RCC_ClockConfig+0x52>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003dca: 2303 movs r3, #3
|
|
8003dcc: e0ca b.n 8003f64 <HAL_RCC_ClockConfig+0x1e8>
|
|
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
8003dce: 4b67 ldr r3, [pc, #412] ; (8003f6c <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003dd0: 681b ldr r3, [r3, #0]
|
|
8003dd2: 2207 movs r2, #7
|
|
8003dd4: 4013 ands r3, r2
|
|
8003dd6: 683a ldr r2, [r7, #0]
|
|
8003dd8: 429a cmp r2, r3
|
|
8003dda: d1ee bne.n 8003dba <HAL_RCC_ClockConfig+0x3e>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8003ddc: 687b ldr r3, [r7, #4]
|
|
8003dde: 681b ldr r3, [r3, #0]
|
|
8003de0: 2202 movs r2, #2
|
|
8003de2: 4013 ands r3, r2
|
|
8003de4: d015 beq.n 8003e12 <HAL_RCC_ClockConfig+0x96>
|
|
{
|
|
/* Set the highest APB divider in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8003de6: 687b ldr r3, [r7, #4]
|
|
8003de8: 681b ldr r3, [r3, #0]
|
|
8003dea: 2204 movs r2, #4
|
|
8003dec: 4013 ands r3, r2
|
|
8003dee: d006 beq.n 8003dfe <HAL_RCC_ClockConfig+0x82>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
|
|
8003df0: 4b60 ldr r3, [pc, #384] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003df2: 689a ldr r2, [r3, #8]
|
|
8003df4: 4b5f ldr r3, [pc, #380] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003df6: 21e0 movs r1, #224 ; 0xe0
|
|
8003df8: 01c9 lsls r1, r1, #7
|
|
8003dfa: 430a orrs r2, r1
|
|
8003dfc: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Set the new HCLK clock divider */
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8003dfe: 4b5d ldr r3, [pc, #372] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003e00: 689b ldr r3, [r3, #8]
|
|
8003e02: 4a5d ldr r2, [pc, #372] ; (8003f78 <HAL_RCC_ClockConfig+0x1fc>)
|
|
8003e04: 4013 ands r3, r2
|
|
8003e06: 0019 movs r1, r3
|
|
8003e08: 687b ldr r3, [r7, #4]
|
|
8003e0a: 689a ldr r2, [r3, #8]
|
|
8003e0c: 4b59 ldr r3, [pc, #356] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003e0e: 430a orrs r2, r1
|
|
8003e10: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8003e12: 687b ldr r3, [r7, #4]
|
|
8003e14: 681b ldr r3, [r3, #0]
|
|
8003e16: 2201 movs r2, #1
|
|
8003e18: 4013 ands r3, r2
|
|
8003e1a: d057 beq.n 8003ecc <HAL_RCC_ClockConfig+0x150>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8003e1c: 687b ldr r3, [r7, #4]
|
|
8003e1e: 685b ldr r3, [r3, #4]
|
|
8003e20: 2b01 cmp r3, #1
|
|
8003e22: d107 bne.n 8003e34 <HAL_RCC_ClockConfig+0xb8>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8003e24: 4b53 ldr r3, [pc, #332] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003e26: 681a ldr r2, [r3, #0]
|
|
8003e28: 2380 movs r3, #128 ; 0x80
|
|
8003e2a: 029b lsls r3, r3, #10
|
|
8003e2c: 4013 ands r3, r2
|
|
8003e2e: d12b bne.n 8003e88 <HAL_RCC_ClockConfig+0x10c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003e30: 2301 movs r3, #1
|
|
8003e32: e097 b.n 8003f64 <HAL_RCC_ClockConfig+0x1e8>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8003e34: 687b ldr r3, [r7, #4]
|
|
8003e36: 685b ldr r3, [r3, #4]
|
|
8003e38: 2b02 cmp r3, #2
|
|
8003e3a: d107 bne.n 8003e4c <HAL_RCC_ClockConfig+0xd0>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003e3c: 4b4d ldr r3, [pc, #308] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003e3e: 681a ldr r2, [r3, #0]
|
|
8003e40: 2380 movs r3, #128 ; 0x80
|
|
8003e42: 049b lsls r3, r3, #18
|
|
8003e44: 4013 ands r3, r2
|
|
8003e46: d11f bne.n 8003e88 <HAL_RCC_ClockConfig+0x10c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003e48: 2301 movs r3, #1
|
|
8003e4a: e08b b.n 8003f64 <HAL_RCC_ClockConfig+0x1e8>
|
|
}
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
|
|
8003e4c: 687b ldr r3, [r7, #4]
|
|
8003e4e: 685b ldr r3, [r3, #4]
|
|
8003e50: 2b00 cmp r3, #0
|
|
8003e52: d107 bne.n 8003e64 <HAL_RCC_ClockConfig+0xe8>
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8003e54: 4b47 ldr r3, [pc, #284] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003e56: 681a ldr r2, [r3, #0]
|
|
8003e58: 2380 movs r3, #128 ; 0x80
|
|
8003e5a: 00db lsls r3, r3, #3
|
|
8003e5c: 4013 ands r3, r2
|
|
8003e5e: d113 bne.n 8003e88 <HAL_RCC_ClockConfig+0x10c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003e60: 2301 movs r3, #1
|
|
8003e62: e07f b.n 8003f64 <HAL_RCC_ClockConfig+0x1e8>
|
|
}
|
|
}
|
|
/* LSI is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
|
|
8003e64: 687b ldr r3, [r7, #4]
|
|
8003e66: 685b ldr r3, [r3, #4]
|
|
8003e68: 2b03 cmp r3, #3
|
|
8003e6a: d106 bne.n 8003e7a <HAL_RCC_ClockConfig+0xfe>
|
|
{
|
|
/* Check the LSI ready flag */
|
|
if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8003e6c: 4b41 ldr r3, [pc, #260] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003e6e: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
8003e70: 2202 movs r2, #2
|
|
8003e72: 4013 ands r3, r2
|
|
8003e74: d108 bne.n 8003e88 <HAL_RCC_ClockConfig+0x10c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003e76: 2301 movs r3, #1
|
|
8003e78: e074 b.n 8003f64 <HAL_RCC_ClockConfig+0x1e8>
|
|
}
|
|
/* LSE is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the LSE ready flag */
|
|
if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8003e7a: 4b3e ldr r3, [pc, #248] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003e7c: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
8003e7e: 2202 movs r2, #2
|
|
8003e80: 4013 ands r3, r2
|
|
8003e82: d101 bne.n 8003e88 <HAL_RCC_ClockConfig+0x10c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003e84: 2301 movs r3, #1
|
|
8003e86: e06d b.n 8003f64 <HAL_RCC_ClockConfig+0x1e8>
|
|
}
|
|
}
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
8003e88: 4b3a ldr r3, [pc, #232] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003e8a: 689b ldr r3, [r3, #8]
|
|
8003e8c: 2207 movs r2, #7
|
|
8003e8e: 4393 bics r3, r2
|
|
8003e90: 0019 movs r1, r3
|
|
8003e92: 687b ldr r3, [r7, #4]
|
|
8003e94: 685a ldr r2, [r3, #4]
|
|
8003e96: 4b37 ldr r3, [pc, #220] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003e98: 430a orrs r2, r1
|
|
8003e9a: 609a str r2, [r3, #8]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003e9c: f7fd ff66 bl 8001d6c <HAL_GetTick>
|
|
8003ea0: 0003 movs r3, r0
|
|
8003ea2: 60fb str r3, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8003ea4: e009 b.n 8003eba <HAL_RCC_ClockConfig+0x13e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8003ea6: f7fd ff61 bl 8001d6c <HAL_GetTick>
|
|
8003eaa: 0002 movs r2, r0
|
|
8003eac: 68fb ldr r3, [r7, #12]
|
|
8003eae: 1ad3 subs r3, r2, r3
|
|
8003eb0: 4a2f ldr r2, [pc, #188] ; (8003f70 <HAL_RCC_ClockConfig+0x1f4>)
|
|
8003eb2: 4293 cmp r3, r2
|
|
8003eb4: d901 bls.n 8003eba <HAL_RCC_ClockConfig+0x13e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003eb6: 2303 movs r3, #3
|
|
8003eb8: e054 b.n 8003f64 <HAL_RCC_ClockConfig+0x1e8>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8003eba: 4b2e ldr r3, [pc, #184] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003ebc: 689b ldr r3, [r3, #8]
|
|
8003ebe: 2238 movs r2, #56 ; 0x38
|
|
8003ec0: 401a ands r2, r3
|
|
8003ec2: 687b ldr r3, [r7, #4]
|
|
8003ec4: 685b ldr r3, [r3, #4]
|
|
8003ec6: 00db lsls r3, r3, #3
|
|
8003ec8: 429a cmp r2, r3
|
|
8003eca: d1ec bne.n 8003ea6 <HAL_RCC_ClockConfig+0x12a>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8003ecc: 4b27 ldr r3, [pc, #156] ; (8003f6c <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003ece: 681b ldr r3, [r3, #0]
|
|
8003ed0: 2207 movs r2, #7
|
|
8003ed2: 4013 ands r3, r2
|
|
8003ed4: 683a ldr r2, [r7, #0]
|
|
8003ed6: 429a cmp r2, r3
|
|
8003ed8: d21e bcs.n 8003f18 <HAL_RCC_ClockConfig+0x19c>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8003eda: 4b24 ldr r3, [pc, #144] ; (8003f6c <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003edc: 681b ldr r3, [r3, #0]
|
|
8003ede: 2207 movs r2, #7
|
|
8003ee0: 4393 bics r3, r2
|
|
8003ee2: 0019 movs r1, r3
|
|
8003ee4: 4b21 ldr r3, [pc, #132] ; (8003f6c <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003ee6: 683a ldr r2, [r7, #0]
|
|
8003ee8: 430a orrs r2, r1
|
|
8003eea: 601a str r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by polling the FLASH_ACR register */
|
|
tickstart = HAL_GetTick();
|
|
8003eec: f7fd ff3e bl 8001d6c <HAL_GetTick>
|
|
8003ef0: 0003 movs r3, r0
|
|
8003ef2: 60fb str r3, [r7, #12]
|
|
|
|
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
8003ef4: e009 b.n 8003f0a <HAL_RCC_ClockConfig+0x18e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8003ef6: f7fd ff39 bl 8001d6c <HAL_GetTick>
|
|
8003efa: 0002 movs r2, r0
|
|
8003efc: 68fb ldr r3, [r7, #12]
|
|
8003efe: 1ad3 subs r3, r2, r3
|
|
8003f00: 4a1b ldr r2, [pc, #108] ; (8003f70 <HAL_RCC_ClockConfig+0x1f4>)
|
|
8003f02: 4293 cmp r3, r2
|
|
8003f04: d901 bls.n 8003f0a <HAL_RCC_ClockConfig+0x18e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003f06: 2303 movs r3, #3
|
|
8003f08: e02c b.n 8003f64 <HAL_RCC_ClockConfig+0x1e8>
|
|
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
8003f0a: 4b18 ldr r3, [pc, #96] ; (8003f6c <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003f0c: 681b ldr r3, [r3, #0]
|
|
8003f0e: 2207 movs r2, #7
|
|
8003f10: 4013 ands r3, r2
|
|
8003f12: 683a ldr r2, [r7, #0]
|
|
8003f14: 429a cmp r2, r3
|
|
8003f16: d1ee bne.n 8003ef6 <HAL_RCC_ClockConfig+0x17a>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8003f18: 687b ldr r3, [r7, #4]
|
|
8003f1a: 681b ldr r3, [r3, #0]
|
|
8003f1c: 2204 movs r2, #4
|
|
8003f1e: 4013 ands r3, r2
|
|
8003f20: d009 beq.n 8003f36 <HAL_RCC_ClockConfig+0x1ba>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8003f22: 4b14 ldr r3, [pc, #80] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003f24: 689b ldr r3, [r3, #8]
|
|
8003f26: 4a15 ldr r2, [pc, #84] ; (8003f7c <HAL_RCC_ClockConfig+0x200>)
|
|
8003f28: 4013 ands r3, r2
|
|
8003f2a: 0019 movs r1, r3
|
|
8003f2c: 687b ldr r3, [r7, #4]
|
|
8003f2e: 68da ldr r2, [r3, #12]
|
|
8003f30: 4b10 ldr r3, [pc, #64] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003f32: 430a orrs r2, r1
|
|
8003f34: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
|
|
8003f36: f000 f829 bl 8003f8c <HAL_RCC_GetSysClockFreq>
|
|
8003f3a: 0001 movs r1, r0
|
|
8003f3c: 4b0d ldr r3, [pc, #52] ; (8003f74 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8003f3e: 689b ldr r3, [r3, #8]
|
|
8003f40: 0a1b lsrs r3, r3, #8
|
|
8003f42: 220f movs r2, #15
|
|
8003f44: 401a ands r2, r3
|
|
8003f46: 4b0e ldr r3, [pc, #56] ; (8003f80 <HAL_RCC_ClockConfig+0x204>)
|
|
8003f48: 0092 lsls r2, r2, #2
|
|
8003f4a: 58d3 ldr r3, [r2, r3]
|
|
8003f4c: 221f movs r2, #31
|
|
8003f4e: 4013 ands r3, r2
|
|
8003f50: 000a movs r2, r1
|
|
8003f52: 40da lsrs r2, r3
|
|
8003f54: 4b0b ldr r3, [pc, #44] ; (8003f84 <HAL_RCC_ClockConfig+0x208>)
|
|
8003f56: 601a str r2, [r3, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
return HAL_InitTick(uwTickPrio);
|
|
8003f58: 4b0b ldr r3, [pc, #44] ; (8003f88 <HAL_RCC_ClockConfig+0x20c>)
|
|
8003f5a: 681b ldr r3, [r3, #0]
|
|
8003f5c: 0018 movs r0, r3
|
|
8003f5e: f7fd fea9 bl 8001cb4 <HAL_InitTick>
|
|
8003f62: 0003 movs r3, r0
|
|
}
|
|
8003f64: 0018 movs r0, r3
|
|
8003f66: 46bd mov sp, r7
|
|
8003f68: b004 add sp, #16
|
|
8003f6a: bd80 pop {r7, pc}
|
|
8003f6c: 40022000 .word 0x40022000
|
|
8003f70: 00001388 .word 0x00001388
|
|
8003f74: 40021000 .word 0x40021000
|
|
8003f78: fffff0ff .word 0xfffff0ff
|
|
8003f7c: ffff8fff .word 0xffff8fff
|
|
8003f80: 080067e8 .word 0x080067e8
|
|
8003f84: 20000004 .word 0x20000004
|
|
8003f88: 20000008 .word 0x20000008
|
|
|
|
08003f8c <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8003f8c: b580 push {r7, lr}
|
|
8003f8e: b086 sub sp, #24
|
|
8003f90: af00 add r7, sp, #0
|
|
uint32_t pllvco, pllsource, pllr, pllm, hsidiv;
|
|
uint32_t sysclockfreq;
|
|
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
8003f92: 4b3c ldr r3, [pc, #240] ; (8004084 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8003f94: 689b ldr r3, [r3, #8]
|
|
8003f96: 2238 movs r2, #56 ; 0x38
|
|
8003f98: 4013 ands r3, r2
|
|
8003f9a: d10f bne.n 8003fbc <HAL_RCC_GetSysClockFreq+0x30>
|
|
{
|
|
/* HSISYS can be derived for HSI16 */
|
|
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
|
|
8003f9c: 4b39 ldr r3, [pc, #228] ; (8004084 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8003f9e: 681b ldr r3, [r3, #0]
|
|
8003fa0: 0adb lsrs r3, r3, #11
|
|
8003fa2: 2207 movs r2, #7
|
|
8003fa4: 4013 ands r3, r2
|
|
8003fa6: 2201 movs r2, #1
|
|
8003fa8: 409a lsls r2, r3
|
|
8003faa: 0013 movs r3, r2
|
|
8003fac: 603b str r3, [r7, #0]
|
|
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = (HSI_VALUE / hsidiv);
|
|
8003fae: 6839 ldr r1, [r7, #0]
|
|
8003fb0: 4835 ldr r0, [pc, #212] ; (8004088 <HAL_RCC_GetSysClockFreq+0xfc>)
|
|
8003fb2: f7fc f8a9 bl 8000108 <__udivsi3>
|
|
8003fb6: 0003 movs r3, r0
|
|
8003fb8: 613b str r3, [r7, #16]
|
|
8003fba: e05d b.n 8004078 <HAL_RCC_GetSysClockFreq+0xec>
|
|
}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
8003fbc: 4b31 ldr r3, [pc, #196] ; (8004084 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8003fbe: 689b ldr r3, [r3, #8]
|
|
8003fc0: 2238 movs r2, #56 ; 0x38
|
|
8003fc2: 4013 ands r3, r2
|
|
8003fc4: 2b08 cmp r3, #8
|
|
8003fc6: d102 bne.n 8003fce <HAL_RCC_GetSysClockFreq+0x42>
|
|
{
|
|
/* HSE used as system clock source */
|
|
sysclockfreq = HSE_VALUE;
|
|
8003fc8: 4b30 ldr r3, [pc, #192] ; (800408c <HAL_RCC_GetSysClockFreq+0x100>)
|
|
8003fca: 613b str r3, [r7, #16]
|
|
8003fcc: e054 b.n 8004078 <HAL_RCC_GetSysClockFreq+0xec>
|
|
}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
8003fce: 4b2d ldr r3, [pc, #180] ; (8004084 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8003fd0: 689b ldr r3, [r3, #8]
|
|
8003fd2: 2238 movs r2, #56 ; 0x38
|
|
8003fd4: 4013 ands r3, r2
|
|
8003fd6: 2b10 cmp r3, #16
|
|
8003fd8: d138 bne.n 800404c <HAL_RCC_GetSysClockFreq+0xc0>
|
|
/* PLL used as system clock source */
|
|
|
|
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
|
8003fda: 4b2a ldr r3, [pc, #168] ; (8004084 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8003fdc: 68db ldr r3, [r3, #12]
|
|
8003fde: 2203 movs r2, #3
|
|
8003fe0: 4013 ands r3, r2
|
|
8003fe2: 60fb str r3, [r7, #12]
|
|
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
8003fe4: 4b27 ldr r3, [pc, #156] ; (8004084 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8003fe6: 68db ldr r3, [r3, #12]
|
|
8003fe8: 091b lsrs r3, r3, #4
|
|
8003fea: 2207 movs r2, #7
|
|
8003fec: 4013 ands r3, r2
|
|
8003fee: 3301 adds r3, #1
|
|
8003ff0: 60bb str r3, [r7, #8]
|
|
|
|
switch (pllsource)
|
|
8003ff2: 68fb ldr r3, [r7, #12]
|
|
8003ff4: 2b03 cmp r3, #3
|
|
8003ff6: d10d bne.n 8004014 <HAL_RCC_GetSysClockFreq+0x88>
|
|
{
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
8003ff8: 68b9 ldr r1, [r7, #8]
|
|
8003ffa: 4824 ldr r0, [pc, #144] ; (800408c <HAL_RCC_GetSysClockFreq+0x100>)
|
|
8003ffc: f7fc f884 bl 8000108 <__udivsi3>
|
|
8004000: 0003 movs r3, r0
|
|
8004002: 0019 movs r1, r3
|
|
8004004: 4b1f ldr r3, [pc, #124] ; (8004084 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8004006: 68db ldr r3, [r3, #12]
|
|
8004008: 0a1b lsrs r3, r3, #8
|
|
800400a: 227f movs r2, #127 ; 0x7f
|
|
800400c: 4013 ands r3, r2
|
|
800400e: 434b muls r3, r1
|
|
8004010: 617b str r3, [r7, #20]
|
|
break;
|
|
8004012: e00d b.n 8004030 <HAL_RCC_GetSysClockFreq+0xa4>
|
|
|
|
case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */
|
|
default: /* HSI16 used as PLL clock source */
|
|
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ;
|
|
8004014: 68b9 ldr r1, [r7, #8]
|
|
8004016: 481c ldr r0, [pc, #112] ; (8004088 <HAL_RCC_GetSysClockFreq+0xfc>)
|
|
8004018: f7fc f876 bl 8000108 <__udivsi3>
|
|
800401c: 0003 movs r3, r0
|
|
800401e: 0019 movs r1, r3
|
|
8004020: 4b18 ldr r3, [pc, #96] ; (8004084 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8004022: 68db ldr r3, [r3, #12]
|
|
8004024: 0a1b lsrs r3, r3, #8
|
|
8004026: 227f movs r2, #127 ; 0x7f
|
|
8004028: 4013 ands r3, r2
|
|
800402a: 434b muls r3, r1
|
|
800402c: 617b str r3, [r7, #20]
|
|
break;
|
|
800402e: 46c0 nop ; (mov r8, r8)
|
|
}
|
|
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
|
|
8004030: 4b14 ldr r3, [pc, #80] ; (8004084 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8004032: 68db ldr r3, [r3, #12]
|
|
8004034: 0f5b lsrs r3, r3, #29
|
|
8004036: 2207 movs r2, #7
|
|
8004038: 4013 ands r3, r2
|
|
800403a: 3301 adds r3, #1
|
|
800403c: 607b str r3, [r7, #4]
|
|
sysclockfreq = pllvco / pllr;
|
|
800403e: 6879 ldr r1, [r7, #4]
|
|
8004040: 6978 ldr r0, [r7, #20]
|
|
8004042: f7fc f861 bl 8000108 <__udivsi3>
|
|
8004046: 0003 movs r3, r0
|
|
8004048: 613b str r3, [r7, #16]
|
|
800404a: e015 b.n 8004078 <HAL_RCC_GetSysClockFreq+0xec>
|
|
}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
|
|
800404c: 4b0d ldr r3, [pc, #52] ; (8004084 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
800404e: 689b ldr r3, [r3, #8]
|
|
8004050: 2238 movs r2, #56 ; 0x38
|
|
8004052: 4013 ands r3, r2
|
|
8004054: 2b20 cmp r3, #32
|
|
8004056: d103 bne.n 8004060 <HAL_RCC_GetSysClockFreq+0xd4>
|
|
{
|
|
/* LSE used as system clock source */
|
|
sysclockfreq = LSE_VALUE;
|
|
8004058: 2380 movs r3, #128 ; 0x80
|
|
800405a: 021b lsls r3, r3, #8
|
|
800405c: 613b str r3, [r7, #16]
|
|
800405e: e00b b.n 8004078 <HAL_RCC_GetSysClockFreq+0xec>
|
|
}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
|
|
8004060: 4b08 ldr r3, [pc, #32] ; (8004084 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8004062: 689b ldr r3, [r3, #8]
|
|
8004064: 2238 movs r2, #56 ; 0x38
|
|
8004066: 4013 ands r3, r2
|
|
8004068: 2b18 cmp r3, #24
|
|
800406a: d103 bne.n 8004074 <HAL_RCC_GetSysClockFreq+0xe8>
|
|
{
|
|
/* LSI used as system clock source */
|
|
sysclockfreq = LSI_VALUE;
|
|
800406c: 23fa movs r3, #250 ; 0xfa
|
|
800406e: 01db lsls r3, r3, #7
|
|
8004070: 613b str r3, [r7, #16]
|
|
8004072: e001 b.n 8004078 <HAL_RCC_GetSysClockFreq+0xec>
|
|
}
|
|
else
|
|
{
|
|
sysclockfreq = 0U;
|
|
8004074: 2300 movs r3, #0
|
|
8004076: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
return sysclockfreq;
|
|
8004078: 693b ldr r3, [r7, #16]
|
|
}
|
|
800407a: 0018 movs r0, r3
|
|
800407c: 46bd mov sp, r7
|
|
800407e: b006 add sp, #24
|
|
8004080: bd80 pop {r7, pc}
|
|
8004082: 46c0 nop ; (mov r8, r8)
|
|
8004084: 40021000 .word 0x40021000
|
|
8004088: 00f42400 .word 0x00f42400
|
|
800408c: 007a1200 .word 0x007a1200
|
|
|
|
08004090 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the RTC clock source: in this case the access to Backup domain is enabled.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8004090: b580 push {r7, lr}
|
|
8004092: b086 sub sp, #24
|
|
8004094: af00 add r7, sp, #0
|
|
8004096: 6078 str r0, [r7, #4]
|
|
uint32_t tmpregister;
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
|
|
8004098: 2313 movs r3, #19
|
|
800409a: 18fb adds r3, r7, r3
|
|
800409c: 2200 movs r2, #0
|
|
800409e: 701a strb r2, [r3, #0]
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
80040a0: 2312 movs r3, #18
|
|
80040a2: 18fb adds r3, r7, r3
|
|
80040a4: 2200 movs r2, #0
|
|
80040a6: 701a strb r2, [r3, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
|
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
80040a8: 687b ldr r3, [r7, #4]
|
|
80040aa: 681a ldr r2, [r3, #0]
|
|
80040ac: 2380 movs r3, #128 ; 0x80
|
|
80040ae: 029b lsls r3, r3, #10
|
|
80040b0: 4013 ands r3, r2
|
|
80040b2: d100 bne.n 80040b6 <HAL_RCCEx_PeriphCLKConfig+0x26>
|
|
80040b4: e0a3 b.n 80041fe <HAL_RCCEx_PeriphCLKConfig+0x16e>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
80040b6: 2011 movs r0, #17
|
|
80040b8: 183b adds r3, r7, r0
|
|
80040ba: 2200 movs r2, #0
|
|
80040bc: 701a strb r2, [r3, #0]
|
|
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
80040be: 4ba5 ldr r3, [pc, #660] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80040c0: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
80040c2: 2380 movs r3, #128 ; 0x80
|
|
80040c4: 055b lsls r3, r3, #21
|
|
80040c6: 4013 ands r3, r2
|
|
80040c8: d110 bne.n 80040ec <HAL_RCCEx_PeriphCLKConfig+0x5c>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80040ca: 4ba2 ldr r3, [pc, #648] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80040cc: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
80040ce: 4ba1 ldr r3, [pc, #644] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80040d0: 2180 movs r1, #128 ; 0x80
|
|
80040d2: 0549 lsls r1, r1, #21
|
|
80040d4: 430a orrs r2, r1
|
|
80040d6: 63da str r2, [r3, #60] ; 0x3c
|
|
80040d8: 4b9e ldr r3, [pc, #632] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80040da: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
80040dc: 2380 movs r3, #128 ; 0x80
|
|
80040de: 055b lsls r3, r3, #21
|
|
80040e0: 4013 ands r3, r2
|
|
80040e2: 60bb str r3, [r7, #8]
|
|
80040e4: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
80040e6: 183b adds r3, r7, r0
|
|
80040e8: 2201 movs r2, #1
|
|
80040ea: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
80040ec: 4b9a ldr r3, [pc, #616] ; (8004358 <HAL_RCCEx_PeriphCLKConfig+0x2c8>)
|
|
80040ee: 681a ldr r2, [r3, #0]
|
|
80040f0: 4b99 ldr r3, [pc, #612] ; (8004358 <HAL_RCCEx_PeriphCLKConfig+0x2c8>)
|
|
80040f2: 2180 movs r1, #128 ; 0x80
|
|
80040f4: 0049 lsls r1, r1, #1
|
|
80040f6: 430a orrs r2, r1
|
|
80040f8: 601a str r2, [r3, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
80040fa: f7fd fe37 bl 8001d6c <HAL_GetTick>
|
|
80040fe: 0003 movs r3, r0
|
|
8004100: 60fb str r3, [r7, #12]
|
|
|
|
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
|
|
8004102: e00b b.n 800411c <HAL_RCCEx_PeriphCLKConfig+0x8c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8004104: f7fd fe32 bl 8001d6c <HAL_GetTick>
|
|
8004108: 0002 movs r2, r0
|
|
800410a: 68fb ldr r3, [r7, #12]
|
|
800410c: 1ad3 subs r3, r2, r3
|
|
800410e: 2b02 cmp r3, #2
|
|
8004110: d904 bls.n 800411c <HAL_RCCEx_PeriphCLKConfig+0x8c>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8004112: 2313 movs r3, #19
|
|
8004114: 18fb adds r3, r7, r3
|
|
8004116: 2203 movs r2, #3
|
|
8004118: 701a strb r2, [r3, #0]
|
|
break;
|
|
800411a: e005 b.n 8004128 <HAL_RCCEx_PeriphCLKConfig+0x98>
|
|
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
|
|
800411c: 4b8e ldr r3, [pc, #568] ; (8004358 <HAL_RCCEx_PeriphCLKConfig+0x2c8>)
|
|
800411e: 681a ldr r2, [r3, #0]
|
|
8004120: 2380 movs r3, #128 ; 0x80
|
|
8004122: 005b lsls r3, r3, #1
|
|
8004124: 4013 ands r3, r2
|
|
8004126: d0ed beq.n 8004104 <HAL_RCCEx_PeriphCLKConfig+0x74>
|
|
}
|
|
}
|
|
|
|
if (ret == HAL_OK)
|
|
8004128: 2313 movs r3, #19
|
|
800412a: 18fb adds r3, r7, r3
|
|
800412c: 781b ldrb r3, [r3, #0]
|
|
800412e: 2b00 cmp r3, #0
|
|
8004130: d154 bne.n 80041dc <HAL_RCCEx_PeriphCLKConfig+0x14c>
|
|
{
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
|
|
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
|
|
8004132: 4b88 ldr r3, [pc, #544] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004134: 6dda ldr r2, [r3, #92] ; 0x5c
|
|
8004136: 23c0 movs r3, #192 ; 0xc0
|
|
8004138: 009b lsls r3, r3, #2
|
|
800413a: 4013 ands r3, r2
|
|
800413c: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified */
|
|
if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
|
|
800413e: 697b ldr r3, [r7, #20]
|
|
8004140: 2b00 cmp r3, #0
|
|
8004142: d019 beq.n 8004178 <HAL_RCCEx_PeriphCLKConfig+0xe8>
|
|
8004144: 687b ldr r3, [r7, #4]
|
|
8004146: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8004148: 697a ldr r2, [r7, #20]
|
|
800414a: 429a cmp r2, r3
|
|
800414c: d014 beq.n 8004178 <HAL_RCCEx_PeriphCLKConfig+0xe8>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
|
|
800414e: 4b81 ldr r3, [pc, #516] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004150: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
8004152: 4a82 ldr r2, [pc, #520] ; (800435c <HAL_RCCEx_PeriphCLKConfig+0x2cc>)
|
|
8004154: 4013 ands r3, r2
|
|
8004156: 617b str r3, [r7, #20]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8004158: 4b7e ldr r3, [pc, #504] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
800415a: 6dda ldr r2, [r3, #92] ; 0x5c
|
|
800415c: 4b7d ldr r3, [pc, #500] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
800415e: 2180 movs r1, #128 ; 0x80
|
|
8004160: 0249 lsls r1, r1, #9
|
|
8004162: 430a orrs r2, r1
|
|
8004164: 65da str r2, [r3, #92] ; 0x5c
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8004166: 4b7b ldr r3, [pc, #492] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004168: 6dda ldr r2, [r3, #92] ; 0x5c
|
|
800416a: 4b7a ldr r3, [pc, #488] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
800416c: 497c ldr r1, [pc, #496] ; (8004360 <HAL_RCCEx_PeriphCLKConfig+0x2d0>)
|
|
800416e: 400a ands r2, r1
|
|
8004170: 65da str r2, [r3, #92] ; 0x5c
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpregister;
|
|
8004172: 4b78 ldr r3, [pc, #480] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004174: 697a ldr r2, [r7, #20]
|
|
8004176: 65da str r2, [r3, #92] ; 0x5c
|
|
}
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
|
|
8004178: 697b ldr r3, [r7, #20]
|
|
800417a: 2201 movs r2, #1
|
|
800417c: 4013 ands r3, r2
|
|
800417e: d016 beq.n 80041ae <HAL_RCCEx_PeriphCLKConfig+0x11e>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004180: f7fd fdf4 bl 8001d6c <HAL_GetTick>
|
|
8004184: 0003 movs r3, r0
|
|
8004186: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8004188: e00c b.n 80041a4 <HAL_RCCEx_PeriphCLKConfig+0x114>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800418a: f7fd fdef bl 8001d6c <HAL_GetTick>
|
|
800418e: 0002 movs r2, r0
|
|
8004190: 68fb ldr r3, [r7, #12]
|
|
8004192: 1ad3 subs r3, r2, r3
|
|
8004194: 4a73 ldr r2, [pc, #460] ; (8004364 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
|
|
8004196: 4293 cmp r3, r2
|
|
8004198: d904 bls.n 80041a4 <HAL_RCCEx_PeriphCLKConfig+0x114>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
800419a: 2313 movs r3, #19
|
|
800419c: 18fb adds r3, r7, r3
|
|
800419e: 2203 movs r2, #3
|
|
80041a0: 701a strb r2, [r3, #0]
|
|
break;
|
|
80041a2: e004 b.n 80041ae <HAL_RCCEx_PeriphCLKConfig+0x11e>
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
80041a4: 4b6b ldr r3, [pc, #428] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80041a6: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
80041a8: 2202 movs r2, #2
|
|
80041aa: 4013 ands r3, r2
|
|
80041ac: d0ed beq.n 800418a <HAL_RCCEx_PeriphCLKConfig+0xfa>
|
|
}
|
|
}
|
|
}
|
|
|
|
if (ret == HAL_OK)
|
|
80041ae: 2313 movs r3, #19
|
|
80041b0: 18fb adds r3, r7, r3
|
|
80041b2: 781b ldrb r3, [r3, #0]
|
|
80041b4: 2b00 cmp r3, #0
|
|
80041b6: d10a bne.n 80041ce <HAL_RCCEx_PeriphCLKConfig+0x13e>
|
|
{
|
|
/* Apply new RTC clock source selection */
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
80041b8: 4b66 ldr r3, [pc, #408] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80041ba: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
80041bc: 4a67 ldr r2, [pc, #412] ; (800435c <HAL_RCCEx_PeriphCLKConfig+0x2cc>)
|
|
80041be: 4013 ands r3, r2
|
|
80041c0: 0019 movs r1, r3
|
|
80041c2: 687b ldr r3, [r7, #4]
|
|
80041c4: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
80041c6: 4b63 ldr r3, [pc, #396] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80041c8: 430a orrs r2, r1
|
|
80041ca: 65da str r2, [r3, #92] ; 0x5c
|
|
80041cc: e00c b.n 80041e8 <HAL_RCCEx_PeriphCLKConfig+0x158>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80041ce: 2312 movs r3, #18
|
|
80041d0: 18fb adds r3, r7, r3
|
|
80041d2: 2213 movs r2, #19
|
|
80041d4: 18ba adds r2, r7, r2
|
|
80041d6: 7812 ldrb r2, [r2, #0]
|
|
80041d8: 701a strb r2, [r3, #0]
|
|
80041da: e005 b.n 80041e8 <HAL_RCCEx_PeriphCLKConfig+0x158>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80041dc: 2312 movs r3, #18
|
|
80041de: 18fb adds r3, r7, r3
|
|
80041e0: 2213 movs r2, #19
|
|
80041e2: 18ba adds r2, r7, r2
|
|
80041e4: 7812 ldrb r2, [r2, #0]
|
|
80041e6: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
80041e8: 2311 movs r3, #17
|
|
80041ea: 18fb adds r3, r7, r3
|
|
80041ec: 781b ldrb r3, [r3, #0]
|
|
80041ee: 2b01 cmp r3, #1
|
|
80041f0: d105 bne.n 80041fe <HAL_RCCEx_PeriphCLKConfig+0x16e>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
80041f2: 4b58 ldr r3, [pc, #352] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80041f4: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
80041f6: 4b57 ldr r3, [pc, #348] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80041f8: 495b ldr r1, [pc, #364] ; (8004368 <HAL_RCCEx_PeriphCLKConfig+0x2d8>)
|
|
80041fa: 400a ands r2, r1
|
|
80041fc: 63da str r2, [r3, #60] ; 0x3c
|
|
}
|
|
}
|
|
|
|
/*-------------------------- USART1 clock source configuration -------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
80041fe: 687b ldr r3, [r7, #4]
|
|
8004200: 681b ldr r3, [r3, #0]
|
|
8004202: 2201 movs r2, #1
|
|
8004204: 4013 ands r3, r2
|
|
8004206: d009 beq.n 800421c <HAL_RCCEx_PeriphCLKConfig+0x18c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
8004208: 4b52 ldr r3, [pc, #328] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
800420a: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
800420c: 2203 movs r2, #3
|
|
800420e: 4393 bics r3, r2
|
|
8004210: 0019 movs r1, r3
|
|
8004212: 687b ldr r3, [r7, #4]
|
|
8004214: 685a ldr r2, [r3, #4]
|
|
8004216: 4b4f ldr r3, [pc, #316] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004218: 430a orrs r2, r1
|
|
800421a: 655a str r2, [r3, #84] ; 0x54
|
|
}
|
|
#endif /* RCC_CCIPR_USART3SEL */
|
|
|
|
#if defined(LPUART1)
|
|
/*-------------------------- LPUART1 clock source configuration ------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
|
800421c: 687b ldr r3, [r7, #4]
|
|
800421e: 681b ldr r3, [r3, #0]
|
|
8004220: 2210 movs r2, #16
|
|
8004222: 4013 ands r3, r2
|
|
8004224: d009 beq.n 800423a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
|
|
|
/* Configure the LPUART1 clock source */
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
|
8004226: 4b4b ldr r3, [pc, #300] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004228: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
800422a: 4a50 ldr r2, [pc, #320] ; (800436c <HAL_RCCEx_PeriphCLKConfig+0x2dc>)
|
|
800422c: 4013 ands r3, r2
|
|
800422e: 0019 movs r1, r3
|
|
8004230: 687b ldr r3, [r7, #4]
|
|
8004232: 689a ldr r2, [r3, #8]
|
|
8004234: 4b47 ldr r3, [pc, #284] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004236: 430a orrs r2, r1
|
|
8004238: 655a str r2, [r3, #84] ; 0x54
|
|
}
|
|
#endif /* LPUART2 */
|
|
|
|
#if defined(RCC_CCIPR_LPTIM1SEL)
|
|
/*-------------------------- LPTIM1 clock source configuration -------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
|
|
800423a: 687b ldr r3, [r7, #4]
|
|
800423c: 681a ldr r2, [r3, #0]
|
|
800423e: 2380 movs r3, #128 ; 0x80
|
|
8004240: 009b lsls r3, r3, #2
|
|
8004242: 4013 ands r3, r2
|
|
8004244: d009 beq.n 800425a <HAL_RCCEx_PeriphCLKConfig+0x1ca>
|
|
{
|
|
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
|
8004246: 4b43 ldr r3, [pc, #268] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004248: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
800424a: 4a49 ldr r2, [pc, #292] ; (8004370 <HAL_RCCEx_PeriphCLKConfig+0x2e0>)
|
|
800424c: 4013 ands r3, r2
|
|
800424e: 0019 movs r1, r3
|
|
8004250: 687b ldr r3, [r7, #4]
|
|
8004252: 695a ldr r2, [r3, #20]
|
|
8004254: 4b3f ldr r3, [pc, #252] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004256: 430a orrs r2, r1
|
|
8004258: 655a str r2, [r3, #84] ; 0x54
|
|
}
|
|
#endif /* RCC_CCIPR_LPTIM1SEL */
|
|
|
|
#if defined(RCC_CCIPR_LPTIM2SEL)
|
|
/*-------------------------- LPTIM2 clock source configuration -------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
|
|
800425a: 687b ldr r3, [r7, #4]
|
|
800425c: 681a ldr r2, [r3, #0]
|
|
800425e: 2380 movs r3, #128 ; 0x80
|
|
8004260: 00db lsls r3, r3, #3
|
|
8004262: 4013 ands r3, r2
|
|
8004264: d009 beq.n 800427a <HAL_RCCEx_PeriphCLKConfig+0x1ea>
|
|
{
|
|
assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection));
|
|
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
|
|
8004266: 4b3b ldr r3, [pc, #236] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004268: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
800426a: 4a42 ldr r2, [pc, #264] ; (8004374 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
|
|
800426c: 4013 ands r3, r2
|
|
800426e: 0019 movs r1, r3
|
|
8004270: 687b ldr r3, [r7, #4]
|
|
8004272: 699a ldr r2, [r3, #24]
|
|
8004274: 4b37 ldr r3, [pc, #220] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004276: 430a orrs r2, r1
|
|
8004278: 655a str r2, [r3, #84] ; 0x54
|
|
}
|
|
#endif /* RCC_CCIPR_LPTIM2SEL */
|
|
|
|
/*-------------------------- I2C1 clock source configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
800427a: 687b ldr r3, [r7, #4]
|
|
800427c: 681b ldr r3, [r3, #0]
|
|
800427e: 2220 movs r2, #32
|
|
8004280: 4013 ands r3, r2
|
|
8004282: d009 beq.n 8004298 <HAL_RCCEx_PeriphCLKConfig+0x208>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
8004284: 4b33 ldr r3, [pc, #204] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004286: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8004288: 4a3b ldr r2, [pc, #236] ; (8004378 <HAL_RCCEx_PeriphCLKConfig+0x2e8>)
|
|
800428a: 4013 ands r3, r2
|
|
800428c: 0019 movs r1, r3
|
|
800428e: 687b ldr r3, [r7, #4]
|
|
8004290: 68da ldr r2, [r3, #12]
|
|
8004292: 4b30 ldr r3, [pc, #192] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004294: 430a orrs r2, r1
|
|
8004296: 655a str r2, [r3, #84] ; 0x54
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
|
|
}
|
|
}
|
|
#endif /* RNG */
|
|
/*-------------------------- ADC clock source configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
8004298: 687b ldr r3, [r7, #4]
|
|
800429a: 681a ldr r2, [r3, #0]
|
|
800429c: 2380 movs r3, #128 ; 0x80
|
|
800429e: 01db lsls r3, r3, #7
|
|
80042a0: 4013 ands r3, r2
|
|
80042a2: d015 beq.n 80042d0 <HAL_RCCEx_PeriphCLKConfig+0x240>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
|
|
|
|
/* Configure the ADC interface clock source */
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
80042a4: 4b2b ldr r3, [pc, #172] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80042a6: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80042a8: 009b lsls r3, r3, #2
|
|
80042aa: 0899 lsrs r1, r3, #2
|
|
80042ac: 687b ldr r3, [r7, #4]
|
|
80042ae: 69da ldr r2, [r3, #28]
|
|
80042b0: 4b28 ldr r3, [pc, #160] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80042b2: 430a orrs r2, r1
|
|
80042b4: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC)
|
|
80042b6: 687b ldr r3, [r7, #4]
|
|
80042b8: 69da ldr r2, [r3, #28]
|
|
80042ba: 2380 movs r3, #128 ; 0x80
|
|
80042bc: 05db lsls r3, r3, #23
|
|
80042be: 429a cmp r2, r3
|
|
80042c0: d106 bne.n 80042d0 <HAL_RCCEx_PeriphCLKConfig+0x240>
|
|
{
|
|
/* Enable PLLPCLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
|
|
80042c2: 4b24 ldr r3, [pc, #144] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80042c4: 68da ldr r2, [r3, #12]
|
|
80042c6: 4b23 ldr r3, [pc, #140] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80042c8: 2180 movs r1, #128 ; 0x80
|
|
80042ca: 0249 lsls r1, r1, #9
|
|
80042cc: 430a orrs r2, r1
|
|
80042ce: 60da str r2, [r3, #12]
|
|
}
|
|
#endif /* CEC */
|
|
|
|
#if defined(RCC_CCIPR_TIM1SEL)
|
|
/*-------------------------- TIM1 clock source configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
|
|
80042d0: 687b ldr r3, [r7, #4]
|
|
80042d2: 681a ldr r2, [r3, #0]
|
|
80042d4: 2380 movs r3, #128 ; 0x80
|
|
80042d6: 039b lsls r3, r3, #14
|
|
80042d8: 4013 ands r3, r2
|
|
80042da: d016 beq.n 800430a <HAL_RCCEx_PeriphCLKConfig+0x27a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
|
|
|
|
/* Configure the TIM1 clock source */
|
|
__HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
|
|
80042dc: 4b1d ldr r3, [pc, #116] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80042de: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80042e0: 4a26 ldr r2, [pc, #152] ; (800437c <HAL_RCCEx_PeriphCLKConfig+0x2ec>)
|
|
80042e2: 4013 ands r3, r2
|
|
80042e4: 0019 movs r1, r3
|
|
80042e6: 687b ldr r3, [r7, #4]
|
|
80042e8: 6a1a ldr r2, [r3, #32]
|
|
80042ea: 4b1a ldr r3, [pc, #104] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80042ec: 430a orrs r2, r1
|
|
80042ee: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
if (PeriphClkInit->Tim1ClockSelection == RCC_TIM1CLKSOURCE_PLL)
|
|
80042f0: 687b ldr r3, [r7, #4]
|
|
80042f2: 6a1a ldr r2, [r3, #32]
|
|
80042f4: 2380 movs r3, #128 ; 0x80
|
|
80042f6: 03db lsls r3, r3, #15
|
|
80042f8: 429a cmp r2, r3
|
|
80042fa: d106 bne.n 800430a <HAL_RCCEx_PeriphCLKConfig+0x27a>
|
|
{
|
|
/* Enable PLLQCLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
|
|
80042fc: 4b15 ldr r3, [pc, #84] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
80042fe: 68da ldr r2, [r3, #12]
|
|
8004300: 4b14 ldr r3, [pc, #80] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004302: 2180 movs r1, #128 ; 0x80
|
|
8004304: 0449 lsls r1, r1, #17
|
|
8004306: 430a orrs r2, r1
|
|
8004308: 60da str r2, [r3, #12]
|
|
}
|
|
}
|
|
#endif /* RCC_CCIPR_TIM15SEL */
|
|
|
|
/*-------------------------- I2S1 clock source configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1)
|
|
800430a: 687b ldr r3, [r7, #4]
|
|
800430c: 681a ldr r2, [r3, #0]
|
|
800430e: 2380 movs r3, #128 ; 0x80
|
|
8004310: 011b lsls r3, r3, #4
|
|
8004312: 4013 ands r3, r2
|
|
8004314: d016 beq.n 8004344 <HAL_RCCEx_PeriphCLKConfig+0x2b4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection));
|
|
|
|
/* Configure the I2S1 clock source */
|
|
__HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection);
|
|
8004316: 4b0f ldr r3, [pc, #60] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004318: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
800431a: 4a19 ldr r2, [pc, #100] ; (8004380 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
|
|
800431c: 4013 ands r3, r2
|
|
800431e: 0019 movs r1, r3
|
|
8004320: 687b ldr r3, [r7, #4]
|
|
8004322: 691a ldr r2, [r3, #16]
|
|
8004324: 4b0b ldr r3, [pc, #44] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004326: 430a orrs r2, r1
|
|
8004328: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL)
|
|
800432a: 687b ldr r3, [r7, #4]
|
|
800432c: 691a ldr r2, [r3, #16]
|
|
800432e: 2380 movs r3, #128 ; 0x80
|
|
8004330: 01db lsls r3, r3, #7
|
|
8004332: 429a cmp r2, r3
|
|
8004334: d106 bne.n 8004344 <HAL_RCCEx_PeriphCLKConfig+0x2b4>
|
|
{
|
|
/* Enable PLLPCLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
|
|
8004336: 4b07 ldr r3, [pc, #28] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
8004338: 68da ldr r2, [r3, #12]
|
|
800433a: 4b06 ldr r3, [pc, #24] ; (8004354 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
|
|
800433c: 2180 movs r1, #128 ; 0x80
|
|
800433e: 0249 lsls r1, r1, #9
|
|
8004340: 430a orrs r2, r1
|
|
8004342: 60da str r2, [r3, #12]
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
|
|
}
|
|
}
|
|
#endif /* FDCAN1 || FDCAN2 */
|
|
|
|
return status;
|
|
8004344: 2312 movs r3, #18
|
|
8004346: 18fb adds r3, r7, r3
|
|
8004348: 781b ldrb r3, [r3, #0]
|
|
}
|
|
800434a: 0018 movs r0, r3
|
|
800434c: 46bd mov sp, r7
|
|
800434e: b006 add sp, #24
|
|
8004350: bd80 pop {r7, pc}
|
|
8004352: 46c0 nop ; (mov r8, r8)
|
|
8004354: 40021000 .word 0x40021000
|
|
8004358: 40007000 .word 0x40007000
|
|
800435c: fffffcff .word 0xfffffcff
|
|
8004360: fffeffff .word 0xfffeffff
|
|
8004364: 00001388 .word 0x00001388
|
|
8004368: efffffff .word 0xefffffff
|
|
800436c: fffff3ff .word 0xfffff3ff
|
|
8004370: fff3ffff .word 0xfff3ffff
|
|
8004374: ffcfffff .word 0xffcfffff
|
|
8004378: ffffcfff .word 0xffffcfff
|
|
800437c: ffbfffff .word 0xffbfffff
|
|
8004380: ffff3fff .word 0xffff3fff
|
|
|
|
08004384 <HAL_TIM_Base_Init>:
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
8004384: b580 push {r7, lr}
|
|
8004386: b082 sub sp, #8
|
|
8004388: af00 add r7, sp, #0
|
|
800438a: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
800438c: 687b ldr r3, [r7, #4]
|
|
800438e: 2b00 cmp r3, #0
|
|
8004390: d101 bne.n 8004396 <HAL_TIM_Base_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004392: 2301 movs r3, #1
|
|
8004394: e04a b.n 800442c <HAL_TIM_Base_Init+0xa8>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8004396: 687b ldr r3, [r7, #4]
|
|
8004398: 223d movs r2, #61 ; 0x3d
|
|
800439a: 5c9b ldrb r3, [r3, r2]
|
|
800439c: b2db uxtb r3, r3
|
|
800439e: 2b00 cmp r3, #0
|
|
80043a0: d107 bne.n 80043b2 <HAL_TIM_Base_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
80043a2: 687b ldr r3, [r7, #4]
|
|
80043a4: 223c movs r2, #60 ; 0x3c
|
|
80043a6: 2100 movs r1, #0
|
|
80043a8: 5499 strb r1, [r3, r2]
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Base_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_TIM_Base_MspInit(htim);
|
|
80043aa: 687b ldr r3, [r7, #4]
|
|
80043ac: 0018 movs r0, r3
|
|
80043ae: f7fd fb59 bl 8001a64 <HAL_TIM_Base_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80043b2: 687b ldr r3, [r7, #4]
|
|
80043b4: 223d movs r2, #61 ; 0x3d
|
|
80043b6: 2102 movs r1, #2
|
|
80043b8: 5499 strb r1, [r3, r2]
|
|
|
|
/* Set the Time Base configuration */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
80043ba: 687b ldr r3, [r7, #4]
|
|
80043bc: 681a ldr r2, [r3, #0]
|
|
80043be: 687b ldr r3, [r7, #4]
|
|
80043c0: 3304 adds r3, #4
|
|
80043c2: 0019 movs r1, r3
|
|
80043c4: 0010 movs r0, r2
|
|
80043c6: f000 fd1d bl 8004e04 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
80043ca: 687b ldr r3, [r7, #4]
|
|
80043cc: 2248 movs r2, #72 ; 0x48
|
|
80043ce: 2101 movs r1, #1
|
|
80043d0: 5499 strb r1, [r3, r2]
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
80043d2: 687b ldr r3, [r7, #4]
|
|
80043d4: 223e movs r2, #62 ; 0x3e
|
|
80043d6: 2101 movs r1, #1
|
|
80043d8: 5499 strb r1, [r3, r2]
|
|
80043da: 687b ldr r3, [r7, #4]
|
|
80043dc: 223f movs r2, #63 ; 0x3f
|
|
80043de: 2101 movs r1, #1
|
|
80043e0: 5499 strb r1, [r3, r2]
|
|
80043e2: 687b ldr r3, [r7, #4]
|
|
80043e4: 2240 movs r2, #64 ; 0x40
|
|
80043e6: 2101 movs r1, #1
|
|
80043e8: 5499 strb r1, [r3, r2]
|
|
80043ea: 687b ldr r3, [r7, #4]
|
|
80043ec: 2241 movs r2, #65 ; 0x41
|
|
80043ee: 2101 movs r1, #1
|
|
80043f0: 5499 strb r1, [r3, r2]
|
|
80043f2: 687b ldr r3, [r7, #4]
|
|
80043f4: 2242 movs r2, #66 ; 0x42
|
|
80043f6: 2101 movs r1, #1
|
|
80043f8: 5499 strb r1, [r3, r2]
|
|
80043fa: 687b ldr r3, [r7, #4]
|
|
80043fc: 2243 movs r2, #67 ; 0x43
|
|
80043fe: 2101 movs r1, #1
|
|
8004400: 5499 strb r1, [r3, r2]
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8004402: 687b ldr r3, [r7, #4]
|
|
8004404: 2244 movs r2, #68 ; 0x44
|
|
8004406: 2101 movs r1, #1
|
|
8004408: 5499 strb r1, [r3, r2]
|
|
800440a: 687b ldr r3, [r7, #4]
|
|
800440c: 2245 movs r2, #69 ; 0x45
|
|
800440e: 2101 movs r1, #1
|
|
8004410: 5499 strb r1, [r3, r2]
|
|
8004412: 687b ldr r3, [r7, #4]
|
|
8004414: 2246 movs r2, #70 ; 0x46
|
|
8004416: 2101 movs r1, #1
|
|
8004418: 5499 strb r1, [r3, r2]
|
|
800441a: 687b ldr r3, [r7, #4]
|
|
800441c: 2247 movs r2, #71 ; 0x47
|
|
800441e: 2101 movs r1, #1
|
|
8004420: 5499 strb r1, [r3, r2]
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8004422: 687b ldr r3, [r7, #4]
|
|
8004424: 223d movs r2, #61 ; 0x3d
|
|
8004426: 2101 movs r1, #1
|
|
8004428: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_OK;
|
|
800442a: 2300 movs r3, #0
|
|
}
|
|
800442c: 0018 movs r0, r3
|
|
800442e: 46bd mov sp, r7
|
|
8004430: b002 add sp, #8
|
|
8004432: bd80 pop {r7, pc}
|
|
|
|
08004434 <HAL_TIM_Base_Start_IT>:
|
|
* @brief Starts the TIM Base generation in interrupt mode.
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
|
|
{
|
|
8004434: b580 push {r7, lr}
|
|
8004436: b084 sub sp, #16
|
|
8004438: af00 add r7, sp, #0
|
|
800443a: 6078 str r0, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
|
/* Check the TIM state */
|
|
if (htim->State != HAL_TIM_STATE_READY)
|
|
800443c: 687b ldr r3, [r7, #4]
|
|
800443e: 223d movs r2, #61 ; 0x3d
|
|
8004440: 5c9b ldrb r3, [r3, r2]
|
|
8004442: b2db uxtb r3, r3
|
|
8004444: 2b01 cmp r3, #1
|
|
8004446: d001 beq.n 800444c <HAL_TIM_Base_Start_IT+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
8004448: 2301 movs r3, #1
|
|
800444a: e03d b.n 80044c8 <HAL_TIM_Base_Start_IT+0x94>
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800444c: 687b ldr r3, [r7, #4]
|
|
800444e: 223d movs r2, #61 ; 0x3d
|
|
8004450: 2102 movs r1, #2
|
|
8004452: 5499 strb r1, [r3, r2]
|
|
|
|
/* Enable the TIM Update interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
|
|
8004454: 687b ldr r3, [r7, #4]
|
|
8004456: 681b ldr r3, [r3, #0]
|
|
8004458: 68da ldr r2, [r3, #12]
|
|
800445a: 687b ldr r3, [r7, #4]
|
|
800445c: 681b ldr r3, [r3, #0]
|
|
800445e: 2101 movs r1, #1
|
|
8004460: 430a orrs r2, r1
|
|
8004462: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8004464: 687b ldr r3, [r7, #4]
|
|
8004466: 681b ldr r3, [r3, #0]
|
|
8004468: 4a19 ldr r2, [pc, #100] ; (80044d0 <HAL_TIM_Base_Start_IT+0x9c>)
|
|
800446a: 4293 cmp r3, r2
|
|
800446c: d00a beq.n 8004484 <HAL_TIM_Base_Start_IT+0x50>
|
|
800446e: 687b ldr r3, [r7, #4]
|
|
8004470: 681a ldr r2, [r3, #0]
|
|
8004472: 2380 movs r3, #128 ; 0x80
|
|
8004474: 05db lsls r3, r3, #23
|
|
8004476: 429a cmp r2, r3
|
|
8004478: d004 beq.n 8004484 <HAL_TIM_Base_Start_IT+0x50>
|
|
800447a: 687b ldr r3, [r7, #4]
|
|
800447c: 681b ldr r3, [r3, #0]
|
|
800447e: 4a15 ldr r2, [pc, #84] ; (80044d4 <HAL_TIM_Base_Start_IT+0xa0>)
|
|
8004480: 4293 cmp r3, r2
|
|
8004482: d116 bne.n 80044b2 <HAL_TIM_Base_Start_IT+0x7e>
|
|
{
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
8004484: 687b ldr r3, [r7, #4]
|
|
8004486: 681b ldr r3, [r3, #0]
|
|
8004488: 689b ldr r3, [r3, #8]
|
|
800448a: 4a13 ldr r2, [pc, #76] ; (80044d8 <HAL_TIM_Base_Start_IT+0xa4>)
|
|
800448c: 4013 ands r3, r2
|
|
800448e: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8004490: 68fb ldr r3, [r7, #12]
|
|
8004492: 2b06 cmp r3, #6
|
|
8004494: d016 beq.n 80044c4 <HAL_TIM_Base_Start_IT+0x90>
|
|
8004496: 68fa ldr r2, [r7, #12]
|
|
8004498: 2380 movs r3, #128 ; 0x80
|
|
800449a: 025b lsls r3, r3, #9
|
|
800449c: 429a cmp r2, r3
|
|
800449e: d011 beq.n 80044c4 <HAL_TIM_Base_Start_IT+0x90>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
80044a0: 687b ldr r3, [r7, #4]
|
|
80044a2: 681b ldr r3, [r3, #0]
|
|
80044a4: 681a ldr r2, [r3, #0]
|
|
80044a6: 687b ldr r3, [r7, #4]
|
|
80044a8: 681b ldr r3, [r3, #0]
|
|
80044aa: 2101 movs r1, #1
|
|
80044ac: 430a orrs r2, r1
|
|
80044ae: 601a str r2, [r3, #0]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
80044b0: e008 b.n 80044c4 <HAL_TIM_Base_Start_IT+0x90>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
80044b2: 687b ldr r3, [r7, #4]
|
|
80044b4: 681b ldr r3, [r3, #0]
|
|
80044b6: 681a ldr r2, [r3, #0]
|
|
80044b8: 687b ldr r3, [r7, #4]
|
|
80044ba: 681b ldr r3, [r3, #0]
|
|
80044bc: 2101 movs r1, #1
|
|
80044be: 430a orrs r2, r1
|
|
80044c0: 601a str r2, [r3, #0]
|
|
80044c2: e000 b.n 80044c6 <HAL_TIM_Base_Start_IT+0x92>
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
80044c4: 46c0 nop ; (mov r8, r8)
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80044c6: 2300 movs r3, #0
|
|
}
|
|
80044c8: 0018 movs r0, r3
|
|
80044ca: 46bd mov sp, r7
|
|
80044cc: b004 add sp, #16
|
|
80044ce: bd80 pop {r7, pc}
|
|
80044d0: 40012c00 .word 0x40012c00
|
|
80044d4: 40000400 .word 0x40000400
|
|
80044d8: 00010007 .word 0x00010007
|
|
|
|
080044dc <HAL_TIM_Base_Stop_IT>:
|
|
* @brief Stops the TIM Base generation in interrupt mode.
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
|
|
{
|
|
80044dc: b580 push {r7, lr}
|
|
80044de: b082 sub sp, #8
|
|
80044e0: af00 add r7, sp, #0
|
|
80044e2: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
|
/* Disable the TIM Update interrupt */
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
|
|
80044e4: 687b ldr r3, [r7, #4]
|
|
80044e6: 681b ldr r3, [r3, #0]
|
|
80044e8: 68da ldr r2, [r3, #12]
|
|
80044ea: 687b ldr r3, [r7, #4]
|
|
80044ec: 681b ldr r3, [r3, #0]
|
|
80044ee: 2101 movs r1, #1
|
|
80044f0: 438a bics r2, r1
|
|
80044f2: 60da str r2, [r3, #12]
|
|
|
|
/* Disable the Peripheral */
|
|
__HAL_TIM_DISABLE(htim);
|
|
80044f4: 687b ldr r3, [r7, #4]
|
|
80044f6: 681b ldr r3, [r3, #0]
|
|
80044f8: 6a1b ldr r3, [r3, #32]
|
|
80044fa: 4a0d ldr r2, [pc, #52] ; (8004530 <HAL_TIM_Base_Stop_IT+0x54>)
|
|
80044fc: 4013 ands r3, r2
|
|
80044fe: d10d bne.n 800451c <HAL_TIM_Base_Stop_IT+0x40>
|
|
8004500: 687b ldr r3, [r7, #4]
|
|
8004502: 681b ldr r3, [r3, #0]
|
|
8004504: 6a1b ldr r3, [r3, #32]
|
|
8004506: 4a0b ldr r2, [pc, #44] ; (8004534 <HAL_TIM_Base_Stop_IT+0x58>)
|
|
8004508: 4013 ands r3, r2
|
|
800450a: d107 bne.n 800451c <HAL_TIM_Base_Stop_IT+0x40>
|
|
800450c: 687b ldr r3, [r7, #4]
|
|
800450e: 681b ldr r3, [r3, #0]
|
|
8004510: 681a ldr r2, [r3, #0]
|
|
8004512: 687b ldr r3, [r7, #4]
|
|
8004514: 681b ldr r3, [r3, #0]
|
|
8004516: 2101 movs r1, #1
|
|
8004518: 438a bics r2, r1
|
|
800451a: 601a str r2, [r3, #0]
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800451c: 687b ldr r3, [r7, #4]
|
|
800451e: 223d movs r2, #61 ; 0x3d
|
|
8004520: 2101 movs r1, #1
|
|
8004522: 5499 strb r1, [r3, r2]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8004524: 2300 movs r3, #0
|
|
}
|
|
8004526: 0018 movs r0, r3
|
|
8004528: 46bd mov sp, r7
|
|
800452a: b002 add sp, #8
|
|
800452c: bd80 pop {r7, pc}
|
|
800452e: 46c0 nop ; (mov r8, r8)
|
|
8004530: 00001111 .word 0x00001111
|
|
8004534: 00000444 .word 0x00000444
|
|
|
|
08004538 <HAL_TIM_PWM_Init>:
|
|
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
|
|
* @param htim TIM PWM handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
8004538: b580 push {r7, lr}
|
|
800453a: b082 sub sp, #8
|
|
800453c: af00 add r7, sp, #0
|
|
800453e: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
8004540: 687b ldr r3, [r7, #4]
|
|
8004542: 2b00 cmp r3, #0
|
|
8004544: d101 bne.n 800454a <HAL_TIM_PWM_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004546: 2301 movs r3, #1
|
|
8004548: e04a b.n 80045e0 <HAL_TIM_PWM_Init+0xa8>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
800454a: 687b ldr r3, [r7, #4]
|
|
800454c: 223d movs r2, #61 ; 0x3d
|
|
800454e: 5c9b ldrb r3, [r3, r2]
|
|
8004550: b2db uxtb r3, r3
|
|
8004552: 2b00 cmp r3, #0
|
|
8004554: d107 bne.n 8004566 <HAL_TIM_PWM_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8004556: 687b ldr r3, [r7, #4]
|
|
8004558: 223c movs r2, #60 ; 0x3c
|
|
800455a: 2100 movs r1, #0
|
|
800455c: 5499 strb r1, [r3, r2]
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->PWM_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_PWM_MspInit(htim);
|
|
800455e: 687b ldr r3, [r7, #4]
|
|
8004560: 0018 movs r0, r3
|
|
8004562: f000 f841 bl 80045e8 <HAL_TIM_PWM_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8004566: 687b ldr r3, [r7, #4]
|
|
8004568: 223d movs r2, #61 ; 0x3d
|
|
800456a: 2102 movs r1, #2
|
|
800456c: 5499 strb r1, [r3, r2]
|
|
|
|
/* Init the base time for the PWM */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
800456e: 687b ldr r3, [r7, #4]
|
|
8004570: 681a ldr r2, [r3, #0]
|
|
8004572: 687b ldr r3, [r7, #4]
|
|
8004574: 3304 adds r3, #4
|
|
8004576: 0019 movs r1, r3
|
|
8004578: 0010 movs r0, r2
|
|
800457a: f000 fc43 bl 8004e04 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
800457e: 687b ldr r3, [r7, #4]
|
|
8004580: 2248 movs r2, #72 ; 0x48
|
|
8004582: 2101 movs r1, #1
|
|
8004584: 5499 strb r1, [r3, r2]
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8004586: 687b ldr r3, [r7, #4]
|
|
8004588: 223e movs r2, #62 ; 0x3e
|
|
800458a: 2101 movs r1, #1
|
|
800458c: 5499 strb r1, [r3, r2]
|
|
800458e: 687b ldr r3, [r7, #4]
|
|
8004590: 223f movs r2, #63 ; 0x3f
|
|
8004592: 2101 movs r1, #1
|
|
8004594: 5499 strb r1, [r3, r2]
|
|
8004596: 687b ldr r3, [r7, #4]
|
|
8004598: 2240 movs r2, #64 ; 0x40
|
|
800459a: 2101 movs r1, #1
|
|
800459c: 5499 strb r1, [r3, r2]
|
|
800459e: 687b ldr r3, [r7, #4]
|
|
80045a0: 2241 movs r2, #65 ; 0x41
|
|
80045a2: 2101 movs r1, #1
|
|
80045a4: 5499 strb r1, [r3, r2]
|
|
80045a6: 687b ldr r3, [r7, #4]
|
|
80045a8: 2242 movs r2, #66 ; 0x42
|
|
80045aa: 2101 movs r1, #1
|
|
80045ac: 5499 strb r1, [r3, r2]
|
|
80045ae: 687b ldr r3, [r7, #4]
|
|
80045b0: 2243 movs r2, #67 ; 0x43
|
|
80045b2: 2101 movs r1, #1
|
|
80045b4: 5499 strb r1, [r3, r2]
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
80045b6: 687b ldr r3, [r7, #4]
|
|
80045b8: 2244 movs r2, #68 ; 0x44
|
|
80045ba: 2101 movs r1, #1
|
|
80045bc: 5499 strb r1, [r3, r2]
|
|
80045be: 687b ldr r3, [r7, #4]
|
|
80045c0: 2245 movs r2, #69 ; 0x45
|
|
80045c2: 2101 movs r1, #1
|
|
80045c4: 5499 strb r1, [r3, r2]
|
|
80045c6: 687b ldr r3, [r7, #4]
|
|
80045c8: 2246 movs r2, #70 ; 0x46
|
|
80045ca: 2101 movs r1, #1
|
|
80045cc: 5499 strb r1, [r3, r2]
|
|
80045ce: 687b ldr r3, [r7, #4]
|
|
80045d0: 2247 movs r2, #71 ; 0x47
|
|
80045d2: 2101 movs r1, #1
|
|
80045d4: 5499 strb r1, [r3, r2]
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80045d6: 687b ldr r3, [r7, #4]
|
|
80045d8: 223d movs r2, #61 ; 0x3d
|
|
80045da: 2101 movs r1, #1
|
|
80045dc: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_OK;
|
|
80045de: 2300 movs r3, #0
|
|
}
|
|
80045e0: 0018 movs r0, r3
|
|
80045e2: 46bd mov sp, r7
|
|
80045e4: b002 add sp, #8
|
|
80045e6: bd80 pop {r7, pc}
|
|
|
|
080045e8 <HAL_TIM_PWM_MspInit>:
|
|
* @brief Initializes the TIM PWM MSP.
|
|
* @param htim TIM PWM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
|
|
{
|
|
80045e8: b580 push {r7, lr}
|
|
80045ea: b082 sub sp, #8
|
|
80045ec: af00 add r7, sp, #0
|
|
80045ee: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_MspInit could be implemented in the user file
|
|
*/
|
|
}
|
|
80045f0: 46c0 nop ; (mov r8, r8)
|
|
80045f2: 46bd mov sp, r7
|
|
80045f4: b002 add sp, #8
|
|
80045f6: bd80 pop {r7, pc}
|
|
|
|
080045f8 <HAL_TIM_PWM_Start>:
|
|
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
80045f8: b580 push {r7, lr}
|
|
80045fa: b084 sub sp, #16
|
|
80045fc: af00 add r7, sp, #0
|
|
80045fe: 6078 str r0, [r7, #4]
|
|
8004600: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
|
/* Check the TIM channel state */
|
|
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
|
8004602: 683b ldr r3, [r7, #0]
|
|
8004604: 2b00 cmp r3, #0
|
|
8004606: d108 bne.n 800461a <HAL_TIM_PWM_Start+0x22>
|
|
8004608: 687b ldr r3, [r7, #4]
|
|
800460a: 223e movs r2, #62 ; 0x3e
|
|
800460c: 5c9b ldrb r3, [r3, r2]
|
|
800460e: b2db uxtb r3, r3
|
|
8004610: 3b01 subs r3, #1
|
|
8004612: 1e5a subs r2, r3, #1
|
|
8004614: 4193 sbcs r3, r2
|
|
8004616: b2db uxtb r3, r3
|
|
8004618: e037 b.n 800468a <HAL_TIM_PWM_Start+0x92>
|
|
800461a: 683b ldr r3, [r7, #0]
|
|
800461c: 2b04 cmp r3, #4
|
|
800461e: d108 bne.n 8004632 <HAL_TIM_PWM_Start+0x3a>
|
|
8004620: 687b ldr r3, [r7, #4]
|
|
8004622: 223f movs r2, #63 ; 0x3f
|
|
8004624: 5c9b ldrb r3, [r3, r2]
|
|
8004626: b2db uxtb r3, r3
|
|
8004628: 3b01 subs r3, #1
|
|
800462a: 1e5a subs r2, r3, #1
|
|
800462c: 4193 sbcs r3, r2
|
|
800462e: b2db uxtb r3, r3
|
|
8004630: e02b b.n 800468a <HAL_TIM_PWM_Start+0x92>
|
|
8004632: 683b ldr r3, [r7, #0]
|
|
8004634: 2b08 cmp r3, #8
|
|
8004636: d108 bne.n 800464a <HAL_TIM_PWM_Start+0x52>
|
|
8004638: 687b ldr r3, [r7, #4]
|
|
800463a: 2240 movs r2, #64 ; 0x40
|
|
800463c: 5c9b ldrb r3, [r3, r2]
|
|
800463e: b2db uxtb r3, r3
|
|
8004640: 3b01 subs r3, #1
|
|
8004642: 1e5a subs r2, r3, #1
|
|
8004644: 4193 sbcs r3, r2
|
|
8004646: b2db uxtb r3, r3
|
|
8004648: e01f b.n 800468a <HAL_TIM_PWM_Start+0x92>
|
|
800464a: 683b ldr r3, [r7, #0]
|
|
800464c: 2b0c cmp r3, #12
|
|
800464e: d108 bne.n 8004662 <HAL_TIM_PWM_Start+0x6a>
|
|
8004650: 687b ldr r3, [r7, #4]
|
|
8004652: 2241 movs r2, #65 ; 0x41
|
|
8004654: 5c9b ldrb r3, [r3, r2]
|
|
8004656: b2db uxtb r3, r3
|
|
8004658: 3b01 subs r3, #1
|
|
800465a: 1e5a subs r2, r3, #1
|
|
800465c: 4193 sbcs r3, r2
|
|
800465e: b2db uxtb r3, r3
|
|
8004660: e013 b.n 800468a <HAL_TIM_PWM_Start+0x92>
|
|
8004662: 683b ldr r3, [r7, #0]
|
|
8004664: 2b10 cmp r3, #16
|
|
8004666: d108 bne.n 800467a <HAL_TIM_PWM_Start+0x82>
|
|
8004668: 687b ldr r3, [r7, #4]
|
|
800466a: 2242 movs r2, #66 ; 0x42
|
|
800466c: 5c9b ldrb r3, [r3, r2]
|
|
800466e: b2db uxtb r3, r3
|
|
8004670: 3b01 subs r3, #1
|
|
8004672: 1e5a subs r2, r3, #1
|
|
8004674: 4193 sbcs r3, r2
|
|
8004676: b2db uxtb r3, r3
|
|
8004678: e007 b.n 800468a <HAL_TIM_PWM_Start+0x92>
|
|
800467a: 687b ldr r3, [r7, #4]
|
|
800467c: 2243 movs r2, #67 ; 0x43
|
|
800467e: 5c9b ldrb r3, [r3, r2]
|
|
8004680: b2db uxtb r3, r3
|
|
8004682: 3b01 subs r3, #1
|
|
8004684: 1e5a subs r2, r3, #1
|
|
8004686: 4193 sbcs r3, r2
|
|
8004688: b2db uxtb r3, r3
|
|
800468a: 2b00 cmp r3, #0
|
|
800468c: d001 beq.n 8004692 <HAL_TIM_PWM_Start+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
800468e: 2301 movs r3, #1
|
|
8004690: e081 b.n 8004796 <HAL_TIM_PWM_Start+0x19e>
|
|
}
|
|
|
|
/* Set the TIM channel state */
|
|
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8004692: 683b ldr r3, [r7, #0]
|
|
8004694: 2b00 cmp r3, #0
|
|
8004696: d104 bne.n 80046a2 <HAL_TIM_PWM_Start+0xaa>
|
|
8004698: 687b ldr r3, [r7, #4]
|
|
800469a: 223e movs r2, #62 ; 0x3e
|
|
800469c: 2102 movs r1, #2
|
|
800469e: 5499 strb r1, [r3, r2]
|
|
80046a0: e023 b.n 80046ea <HAL_TIM_PWM_Start+0xf2>
|
|
80046a2: 683b ldr r3, [r7, #0]
|
|
80046a4: 2b04 cmp r3, #4
|
|
80046a6: d104 bne.n 80046b2 <HAL_TIM_PWM_Start+0xba>
|
|
80046a8: 687b ldr r3, [r7, #4]
|
|
80046aa: 223f movs r2, #63 ; 0x3f
|
|
80046ac: 2102 movs r1, #2
|
|
80046ae: 5499 strb r1, [r3, r2]
|
|
80046b0: e01b b.n 80046ea <HAL_TIM_PWM_Start+0xf2>
|
|
80046b2: 683b ldr r3, [r7, #0]
|
|
80046b4: 2b08 cmp r3, #8
|
|
80046b6: d104 bne.n 80046c2 <HAL_TIM_PWM_Start+0xca>
|
|
80046b8: 687b ldr r3, [r7, #4]
|
|
80046ba: 2240 movs r2, #64 ; 0x40
|
|
80046bc: 2102 movs r1, #2
|
|
80046be: 5499 strb r1, [r3, r2]
|
|
80046c0: e013 b.n 80046ea <HAL_TIM_PWM_Start+0xf2>
|
|
80046c2: 683b ldr r3, [r7, #0]
|
|
80046c4: 2b0c cmp r3, #12
|
|
80046c6: d104 bne.n 80046d2 <HAL_TIM_PWM_Start+0xda>
|
|
80046c8: 687b ldr r3, [r7, #4]
|
|
80046ca: 2241 movs r2, #65 ; 0x41
|
|
80046cc: 2102 movs r1, #2
|
|
80046ce: 5499 strb r1, [r3, r2]
|
|
80046d0: e00b b.n 80046ea <HAL_TIM_PWM_Start+0xf2>
|
|
80046d2: 683b ldr r3, [r7, #0]
|
|
80046d4: 2b10 cmp r3, #16
|
|
80046d6: d104 bne.n 80046e2 <HAL_TIM_PWM_Start+0xea>
|
|
80046d8: 687b ldr r3, [r7, #4]
|
|
80046da: 2242 movs r2, #66 ; 0x42
|
|
80046dc: 2102 movs r1, #2
|
|
80046de: 5499 strb r1, [r3, r2]
|
|
80046e0: e003 b.n 80046ea <HAL_TIM_PWM_Start+0xf2>
|
|
80046e2: 687b ldr r3, [r7, #4]
|
|
80046e4: 2243 movs r2, #67 ; 0x43
|
|
80046e6: 2102 movs r1, #2
|
|
80046e8: 5499 strb r1, [r3, r2]
|
|
|
|
/* Enable the Capture compare channel */
|
|
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
80046ea: 687b ldr r3, [r7, #4]
|
|
80046ec: 681b ldr r3, [r3, #0]
|
|
80046ee: 6839 ldr r1, [r7, #0]
|
|
80046f0: 2201 movs r2, #1
|
|
80046f2: 0018 movs r0, r3
|
|
80046f4: f000 ff34 bl 8005560 <TIM_CCxChannelCmd>
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
80046f8: 687b ldr r3, [r7, #4]
|
|
80046fa: 681b ldr r3, [r3, #0]
|
|
80046fc: 4a28 ldr r2, [pc, #160] ; (80047a0 <HAL_TIM_PWM_Start+0x1a8>)
|
|
80046fe: 4293 cmp r3, r2
|
|
8004700: d009 beq.n 8004716 <HAL_TIM_PWM_Start+0x11e>
|
|
8004702: 687b ldr r3, [r7, #4]
|
|
8004704: 681b ldr r3, [r3, #0]
|
|
8004706: 4a27 ldr r2, [pc, #156] ; (80047a4 <HAL_TIM_PWM_Start+0x1ac>)
|
|
8004708: 4293 cmp r3, r2
|
|
800470a: d004 beq.n 8004716 <HAL_TIM_PWM_Start+0x11e>
|
|
800470c: 687b ldr r3, [r7, #4]
|
|
800470e: 681b ldr r3, [r3, #0]
|
|
8004710: 4a25 ldr r2, [pc, #148] ; (80047a8 <HAL_TIM_PWM_Start+0x1b0>)
|
|
8004712: 4293 cmp r3, r2
|
|
8004714: d101 bne.n 800471a <HAL_TIM_PWM_Start+0x122>
|
|
8004716: 2301 movs r3, #1
|
|
8004718: e000 b.n 800471c <HAL_TIM_PWM_Start+0x124>
|
|
800471a: 2300 movs r3, #0
|
|
800471c: 2b00 cmp r3, #0
|
|
800471e: d008 beq.n 8004732 <HAL_TIM_PWM_Start+0x13a>
|
|
{
|
|
/* Enable the main output */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
8004720: 687b ldr r3, [r7, #4]
|
|
8004722: 681b ldr r3, [r3, #0]
|
|
8004724: 6c5a ldr r2, [r3, #68] ; 0x44
|
|
8004726: 687b ldr r3, [r7, #4]
|
|
8004728: 681b ldr r3, [r3, #0]
|
|
800472a: 2180 movs r1, #128 ; 0x80
|
|
800472c: 0209 lsls r1, r1, #8
|
|
800472e: 430a orrs r2, r1
|
|
8004730: 645a str r2, [r3, #68] ; 0x44
|
|
}
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8004732: 687b ldr r3, [r7, #4]
|
|
8004734: 681b ldr r3, [r3, #0]
|
|
8004736: 4a1a ldr r2, [pc, #104] ; (80047a0 <HAL_TIM_PWM_Start+0x1a8>)
|
|
8004738: 4293 cmp r3, r2
|
|
800473a: d00a beq.n 8004752 <HAL_TIM_PWM_Start+0x15a>
|
|
800473c: 687b ldr r3, [r7, #4]
|
|
800473e: 681a ldr r2, [r3, #0]
|
|
8004740: 2380 movs r3, #128 ; 0x80
|
|
8004742: 05db lsls r3, r3, #23
|
|
8004744: 429a cmp r2, r3
|
|
8004746: d004 beq.n 8004752 <HAL_TIM_PWM_Start+0x15a>
|
|
8004748: 687b ldr r3, [r7, #4]
|
|
800474a: 681b ldr r3, [r3, #0]
|
|
800474c: 4a17 ldr r2, [pc, #92] ; (80047ac <HAL_TIM_PWM_Start+0x1b4>)
|
|
800474e: 4293 cmp r3, r2
|
|
8004750: d116 bne.n 8004780 <HAL_TIM_PWM_Start+0x188>
|
|
{
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
8004752: 687b ldr r3, [r7, #4]
|
|
8004754: 681b ldr r3, [r3, #0]
|
|
8004756: 689b ldr r3, [r3, #8]
|
|
8004758: 4a15 ldr r2, [pc, #84] ; (80047b0 <HAL_TIM_PWM_Start+0x1b8>)
|
|
800475a: 4013 ands r3, r2
|
|
800475c: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
800475e: 68fb ldr r3, [r7, #12]
|
|
8004760: 2b06 cmp r3, #6
|
|
8004762: d016 beq.n 8004792 <HAL_TIM_PWM_Start+0x19a>
|
|
8004764: 68fa ldr r2, [r7, #12]
|
|
8004766: 2380 movs r3, #128 ; 0x80
|
|
8004768: 025b lsls r3, r3, #9
|
|
800476a: 429a cmp r2, r3
|
|
800476c: d011 beq.n 8004792 <HAL_TIM_PWM_Start+0x19a>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
800476e: 687b ldr r3, [r7, #4]
|
|
8004770: 681b ldr r3, [r3, #0]
|
|
8004772: 681a ldr r2, [r3, #0]
|
|
8004774: 687b ldr r3, [r7, #4]
|
|
8004776: 681b ldr r3, [r3, #0]
|
|
8004778: 2101 movs r1, #1
|
|
800477a: 430a orrs r2, r1
|
|
800477c: 601a str r2, [r3, #0]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
800477e: e008 b.n 8004792 <HAL_TIM_PWM_Start+0x19a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8004780: 687b ldr r3, [r7, #4]
|
|
8004782: 681b ldr r3, [r3, #0]
|
|
8004784: 681a ldr r2, [r3, #0]
|
|
8004786: 687b ldr r3, [r7, #4]
|
|
8004788: 681b ldr r3, [r3, #0]
|
|
800478a: 2101 movs r1, #1
|
|
800478c: 430a orrs r2, r1
|
|
800478e: 601a str r2, [r3, #0]
|
|
8004790: e000 b.n 8004794 <HAL_TIM_PWM_Start+0x19c>
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8004792: 46c0 nop ; (mov r8, r8)
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8004794: 2300 movs r3, #0
|
|
}
|
|
8004796: 0018 movs r0, r3
|
|
8004798: 46bd mov sp, r7
|
|
800479a: b004 add sp, #16
|
|
800479c: bd80 pop {r7, pc}
|
|
800479e: 46c0 nop ; (mov r8, r8)
|
|
80047a0: 40012c00 .word 0x40012c00
|
|
80047a4: 40014400 .word 0x40014400
|
|
80047a8: 40014800 .word 0x40014800
|
|
80047ac: 40000400 .word 0x40000400
|
|
80047b0: 00010007 .word 0x00010007
|
|
|
|
080047b4 <HAL_TIM_IRQHandler>:
|
|
* @brief This function handles TIM interrupts requests.
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|
{
|
|
80047b4: b580 push {r7, lr}
|
|
80047b6: b082 sub sp, #8
|
|
80047b8: af00 add r7, sp, #0
|
|
80047ba: 6078 str r0, [r7, #4]
|
|
/* Capture compare 1 event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
|
|
80047bc: 687b ldr r3, [r7, #4]
|
|
80047be: 681b ldr r3, [r3, #0]
|
|
80047c0: 691b ldr r3, [r3, #16]
|
|
80047c2: 2202 movs r2, #2
|
|
80047c4: 4013 ands r3, r2
|
|
80047c6: 2b02 cmp r3, #2
|
|
80047c8: d124 bne.n 8004814 <HAL_TIM_IRQHandler+0x60>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
|
|
80047ca: 687b ldr r3, [r7, #4]
|
|
80047cc: 681b ldr r3, [r3, #0]
|
|
80047ce: 68db ldr r3, [r3, #12]
|
|
80047d0: 2202 movs r2, #2
|
|
80047d2: 4013 ands r3, r2
|
|
80047d4: 2b02 cmp r3, #2
|
|
80047d6: d11d bne.n 8004814 <HAL_TIM_IRQHandler+0x60>
|
|
{
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
|
|
80047d8: 687b ldr r3, [r7, #4]
|
|
80047da: 681b ldr r3, [r3, #0]
|
|
80047dc: 2203 movs r2, #3
|
|
80047de: 4252 negs r2, r2
|
|
80047e0: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
80047e2: 687b ldr r3, [r7, #4]
|
|
80047e4: 2201 movs r2, #1
|
|
80047e6: 771a strb r2, [r3, #28]
|
|
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
|
|
80047e8: 687b ldr r3, [r7, #4]
|
|
80047ea: 681b ldr r3, [r3, #0]
|
|
80047ec: 699b ldr r3, [r3, #24]
|
|
80047ee: 2203 movs r2, #3
|
|
80047f0: 4013 ands r3, r2
|
|
80047f2: d004 beq.n 80047fe <HAL_TIM_IRQHandler+0x4a>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
80047f4: 687b ldr r3, [r7, #4]
|
|
80047f6: 0018 movs r0, r3
|
|
80047f8: f000 faec bl 8004dd4 <HAL_TIM_IC_CaptureCallback>
|
|
80047fc: e007 b.n 800480e <HAL_TIM_IRQHandler+0x5a>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
80047fe: 687b ldr r3, [r7, #4]
|
|
8004800: 0018 movs r0, r3
|
|
8004802: f000 fadf bl 8004dc4 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8004806: 687b ldr r3, [r7, #4]
|
|
8004808: 0018 movs r0, r3
|
|
800480a: f000 faeb bl 8004de4 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800480e: 687b ldr r3, [r7, #4]
|
|
8004810: 2200 movs r2, #0
|
|
8004812: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
}
|
|
/* Capture compare 2 event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
|
|
8004814: 687b ldr r3, [r7, #4]
|
|
8004816: 681b ldr r3, [r3, #0]
|
|
8004818: 691b ldr r3, [r3, #16]
|
|
800481a: 2204 movs r2, #4
|
|
800481c: 4013 ands r3, r2
|
|
800481e: 2b04 cmp r3, #4
|
|
8004820: d125 bne.n 800486e <HAL_TIM_IRQHandler+0xba>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
|
|
8004822: 687b ldr r3, [r7, #4]
|
|
8004824: 681b ldr r3, [r3, #0]
|
|
8004826: 68db ldr r3, [r3, #12]
|
|
8004828: 2204 movs r2, #4
|
|
800482a: 4013 ands r3, r2
|
|
800482c: 2b04 cmp r3, #4
|
|
800482e: d11e bne.n 800486e <HAL_TIM_IRQHandler+0xba>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
|
|
8004830: 687b ldr r3, [r7, #4]
|
|
8004832: 681b ldr r3, [r3, #0]
|
|
8004834: 2205 movs r2, #5
|
|
8004836: 4252 negs r2, r2
|
|
8004838: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
800483a: 687b ldr r3, [r7, #4]
|
|
800483c: 2202 movs r2, #2
|
|
800483e: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
|
8004840: 687b ldr r3, [r7, #4]
|
|
8004842: 681b ldr r3, [r3, #0]
|
|
8004844: 699a ldr r2, [r3, #24]
|
|
8004846: 23c0 movs r3, #192 ; 0xc0
|
|
8004848: 009b lsls r3, r3, #2
|
|
800484a: 4013 ands r3, r2
|
|
800484c: d004 beq.n 8004858 <HAL_TIM_IRQHandler+0xa4>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800484e: 687b ldr r3, [r7, #4]
|
|
8004850: 0018 movs r0, r3
|
|
8004852: f000 fabf bl 8004dd4 <HAL_TIM_IC_CaptureCallback>
|
|
8004856: e007 b.n 8004868 <HAL_TIM_IRQHandler+0xb4>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8004858: 687b ldr r3, [r7, #4]
|
|
800485a: 0018 movs r0, r3
|
|
800485c: f000 fab2 bl 8004dc4 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8004860: 687b ldr r3, [r7, #4]
|
|
8004862: 0018 movs r0, r3
|
|
8004864: f000 fabe bl 8004de4 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8004868: 687b ldr r3, [r7, #4]
|
|
800486a: 2200 movs r2, #0
|
|
800486c: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 3 event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
|
|
800486e: 687b ldr r3, [r7, #4]
|
|
8004870: 681b ldr r3, [r3, #0]
|
|
8004872: 691b ldr r3, [r3, #16]
|
|
8004874: 2208 movs r2, #8
|
|
8004876: 4013 ands r3, r2
|
|
8004878: 2b08 cmp r3, #8
|
|
800487a: d124 bne.n 80048c6 <HAL_TIM_IRQHandler+0x112>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
|
|
800487c: 687b ldr r3, [r7, #4]
|
|
800487e: 681b ldr r3, [r3, #0]
|
|
8004880: 68db ldr r3, [r3, #12]
|
|
8004882: 2208 movs r2, #8
|
|
8004884: 4013 ands r3, r2
|
|
8004886: 2b08 cmp r3, #8
|
|
8004888: d11d bne.n 80048c6 <HAL_TIM_IRQHandler+0x112>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
|
|
800488a: 687b ldr r3, [r7, #4]
|
|
800488c: 681b ldr r3, [r3, #0]
|
|
800488e: 2209 movs r2, #9
|
|
8004890: 4252 negs r2, r2
|
|
8004892: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
8004894: 687b ldr r3, [r7, #4]
|
|
8004896: 2204 movs r2, #4
|
|
8004898: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
|
800489a: 687b ldr r3, [r7, #4]
|
|
800489c: 681b ldr r3, [r3, #0]
|
|
800489e: 69db ldr r3, [r3, #28]
|
|
80048a0: 2203 movs r2, #3
|
|
80048a2: 4013 ands r3, r2
|
|
80048a4: d004 beq.n 80048b0 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
80048a6: 687b ldr r3, [r7, #4]
|
|
80048a8: 0018 movs r0, r3
|
|
80048aa: f000 fa93 bl 8004dd4 <HAL_TIM_IC_CaptureCallback>
|
|
80048ae: e007 b.n 80048c0 <HAL_TIM_IRQHandler+0x10c>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
80048b0: 687b ldr r3, [r7, #4]
|
|
80048b2: 0018 movs r0, r3
|
|
80048b4: f000 fa86 bl 8004dc4 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
80048b8: 687b ldr r3, [r7, #4]
|
|
80048ba: 0018 movs r0, r3
|
|
80048bc: f000 fa92 bl 8004de4 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
80048c0: 687b ldr r3, [r7, #4]
|
|
80048c2: 2200 movs r2, #0
|
|
80048c4: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 4 event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
|
|
80048c6: 687b ldr r3, [r7, #4]
|
|
80048c8: 681b ldr r3, [r3, #0]
|
|
80048ca: 691b ldr r3, [r3, #16]
|
|
80048cc: 2210 movs r2, #16
|
|
80048ce: 4013 ands r3, r2
|
|
80048d0: 2b10 cmp r3, #16
|
|
80048d2: d125 bne.n 8004920 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
|
|
80048d4: 687b ldr r3, [r7, #4]
|
|
80048d6: 681b ldr r3, [r3, #0]
|
|
80048d8: 68db ldr r3, [r3, #12]
|
|
80048da: 2210 movs r2, #16
|
|
80048dc: 4013 ands r3, r2
|
|
80048de: 2b10 cmp r3, #16
|
|
80048e0: d11e bne.n 8004920 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
|
|
80048e2: 687b ldr r3, [r7, #4]
|
|
80048e4: 681b ldr r3, [r3, #0]
|
|
80048e6: 2211 movs r2, #17
|
|
80048e8: 4252 negs r2, r2
|
|
80048ea: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
80048ec: 687b ldr r3, [r7, #4]
|
|
80048ee: 2208 movs r2, #8
|
|
80048f0: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
|
80048f2: 687b ldr r3, [r7, #4]
|
|
80048f4: 681b ldr r3, [r3, #0]
|
|
80048f6: 69da ldr r2, [r3, #28]
|
|
80048f8: 23c0 movs r3, #192 ; 0xc0
|
|
80048fa: 009b lsls r3, r3, #2
|
|
80048fc: 4013 ands r3, r2
|
|
80048fe: d004 beq.n 800490a <HAL_TIM_IRQHandler+0x156>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8004900: 687b ldr r3, [r7, #4]
|
|
8004902: 0018 movs r0, r3
|
|
8004904: f000 fa66 bl 8004dd4 <HAL_TIM_IC_CaptureCallback>
|
|
8004908: e007 b.n 800491a <HAL_TIM_IRQHandler+0x166>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800490a: 687b ldr r3, [r7, #4]
|
|
800490c: 0018 movs r0, r3
|
|
800490e: f000 fa59 bl 8004dc4 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8004912: 687b ldr r3, [r7, #4]
|
|
8004914: 0018 movs r0, r3
|
|
8004916: f000 fa65 bl 8004de4 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800491a: 687b ldr r3, [r7, #4]
|
|
800491c: 2200 movs r2, #0
|
|
800491e: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* TIM Update event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
|
|
8004920: 687b ldr r3, [r7, #4]
|
|
8004922: 681b ldr r3, [r3, #0]
|
|
8004924: 691b ldr r3, [r3, #16]
|
|
8004926: 2201 movs r2, #1
|
|
8004928: 4013 ands r3, r2
|
|
800492a: 2b01 cmp r3, #1
|
|
800492c: d10f bne.n 800494e <HAL_TIM_IRQHandler+0x19a>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
|
|
800492e: 687b ldr r3, [r7, #4]
|
|
8004930: 681b ldr r3, [r3, #0]
|
|
8004932: 68db ldr r3, [r3, #12]
|
|
8004934: 2201 movs r2, #1
|
|
8004936: 4013 ands r3, r2
|
|
8004938: 2b01 cmp r3, #1
|
|
800493a: d108 bne.n 800494e <HAL_TIM_IRQHandler+0x19a>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
|
|
800493c: 687b ldr r3, [r7, #4]
|
|
800493e: 681b ldr r3, [r3, #0]
|
|
8004940: 2202 movs r2, #2
|
|
8004942: 4252 negs r2, r2
|
|
8004944: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->PeriodElapsedCallback(htim);
|
|
#else
|
|
HAL_TIM_PeriodElapsedCallback(htim);
|
|
8004946: 687b ldr r3, [r7, #4]
|
|
8004948: 0018 movs r0, r3
|
|
800494a: f7fc ff8f bl 800186c <HAL_TIM_PeriodElapsedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break input event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
|
|
800494e: 687b ldr r3, [r7, #4]
|
|
8004950: 681b ldr r3, [r3, #0]
|
|
8004952: 691b ldr r3, [r3, #16]
|
|
8004954: 2280 movs r2, #128 ; 0x80
|
|
8004956: 4013 ands r3, r2
|
|
8004958: 2b80 cmp r3, #128 ; 0x80
|
|
800495a: d10f bne.n 800497c <HAL_TIM_IRQHandler+0x1c8>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
|
|
800495c: 687b ldr r3, [r7, #4]
|
|
800495e: 681b ldr r3, [r3, #0]
|
|
8004960: 68db ldr r3, [r3, #12]
|
|
8004962: 2280 movs r2, #128 ; 0x80
|
|
8004964: 4013 ands r3, r2
|
|
8004966: 2b80 cmp r3, #128 ; 0x80
|
|
8004968: d108 bne.n 800497c <HAL_TIM_IRQHandler+0x1c8>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
|
|
800496a: 687b ldr r3, [r7, #4]
|
|
800496c: 681b ldr r3, [r3, #0]
|
|
800496e: 2281 movs r2, #129 ; 0x81
|
|
8004970: 4252 negs r2, r2
|
|
8004972: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->BreakCallback(htim);
|
|
#else
|
|
HAL_TIMEx_BreakCallback(htim);
|
|
8004974: 687b ldr r3, [r7, #4]
|
|
8004976: 0018 movs r0, r3
|
|
8004978: f000 fe86 bl 8005688 <HAL_TIMEx_BreakCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break2 input event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
|
|
800497c: 687b ldr r3, [r7, #4]
|
|
800497e: 681b ldr r3, [r3, #0]
|
|
8004980: 691a ldr r2, [r3, #16]
|
|
8004982: 2380 movs r3, #128 ; 0x80
|
|
8004984: 005b lsls r3, r3, #1
|
|
8004986: 401a ands r2, r3
|
|
8004988: 2380 movs r3, #128 ; 0x80
|
|
800498a: 005b lsls r3, r3, #1
|
|
800498c: 429a cmp r2, r3
|
|
800498e: d10e bne.n 80049ae <HAL_TIM_IRQHandler+0x1fa>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
|
|
8004990: 687b ldr r3, [r7, #4]
|
|
8004992: 681b ldr r3, [r3, #0]
|
|
8004994: 68db ldr r3, [r3, #12]
|
|
8004996: 2280 movs r2, #128 ; 0x80
|
|
8004998: 4013 ands r3, r2
|
|
800499a: 2b80 cmp r3, #128 ; 0x80
|
|
800499c: d107 bne.n 80049ae <HAL_TIM_IRQHandler+0x1fa>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
|
|
800499e: 687b ldr r3, [r7, #4]
|
|
80049a0: 681b ldr r3, [r3, #0]
|
|
80049a2: 4a1c ldr r2, [pc, #112] ; (8004a14 <HAL_TIM_IRQHandler+0x260>)
|
|
80049a4: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->Break2Callback(htim);
|
|
#else
|
|
HAL_TIMEx_Break2Callback(htim);
|
|
80049a6: 687b ldr r3, [r7, #4]
|
|
80049a8: 0018 movs r0, r3
|
|
80049aa: f000 fe75 bl 8005698 <HAL_TIMEx_Break2Callback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Trigger detection event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
|
|
80049ae: 687b ldr r3, [r7, #4]
|
|
80049b0: 681b ldr r3, [r3, #0]
|
|
80049b2: 691b ldr r3, [r3, #16]
|
|
80049b4: 2240 movs r2, #64 ; 0x40
|
|
80049b6: 4013 ands r3, r2
|
|
80049b8: 2b40 cmp r3, #64 ; 0x40
|
|
80049ba: d10f bne.n 80049dc <HAL_TIM_IRQHandler+0x228>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
|
|
80049bc: 687b ldr r3, [r7, #4]
|
|
80049be: 681b ldr r3, [r3, #0]
|
|
80049c0: 68db ldr r3, [r3, #12]
|
|
80049c2: 2240 movs r2, #64 ; 0x40
|
|
80049c4: 4013 ands r3, r2
|
|
80049c6: 2b40 cmp r3, #64 ; 0x40
|
|
80049c8: d108 bne.n 80049dc <HAL_TIM_IRQHandler+0x228>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
|
|
80049ca: 687b ldr r3, [r7, #4]
|
|
80049cc: 681b ldr r3, [r3, #0]
|
|
80049ce: 2241 movs r2, #65 ; 0x41
|
|
80049d0: 4252 negs r2, r2
|
|
80049d2: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->TriggerCallback(htim);
|
|
#else
|
|
HAL_TIM_TriggerCallback(htim);
|
|
80049d4: 687b ldr r3, [r7, #4]
|
|
80049d6: 0018 movs r0, r3
|
|
80049d8: f000 fa0c bl 8004df4 <HAL_TIM_TriggerCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM commutation event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
|
|
80049dc: 687b ldr r3, [r7, #4]
|
|
80049de: 681b ldr r3, [r3, #0]
|
|
80049e0: 691b ldr r3, [r3, #16]
|
|
80049e2: 2220 movs r2, #32
|
|
80049e4: 4013 ands r3, r2
|
|
80049e6: 2b20 cmp r3, #32
|
|
80049e8: d10f bne.n 8004a0a <HAL_TIM_IRQHandler+0x256>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
|
|
80049ea: 687b ldr r3, [r7, #4]
|
|
80049ec: 681b ldr r3, [r3, #0]
|
|
80049ee: 68db ldr r3, [r3, #12]
|
|
80049f0: 2220 movs r2, #32
|
|
80049f2: 4013 ands r3, r2
|
|
80049f4: 2b20 cmp r3, #32
|
|
80049f6: d108 bne.n 8004a0a <HAL_TIM_IRQHandler+0x256>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
|
|
80049f8: 687b ldr r3, [r7, #4]
|
|
80049fa: 681b ldr r3, [r3, #0]
|
|
80049fc: 2221 movs r2, #33 ; 0x21
|
|
80049fe: 4252 negs r2, r2
|
|
8004a00: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->CommutationCallback(htim);
|
|
#else
|
|
HAL_TIMEx_CommutCallback(htim);
|
|
8004a02: 687b ldr r3, [r7, #4]
|
|
8004a04: 0018 movs r0, r3
|
|
8004a06: f000 fe37 bl 8005678 <HAL_TIMEx_CommutCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
}
|
|
8004a0a: 46c0 nop ; (mov r8, r8)
|
|
8004a0c: 46bd mov sp, r7
|
|
8004a0e: b002 add sp, #8
|
|
8004a10: bd80 pop {r7, pc}
|
|
8004a12: 46c0 nop ; (mov r8, r8)
|
|
8004a14: fffffeff .word 0xfffffeff
|
|
|
|
08004a18 <HAL_TIM_PWM_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
const TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
8004a18: b580 push {r7, lr}
|
|
8004a1a: b086 sub sp, #24
|
|
8004a1c: af00 add r7, sp, #0
|
|
8004a1e: 60f8 str r0, [r7, #12]
|
|
8004a20: 60b9 str r1, [r7, #8]
|
|
8004a22: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8004a24: 2317 movs r3, #23
|
|
8004a26: 18fb adds r3, r7, r3
|
|
8004a28: 2200 movs r2, #0
|
|
8004a2a: 701a strb r2, [r3, #0]
|
|
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
8004a2c: 68fb ldr r3, [r7, #12]
|
|
8004a2e: 223c movs r2, #60 ; 0x3c
|
|
8004a30: 5c9b ldrb r3, [r3, r2]
|
|
8004a32: 2b01 cmp r3, #1
|
|
8004a34: d101 bne.n 8004a3a <HAL_TIM_PWM_ConfigChannel+0x22>
|
|
8004a36: 2302 movs r3, #2
|
|
8004a38: e0e5 b.n 8004c06 <HAL_TIM_PWM_ConfigChannel+0x1ee>
|
|
8004a3a: 68fb ldr r3, [r7, #12]
|
|
8004a3c: 223c movs r2, #60 ; 0x3c
|
|
8004a3e: 2101 movs r1, #1
|
|
8004a40: 5499 strb r1, [r3, r2]
|
|
|
|
switch (Channel)
|
|
8004a42: 687b ldr r3, [r7, #4]
|
|
8004a44: 2b14 cmp r3, #20
|
|
8004a46: d900 bls.n 8004a4a <HAL_TIM_PWM_ConfigChannel+0x32>
|
|
8004a48: e0d1 b.n 8004bee <HAL_TIM_PWM_ConfigChannel+0x1d6>
|
|
8004a4a: 687b ldr r3, [r7, #4]
|
|
8004a4c: 009a lsls r2, r3, #2
|
|
8004a4e: 4b70 ldr r3, [pc, #448] ; (8004c10 <HAL_TIM_PWM_ConfigChannel+0x1f8>)
|
|
8004a50: 18d3 adds r3, r2, r3
|
|
8004a52: 681b ldr r3, [r3, #0]
|
|
8004a54: 469f mov pc, r3
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 1 in PWM mode */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
8004a56: 68fb ldr r3, [r7, #12]
|
|
8004a58: 681b ldr r3, [r3, #0]
|
|
8004a5a: 68ba ldr r2, [r7, #8]
|
|
8004a5c: 0011 movs r1, r2
|
|
8004a5e: 0018 movs r0, r3
|
|
8004a60: f000 fa46 bl 8004ef0 <TIM_OC1_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel1 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
8004a64: 68fb ldr r3, [r7, #12]
|
|
8004a66: 681b ldr r3, [r3, #0]
|
|
8004a68: 699a ldr r2, [r3, #24]
|
|
8004a6a: 68fb ldr r3, [r7, #12]
|
|
8004a6c: 681b ldr r3, [r3, #0]
|
|
8004a6e: 2108 movs r1, #8
|
|
8004a70: 430a orrs r2, r1
|
|
8004a72: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
8004a74: 68fb ldr r3, [r7, #12]
|
|
8004a76: 681b ldr r3, [r3, #0]
|
|
8004a78: 699a ldr r2, [r3, #24]
|
|
8004a7a: 68fb ldr r3, [r7, #12]
|
|
8004a7c: 681b ldr r3, [r3, #0]
|
|
8004a7e: 2104 movs r1, #4
|
|
8004a80: 438a bics r2, r1
|
|
8004a82: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
|
8004a84: 68fb ldr r3, [r7, #12]
|
|
8004a86: 681b ldr r3, [r3, #0]
|
|
8004a88: 6999 ldr r1, [r3, #24]
|
|
8004a8a: 68bb ldr r3, [r7, #8]
|
|
8004a8c: 691a ldr r2, [r3, #16]
|
|
8004a8e: 68fb ldr r3, [r7, #12]
|
|
8004a90: 681b ldr r3, [r3, #0]
|
|
8004a92: 430a orrs r2, r1
|
|
8004a94: 619a str r2, [r3, #24]
|
|
break;
|
|
8004a96: e0af b.n 8004bf8 <HAL_TIM_PWM_ConfigChannel+0x1e0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 2 in PWM mode */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
8004a98: 68fb ldr r3, [r7, #12]
|
|
8004a9a: 681b ldr r3, [r3, #0]
|
|
8004a9c: 68ba ldr r2, [r7, #8]
|
|
8004a9e: 0011 movs r1, r2
|
|
8004aa0: 0018 movs r0, r3
|
|
8004aa2: f000 faa5 bl 8004ff0 <TIM_OC2_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel2 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
|
8004aa6: 68fb ldr r3, [r7, #12]
|
|
8004aa8: 681b ldr r3, [r3, #0]
|
|
8004aaa: 699a ldr r2, [r3, #24]
|
|
8004aac: 68fb ldr r3, [r7, #12]
|
|
8004aae: 681b ldr r3, [r3, #0]
|
|
8004ab0: 2180 movs r1, #128 ; 0x80
|
|
8004ab2: 0109 lsls r1, r1, #4
|
|
8004ab4: 430a orrs r2, r1
|
|
8004ab6: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
|
8004ab8: 68fb ldr r3, [r7, #12]
|
|
8004aba: 681b ldr r3, [r3, #0]
|
|
8004abc: 699a ldr r2, [r3, #24]
|
|
8004abe: 68fb ldr r3, [r7, #12]
|
|
8004ac0: 681b ldr r3, [r3, #0]
|
|
8004ac2: 4954 ldr r1, [pc, #336] ; (8004c14 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
|
|
8004ac4: 400a ands r2, r1
|
|
8004ac6: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
|
|
8004ac8: 68fb ldr r3, [r7, #12]
|
|
8004aca: 681b ldr r3, [r3, #0]
|
|
8004acc: 6999 ldr r1, [r3, #24]
|
|
8004ace: 68bb ldr r3, [r7, #8]
|
|
8004ad0: 691b ldr r3, [r3, #16]
|
|
8004ad2: 021a lsls r2, r3, #8
|
|
8004ad4: 68fb ldr r3, [r7, #12]
|
|
8004ad6: 681b ldr r3, [r3, #0]
|
|
8004ad8: 430a orrs r2, r1
|
|
8004ada: 619a str r2, [r3, #24]
|
|
break;
|
|
8004adc: e08c b.n 8004bf8 <HAL_TIM_PWM_ConfigChannel+0x1e0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 3 in PWM mode */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
8004ade: 68fb ldr r3, [r7, #12]
|
|
8004ae0: 681b ldr r3, [r3, #0]
|
|
8004ae2: 68ba ldr r2, [r7, #8]
|
|
8004ae4: 0011 movs r1, r2
|
|
8004ae6: 0018 movs r0, r3
|
|
8004ae8: f000 fb00 bl 80050ec <TIM_OC3_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel3 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
|
8004aec: 68fb ldr r3, [r7, #12]
|
|
8004aee: 681b ldr r3, [r3, #0]
|
|
8004af0: 69da ldr r2, [r3, #28]
|
|
8004af2: 68fb ldr r3, [r7, #12]
|
|
8004af4: 681b ldr r3, [r3, #0]
|
|
8004af6: 2108 movs r1, #8
|
|
8004af8: 430a orrs r2, r1
|
|
8004afa: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
8004afc: 68fb ldr r3, [r7, #12]
|
|
8004afe: 681b ldr r3, [r3, #0]
|
|
8004b00: 69da ldr r2, [r3, #28]
|
|
8004b02: 68fb ldr r3, [r7, #12]
|
|
8004b04: 681b ldr r3, [r3, #0]
|
|
8004b06: 2104 movs r1, #4
|
|
8004b08: 438a bics r2, r1
|
|
8004b0a: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
|
8004b0c: 68fb ldr r3, [r7, #12]
|
|
8004b0e: 681b ldr r3, [r3, #0]
|
|
8004b10: 69d9 ldr r1, [r3, #28]
|
|
8004b12: 68bb ldr r3, [r7, #8]
|
|
8004b14: 691a ldr r2, [r3, #16]
|
|
8004b16: 68fb ldr r3, [r7, #12]
|
|
8004b18: 681b ldr r3, [r3, #0]
|
|
8004b1a: 430a orrs r2, r1
|
|
8004b1c: 61da str r2, [r3, #28]
|
|
break;
|
|
8004b1e: e06b b.n 8004bf8 <HAL_TIM_PWM_ConfigChannel+0x1e0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 4 in PWM mode */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
8004b20: 68fb ldr r3, [r7, #12]
|
|
8004b22: 681b ldr r3, [r3, #0]
|
|
8004b24: 68ba ldr r2, [r7, #8]
|
|
8004b26: 0011 movs r1, r2
|
|
8004b28: 0018 movs r0, r3
|
|
8004b2a: f000 fb61 bl 80051f0 <TIM_OC4_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel4 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
|
8004b2e: 68fb ldr r3, [r7, #12]
|
|
8004b30: 681b ldr r3, [r3, #0]
|
|
8004b32: 69da ldr r2, [r3, #28]
|
|
8004b34: 68fb ldr r3, [r7, #12]
|
|
8004b36: 681b ldr r3, [r3, #0]
|
|
8004b38: 2180 movs r1, #128 ; 0x80
|
|
8004b3a: 0109 lsls r1, r1, #4
|
|
8004b3c: 430a orrs r2, r1
|
|
8004b3e: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
|
8004b40: 68fb ldr r3, [r7, #12]
|
|
8004b42: 681b ldr r3, [r3, #0]
|
|
8004b44: 69da ldr r2, [r3, #28]
|
|
8004b46: 68fb ldr r3, [r7, #12]
|
|
8004b48: 681b ldr r3, [r3, #0]
|
|
8004b4a: 4932 ldr r1, [pc, #200] ; (8004c14 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
|
|
8004b4c: 400a ands r2, r1
|
|
8004b4e: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
|
|
8004b50: 68fb ldr r3, [r7, #12]
|
|
8004b52: 681b ldr r3, [r3, #0]
|
|
8004b54: 69d9 ldr r1, [r3, #28]
|
|
8004b56: 68bb ldr r3, [r7, #8]
|
|
8004b58: 691b ldr r3, [r3, #16]
|
|
8004b5a: 021a lsls r2, r3, #8
|
|
8004b5c: 68fb ldr r3, [r7, #12]
|
|
8004b5e: 681b ldr r3, [r3, #0]
|
|
8004b60: 430a orrs r2, r1
|
|
8004b62: 61da str r2, [r3, #28]
|
|
break;
|
|
8004b64: e048 b.n 8004bf8 <HAL_TIM_PWM_ConfigChannel+0x1e0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 5 in PWM mode */
|
|
TIM_OC5_SetConfig(htim->Instance, sConfig);
|
|
8004b66: 68fb ldr r3, [r7, #12]
|
|
8004b68: 681b ldr r3, [r3, #0]
|
|
8004b6a: 68ba ldr r2, [r7, #8]
|
|
8004b6c: 0011 movs r1, r2
|
|
8004b6e: 0018 movs r0, r3
|
|
8004b70: f000 fba2 bl 80052b8 <TIM_OC5_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel5*/
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
|
|
8004b74: 68fb ldr r3, [r7, #12]
|
|
8004b76: 681b ldr r3, [r3, #0]
|
|
8004b78: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
8004b7a: 68fb ldr r3, [r7, #12]
|
|
8004b7c: 681b ldr r3, [r3, #0]
|
|
8004b7e: 2108 movs r1, #8
|
|
8004b80: 430a orrs r2, r1
|
|
8004b82: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
|
|
8004b84: 68fb ldr r3, [r7, #12]
|
|
8004b86: 681b ldr r3, [r3, #0]
|
|
8004b88: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
8004b8a: 68fb ldr r3, [r7, #12]
|
|
8004b8c: 681b ldr r3, [r3, #0]
|
|
8004b8e: 2104 movs r1, #4
|
|
8004b90: 438a bics r2, r1
|
|
8004b92: 655a str r2, [r3, #84] ; 0x54
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode;
|
|
8004b94: 68fb ldr r3, [r7, #12]
|
|
8004b96: 681b ldr r3, [r3, #0]
|
|
8004b98: 6d59 ldr r1, [r3, #84] ; 0x54
|
|
8004b9a: 68bb ldr r3, [r7, #8]
|
|
8004b9c: 691a ldr r2, [r3, #16]
|
|
8004b9e: 68fb ldr r3, [r7, #12]
|
|
8004ba0: 681b ldr r3, [r3, #0]
|
|
8004ba2: 430a orrs r2, r1
|
|
8004ba4: 655a str r2, [r3, #84] ; 0x54
|
|
break;
|
|
8004ba6: e027 b.n 8004bf8 <HAL_TIM_PWM_ConfigChannel+0x1e0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 6 in PWM mode */
|
|
TIM_OC6_SetConfig(htim->Instance, sConfig);
|
|
8004ba8: 68fb ldr r3, [r7, #12]
|
|
8004baa: 681b ldr r3, [r3, #0]
|
|
8004bac: 68ba ldr r2, [r7, #8]
|
|
8004bae: 0011 movs r1, r2
|
|
8004bb0: 0018 movs r0, r3
|
|
8004bb2: f000 fbdb bl 800536c <TIM_OC6_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel6 */
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
|
|
8004bb6: 68fb ldr r3, [r7, #12]
|
|
8004bb8: 681b ldr r3, [r3, #0]
|
|
8004bba: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
8004bbc: 68fb ldr r3, [r7, #12]
|
|
8004bbe: 681b ldr r3, [r3, #0]
|
|
8004bc0: 2180 movs r1, #128 ; 0x80
|
|
8004bc2: 0109 lsls r1, r1, #4
|
|
8004bc4: 430a orrs r2, r1
|
|
8004bc6: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
|
|
8004bc8: 68fb ldr r3, [r7, #12]
|
|
8004bca: 681b ldr r3, [r3, #0]
|
|
8004bcc: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
8004bce: 68fb ldr r3, [r7, #12]
|
|
8004bd0: 681b ldr r3, [r3, #0]
|
|
8004bd2: 4910 ldr r1, [pc, #64] ; (8004c14 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
|
|
8004bd4: 400a ands r2, r1
|
|
8004bd6: 655a str r2, [r3, #84] ; 0x54
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
|
|
8004bd8: 68fb ldr r3, [r7, #12]
|
|
8004bda: 681b ldr r3, [r3, #0]
|
|
8004bdc: 6d59 ldr r1, [r3, #84] ; 0x54
|
|
8004bde: 68bb ldr r3, [r7, #8]
|
|
8004be0: 691b ldr r3, [r3, #16]
|
|
8004be2: 021a lsls r2, r3, #8
|
|
8004be4: 68fb ldr r3, [r7, #12]
|
|
8004be6: 681b ldr r3, [r3, #0]
|
|
8004be8: 430a orrs r2, r1
|
|
8004bea: 655a str r2, [r3, #84] ; 0x54
|
|
break;
|
|
8004bec: e004 b.n 8004bf8 <HAL_TIM_PWM_ConfigChannel+0x1e0>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
8004bee: 2317 movs r3, #23
|
|
8004bf0: 18fb adds r3, r7, r3
|
|
8004bf2: 2201 movs r2, #1
|
|
8004bf4: 701a strb r2, [r3, #0]
|
|
break;
|
|
8004bf6: 46c0 nop ; (mov r8, r8)
|
|
}
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8004bf8: 68fb ldr r3, [r7, #12]
|
|
8004bfa: 223c movs r2, #60 ; 0x3c
|
|
8004bfc: 2100 movs r1, #0
|
|
8004bfe: 5499 strb r1, [r3, r2]
|
|
|
|
return status;
|
|
8004c00: 2317 movs r3, #23
|
|
8004c02: 18fb adds r3, r7, r3
|
|
8004c04: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8004c06: 0018 movs r0, r3
|
|
8004c08: 46bd mov sp, r7
|
|
8004c0a: b006 add sp, #24
|
|
8004c0c: bd80 pop {r7, pc}
|
|
8004c0e: 46c0 nop ; (mov r8, r8)
|
|
8004c10: 08006828 .word 0x08006828
|
|
8004c14: fffffbff .word 0xfffffbff
|
|
|
|
08004c18 <HAL_TIM_ConfigClockSource>:
|
|
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
|
|
* contains the clock source information for the TIM peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
|
|
{
|
|
8004c18: b580 push {r7, lr}
|
|
8004c1a: b084 sub sp, #16
|
|
8004c1c: af00 add r7, sp, #0
|
|
8004c1e: 6078 str r0, [r7, #4]
|
|
8004c20: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8004c22: 230f movs r3, #15
|
|
8004c24: 18fb adds r3, r7, r3
|
|
8004c26: 2200 movs r2, #0
|
|
8004c28: 701a strb r2, [r3, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
8004c2a: 687b ldr r3, [r7, #4]
|
|
8004c2c: 223c movs r2, #60 ; 0x3c
|
|
8004c2e: 5c9b ldrb r3, [r3, r2]
|
|
8004c30: 2b01 cmp r3, #1
|
|
8004c32: d101 bne.n 8004c38 <HAL_TIM_ConfigClockSource+0x20>
|
|
8004c34: 2302 movs r3, #2
|
|
8004c36: e0bc b.n 8004db2 <HAL_TIM_ConfigClockSource+0x19a>
|
|
8004c38: 687b ldr r3, [r7, #4]
|
|
8004c3a: 223c movs r2, #60 ; 0x3c
|
|
8004c3c: 2101 movs r1, #1
|
|
8004c3e: 5499 strb r1, [r3, r2]
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8004c40: 687b ldr r3, [r7, #4]
|
|
8004c42: 223d movs r2, #61 ; 0x3d
|
|
8004c44: 2102 movs r1, #2
|
|
8004c46: 5499 strb r1, [r3, r2]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
|
|
|
|
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8004c48: 687b ldr r3, [r7, #4]
|
|
8004c4a: 681b ldr r3, [r3, #0]
|
|
8004c4c: 689b ldr r3, [r3, #8]
|
|
8004c4e: 60bb str r3, [r7, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
|
8004c50: 68bb ldr r3, [r7, #8]
|
|
8004c52: 4a5a ldr r2, [pc, #360] ; (8004dbc <HAL_TIM_ConfigClockSource+0x1a4>)
|
|
8004c54: 4013 ands r3, r2
|
|
8004c56: 60bb str r3, [r7, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
8004c58: 68bb ldr r3, [r7, #8]
|
|
8004c5a: 4a59 ldr r2, [pc, #356] ; (8004dc0 <HAL_TIM_ConfigClockSource+0x1a8>)
|
|
8004c5c: 4013 ands r3, r2
|
|
8004c5e: 60bb str r3, [r7, #8]
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8004c60: 687b ldr r3, [r7, #4]
|
|
8004c62: 681b ldr r3, [r3, #0]
|
|
8004c64: 68ba ldr r2, [r7, #8]
|
|
8004c66: 609a str r2, [r3, #8]
|
|
|
|
switch (sClockSourceConfig->ClockSource)
|
|
8004c68: 683b ldr r3, [r7, #0]
|
|
8004c6a: 681b ldr r3, [r3, #0]
|
|
8004c6c: 2280 movs r2, #128 ; 0x80
|
|
8004c6e: 0192 lsls r2, r2, #6
|
|
8004c70: 4293 cmp r3, r2
|
|
8004c72: d040 beq.n 8004cf6 <HAL_TIM_ConfigClockSource+0xde>
|
|
8004c74: 2280 movs r2, #128 ; 0x80
|
|
8004c76: 0192 lsls r2, r2, #6
|
|
8004c78: 4293 cmp r3, r2
|
|
8004c7a: d900 bls.n 8004c7e <HAL_TIM_ConfigClockSource+0x66>
|
|
8004c7c: e088 b.n 8004d90 <HAL_TIM_ConfigClockSource+0x178>
|
|
8004c7e: 2280 movs r2, #128 ; 0x80
|
|
8004c80: 0152 lsls r2, r2, #5
|
|
8004c82: 4293 cmp r3, r2
|
|
8004c84: d100 bne.n 8004c88 <HAL_TIM_ConfigClockSource+0x70>
|
|
8004c86: e088 b.n 8004d9a <HAL_TIM_ConfigClockSource+0x182>
|
|
8004c88: 2280 movs r2, #128 ; 0x80
|
|
8004c8a: 0152 lsls r2, r2, #5
|
|
8004c8c: 4293 cmp r3, r2
|
|
8004c8e: d900 bls.n 8004c92 <HAL_TIM_ConfigClockSource+0x7a>
|
|
8004c90: e07e b.n 8004d90 <HAL_TIM_ConfigClockSource+0x178>
|
|
8004c92: 2b70 cmp r3, #112 ; 0x70
|
|
8004c94: d018 beq.n 8004cc8 <HAL_TIM_ConfigClockSource+0xb0>
|
|
8004c96: d900 bls.n 8004c9a <HAL_TIM_ConfigClockSource+0x82>
|
|
8004c98: e07a b.n 8004d90 <HAL_TIM_ConfigClockSource+0x178>
|
|
8004c9a: 2b60 cmp r3, #96 ; 0x60
|
|
8004c9c: d04f beq.n 8004d3e <HAL_TIM_ConfigClockSource+0x126>
|
|
8004c9e: d900 bls.n 8004ca2 <HAL_TIM_ConfigClockSource+0x8a>
|
|
8004ca0: e076 b.n 8004d90 <HAL_TIM_ConfigClockSource+0x178>
|
|
8004ca2: 2b50 cmp r3, #80 ; 0x50
|
|
8004ca4: d03b beq.n 8004d1e <HAL_TIM_ConfigClockSource+0x106>
|
|
8004ca6: d900 bls.n 8004caa <HAL_TIM_ConfigClockSource+0x92>
|
|
8004ca8: e072 b.n 8004d90 <HAL_TIM_ConfigClockSource+0x178>
|
|
8004caa: 2b40 cmp r3, #64 ; 0x40
|
|
8004cac: d057 beq.n 8004d5e <HAL_TIM_ConfigClockSource+0x146>
|
|
8004cae: d900 bls.n 8004cb2 <HAL_TIM_ConfigClockSource+0x9a>
|
|
8004cb0: e06e b.n 8004d90 <HAL_TIM_ConfigClockSource+0x178>
|
|
8004cb2: 2b30 cmp r3, #48 ; 0x30
|
|
8004cb4: d063 beq.n 8004d7e <HAL_TIM_ConfigClockSource+0x166>
|
|
8004cb6: d86b bhi.n 8004d90 <HAL_TIM_ConfigClockSource+0x178>
|
|
8004cb8: 2b20 cmp r3, #32
|
|
8004cba: d060 beq.n 8004d7e <HAL_TIM_ConfigClockSource+0x166>
|
|
8004cbc: d868 bhi.n 8004d90 <HAL_TIM_ConfigClockSource+0x178>
|
|
8004cbe: 2b00 cmp r3, #0
|
|
8004cc0: d05d beq.n 8004d7e <HAL_TIM_ConfigClockSource+0x166>
|
|
8004cc2: 2b10 cmp r3, #16
|
|
8004cc4: d05b beq.n 8004d7e <HAL_TIM_ConfigClockSource+0x166>
|
|
8004cc6: e063 b.n 8004d90 <HAL_TIM_ConfigClockSource+0x178>
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
/* Configure the ETR Clock source */
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
8004cc8: 687b ldr r3, [r7, #4]
|
|
8004cca: 6818 ldr r0, [r3, #0]
|
|
8004ccc: 683b ldr r3, [r7, #0]
|
|
8004cce: 6899 ldr r1, [r3, #8]
|
|
8004cd0: 683b ldr r3, [r7, #0]
|
|
8004cd2: 685a ldr r2, [r3, #4]
|
|
8004cd4: 683b ldr r3, [r7, #0]
|
|
8004cd6: 68db ldr r3, [r3, #12]
|
|
8004cd8: f000 fc22 bl 8005520 <TIM_ETR_SetConfig>
|
|
sClockSourceConfig->ClockPrescaler,
|
|
sClockSourceConfig->ClockPolarity,
|
|
sClockSourceConfig->ClockFilter);
|
|
|
|
/* Select the External clock mode1 and the ETRF trigger */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8004cdc: 687b ldr r3, [r7, #4]
|
|
8004cde: 681b ldr r3, [r3, #0]
|
|
8004ce0: 689b ldr r3, [r3, #8]
|
|
8004ce2: 60bb str r3, [r7, #8]
|
|
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
8004ce4: 68bb ldr r3, [r7, #8]
|
|
8004ce6: 2277 movs r2, #119 ; 0x77
|
|
8004ce8: 4313 orrs r3, r2
|
|
8004cea: 60bb str r3, [r7, #8]
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8004cec: 687b ldr r3, [r7, #4]
|
|
8004cee: 681b ldr r3, [r3, #0]
|
|
8004cf0: 68ba ldr r2, [r7, #8]
|
|
8004cf2: 609a str r2, [r3, #8]
|
|
break;
|
|
8004cf4: e052 b.n 8004d9c <HAL_TIM_ConfigClockSource+0x184>
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
/* Configure the ETR Clock source */
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
8004cf6: 687b ldr r3, [r7, #4]
|
|
8004cf8: 6818 ldr r0, [r3, #0]
|
|
8004cfa: 683b ldr r3, [r7, #0]
|
|
8004cfc: 6899 ldr r1, [r3, #8]
|
|
8004cfe: 683b ldr r3, [r7, #0]
|
|
8004d00: 685a ldr r2, [r3, #4]
|
|
8004d02: 683b ldr r3, [r7, #0]
|
|
8004d04: 68db ldr r3, [r3, #12]
|
|
8004d06: f000 fc0b bl 8005520 <TIM_ETR_SetConfig>
|
|
sClockSourceConfig->ClockPrescaler,
|
|
sClockSourceConfig->ClockPolarity,
|
|
sClockSourceConfig->ClockFilter);
|
|
/* Enable the External clock mode2 */
|
|
htim->Instance->SMCR |= TIM_SMCR_ECE;
|
|
8004d0a: 687b ldr r3, [r7, #4]
|
|
8004d0c: 681b ldr r3, [r3, #0]
|
|
8004d0e: 689a ldr r2, [r3, #8]
|
|
8004d10: 687b ldr r3, [r7, #4]
|
|
8004d12: 681b ldr r3, [r3, #0]
|
|
8004d14: 2180 movs r1, #128 ; 0x80
|
|
8004d16: 01c9 lsls r1, r1, #7
|
|
8004d18: 430a orrs r2, r1
|
|
8004d1a: 609a str r2, [r3, #8]
|
|
break;
|
|
8004d1c: e03e b.n 8004d9c <HAL_TIM_ConfigClockSource+0x184>
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
8004d1e: 687b ldr r3, [r7, #4]
|
|
8004d20: 6818 ldr r0, [r3, #0]
|
|
8004d22: 683b ldr r3, [r7, #0]
|
|
8004d24: 6859 ldr r1, [r3, #4]
|
|
8004d26: 683b ldr r3, [r7, #0]
|
|
8004d28: 68db ldr r3, [r3, #12]
|
|
8004d2a: 001a movs r2, r3
|
|
8004d2c: f000 fb7c bl 8005428 <TIM_TI1_ConfigInputStage>
|
|
sClockSourceConfig->ClockPolarity,
|
|
sClockSourceConfig->ClockFilter);
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
|
|
8004d30: 687b ldr r3, [r7, #4]
|
|
8004d32: 681b ldr r3, [r3, #0]
|
|
8004d34: 2150 movs r1, #80 ; 0x50
|
|
8004d36: 0018 movs r0, r3
|
|
8004d38: f000 fbd6 bl 80054e8 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8004d3c: e02e b.n 8004d9c <HAL_TIM_ConfigClockSource+0x184>
|
|
|
|
/* Check TI2 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
8004d3e: 687b ldr r3, [r7, #4]
|
|
8004d40: 6818 ldr r0, [r3, #0]
|
|
8004d42: 683b ldr r3, [r7, #0]
|
|
8004d44: 6859 ldr r1, [r3, #4]
|
|
8004d46: 683b ldr r3, [r7, #0]
|
|
8004d48: 68db ldr r3, [r3, #12]
|
|
8004d4a: 001a movs r2, r3
|
|
8004d4c: f000 fb9a bl 8005484 <TIM_TI2_ConfigInputStage>
|
|
sClockSourceConfig->ClockPolarity,
|
|
sClockSourceConfig->ClockFilter);
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
|
|
8004d50: 687b ldr r3, [r7, #4]
|
|
8004d52: 681b ldr r3, [r3, #0]
|
|
8004d54: 2160 movs r1, #96 ; 0x60
|
|
8004d56: 0018 movs r0, r3
|
|
8004d58: f000 fbc6 bl 80054e8 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8004d5c: e01e b.n 8004d9c <HAL_TIM_ConfigClockSource+0x184>
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
8004d5e: 687b ldr r3, [r7, #4]
|
|
8004d60: 6818 ldr r0, [r3, #0]
|
|
8004d62: 683b ldr r3, [r7, #0]
|
|
8004d64: 6859 ldr r1, [r3, #4]
|
|
8004d66: 683b ldr r3, [r7, #0]
|
|
8004d68: 68db ldr r3, [r3, #12]
|
|
8004d6a: 001a movs r2, r3
|
|
8004d6c: f000 fb5c bl 8005428 <TIM_TI1_ConfigInputStage>
|
|
sClockSourceConfig->ClockPolarity,
|
|
sClockSourceConfig->ClockFilter);
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
|
|
8004d70: 687b ldr r3, [r7, #4]
|
|
8004d72: 681b ldr r3, [r3, #0]
|
|
8004d74: 2140 movs r1, #64 ; 0x40
|
|
8004d76: 0018 movs r0, r3
|
|
8004d78: f000 fbb6 bl 80054e8 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8004d7c: e00e b.n 8004d9c <HAL_TIM_ConfigClockSource+0x184>
|
|
case TIM_CLOCKSOURCE_ITR3:
|
|
{
|
|
/* Check whether or not the timer instance supports internal trigger input */
|
|
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
|
|
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
8004d7e: 687b ldr r3, [r7, #4]
|
|
8004d80: 681a ldr r2, [r3, #0]
|
|
8004d82: 683b ldr r3, [r7, #0]
|
|
8004d84: 681b ldr r3, [r3, #0]
|
|
8004d86: 0019 movs r1, r3
|
|
8004d88: 0010 movs r0, r2
|
|
8004d8a: f000 fbad bl 80054e8 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8004d8e: e005 b.n 8004d9c <HAL_TIM_ConfigClockSource+0x184>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
8004d90: 230f movs r3, #15
|
|
8004d92: 18fb adds r3, r7, r3
|
|
8004d94: 2201 movs r2, #1
|
|
8004d96: 701a strb r2, [r3, #0]
|
|
break;
|
|
8004d98: e000 b.n 8004d9c <HAL_TIM_ConfigClockSource+0x184>
|
|
break;
|
|
8004d9a: 46c0 nop ; (mov r8, r8)
|
|
}
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8004d9c: 687b ldr r3, [r7, #4]
|
|
8004d9e: 223d movs r2, #61 ; 0x3d
|
|
8004da0: 2101 movs r1, #1
|
|
8004da2: 5499 strb r1, [r3, r2]
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8004da4: 687b ldr r3, [r7, #4]
|
|
8004da6: 223c movs r2, #60 ; 0x3c
|
|
8004da8: 2100 movs r1, #0
|
|
8004daa: 5499 strb r1, [r3, r2]
|
|
|
|
return status;
|
|
8004dac: 230f movs r3, #15
|
|
8004dae: 18fb adds r3, r7, r3
|
|
8004db0: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8004db2: 0018 movs r0, r3
|
|
8004db4: 46bd mov sp, r7
|
|
8004db6: b004 add sp, #16
|
|
8004db8: bd80 pop {r7, pc}
|
|
8004dba: 46c0 nop ; (mov r8, r8)
|
|
8004dbc: ffceff88 .word 0xffceff88
|
|
8004dc0: ffff00ff .word 0xffff00ff
|
|
|
|
08004dc4 <HAL_TIM_OC_DelayElapsedCallback>:
|
|
* @brief Output Compare callback in non-blocking mode
|
|
* @param htim TIM OC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8004dc4: b580 push {r7, lr}
|
|
8004dc6: b082 sub sp, #8
|
|
8004dc8: af00 add r7, sp, #0
|
|
8004dca: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8004dcc: 46c0 nop ; (mov r8, r8)
|
|
8004dce: 46bd mov sp, r7
|
|
8004dd0: b002 add sp, #8
|
|
8004dd2: bd80 pop {r7, pc}
|
|
|
|
08004dd4 <HAL_TIM_IC_CaptureCallback>:
|
|
* @brief Input Capture callback in non-blocking mode
|
|
* @param htim TIM IC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8004dd4: b580 push {r7, lr}
|
|
8004dd6: b082 sub sp, #8
|
|
8004dd8: af00 add r7, sp, #0
|
|
8004dda: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8004ddc: 46c0 nop ; (mov r8, r8)
|
|
8004dde: 46bd mov sp, r7
|
|
8004de0: b002 add sp, #8
|
|
8004de2: bd80 pop {r7, pc}
|
|
|
|
08004de4 <HAL_TIM_PWM_PulseFinishedCallback>:
|
|
* @brief PWM Pulse finished callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8004de4: b580 push {r7, lr}
|
|
8004de6: b082 sub sp, #8
|
|
8004de8: af00 add r7, sp, #0
|
|
8004dea: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8004dec: 46c0 nop ; (mov r8, r8)
|
|
8004dee: 46bd mov sp, r7
|
|
8004df0: b002 add sp, #8
|
|
8004df2: bd80 pop {r7, pc}
|
|
|
|
08004df4 <HAL_TIM_TriggerCallback>:
|
|
* @brief Hall Trigger detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8004df4: b580 push {r7, lr}
|
|
8004df6: b082 sub sp, #8
|
|
8004df8: af00 add r7, sp, #0
|
|
8004dfa: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_TriggerCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8004dfc: 46c0 nop ; (mov r8, r8)
|
|
8004dfe: 46bd mov sp, r7
|
|
8004e00: b002 add sp, #8
|
|
8004e02: bd80 pop {r7, pc}
|
|
|
|
08004e04 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8004e04: b580 push {r7, lr}
|
|
8004e06: b084 sub sp, #16
|
|
8004e08: af00 add r7, sp, #0
|
|
8004e0a: 6078 str r0, [r7, #4]
|
|
8004e0c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
8004e0e: 687b ldr r3, [r7, #4]
|
|
8004e10: 681b ldr r3, [r3, #0]
|
|
8004e12: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8004e14: 687b ldr r3, [r7, #4]
|
|
8004e16: 4a30 ldr r2, [pc, #192] ; (8004ed8 <TIM_Base_SetConfig+0xd4>)
|
|
8004e18: 4293 cmp r3, r2
|
|
8004e1a: d008 beq.n 8004e2e <TIM_Base_SetConfig+0x2a>
|
|
8004e1c: 687a ldr r2, [r7, #4]
|
|
8004e1e: 2380 movs r3, #128 ; 0x80
|
|
8004e20: 05db lsls r3, r3, #23
|
|
8004e22: 429a cmp r2, r3
|
|
8004e24: d003 beq.n 8004e2e <TIM_Base_SetConfig+0x2a>
|
|
8004e26: 687b ldr r3, [r7, #4]
|
|
8004e28: 4a2c ldr r2, [pc, #176] ; (8004edc <TIM_Base_SetConfig+0xd8>)
|
|
8004e2a: 4293 cmp r3, r2
|
|
8004e2c: d108 bne.n 8004e40 <TIM_Base_SetConfig+0x3c>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
8004e2e: 68fb ldr r3, [r7, #12]
|
|
8004e30: 2270 movs r2, #112 ; 0x70
|
|
8004e32: 4393 bics r3, r2
|
|
8004e34: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
8004e36: 683b ldr r3, [r7, #0]
|
|
8004e38: 685b ldr r3, [r3, #4]
|
|
8004e3a: 68fa ldr r2, [r7, #12]
|
|
8004e3c: 4313 orrs r3, r2
|
|
8004e3e: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
8004e40: 687b ldr r3, [r7, #4]
|
|
8004e42: 4a25 ldr r2, [pc, #148] ; (8004ed8 <TIM_Base_SetConfig+0xd4>)
|
|
8004e44: 4293 cmp r3, r2
|
|
8004e46: d014 beq.n 8004e72 <TIM_Base_SetConfig+0x6e>
|
|
8004e48: 687a ldr r2, [r7, #4]
|
|
8004e4a: 2380 movs r3, #128 ; 0x80
|
|
8004e4c: 05db lsls r3, r3, #23
|
|
8004e4e: 429a cmp r2, r3
|
|
8004e50: d00f beq.n 8004e72 <TIM_Base_SetConfig+0x6e>
|
|
8004e52: 687b ldr r3, [r7, #4]
|
|
8004e54: 4a21 ldr r2, [pc, #132] ; (8004edc <TIM_Base_SetConfig+0xd8>)
|
|
8004e56: 4293 cmp r3, r2
|
|
8004e58: d00b beq.n 8004e72 <TIM_Base_SetConfig+0x6e>
|
|
8004e5a: 687b ldr r3, [r7, #4]
|
|
8004e5c: 4a20 ldr r2, [pc, #128] ; (8004ee0 <TIM_Base_SetConfig+0xdc>)
|
|
8004e5e: 4293 cmp r3, r2
|
|
8004e60: d007 beq.n 8004e72 <TIM_Base_SetConfig+0x6e>
|
|
8004e62: 687b ldr r3, [r7, #4]
|
|
8004e64: 4a1f ldr r2, [pc, #124] ; (8004ee4 <TIM_Base_SetConfig+0xe0>)
|
|
8004e66: 4293 cmp r3, r2
|
|
8004e68: d003 beq.n 8004e72 <TIM_Base_SetConfig+0x6e>
|
|
8004e6a: 687b ldr r3, [r7, #4]
|
|
8004e6c: 4a1e ldr r2, [pc, #120] ; (8004ee8 <TIM_Base_SetConfig+0xe4>)
|
|
8004e6e: 4293 cmp r3, r2
|
|
8004e70: d108 bne.n 8004e84 <TIM_Base_SetConfig+0x80>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
8004e72: 68fb ldr r3, [r7, #12]
|
|
8004e74: 4a1d ldr r2, [pc, #116] ; (8004eec <TIM_Base_SetConfig+0xe8>)
|
|
8004e76: 4013 ands r3, r2
|
|
8004e78: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
8004e7a: 683b ldr r3, [r7, #0]
|
|
8004e7c: 68db ldr r3, [r3, #12]
|
|
8004e7e: 68fa ldr r2, [r7, #12]
|
|
8004e80: 4313 orrs r3, r2
|
|
8004e82: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
8004e84: 68fb ldr r3, [r7, #12]
|
|
8004e86: 2280 movs r2, #128 ; 0x80
|
|
8004e88: 4393 bics r3, r2
|
|
8004e8a: 001a movs r2, r3
|
|
8004e8c: 683b ldr r3, [r7, #0]
|
|
8004e8e: 695b ldr r3, [r3, #20]
|
|
8004e90: 4313 orrs r3, r2
|
|
8004e92: 60fb str r3, [r7, #12]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
8004e94: 687b ldr r3, [r7, #4]
|
|
8004e96: 68fa ldr r2, [r7, #12]
|
|
8004e98: 601a str r2, [r3, #0]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
8004e9a: 683b ldr r3, [r7, #0]
|
|
8004e9c: 689a ldr r2, [r3, #8]
|
|
8004e9e: 687b ldr r3, [r7, #4]
|
|
8004ea0: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
8004ea2: 683b ldr r3, [r7, #0]
|
|
8004ea4: 681a ldr r2, [r3, #0]
|
|
8004ea6: 687b ldr r3, [r7, #4]
|
|
8004ea8: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
8004eaa: 687b ldr r3, [r7, #4]
|
|
8004eac: 4a0a ldr r2, [pc, #40] ; (8004ed8 <TIM_Base_SetConfig+0xd4>)
|
|
8004eae: 4293 cmp r3, r2
|
|
8004eb0: d007 beq.n 8004ec2 <TIM_Base_SetConfig+0xbe>
|
|
8004eb2: 687b ldr r3, [r7, #4]
|
|
8004eb4: 4a0b ldr r2, [pc, #44] ; (8004ee4 <TIM_Base_SetConfig+0xe0>)
|
|
8004eb6: 4293 cmp r3, r2
|
|
8004eb8: d003 beq.n 8004ec2 <TIM_Base_SetConfig+0xbe>
|
|
8004eba: 687b ldr r3, [r7, #4]
|
|
8004ebc: 4a0a ldr r2, [pc, #40] ; (8004ee8 <TIM_Base_SetConfig+0xe4>)
|
|
8004ebe: 4293 cmp r3, r2
|
|
8004ec0: d103 bne.n 8004eca <TIM_Base_SetConfig+0xc6>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
8004ec2: 683b ldr r3, [r7, #0]
|
|
8004ec4: 691a ldr r2, [r3, #16]
|
|
8004ec6: 687b ldr r3, [r7, #4]
|
|
8004ec8: 631a str r2, [r3, #48] ; 0x30
|
|
}
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
8004eca: 687b ldr r3, [r7, #4]
|
|
8004ecc: 2201 movs r2, #1
|
|
8004ece: 615a str r2, [r3, #20]
|
|
}
|
|
8004ed0: 46c0 nop ; (mov r8, r8)
|
|
8004ed2: 46bd mov sp, r7
|
|
8004ed4: b004 add sp, #16
|
|
8004ed6: bd80 pop {r7, pc}
|
|
8004ed8: 40012c00 .word 0x40012c00
|
|
8004edc: 40000400 .word 0x40000400
|
|
8004ee0: 40002000 .word 0x40002000
|
|
8004ee4: 40014400 .word 0x40014400
|
|
8004ee8: 40014800 .word 0x40014800
|
|
8004eec: fffffcff .word 0xfffffcff
|
|
|
|
08004ef0 <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004ef0: b580 push {r7, lr}
|
|
8004ef2: b086 sub sp, #24
|
|
8004ef4: af00 add r7, sp, #0
|
|
8004ef6: 6078 str r0, [r7, #4]
|
|
8004ef8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
8004efa: 687b ldr r3, [r7, #4]
|
|
8004efc: 6a1b ldr r3, [r3, #32]
|
|
8004efe: 2201 movs r2, #1
|
|
8004f00: 4393 bics r3, r2
|
|
8004f02: 001a movs r2, r3
|
|
8004f04: 687b ldr r3, [r7, #4]
|
|
8004f06: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8004f08: 687b ldr r3, [r7, #4]
|
|
8004f0a: 6a1b ldr r3, [r3, #32]
|
|
8004f0c: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8004f0e: 687b ldr r3, [r7, #4]
|
|
8004f10: 685b ldr r3, [r3, #4]
|
|
8004f12: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8004f14: 687b ldr r3, [r7, #4]
|
|
8004f16: 699b ldr r3, [r3, #24]
|
|
8004f18: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
8004f1a: 68fb ldr r3, [r7, #12]
|
|
8004f1c: 4a2e ldr r2, [pc, #184] ; (8004fd8 <TIM_OC1_SetConfig+0xe8>)
|
|
8004f1e: 4013 ands r3, r2
|
|
8004f20: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
8004f22: 68fb ldr r3, [r7, #12]
|
|
8004f24: 2203 movs r2, #3
|
|
8004f26: 4393 bics r3, r2
|
|
8004f28: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8004f2a: 683b ldr r3, [r7, #0]
|
|
8004f2c: 681b ldr r3, [r3, #0]
|
|
8004f2e: 68fa ldr r2, [r7, #12]
|
|
8004f30: 4313 orrs r3, r2
|
|
8004f32: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
8004f34: 697b ldr r3, [r7, #20]
|
|
8004f36: 2202 movs r2, #2
|
|
8004f38: 4393 bics r3, r2
|
|
8004f3a: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
8004f3c: 683b ldr r3, [r7, #0]
|
|
8004f3e: 689b ldr r3, [r3, #8]
|
|
8004f40: 697a ldr r2, [r7, #20]
|
|
8004f42: 4313 orrs r3, r2
|
|
8004f44: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
8004f46: 687b ldr r3, [r7, #4]
|
|
8004f48: 4a24 ldr r2, [pc, #144] ; (8004fdc <TIM_OC1_SetConfig+0xec>)
|
|
8004f4a: 4293 cmp r3, r2
|
|
8004f4c: d007 beq.n 8004f5e <TIM_OC1_SetConfig+0x6e>
|
|
8004f4e: 687b ldr r3, [r7, #4]
|
|
8004f50: 4a23 ldr r2, [pc, #140] ; (8004fe0 <TIM_OC1_SetConfig+0xf0>)
|
|
8004f52: 4293 cmp r3, r2
|
|
8004f54: d003 beq.n 8004f5e <TIM_OC1_SetConfig+0x6e>
|
|
8004f56: 687b ldr r3, [r7, #4]
|
|
8004f58: 4a22 ldr r2, [pc, #136] ; (8004fe4 <TIM_OC1_SetConfig+0xf4>)
|
|
8004f5a: 4293 cmp r3, r2
|
|
8004f5c: d10c bne.n 8004f78 <TIM_OC1_SetConfig+0x88>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
8004f5e: 697b ldr r3, [r7, #20]
|
|
8004f60: 2208 movs r2, #8
|
|
8004f62: 4393 bics r3, r2
|
|
8004f64: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
8004f66: 683b ldr r3, [r7, #0]
|
|
8004f68: 68db ldr r3, [r3, #12]
|
|
8004f6a: 697a ldr r2, [r7, #20]
|
|
8004f6c: 4313 orrs r3, r2
|
|
8004f6e: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
8004f70: 697b ldr r3, [r7, #20]
|
|
8004f72: 2204 movs r2, #4
|
|
8004f74: 4393 bics r3, r2
|
|
8004f76: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004f78: 687b ldr r3, [r7, #4]
|
|
8004f7a: 4a18 ldr r2, [pc, #96] ; (8004fdc <TIM_OC1_SetConfig+0xec>)
|
|
8004f7c: 4293 cmp r3, r2
|
|
8004f7e: d007 beq.n 8004f90 <TIM_OC1_SetConfig+0xa0>
|
|
8004f80: 687b ldr r3, [r7, #4]
|
|
8004f82: 4a17 ldr r2, [pc, #92] ; (8004fe0 <TIM_OC1_SetConfig+0xf0>)
|
|
8004f84: 4293 cmp r3, r2
|
|
8004f86: d003 beq.n 8004f90 <TIM_OC1_SetConfig+0xa0>
|
|
8004f88: 687b ldr r3, [r7, #4]
|
|
8004f8a: 4a16 ldr r2, [pc, #88] ; (8004fe4 <TIM_OC1_SetConfig+0xf4>)
|
|
8004f8c: 4293 cmp r3, r2
|
|
8004f8e: d111 bne.n 8004fb4 <TIM_OC1_SetConfig+0xc4>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
8004f90: 693b ldr r3, [r7, #16]
|
|
8004f92: 4a15 ldr r2, [pc, #84] ; (8004fe8 <TIM_OC1_SetConfig+0xf8>)
|
|
8004f94: 4013 ands r3, r2
|
|
8004f96: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
8004f98: 693b ldr r3, [r7, #16]
|
|
8004f9a: 4a14 ldr r2, [pc, #80] ; (8004fec <TIM_OC1_SetConfig+0xfc>)
|
|
8004f9c: 4013 ands r3, r2
|
|
8004f9e: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
8004fa0: 683b ldr r3, [r7, #0]
|
|
8004fa2: 695b ldr r3, [r3, #20]
|
|
8004fa4: 693a ldr r2, [r7, #16]
|
|
8004fa6: 4313 orrs r3, r2
|
|
8004fa8: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
8004faa: 683b ldr r3, [r7, #0]
|
|
8004fac: 699b ldr r3, [r3, #24]
|
|
8004fae: 693a ldr r2, [r7, #16]
|
|
8004fb0: 4313 orrs r3, r2
|
|
8004fb2: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004fb4: 687b ldr r3, [r7, #4]
|
|
8004fb6: 693a ldr r2, [r7, #16]
|
|
8004fb8: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8004fba: 687b ldr r3, [r7, #4]
|
|
8004fbc: 68fa ldr r2, [r7, #12]
|
|
8004fbe: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
8004fc0: 683b ldr r3, [r7, #0]
|
|
8004fc2: 685a ldr r2, [r3, #4]
|
|
8004fc4: 687b ldr r3, [r7, #4]
|
|
8004fc6: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004fc8: 687b ldr r3, [r7, #4]
|
|
8004fca: 697a ldr r2, [r7, #20]
|
|
8004fcc: 621a str r2, [r3, #32]
|
|
}
|
|
8004fce: 46c0 nop ; (mov r8, r8)
|
|
8004fd0: 46bd mov sp, r7
|
|
8004fd2: b006 add sp, #24
|
|
8004fd4: bd80 pop {r7, pc}
|
|
8004fd6: 46c0 nop ; (mov r8, r8)
|
|
8004fd8: fffeff8f .word 0xfffeff8f
|
|
8004fdc: 40012c00 .word 0x40012c00
|
|
8004fe0: 40014400 .word 0x40014400
|
|
8004fe4: 40014800 .word 0x40014800
|
|
8004fe8: fffffeff .word 0xfffffeff
|
|
8004fec: fffffdff .word 0xfffffdff
|
|
|
|
08004ff0 <TIM_OC2_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004ff0: b580 push {r7, lr}
|
|
8004ff2: b086 sub sp, #24
|
|
8004ff4: af00 add r7, sp, #0
|
|
8004ff6: 6078 str r0, [r7, #4]
|
|
8004ff8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8004ffa: 687b ldr r3, [r7, #4]
|
|
8004ffc: 6a1b ldr r3, [r3, #32]
|
|
8004ffe: 2210 movs r2, #16
|
|
8005000: 4393 bics r3, r2
|
|
8005002: 001a movs r2, r3
|
|
8005004: 687b ldr r3, [r7, #4]
|
|
8005006: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8005008: 687b ldr r3, [r7, #4]
|
|
800500a: 6a1b ldr r3, [r3, #32]
|
|
800500c: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800500e: 687b ldr r3, [r7, #4]
|
|
8005010: 685b ldr r3, [r3, #4]
|
|
8005012: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8005014: 687b ldr r3, [r7, #4]
|
|
8005016: 699b ldr r3, [r3, #24]
|
|
8005018: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
800501a: 68fb ldr r3, [r7, #12]
|
|
800501c: 4a2c ldr r2, [pc, #176] ; (80050d0 <TIM_OC2_SetConfig+0xe0>)
|
|
800501e: 4013 ands r3, r2
|
|
8005020: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
8005022: 68fb ldr r3, [r7, #12]
|
|
8005024: 4a2b ldr r2, [pc, #172] ; (80050d4 <TIM_OC2_SetConfig+0xe4>)
|
|
8005026: 4013 ands r3, r2
|
|
8005028: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
800502a: 683b ldr r3, [r7, #0]
|
|
800502c: 681b ldr r3, [r3, #0]
|
|
800502e: 021b lsls r3, r3, #8
|
|
8005030: 68fa ldr r2, [r7, #12]
|
|
8005032: 4313 orrs r3, r2
|
|
8005034: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
8005036: 697b ldr r3, [r7, #20]
|
|
8005038: 2220 movs r2, #32
|
|
800503a: 4393 bics r3, r2
|
|
800503c: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
800503e: 683b ldr r3, [r7, #0]
|
|
8005040: 689b ldr r3, [r3, #8]
|
|
8005042: 011b lsls r3, r3, #4
|
|
8005044: 697a ldr r2, [r7, #20]
|
|
8005046: 4313 orrs r3, r2
|
|
8005048: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
800504a: 687b ldr r3, [r7, #4]
|
|
800504c: 4a22 ldr r2, [pc, #136] ; (80050d8 <TIM_OC2_SetConfig+0xe8>)
|
|
800504e: 4293 cmp r3, r2
|
|
8005050: d10d bne.n 800506e <TIM_OC2_SetConfig+0x7e>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
8005052: 697b ldr r3, [r7, #20]
|
|
8005054: 2280 movs r2, #128 ; 0x80
|
|
8005056: 4393 bics r3, r2
|
|
8005058: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
800505a: 683b ldr r3, [r7, #0]
|
|
800505c: 68db ldr r3, [r3, #12]
|
|
800505e: 011b lsls r3, r3, #4
|
|
8005060: 697a ldr r2, [r7, #20]
|
|
8005062: 4313 orrs r3, r2
|
|
8005064: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
8005066: 697b ldr r3, [r7, #20]
|
|
8005068: 2240 movs r2, #64 ; 0x40
|
|
800506a: 4393 bics r3, r2
|
|
800506c: 617b str r3, [r7, #20]
|
|
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800506e: 687b ldr r3, [r7, #4]
|
|
8005070: 4a19 ldr r2, [pc, #100] ; (80050d8 <TIM_OC2_SetConfig+0xe8>)
|
|
8005072: 4293 cmp r3, r2
|
|
8005074: d007 beq.n 8005086 <TIM_OC2_SetConfig+0x96>
|
|
8005076: 687b ldr r3, [r7, #4]
|
|
8005078: 4a18 ldr r2, [pc, #96] ; (80050dc <TIM_OC2_SetConfig+0xec>)
|
|
800507a: 4293 cmp r3, r2
|
|
800507c: d003 beq.n 8005086 <TIM_OC2_SetConfig+0x96>
|
|
800507e: 687b ldr r3, [r7, #4]
|
|
8005080: 4a17 ldr r2, [pc, #92] ; (80050e0 <TIM_OC2_SetConfig+0xf0>)
|
|
8005082: 4293 cmp r3, r2
|
|
8005084: d113 bne.n 80050ae <TIM_OC2_SetConfig+0xbe>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
8005086: 693b ldr r3, [r7, #16]
|
|
8005088: 4a16 ldr r2, [pc, #88] ; (80050e4 <TIM_OC2_SetConfig+0xf4>)
|
|
800508a: 4013 ands r3, r2
|
|
800508c: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
800508e: 693b ldr r3, [r7, #16]
|
|
8005090: 4a15 ldr r2, [pc, #84] ; (80050e8 <TIM_OC2_SetConfig+0xf8>)
|
|
8005092: 4013 ands r3, r2
|
|
8005094: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
8005096: 683b ldr r3, [r7, #0]
|
|
8005098: 695b ldr r3, [r3, #20]
|
|
800509a: 009b lsls r3, r3, #2
|
|
800509c: 693a ldr r2, [r7, #16]
|
|
800509e: 4313 orrs r3, r2
|
|
80050a0: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
80050a2: 683b ldr r3, [r7, #0]
|
|
80050a4: 699b ldr r3, [r3, #24]
|
|
80050a6: 009b lsls r3, r3, #2
|
|
80050a8: 693a ldr r2, [r7, #16]
|
|
80050aa: 4313 orrs r3, r2
|
|
80050ac: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
80050ae: 687b ldr r3, [r7, #4]
|
|
80050b0: 693a ldr r2, [r7, #16]
|
|
80050b2: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
80050b4: 687b ldr r3, [r7, #4]
|
|
80050b6: 68fa ldr r2, [r7, #12]
|
|
80050b8: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
80050ba: 683b ldr r3, [r7, #0]
|
|
80050bc: 685a ldr r2, [r3, #4]
|
|
80050be: 687b ldr r3, [r7, #4]
|
|
80050c0: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
80050c2: 687b ldr r3, [r7, #4]
|
|
80050c4: 697a ldr r2, [r7, #20]
|
|
80050c6: 621a str r2, [r3, #32]
|
|
}
|
|
80050c8: 46c0 nop ; (mov r8, r8)
|
|
80050ca: 46bd mov sp, r7
|
|
80050cc: b006 add sp, #24
|
|
80050ce: bd80 pop {r7, pc}
|
|
80050d0: feff8fff .word 0xfeff8fff
|
|
80050d4: fffffcff .word 0xfffffcff
|
|
80050d8: 40012c00 .word 0x40012c00
|
|
80050dc: 40014400 .word 0x40014400
|
|
80050e0: 40014800 .word 0x40014800
|
|
80050e4: fffffbff .word 0xfffffbff
|
|
80050e8: fffff7ff .word 0xfffff7ff
|
|
|
|
080050ec <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
80050ec: b580 push {r7, lr}
|
|
80050ee: b086 sub sp, #24
|
|
80050f0: af00 add r7, sp, #0
|
|
80050f2: 6078 str r0, [r7, #4]
|
|
80050f4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
80050f6: 687b ldr r3, [r7, #4]
|
|
80050f8: 6a1b ldr r3, [r3, #32]
|
|
80050fa: 4a33 ldr r2, [pc, #204] ; (80051c8 <TIM_OC3_SetConfig+0xdc>)
|
|
80050fc: 401a ands r2, r3
|
|
80050fe: 687b ldr r3, [r7, #4]
|
|
8005100: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8005102: 687b ldr r3, [r7, #4]
|
|
8005104: 6a1b ldr r3, [r3, #32]
|
|
8005106: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8005108: 687b ldr r3, [r7, #4]
|
|
800510a: 685b ldr r3, [r3, #4]
|
|
800510c: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
800510e: 687b ldr r3, [r7, #4]
|
|
8005110: 69db ldr r3, [r3, #28]
|
|
8005112: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
8005114: 68fb ldr r3, [r7, #12]
|
|
8005116: 4a2d ldr r2, [pc, #180] ; (80051cc <TIM_OC3_SetConfig+0xe0>)
|
|
8005118: 4013 ands r3, r2
|
|
800511a: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
800511c: 68fb ldr r3, [r7, #12]
|
|
800511e: 2203 movs r2, #3
|
|
8005120: 4393 bics r3, r2
|
|
8005122: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8005124: 683b ldr r3, [r7, #0]
|
|
8005126: 681b ldr r3, [r3, #0]
|
|
8005128: 68fa ldr r2, [r7, #12]
|
|
800512a: 4313 orrs r3, r2
|
|
800512c: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
800512e: 697b ldr r3, [r7, #20]
|
|
8005130: 4a27 ldr r2, [pc, #156] ; (80051d0 <TIM_OC3_SetConfig+0xe4>)
|
|
8005132: 4013 ands r3, r2
|
|
8005134: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
8005136: 683b ldr r3, [r7, #0]
|
|
8005138: 689b ldr r3, [r3, #8]
|
|
800513a: 021b lsls r3, r3, #8
|
|
800513c: 697a ldr r2, [r7, #20]
|
|
800513e: 4313 orrs r3, r2
|
|
8005140: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
8005142: 687b ldr r3, [r7, #4]
|
|
8005144: 4a23 ldr r2, [pc, #140] ; (80051d4 <TIM_OC3_SetConfig+0xe8>)
|
|
8005146: 4293 cmp r3, r2
|
|
8005148: d10d bne.n 8005166 <TIM_OC3_SetConfig+0x7a>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
800514a: 697b ldr r3, [r7, #20]
|
|
800514c: 4a22 ldr r2, [pc, #136] ; (80051d8 <TIM_OC3_SetConfig+0xec>)
|
|
800514e: 4013 ands r3, r2
|
|
8005150: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
8005152: 683b ldr r3, [r7, #0]
|
|
8005154: 68db ldr r3, [r3, #12]
|
|
8005156: 021b lsls r3, r3, #8
|
|
8005158: 697a ldr r2, [r7, #20]
|
|
800515a: 4313 orrs r3, r2
|
|
800515c: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
800515e: 697b ldr r3, [r7, #20]
|
|
8005160: 4a1e ldr r2, [pc, #120] ; (80051dc <TIM_OC3_SetConfig+0xf0>)
|
|
8005162: 4013 ands r3, r2
|
|
8005164: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8005166: 687b ldr r3, [r7, #4]
|
|
8005168: 4a1a ldr r2, [pc, #104] ; (80051d4 <TIM_OC3_SetConfig+0xe8>)
|
|
800516a: 4293 cmp r3, r2
|
|
800516c: d007 beq.n 800517e <TIM_OC3_SetConfig+0x92>
|
|
800516e: 687b ldr r3, [r7, #4]
|
|
8005170: 4a1b ldr r2, [pc, #108] ; (80051e0 <TIM_OC3_SetConfig+0xf4>)
|
|
8005172: 4293 cmp r3, r2
|
|
8005174: d003 beq.n 800517e <TIM_OC3_SetConfig+0x92>
|
|
8005176: 687b ldr r3, [r7, #4]
|
|
8005178: 4a1a ldr r2, [pc, #104] ; (80051e4 <TIM_OC3_SetConfig+0xf8>)
|
|
800517a: 4293 cmp r3, r2
|
|
800517c: d113 bne.n 80051a6 <TIM_OC3_SetConfig+0xba>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
800517e: 693b ldr r3, [r7, #16]
|
|
8005180: 4a19 ldr r2, [pc, #100] ; (80051e8 <TIM_OC3_SetConfig+0xfc>)
|
|
8005182: 4013 ands r3, r2
|
|
8005184: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
8005186: 693b ldr r3, [r7, #16]
|
|
8005188: 4a18 ldr r2, [pc, #96] ; (80051ec <TIM_OC3_SetConfig+0x100>)
|
|
800518a: 4013 ands r3, r2
|
|
800518c: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
800518e: 683b ldr r3, [r7, #0]
|
|
8005190: 695b ldr r3, [r3, #20]
|
|
8005192: 011b lsls r3, r3, #4
|
|
8005194: 693a ldr r2, [r7, #16]
|
|
8005196: 4313 orrs r3, r2
|
|
8005198: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
800519a: 683b ldr r3, [r7, #0]
|
|
800519c: 699b ldr r3, [r3, #24]
|
|
800519e: 011b lsls r3, r3, #4
|
|
80051a0: 693a ldr r2, [r7, #16]
|
|
80051a2: 4313 orrs r3, r2
|
|
80051a4: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
80051a6: 687b ldr r3, [r7, #4]
|
|
80051a8: 693a ldr r2, [r7, #16]
|
|
80051aa: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
80051ac: 687b ldr r3, [r7, #4]
|
|
80051ae: 68fa ldr r2, [r7, #12]
|
|
80051b0: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
80051b2: 683b ldr r3, [r7, #0]
|
|
80051b4: 685a ldr r2, [r3, #4]
|
|
80051b6: 687b ldr r3, [r7, #4]
|
|
80051b8: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
80051ba: 687b ldr r3, [r7, #4]
|
|
80051bc: 697a ldr r2, [r7, #20]
|
|
80051be: 621a str r2, [r3, #32]
|
|
}
|
|
80051c0: 46c0 nop ; (mov r8, r8)
|
|
80051c2: 46bd mov sp, r7
|
|
80051c4: b006 add sp, #24
|
|
80051c6: bd80 pop {r7, pc}
|
|
80051c8: fffffeff .word 0xfffffeff
|
|
80051cc: fffeff8f .word 0xfffeff8f
|
|
80051d0: fffffdff .word 0xfffffdff
|
|
80051d4: 40012c00 .word 0x40012c00
|
|
80051d8: fffff7ff .word 0xfffff7ff
|
|
80051dc: fffffbff .word 0xfffffbff
|
|
80051e0: 40014400 .word 0x40014400
|
|
80051e4: 40014800 .word 0x40014800
|
|
80051e8: ffffefff .word 0xffffefff
|
|
80051ec: ffffdfff .word 0xffffdfff
|
|
|
|
080051f0 <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
80051f0: b580 push {r7, lr}
|
|
80051f2: b086 sub sp, #24
|
|
80051f4: af00 add r7, sp, #0
|
|
80051f6: 6078 str r0, [r7, #4]
|
|
80051f8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
80051fa: 687b ldr r3, [r7, #4]
|
|
80051fc: 6a1b ldr r3, [r3, #32]
|
|
80051fe: 4a26 ldr r2, [pc, #152] ; (8005298 <TIM_OC4_SetConfig+0xa8>)
|
|
8005200: 401a ands r2, r3
|
|
8005202: 687b ldr r3, [r7, #4]
|
|
8005204: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8005206: 687b ldr r3, [r7, #4]
|
|
8005208: 6a1b ldr r3, [r3, #32]
|
|
800520a: 613b str r3, [r7, #16]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800520c: 687b ldr r3, [r7, #4]
|
|
800520e: 685b ldr r3, [r3, #4]
|
|
8005210: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8005212: 687b ldr r3, [r7, #4]
|
|
8005214: 69db ldr r3, [r3, #28]
|
|
8005216: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
8005218: 68fb ldr r3, [r7, #12]
|
|
800521a: 4a20 ldr r2, [pc, #128] ; (800529c <TIM_OC4_SetConfig+0xac>)
|
|
800521c: 4013 ands r3, r2
|
|
800521e: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
8005220: 68fb ldr r3, [r7, #12]
|
|
8005222: 4a1f ldr r2, [pc, #124] ; (80052a0 <TIM_OC4_SetConfig+0xb0>)
|
|
8005224: 4013 ands r3, r2
|
|
8005226: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8005228: 683b ldr r3, [r7, #0]
|
|
800522a: 681b ldr r3, [r3, #0]
|
|
800522c: 021b lsls r3, r3, #8
|
|
800522e: 68fa ldr r2, [r7, #12]
|
|
8005230: 4313 orrs r3, r2
|
|
8005232: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
8005234: 693b ldr r3, [r7, #16]
|
|
8005236: 4a1b ldr r2, [pc, #108] ; (80052a4 <TIM_OC4_SetConfig+0xb4>)
|
|
8005238: 4013 ands r3, r2
|
|
800523a: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
800523c: 683b ldr r3, [r7, #0]
|
|
800523e: 689b ldr r3, [r3, #8]
|
|
8005240: 031b lsls r3, r3, #12
|
|
8005242: 693a ldr r2, [r7, #16]
|
|
8005244: 4313 orrs r3, r2
|
|
8005246: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8005248: 687b ldr r3, [r7, #4]
|
|
800524a: 4a17 ldr r2, [pc, #92] ; (80052a8 <TIM_OC4_SetConfig+0xb8>)
|
|
800524c: 4293 cmp r3, r2
|
|
800524e: d007 beq.n 8005260 <TIM_OC4_SetConfig+0x70>
|
|
8005250: 687b ldr r3, [r7, #4]
|
|
8005252: 4a16 ldr r2, [pc, #88] ; (80052ac <TIM_OC4_SetConfig+0xbc>)
|
|
8005254: 4293 cmp r3, r2
|
|
8005256: d003 beq.n 8005260 <TIM_OC4_SetConfig+0x70>
|
|
8005258: 687b ldr r3, [r7, #4]
|
|
800525a: 4a15 ldr r2, [pc, #84] ; (80052b0 <TIM_OC4_SetConfig+0xc0>)
|
|
800525c: 4293 cmp r3, r2
|
|
800525e: d109 bne.n 8005274 <TIM_OC4_SetConfig+0x84>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
8005260: 697b ldr r3, [r7, #20]
|
|
8005262: 4a14 ldr r2, [pc, #80] ; (80052b4 <TIM_OC4_SetConfig+0xc4>)
|
|
8005264: 4013 ands r3, r2
|
|
8005266: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
8005268: 683b ldr r3, [r7, #0]
|
|
800526a: 695b ldr r3, [r3, #20]
|
|
800526c: 019b lsls r3, r3, #6
|
|
800526e: 697a ldr r2, [r7, #20]
|
|
8005270: 4313 orrs r3, r2
|
|
8005272: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005274: 687b ldr r3, [r7, #4]
|
|
8005276: 697a ldr r2, [r7, #20]
|
|
8005278: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
800527a: 687b ldr r3, [r7, #4]
|
|
800527c: 68fa ldr r2, [r7, #12]
|
|
800527e: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
8005280: 683b ldr r3, [r7, #0]
|
|
8005282: 685a ldr r2, [r3, #4]
|
|
8005284: 687b ldr r3, [r7, #4]
|
|
8005286: 641a str r2, [r3, #64] ; 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8005288: 687b ldr r3, [r7, #4]
|
|
800528a: 693a ldr r2, [r7, #16]
|
|
800528c: 621a str r2, [r3, #32]
|
|
}
|
|
800528e: 46c0 nop ; (mov r8, r8)
|
|
8005290: 46bd mov sp, r7
|
|
8005292: b006 add sp, #24
|
|
8005294: bd80 pop {r7, pc}
|
|
8005296: 46c0 nop ; (mov r8, r8)
|
|
8005298: ffffefff .word 0xffffefff
|
|
800529c: feff8fff .word 0xfeff8fff
|
|
80052a0: fffffcff .word 0xfffffcff
|
|
80052a4: ffffdfff .word 0xffffdfff
|
|
80052a8: 40012c00 .word 0x40012c00
|
|
80052ac: 40014400 .word 0x40014400
|
|
80052b0: 40014800 .word 0x40014800
|
|
80052b4: ffffbfff .word 0xffffbfff
|
|
|
|
080052b8 <TIM_OC5_SetConfig>:
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
80052b8: b580 push {r7, lr}
|
|
80052ba: b086 sub sp, #24
|
|
80052bc: af00 add r7, sp, #0
|
|
80052be: 6078 str r0, [r7, #4]
|
|
80052c0: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC5E;
|
|
80052c2: 687b ldr r3, [r7, #4]
|
|
80052c4: 6a1b ldr r3, [r3, #32]
|
|
80052c6: 4a23 ldr r2, [pc, #140] ; (8005354 <TIM_OC5_SetConfig+0x9c>)
|
|
80052c8: 401a ands r2, r3
|
|
80052ca: 687b ldr r3, [r7, #4]
|
|
80052cc: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
80052ce: 687b ldr r3, [r7, #4]
|
|
80052d0: 6a1b ldr r3, [r3, #32]
|
|
80052d2: 613b str r3, [r7, #16]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80052d4: 687b ldr r3, [r7, #4]
|
|
80052d6: 685b ldr r3, [r3, #4]
|
|
80052d8: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
80052da: 687b ldr r3, [r7, #4]
|
|
80052dc: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80052de: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC5M);
|
|
80052e0: 68fb ldr r3, [r7, #12]
|
|
80052e2: 4a1d ldr r2, [pc, #116] ; (8005358 <TIM_OC5_SetConfig+0xa0>)
|
|
80052e4: 4013 ands r3, r2
|
|
80052e6: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
80052e8: 683b ldr r3, [r7, #0]
|
|
80052ea: 681b ldr r3, [r3, #0]
|
|
80052ec: 68fa ldr r2, [r7, #12]
|
|
80052ee: 4313 orrs r3, r2
|
|
80052f0: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC5P;
|
|
80052f2: 693b ldr r3, [r7, #16]
|
|
80052f4: 4a19 ldr r2, [pc, #100] ; (800535c <TIM_OC5_SetConfig+0xa4>)
|
|
80052f6: 4013 ands r3, r2
|
|
80052f8: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 16U);
|
|
80052fa: 683b ldr r3, [r7, #0]
|
|
80052fc: 689b ldr r3, [r3, #8]
|
|
80052fe: 041b lsls r3, r3, #16
|
|
8005300: 693a ldr r2, [r7, #16]
|
|
8005302: 4313 orrs r3, r2
|
|
8005304: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8005306: 687b ldr r3, [r7, #4]
|
|
8005308: 4a15 ldr r2, [pc, #84] ; (8005360 <TIM_OC5_SetConfig+0xa8>)
|
|
800530a: 4293 cmp r3, r2
|
|
800530c: d007 beq.n 800531e <TIM_OC5_SetConfig+0x66>
|
|
800530e: 687b ldr r3, [r7, #4]
|
|
8005310: 4a14 ldr r2, [pc, #80] ; (8005364 <TIM_OC5_SetConfig+0xac>)
|
|
8005312: 4293 cmp r3, r2
|
|
8005314: d003 beq.n 800531e <TIM_OC5_SetConfig+0x66>
|
|
8005316: 687b ldr r3, [r7, #4]
|
|
8005318: 4a13 ldr r2, [pc, #76] ; (8005368 <TIM_OC5_SetConfig+0xb0>)
|
|
800531a: 4293 cmp r3, r2
|
|
800531c: d109 bne.n 8005332 <TIM_OC5_SetConfig+0x7a>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS5;
|
|
800531e: 697b ldr r3, [r7, #20]
|
|
8005320: 4a0c ldr r2, [pc, #48] ; (8005354 <TIM_OC5_SetConfig+0x9c>)
|
|
8005322: 4013 ands r3, r2
|
|
8005324: 617b str r3, [r7, #20]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 8U);
|
|
8005326: 683b ldr r3, [r7, #0]
|
|
8005328: 695b ldr r3, [r3, #20]
|
|
800532a: 021b lsls r3, r3, #8
|
|
800532c: 697a ldr r2, [r7, #20]
|
|
800532e: 4313 orrs r3, r2
|
|
8005330: 617b str r3, [r7, #20]
|
|
}
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005332: 687b ldr r3, [r7, #4]
|
|
8005334: 697a ldr r2, [r7, #20]
|
|
8005336: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
8005338: 687b ldr r3, [r7, #4]
|
|
800533a: 68fa ldr r2, [r7, #12]
|
|
800533c: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR5 = OC_Config->Pulse;
|
|
800533e: 683b ldr r3, [r7, #0]
|
|
8005340: 685a ldr r2, [r3, #4]
|
|
8005342: 687b ldr r3, [r7, #4]
|
|
8005344: 659a str r2, [r3, #88] ; 0x58
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8005346: 687b ldr r3, [r7, #4]
|
|
8005348: 693a ldr r2, [r7, #16]
|
|
800534a: 621a str r2, [r3, #32]
|
|
}
|
|
800534c: 46c0 nop ; (mov r8, r8)
|
|
800534e: 46bd mov sp, r7
|
|
8005350: b006 add sp, #24
|
|
8005352: bd80 pop {r7, pc}
|
|
8005354: fffeffff .word 0xfffeffff
|
|
8005358: fffeff8f .word 0xfffeff8f
|
|
800535c: fffdffff .word 0xfffdffff
|
|
8005360: 40012c00 .word 0x40012c00
|
|
8005364: 40014400 .word 0x40014400
|
|
8005368: 40014800 .word 0x40014800
|
|
|
|
0800536c <TIM_OC6_SetConfig>:
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800536c: b580 push {r7, lr}
|
|
800536e: b086 sub sp, #24
|
|
8005370: af00 add r7, sp, #0
|
|
8005372: 6078 str r0, [r7, #4]
|
|
8005374: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC6E;
|
|
8005376: 687b ldr r3, [r7, #4]
|
|
8005378: 6a1b ldr r3, [r3, #32]
|
|
800537a: 4a24 ldr r2, [pc, #144] ; (800540c <TIM_OC6_SetConfig+0xa0>)
|
|
800537c: 401a ands r2, r3
|
|
800537e: 687b ldr r3, [r7, #4]
|
|
8005380: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8005382: 687b ldr r3, [r7, #4]
|
|
8005384: 6a1b ldr r3, [r3, #32]
|
|
8005386: 613b str r3, [r7, #16]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8005388: 687b ldr r3, [r7, #4]
|
|
800538a: 685b ldr r3, [r3, #4]
|
|
800538c: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
800538e: 687b ldr r3, [r7, #4]
|
|
8005390: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005392: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC6M);
|
|
8005394: 68fb ldr r3, [r7, #12]
|
|
8005396: 4a1e ldr r2, [pc, #120] ; (8005410 <TIM_OC6_SetConfig+0xa4>)
|
|
8005398: 4013 ands r3, r2
|
|
800539a: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
800539c: 683b ldr r3, [r7, #0]
|
|
800539e: 681b ldr r3, [r3, #0]
|
|
80053a0: 021b lsls r3, r3, #8
|
|
80053a2: 68fa ldr r2, [r7, #12]
|
|
80053a4: 4313 orrs r3, r2
|
|
80053a6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
|
|
80053a8: 693b ldr r3, [r7, #16]
|
|
80053aa: 4a1a ldr r2, [pc, #104] ; (8005414 <TIM_OC6_SetConfig+0xa8>)
|
|
80053ac: 4013 ands r3, r2
|
|
80053ae: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 20U);
|
|
80053b0: 683b ldr r3, [r7, #0]
|
|
80053b2: 689b ldr r3, [r3, #8]
|
|
80053b4: 051b lsls r3, r3, #20
|
|
80053b6: 693a ldr r2, [r7, #16]
|
|
80053b8: 4313 orrs r3, r2
|
|
80053ba: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
80053bc: 687b ldr r3, [r7, #4]
|
|
80053be: 4a16 ldr r2, [pc, #88] ; (8005418 <TIM_OC6_SetConfig+0xac>)
|
|
80053c0: 4293 cmp r3, r2
|
|
80053c2: d007 beq.n 80053d4 <TIM_OC6_SetConfig+0x68>
|
|
80053c4: 687b ldr r3, [r7, #4]
|
|
80053c6: 4a15 ldr r2, [pc, #84] ; (800541c <TIM_OC6_SetConfig+0xb0>)
|
|
80053c8: 4293 cmp r3, r2
|
|
80053ca: d003 beq.n 80053d4 <TIM_OC6_SetConfig+0x68>
|
|
80053cc: 687b ldr r3, [r7, #4]
|
|
80053ce: 4a14 ldr r2, [pc, #80] ; (8005420 <TIM_OC6_SetConfig+0xb4>)
|
|
80053d0: 4293 cmp r3, r2
|
|
80053d2: d109 bne.n 80053e8 <TIM_OC6_SetConfig+0x7c>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS6;
|
|
80053d4: 697b ldr r3, [r7, #20]
|
|
80053d6: 4a13 ldr r2, [pc, #76] ; (8005424 <TIM_OC6_SetConfig+0xb8>)
|
|
80053d8: 4013 ands r3, r2
|
|
80053da: 617b str r3, [r7, #20]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 10U);
|
|
80053dc: 683b ldr r3, [r7, #0]
|
|
80053de: 695b ldr r3, [r3, #20]
|
|
80053e0: 029b lsls r3, r3, #10
|
|
80053e2: 697a ldr r2, [r7, #20]
|
|
80053e4: 4313 orrs r3, r2
|
|
80053e6: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
80053e8: 687b ldr r3, [r7, #4]
|
|
80053ea: 697a ldr r2, [r7, #20]
|
|
80053ec: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
80053ee: 687b ldr r3, [r7, #4]
|
|
80053f0: 68fa ldr r2, [r7, #12]
|
|
80053f2: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR6 = OC_Config->Pulse;
|
|
80053f4: 683b ldr r3, [r7, #0]
|
|
80053f6: 685a ldr r2, [r3, #4]
|
|
80053f8: 687b ldr r3, [r7, #4]
|
|
80053fa: 65da str r2, [r3, #92] ; 0x5c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
80053fc: 687b ldr r3, [r7, #4]
|
|
80053fe: 693a ldr r2, [r7, #16]
|
|
8005400: 621a str r2, [r3, #32]
|
|
}
|
|
8005402: 46c0 nop ; (mov r8, r8)
|
|
8005404: 46bd mov sp, r7
|
|
8005406: b006 add sp, #24
|
|
8005408: bd80 pop {r7, pc}
|
|
800540a: 46c0 nop ; (mov r8, r8)
|
|
800540c: ffefffff .word 0xffefffff
|
|
8005410: feff8fff .word 0xfeff8fff
|
|
8005414: ffdfffff .word 0xffdfffff
|
|
8005418: 40012c00 .word 0x40012c00
|
|
800541c: 40014400 .word 0x40014400
|
|
8005420: 40014800 .word 0x40014800
|
|
8005424: fffbffff .word 0xfffbffff
|
|
|
|
08005428 <TIM_TI1_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
8005428: b580 push {r7, lr}
|
|
800542a: b086 sub sp, #24
|
|
800542c: af00 add r7, sp, #0
|
|
800542e: 60f8 str r0, [r7, #12]
|
|
8005430: 60b9 str r1, [r7, #8]
|
|
8005432: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
8005434: 68fb ldr r3, [r7, #12]
|
|
8005436: 6a1b ldr r3, [r3, #32]
|
|
8005438: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
800543a: 68fb ldr r3, [r7, #12]
|
|
800543c: 6a1b ldr r3, [r3, #32]
|
|
800543e: 2201 movs r2, #1
|
|
8005440: 4393 bics r3, r2
|
|
8005442: 001a movs r2, r3
|
|
8005444: 68fb ldr r3, [r7, #12]
|
|
8005446: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
8005448: 68fb ldr r3, [r7, #12]
|
|
800544a: 699b ldr r3, [r3, #24]
|
|
800544c: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
800544e: 693b ldr r3, [r7, #16]
|
|
8005450: 22f0 movs r2, #240 ; 0xf0
|
|
8005452: 4393 bics r3, r2
|
|
8005454: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
8005456: 687b ldr r3, [r7, #4]
|
|
8005458: 011b lsls r3, r3, #4
|
|
800545a: 693a ldr r2, [r7, #16]
|
|
800545c: 4313 orrs r3, r2
|
|
800545e: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC1E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
8005460: 697b ldr r3, [r7, #20]
|
|
8005462: 220a movs r2, #10
|
|
8005464: 4393 bics r3, r2
|
|
8005466: 617b str r3, [r7, #20]
|
|
tmpccer |= TIM_ICPolarity;
|
|
8005468: 697a ldr r2, [r7, #20]
|
|
800546a: 68bb ldr r3, [r7, #8]
|
|
800546c: 4313 orrs r3, r2
|
|
800546e: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1;
|
|
8005470: 68fb ldr r3, [r7, #12]
|
|
8005472: 693a ldr r2, [r7, #16]
|
|
8005474: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
8005476: 68fb ldr r3, [r7, #12]
|
|
8005478: 697a ldr r2, [r7, #20]
|
|
800547a: 621a str r2, [r3, #32]
|
|
}
|
|
800547c: 46c0 nop ; (mov r8, r8)
|
|
800547e: 46bd mov sp, r7
|
|
8005480: b006 add sp, #24
|
|
8005482: bd80 pop {r7, pc}
|
|
|
|
08005484 <TIM_TI2_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
8005484: b580 push {r7, lr}
|
|
8005486: b086 sub sp, #24
|
|
8005488: af00 add r7, sp, #0
|
|
800548a: 60f8 str r0, [r7, #12]
|
|
800548c: 60b9 str r1, [r7, #8]
|
|
800548e: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8005490: 68fb ldr r3, [r7, #12]
|
|
8005492: 6a1b ldr r3, [r3, #32]
|
|
8005494: 2210 movs r2, #16
|
|
8005496: 4393 bics r3, r2
|
|
8005498: 001a movs r2, r3
|
|
800549a: 68fb ldr r3, [r7, #12]
|
|
800549c: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
800549e: 68fb ldr r3, [r7, #12]
|
|
80054a0: 699b ldr r3, [r3, #24]
|
|
80054a2: 617b str r3, [r7, #20]
|
|
tmpccer = TIMx->CCER;
|
|
80054a4: 68fb ldr r3, [r7, #12]
|
|
80054a6: 6a1b ldr r3, [r3, #32]
|
|
80054a8: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
80054aa: 697b ldr r3, [r7, #20]
|
|
80054ac: 4a0d ldr r2, [pc, #52] ; (80054e4 <TIM_TI2_ConfigInputStage+0x60>)
|
|
80054ae: 4013 ands r3, r2
|
|
80054b0: 617b str r3, [r7, #20]
|
|
tmpccmr1 |= (TIM_ICFilter << 12U);
|
|
80054b2: 687b ldr r3, [r7, #4]
|
|
80054b4: 031b lsls r3, r3, #12
|
|
80054b6: 697a ldr r2, [r7, #20]
|
|
80054b8: 4313 orrs r3, r2
|
|
80054ba: 617b str r3, [r7, #20]
|
|
|
|
/* Select the Polarity and set the CC2E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
80054bc: 693b ldr r3, [r7, #16]
|
|
80054be: 22a0 movs r2, #160 ; 0xa0
|
|
80054c0: 4393 bics r3, r2
|
|
80054c2: 613b str r3, [r7, #16]
|
|
tmpccer |= (TIM_ICPolarity << 4U);
|
|
80054c4: 68bb ldr r3, [r7, #8]
|
|
80054c6: 011b lsls r3, r3, #4
|
|
80054c8: 693a ldr r2, [r7, #16]
|
|
80054ca: 4313 orrs r3, r2
|
|
80054cc: 613b str r3, [r7, #16]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1 ;
|
|
80054ce: 68fb ldr r3, [r7, #12]
|
|
80054d0: 697a ldr r2, [r7, #20]
|
|
80054d2: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
80054d4: 68fb ldr r3, [r7, #12]
|
|
80054d6: 693a ldr r2, [r7, #16]
|
|
80054d8: 621a str r2, [r3, #32]
|
|
}
|
|
80054da: 46c0 nop ; (mov r8, r8)
|
|
80054dc: 46bd mov sp, r7
|
|
80054de: b006 add sp, #24
|
|
80054e0: bd80 pop {r7, pc}
|
|
80054e2: 46c0 nop ; (mov r8, r8)
|
|
80054e4: ffff0fff .word 0xffff0fff
|
|
|
|
080054e8 <TIM_ITRx_SetConfig>:
|
|
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
|
* @arg TIM_TS_ETRF: External Trigger input
|
|
* @retval None
|
|
*/
|
|
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
|
|
{
|
|
80054e8: b580 push {r7, lr}
|
|
80054ea: b084 sub sp, #16
|
|
80054ec: af00 add r7, sp, #0
|
|
80054ee: 6078 str r0, [r7, #4]
|
|
80054f0: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = TIMx->SMCR;
|
|
80054f2: 687b ldr r3, [r7, #4]
|
|
80054f4: 689b ldr r3, [r3, #8]
|
|
80054f6: 60fb str r3, [r7, #12]
|
|
/* Reset the TS Bits */
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
80054f8: 68fb ldr r3, [r7, #12]
|
|
80054fa: 4a08 ldr r2, [pc, #32] ; (800551c <TIM_ITRx_SetConfig+0x34>)
|
|
80054fc: 4013 ands r3, r2
|
|
80054fe: 60fb str r3, [r7, #12]
|
|
/* Set the Input Trigger source and the slave mode*/
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
8005500: 683a ldr r2, [r7, #0]
|
|
8005502: 68fb ldr r3, [r7, #12]
|
|
8005504: 4313 orrs r3, r2
|
|
8005506: 2207 movs r2, #7
|
|
8005508: 4313 orrs r3, r2
|
|
800550a: 60fb str r3, [r7, #12]
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
800550c: 687b ldr r3, [r7, #4]
|
|
800550e: 68fa ldr r2, [r7, #12]
|
|
8005510: 609a str r2, [r3, #8]
|
|
}
|
|
8005512: 46c0 nop ; (mov r8, r8)
|
|
8005514: 46bd mov sp, r7
|
|
8005516: b004 add sp, #16
|
|
8005518: bd80 pop {r7, pc}
|
|
800551a: 46c0 nop ; (mov r8, r8)
|
|
800551c: ffcfff8f .word 0xffcfff8f
|
|
|
|
08005520 <TIM_ETR_SetConfig>:
|
|
* This parameter must be a value between 0x00 and 0x0F
|
|
* @retval None
|
|
*/
|
|
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
|
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
|
|
{
|
|
8005520: b580 push {r7, lr}
|
|
8005522: b086 sub sp, #24
|
|
8005524: af00 add r7, sp, #0
|
|
8005526: 60f8 str r0, [r7, #12]
|
|
8005528: 60b9 str r1, [r7, #8]
|
|
800552a: 607a str r2, [r7, #4]
|
|
800552c: 603b str r3, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
tmpsmcr = TIMx->SMCR;
|
|
800552e: 68fb ldr r3, [r7, #12]
|
|
8005530: 689b ldr r3, [r3, #8]
|
|
8005532: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the ETR Bits */
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
8005534: 697b ldr r3, [r7, #20]
|
|
8005536: 4a09 ldr r2, [pc, #36] ; (800555c <TIM_ETR_SetConfig+0x3c>)
|
|
8005538: 4013 ands r3, r2
|
|
800553a: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Prescaler, the Filter value and the Polarity */
|
|
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
|
|
800553c: 683b ldr r3, [r7, #0]
|
|
800553e: 021a lsls r2, r3, #8
|
|
8005540: 687b ldr r3, [r7, #4]
|
|
8005542: 431a orrs r2, r3
|
|
8005544: 68bb ldr r3, [r7, #8]
|
|
8005546: 4313 orrs r3, r2
|
|
8005548: 697a ldr r2, [r7, #20]
|
|
800554a: 4313 orrs r3, r2
|
|
800554c: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
800554e: 68fb ldr r3, [r7, #12]
|
|
8005550: 697a ldr r2, [r7, #20]
|
|
8005552: 609a str r2, [r3, #8]
|
|
}
|
|
8005554: 46c0 nop ; (mov r8, r8)
|
|
8005556: 46bd mov sp, r7
|
|
8005558: b006 add sp, #24
|
|
800555a: bd80 pop {r7, pc}
|
|
800555c: ffff00ff .word 0xffff00ff
|
|
|
|
08005560 <TIM_CCxChannelCmd>:
|
|
* @param ChannelState specifies the TIM Channel CCxE bit new state.
|
|
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
|
|
* @retval None
|
|
*/
|
|
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
|
|
{
|
|
8005560: b580 push {r7, lr}
|
|
8005562: b086 sub sp, #24
|
|
8005564: af00 add r7, sp, #0
|
|
8005566: 60f8 str r0, [r7, #12]
|
|
8005568: 60b9 str r1, [r7, #8]
|
|
800556a: 607a str r2, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
|
|
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
|
800556c: 68bb ldr r3, [r7, #8]
|
|
800556e: 221f movs r2, #31
|
|
8005570: 4013 ands r3, r2
|
|
8005572: 2201 movs r2, #1
|
|
8005574: 409a lsls r2, r3
|
|
8005576: 0013 movs r3, r2
|
|
8005578: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the CCxE Bit */
|
|
TIMx->CCER &= ~tmp;
|
|
800557a: 68fb ldr r3, [r7, #12]
|
|
800557c: 6a1b ldr r3, [r3, #32]
|
|
800557e: 697a ldr r2, [r7, #20]
|
|
8005580: 43d2 mvns r2, r2
|
|
8005582: 401a ands r2, r3
|
|
8005584: 68fb ldr r3, [r7, #12]
|
|
8005586: 621a str r2, [r3, #32]
|
|
|
|
/* Set or reset the CCxE Bit */
|
|
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
|
8005588: 68fb ldr r3, [r7, #12]
|
|
800558a: 6a1a ldr r2, [r3, #32]
|
|
800558c: 68bb ldr r3, [r7, #8]
|
|
800558e: 211f movs r1, #31
|
|
8005590: 400b ands r3, r1
|
|
8005592: 6879 ldr r1, [r7, #4]
|
|
8005594: 4099 lsls r1, r3
|
|
8005596: 000b movs r3, r1
|
|
8005598: 431a orrs r2, r3
|
|
800559a: 68fb ldr r3, [r7, #12]
|
|
800559c: 621a str r2, [r3, #32]
|
|
}
|
|
800559e: 46c0 nop ; (mov r8, r8)
|
|
80055a0: 46bd mov sp, r7
|
|
80055a2: b006 add sp, #24
|
|
80055a4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080055a8 <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
80055a8: b580 push {r7, lr}
|
|
80055aa: b084 sub sp, #16
|
|
80055ac: af00 add r7, sp, #0
|
|
80055ae: 6078 str r0, [r7, #4]
|
|
80055b0: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
80055b2: 687b ldr r3, [r7, #4]
|
|
80055b4: 223c movs r2, #60 ; 0x3c
|
|
80055b6: 5c9b ldrb r3, [r3, r2]
|
|
80055b8: 2b01 cmp r3, #1
|
|
80055ba: d101 bne.n 80055c0 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
80055bc: 2302 movs r3, #2
|
|
80055be: e050 b.n 8005662 <HAL_TIMEx_MasterConfigSynchronization+0xba>
|
|
80055c0: 687b ldr r3, [r7, #4]
|
|
80055c2: 223c movs r2, #60 ; 0x3c
|
|
80055c4: 2101 movs r1, #1
|
|
80055c6: 5499 strb r1, [r3, r2]
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80055c8: 687b ldr r3, [r7, #4]
|
|
80055ca: 223d movs r2, #61 ; 0x3d
|
|
80055cc: 2102 movs r1, #2
|
|
80055ce: 5499 strb r1, [r3, r2]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
80055d0: 687b ldr r3, [r7, #4]
|
|
80055d2: 681b ldr r3, [r3, #0]
|
|
80055d4: 685b ldr r3, [r3, #4]
|
|
80055d6: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80055d8: 687b ldr r3, [r7, #4]
|
|
80055da: 681b ldr r3, [r3, #0]
|
|
80055dc: 689b ldr r3, [r3, #8]
|
|
80055de: 60bb str r3, [r7, #8]
|
|
|
|
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
|
|
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
|
|
80055e0: 687b ldr r3, [r7, #4]
|
|
80055e2: 681b ldr r3, [r3, #0]
|
|
80055e4: 4a21 ldr r2, [pc, #132] ; (800566c <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
|
|
80055e6: 4293 cmp r3, r2
|
|
80055e8: d108 bne.n 80055fc <HAL_TIMEx_MasterConfigSynchronization+0x54>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
|
|
|
|
/* Clear the MMS2 bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS2;
|
|
80055ea: 68fb ldr r3, [r7, #12]
|
|
80055ec: 4a20 ldr r2, [pc, #128] ; (8005670 <HAL_TIMEx_MasterConfigSynchronization+0xc8>)
|
|
80055ee: 4013 ands r3, r2
|
|
80055f0: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO2 source*/
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
|
|
80055f2: 683b ldr r3, [r7, #0]
|
|
80055f4: 685b ldr r3, [r3, #4]
|
|
80055f6: 68fa ldr r2, [r7, #12]
|
|
80055f8: 4313 orrs r3, r2
|
|
80055fa: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
80055fc: 68fb ldr r3, [r7, #12]
|
|
80055fe: 2270 movs r2, #112 ; 0x70
|
|
8005600: 4393 bics r3, r2
|
|
8005602: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8005604: 683b ldr r3, [r7, #0]
|
|
8005606: 681b ldr r3, [r3, #0]
|
|
8005608: 68fa ldr r2, [r7, #12]
|
|
800560a: 4313 orrs r3, r2
|
|
800560c: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
800560e: 687b ldr r3, [r7, #4]
|
|
8005610: 681b ldr r3, [r3, #0]
|
|
8005612: 68fa ldr r2, [r7, #12]
|
|
8005614: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8005616: 687b ldr r3, [r7, #4]
|
|
8005618: 681b ldr r3, [r3, #0]
|
|
800561a: 4a14 ldr r2, [pc, #80] ; (800566c <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
|
|
800561c: 4293 cmp r3, r2
|
|
800561e: d00a beq.n 8005636 <HAL_TIMEx_MasterConfigSynchronization+0x8e>
|
|
8005620: 687b ldr r3, [r7, #4]
|
|
8005622: 681a ldr r2, [r3, #0]
|
|
8005624: 2380 movs r3, #128 ; 0x80
|
|
8005626: 05db lsls r3, r3, #23
|
|
8005628: 429a cmp r2, r3
|
|
800562a: d004 beq.n 8005636 <HAL_TIMEx_MasterConfigSynchronization+0x8e>
|
|
800562c: 687b ldr r3, [r7, #4]
|
|
800562e: 681b ldr r3, [r3, #0]
|
|
8005630: 4a10 ldr r2, [pc, #64] ; (8005674 <HAL_TIMEx_MasterConfigSynchronization+0xcc>)
|
|
8005632: 4293 cmp r3, r2
|
|
8005634: d10c bne.n 8005650 <HAL_TIMEx_MasterConfigSynchronization+0xa8>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
8005636: 68bb ldr r3, [r7, #8]
|
|
8005638: 2280 movs r2, #128 ; 0x80
|
|
800563a: 4393 bics r3, r2
|
|
800563c: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
800563e: 683b ldr r3, [r7, #0]
|
|
8005640: 689b ldr r3, [r3, #8]
|
|
8005642: 68ba ldr r2, [r7, #8]
|
|
8005644: 4313 orrs r3, r2
|
|
8005646: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8005648: 687b ldr r3, [r7, #4]
|
|
800564a: 681b ldr r3, [r3, #0]
|
|
800564c: 68ba ldr r2, [r7, #8]
|
|
800564e: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005650: 687b ldr r3, [r7, #4]
|
|
8005652: 223d movs r2, #61 ; 0x3d
|
|
8005654: 2101 movs r1, #1
|
|
8005656: 5499 strb r1, [r3, r2]
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8005658: 687b ldr r3, [r7, #4]
|
|
800565a: 223c movs r2, #60 ; 0x3c
|
|
800565c: 2100 movs r1, #0
|
|
800565e: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_OK;
|
|
8005660: 2300 movs r3, #0
|
|
}
|
|
8005662: 0018 movs r0, r3
|
|
8005664: 46bd mov sp, r7
|
|
8005666: b004 add sp, #16
|
|
8005668: bd80 pop {r7, pc}
|
|
800566a: 46c0 nop ; (mov r8, r8)
|
|
800566c: 40012c00 .word 0x40012c00
|
|
8005670: ff0fffff .word 0xff0fffff
|
|
8005674: 40000400 .word 0x40000400
|
|
|
|
08005678 <HAL_TIMEx_CommutCallback>:
|
|
* @brief Hall commutation changed callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005678: b580 push {r7, lr}
|
|
800567a: b082 sub sp, #8
|
|
800567c: af00 add r7, sp, #0
|
|
800567e: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_CommutCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005680: 46c0 nop ; (mov r8, r8)
|
|
8005682: 46bd mov sp, r7
|
|
8005684: b002 add sp, #8
|
|
8005686: bd80 pop {r7, pc}
|
|
|
|
08005688 <HAL_TIMEx_BreakCallback>:
|
|
* @brief Hall Break detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005688: b580 push {r7, lr}
|
|
800568a: b082 sub sp, #8
|
|
800568c: af00 add r7, sp, #0
|
|
800568e: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_BreakCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005690: 46c0 nop ; (mov r8, r8)
|
|
8005692: 46bd mov sp, r7
|
|
8005694: b002 add sp, #8
|
|
8005696: bd80 pop {r7, pc}
|
|
|
|
08005698 <HAL_TIMEx_Break2Callback>:
|
|
* @brief Hall Break2 detection callback in non blocking mode
|
|
* @param htim: TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005698: b580 push {r7, lr}
|
|
800569a: b082 sub sp, #8
|
|
800569c: af00 add r7, sp, #0
|
|
800569e: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_Break2Callback could be implemented in the user file
|
|
*/
|
|
}
|
|
80056a0: 46c0 nop ; (mov r8, r8)
|
|
80056a2: 46bd mov sp, r7
|
|
80056a4: b002 add sp, #8
|
|
80056a6: bd80 pop {r7, pc}
|
|
|
|
080056a8 <writeReg>:
|
|
|
|
//---------------------------------------------------------
|
|
// I2C communication Functions
|
|
//---------------------------------------------------------
|
|
// Write an 8-bit register
|
|
void writeReg(uint8_t reg, uint8_t value) {
|
|
80056a8: b580 push {r7, lr}
|
|
80056aa: b086 sub sp, #24
|
|
80056ac: af04 add r7, sp, #16
|
|
80056ae: 0002 movs r2, r0
|
|
80056b0: 1dfb adds r3, r7, #7
|
|
80056b2: 701a strb r2, [r3, #0]
|
|
80056b4: 1dbb adds r3, r7, #6
|
|
80056b6: 1c0a adds r2, r1, #0
|
|
80056b8: 701a strb r2, [r3, #0]
|
|
HAL_I2C_Mem_Write(&TOF_I2C, g_i2cAddr, reg, I2C_MEMADD_SIZE_8BIT, &value, 1, HAL_MAX_DELAY);
|
|
80056ba: 4b0a ldr r3, [pc, #40] ; (80056e4 <writeReg+0x3c>)
|
|
80056bc: 781b ldrb r3, [r3, #0]
|
|
80056be: b299 uxth r1, r3
|
|
80056c0: 1dfb adds r3, r7, #7
|
|
80056c2: 781b ldrb r3, [r3, #0]
|
|
80056c4: b29a uxth r2, r3
|
|
80056c6: 4808 ldr r0, [pc, #32] ; (80056e8 <writeReg+0x40>)
|
|
80056c8: 2301 movs r3, #1
|
|
80056ca: 425b negs r3, r3
|
|
80056cc: 9302 str r3, [sp, #8]
|
|
80056ce: 2301 movs r3, #1
|
|
80056d0: 9301 str r3, [sp, #4]
|
|
80056d2: 1dbb adds r3, r7, #6
|
|
80056d4: 9300 str r3, [sp, #0]
|
|
80056d6: 2301 movs r3, #1
|
|
80056d8: f7fd fa20 bl 8002b1c <HAL_I2C_Mem_Write>
|
|
}
|
|
80056dc: 46c0 nop ; (mov r8, r8)
|
|
80056de: 46bd mov sp, r7
|
|
80056e0: b002 add sp, #8
|
|
80056e2: bd80 pop {r7, pc}
|
|
80056e4: 2000000d .word 0x2000000d
|
|
80056e8: 200000d8 .word 0x200000d8
|
|
|
|
080056ec <writeReg16Bit>:
|
|
|
|
// Write a 16-bit register
|
|
void writeReg16Bit(uint8_t reg, uint16_t value) {
|
|
80056ec: b590 push {r4, r7, lr}
|
|
80056ee: b089 sub sp, #36 ; 0x24
|
|
80056f0: af04 add r7, sp, #16
|
|
80056f2: 0002 movs r2, r0
|
|
80056f4: 1dfb adds r3, r7, #7
|
|
80056f6: 701a strb r2, [r3, #0]
|
|
80056f8: 1d3b adds r3, r7, #4
|
|
80056fa: 1c0a adds r2, r1, #0
|
|
80056fc: 801a strh r2, [r3, #0]
|
|
uint8_t data[2];
|
|
|
|
data[0] = (value >> 8) & 0xFF;
|
|
80056fe: 1d3b adds r3, r7, #4
|
|
8005700: 881b ldrh r3, [r3, #0]
|
|
8005702: 0a1b lsrs r3, r3, #8
|
|
8005704: b29b uxth r3, r3
|
|
8005706: b2da uxtb r2, r3
|
|
8005708: 240c movs r4, #12
|
|
800570a: 193b adds r3, r7, r4
|
|
800570c: 701a strb r2, [r3, #0]
|
|
data[1] = (value ) & 0xFF;
|
|
800570e: 1d3b adds r3, r7, #4
|
|
8005710: 881b ldrh r3, [r3, #0]
|
|
8005712: b2da uxtb r2, r3
|
|
8005714: 193b adds r3, r7, r4
|
|
8005716: 705a strb r2, [r3, #1]
|
|
HAL_I2C_Mem_Write(&TOF_I2C, g_i2cAddr, reg, I2C_MEMADD_SIZE_8BIT, data, 2, HAL_MAX_DELAY);
|
|
8005718: 4b0a ldr r3, [pc, #40] ; (8005744 <writeReg16Bit+0x58>)
|
|
800571a: 781b ldrb r3, [r3, #0]
|
|
800571c: b299 uxth r1, r3
|
|
800571e: 1dfb adds r3, r7, #7
|
|
8005720: 781b ldrb r3, [r3, #0]
|
|
8005722: b29a uxth r2, r3
|
|
8005724: 4808 ldr r0, [pc, #32] ; (8005748 <writeReg16Bit+0x5c>)
|
|
8005726: 2301 movs r3, #1
|
|
8005728: 425b negs r3, r3
|
|
800572a: 9302 str r3, [sp, #8]
|
|
800572c: 2302 movs r3, #2
|
|
800572e: 9301 str r3, [sp, #4]
|
|
8005730: 193b adds r3, r7, r4
|
|
8005732: 9300 str r3, [sp, #0]
|
|
8005734: 2301 movs r3, #1
|
|
8005736: f7fd f9f1 bl 8002b1c <HAL_I2C_Mem_Write>
|
|
}
|
|
800573a: 46c0 nop ; (mov r8, r8)
|
|
800573c: 46bd mov sp, r7
|
|
800573e: b005 add sp, #20
|
|
8005740: bd90 pop {r4, r7, pc}
|
|
8005742: 46c0 nop ; (mov r8, r8)
|
|
8005744: 2000000d .word 0x2000000d
|
|
8005748: 200000d8 .word 0x200000d8
|
|
|
|
0800574c <writeReg32Bit>:
|
|
|
|
// Write a 32-bit register
|
|
void writeReg32Bit(uint8_t reg, uint32_t value) {
|
|
800574c: b590 push {r4, r7, lr}
|
|
800574e: b089 sub sp, #36 ; 0x24
|
|
8005750: af04 add r7, sp, #16
|
|
8005752: 0002 movs r2, r0
|
|
8005754: 6039 str r1, [r7, #0]
|
|
8005756: 1dfb adds r3, r7, #7
|
|
8005758: 701a strb r2, [r3, #0]
|
|
uint8_t data[4];
|
|
|
|
data[0] = (value >> 24) & 0xFF;
|
|
800575a: 683b ldr r3, [r7, #0]
|
|
800575c: 0e1b lsrs r3, r3, #24
|
|
800575e: b2da uxtb r2, r3
|
|
8005760: 240c movs r4, #12
|
|
8005762: 193b adds r3, r7, r4
|
|
8005764: 701a strb r2, [r3, #0]
|
|
data[1] = (value >> 16) & 0xFF;
|
|
8005766: 683b ldr r3, [r7, #0]
|
|
8005768: 0c1b lsrs r3, r3, #16
|
|
800576a: b2da uxtb r2, r3
|
|
800576c: 193b adds r3, r7, r4
|
|
800576e: 705a strb r2, [r3, #1]
|
|
data[2] = (value >> 8) & 0xFF;
|
|
8005770: 683b ldr r3, [r7, #0]
|
|
8005772: 0a1b lsrs r3, r3, #8
|
|
8005774: b2da uxtb r2, r3
|
|
8005776: 193b adds r3, r7, r4
|
|
8005778: 709a strb r2, [r3, #2]
|
|
data[3] = (value ) & 0xFF;
|
|
800577a: 683b ldr r3, [r7, #0]
|
|
800577c: b2da uxtb r2, r3
|
|
800577e: 193b adds r3, r7, r4
|
|
8005780: 70da strb r2, [r3, #3]
|
|
HAL_I2C_Mem_Write(&TOF_I2C, g_i2cAddr, reg, I2C_MEMADD_SIZE_8BIT, data, 4, HAL_MAX_DELAY);
|
|
8005782: 4b0a ldr r3, [pc, #40] ; (80057ac <writeReg32Bit+0x60>)
|
|
8005784: 781b ldrb r3, [r3, #0]
|
|
8005786: b299 uxth r1, r3
|
|
8005788: 1dfb adds r3, r7, #7
|
|
800578a: 781b ldrb r3, [r3, #0]
|
|
800578c: b29a uxth r2, r3
|
|
800578e: 4808 ldr r0, [pc, #32] ; (80057b0 <writeReg32Bit+0x64>)
|
|
8005790: 2301 movs r3, #1
|
|
8005792: 425b negs r3, r3
|
|
8005794: 9302 str r3, [sp, #8]
|
|
8005796: 2304 movs r3, #4
|
|
8005798: 9301 str r3, [sp, #4]
|
|
800579a: 193b adds r3, r7, r4
|
|
800579c: 9300 str r3, [sp, #0]
|
|
800579e: 2301 movs r3, #1
|
|
80057a0: f7fd f9bc bl 8002b1c <HAL_I2C_Mem_Write>
|
|
}
|
|
80057a4: 46c0 nop ; (mov r8, r8)
|
|
80057a6: 46bd mov sp, r7
|
|
80057a8: b005 add sp, #20
|
|
80057aa: bd90 pop {r4, r7, pc}
|
|
80057ac: 2000000d .word 0x2000000d
|
|
80057b0: 200000d8 .word 0x200000d8
|
|
|
|
080057b4 <readReg>:
|
|
|
|
// Read an 8-bit register
|
|
uint8_t readReg(uint8_t reg) {
|
|
80057b4: b590 push {r4, r7, lr}
|
|
80057b6: b089 sub sp, #36 ; 0x24
|
|
80057b8: af04 add r7, sp, #16
|
|
80057ba: 0002 movs r2, r0
|
|
80057bc: 1dfb adds r3, r7, #7
|
|
80057be: 701a strb r2, [r3, #0]
|
|
uint8_t data;
|
|
|
|
HAL_I2C_Mem_Read(&TOF_I2C, g_i2cAddr, reg, I2C_MEMADD_SIZE_8BIT, &data, 1, HAL_MAX_DELAY);
|
|
80057c0: 4b0b ldr r3, [pc, #44] ; (80057f0 <readReg+0x3c>)
|
|
80057c2: 781b ldrb r3, [r3, #0]
|
|
80057c4: b299 uxth r1, r3
|
|
80057c6: 1dfb adds r3, r7, #7
|
|
80057c8: 781b ldrb r3, [r3, #0]
|
|
80057ca: b29a uxth r2, r3
|
|
80057cc: 4809 ldr r0, [pc, #36] ; (80057f4 <readReg+0x40>)
|
|
80057ce: 2301 movs r3, #1
|
|
80057d0: 425b negs r3, r3
|
|
80057d2: 9302 str r3, [sp, #8]
|
|
80057d4: 2301 movs r3, #1
|
|
80057d6: 9301 str r3, [sp, #4]
|
|
80057d8: 240f movs r4, #15
|
|
80057da: 193b adds r3, r7, r4
|
|
80057dc: 9300 str r3, [sp, #0]
|
|
80057de: 2301 movs r3, #1
|
|
80057e0: f7fd faca bl 8002d78 <HAL_I2C_Mem_Read>
|
|
return data;
|
|
80057e4: 193b adds r3, r7, r4
|
|
80057e6: 781b ldrb r3, [r3, #0]
|
|
}
|
|
80057e8: 0018 movs r0, r3
|
|
80057ea: 46bd mov sp, r7
|
|
80057ec: b005 add sp, #20
|
|
80057ee: bd90 pop {r4, r7, pc}
|
|
80057f0: 2000000d .word 0x2000000d
|
|
80057f4: 200000d8 .word 0x200000d8
|
|
|
|
080057f8 <readReg16Bit>:
|
|
|
|
// Read a 16-bit register
|
|
uint16_t readReg16Bit(uint8_t reg) {
|
|
80057f8: b590 push {r4, r7, lr}
|
|
80057fa: b089 sub sp, #36 ; 0x24
|
|
80057fc: af04 add r7, sp, #16
|
|
80057fe: 0002 movs r2, r0
|
|
8005800: 1dfb adds r3, r7, #7
|
|
8005802: 701a strb r2, [r3, #0]
|
|
uint16_t value;
|
|
uint8_t data[2];
|
|
|
|
HAL_I2C_Mem_Read(&TOF_I2C, g_i2cAddr, reg, I2C_MEMADD_SIZE_8BIT, data, 2, HAL_MAX_DELAY);
|
|
8005804: 4b13 ldr r3, [pc, #76] ; (8005854 <readReg16Bit+0x5c>)
|
|
8005806: 781b ldrb r3, [r3, #0]
|
|
8005808: b299 uxth r1, r3
|
|
800580a: 1dfb adds r3, r7, #7
|
|
800580c: 781b ldrb r3, [r3, #0]
|
|
800580e: b29a uxth r2, r3
|
|
8005810: 4811 ldr r0, [pc, #68] ; (8005858 <readReg16Bit+0x60>)
|
|
8005812: 2301 movs r3, #1
|
|
8005814: 425b negs r3, r3
|
|
8005816: 9302 str r3, [sp, #8]
|
|
8005818: 2302 movs r3, #2
|
|
800581a: 9301 str r3, [sp, #4]
|
|
800581c: 240c movs r4, #12
|
|
800581e: 193b adds r3, r7, r4
|
|
8005820: 9300 str r3, [sp, #0]
|
|
8005822: 2301 movs r3, #1
|
|
8005824: f7fd faa8 bl 8002d78 <HAL_I2C_Mem_Read>
|
|
value = data[0] << 8;
|
|
8005828: 0021 movs r1, r4
|
|
800582a: 187b adds r3, r7, r1
|
|
800582c: 781b ldrb r3, [r3, #0]
|
|
800582e: b29a uxth r2, r3
|
|
8005830: 200e movs r0, #14
|
|
8005832: 183b adds r3, r7, r0
|
|
8005834: 0212 lsls r2, r2, #8
|
|
8005836: 801a strh r2, [r3, #0]
|
|
value |= data[1];
|
|
8005838: 187b adds r3, r7, r1
|
|
800583a: 785b ldrb r3, [r3, #1]
|
|
800583c: b299 uxth r1, r3
|
|
800583e: 183b adds r3, r7, r0
|
|
8005840: 183a adds r2, r7, r0
|
|
8005842: 8812 ldrh r2, [r2, #0]
|
|
8005844: 430a orrs r2, r1
|
|
8005846: 801a strh r2, [r3, #0]
|
|
return value;
|
|
8005848: 183b adds r3, r7, r0
|
|
800584a: 881b ldrh r3, [r3, #0]
|
|
}
|
|
800584c: 0018 movs r0, r3
|
|
800584e: 46bd mov sp, r7
|
|
8005850: b005 add sp, #20
|
|
8005852: bd90 pop {r4, r7, pc}
|
|
8005854: 2000000d .word 0x2000000d
|
|
8005858: 200000d8 .word 0x200000d8
|
|
|
|
0800585c <writeMulti>:
|
|
return value;
|
|
}
|
|
|
|
// Write an arbitrary number of bytes from the given array to the sensor,
|
|
// starting at the given register
|
|
void writeMulti(uint8_t reg, uint8_t *src, uint8_t count) {
|
|
800585c: b590 push {r4, r7, lr}
|
|
800585e: b087 sub sp, #28
|
|
8005860: af04 add r7, sp, #16
|
|
8005862: 6039 str r1, [r7, #0]
|
|
8005864: 0011 movs r1, r2
|
|
8005866: 1dfb adds r3, r7, #7
|
|
8005868: 1c02 adds r2, r0, #0
|
|
800586a: 701a strb r2, [r3, #0]
|
|
800586c: 1dbb adds r3, r7, #6
|
|
800586e: 1c0a adds r2, r1, #0
|
|
8005870: 701a strb r2, [r3, #0]
|
|
HAL_I2C_Mem_Write(&TOF_I2C, g_i2cAddr, reg, I2C_MEMADD_SIZE_8BIT, src, count, HAL_MAX_DELAY);
|
|
8005872: 4b0c ldr r3, [pc, #48] ; (80058a4 <writeMulti+0x48>)
|
|
8005874: 781b ldrb r3, [r3, #0]
|
|
8005876: b299 uxth r1, r3
|
|
8005878: 1dfb adds r3, r7, #7
|
|
800587a: 781b ldrb r3, [r3, #0]
|
|
800587c: b29c uxth r4, r3
|
|
800587e: 1dbb adds r3, r7, #6
|
|
8005880: 781b ldrb r3, [r3, #0]
|
|
8005882: b29b uxth r3, r3
|
|
8005884: 4808 ldr r0, [pc, #32] ; (80058a8 <writeMulti+0x4c>)
|
|
8005886: 2201 movs r2, #1
|
|
8005888: 4252 negs r2, r2
|
|
800588a: 9202 str r2, [sp, #8]
|
|
800588c: 9301 str r3, [sp, #4]
|
|
800588e: 683b ldr r3, [r7, #0]
|
|
8005890: 9300 str r3, [sp, #0]
|
|
8005892: 2301 movs r3, #1
|
|
8005894: 0022 movs r2, r4
|
|
8005896: f7fd f941 bl 8002b1c <HAL_I2C_Mem_Write>
|
|
}
|
|
800589a: 46c0 nop ; (mov r8, r8)
|
|
800589c: 46bd mov sp, r7
|
|
800589e: b003 add sp, #12
|
|
80058a0: bd90 pop {r4, r7, pc}
|
|
80058a2: 46c0 nop ; (mov r8, r8)
|
|
80058a4: 2000000d .word 0x2000000d
|
|
80058a8: 200000d8 .word 0x200000d8
|
|
|
|
080058ac <readMulti>:
|
|
|
|
// Read an arbitrary number of bytes from the sensor, starting at the given
|
|
// register, into the given array
|
|
void readMulti(uint8_t reg, uint8_t * dst, uint8_t count) {
|
|
80058ac: b590 push {r4, r7, lr}
|
|
80058ae: b087 sub sp, #28
|
|
80058b0: af04 add r7, sp, #16
|
|
80058b2: 6039 str r1, [r7, #0]
|
|
80058b4: 0011 movs r1, r2
|
|
80058b6: 1dfb adds r3, r7, #7
|
|
80058b8: 1c02 adds r2, r0, #0
|
|
80058ba: 701a strb r2, [r3, #0]
|
|
80058bc: 1dbb adds r3, r7, #6
|
|
80058be: 1c0a adds r2, r1, #0
|
|
80058c0: 701a strb r2, [r3, #0]
|
|
HAL_I2C_Mem_Read(&TOF_I2C, g_i2cAddr, reg, I2C_MEMADD_SIZE_8BIT, dst, count, HAL_MAX_DELAY);
|
|
80058c2: 4b0c ldr r3, [pc, #48] ; (80058f4 <readMulti+0x48>)
|
|
80058c4: 781b ldrb r3, [r3, #0]
|
|
80058c6: b299 uxth r1, r3
|
|
80058c8: 1dfb adds r3, r7, #7
|
|
80058ca: 781b ldrb r3, [r3, #0]
|
|
80058cc: b29c uxth r4, r3
|
|
80058ce: 1dbb adds r3, r7, #6
|
|
80058d0: 781b ldrb r3, [r3, #0]
|
|
80058d2: b29b uxth r3, r3
|
|
80058d4: 4808 ldr r0, [pc, #32] ; (80058f8 <readMulti+0x4c>)
|
|
80058d6: 2201 movs r2, #1
|
|
80058d8: 4252 negs r2, r2
|
|
80058da: 9202 str r2, [sp, #8]
|
|
80058dc: 9301 str r3, [sp, #4]
|
|
80058de: 683b ldr r3, [r7, #0]
|
|
80058e0: 9300 str r3, [sp, #0]
|
|
80058e2: 2301 movs r3, #1
|
|
80058e4: 0022 movs r2, r4
|
|
80058e6: f7fd fa47 bl 8002d78 <HAL_I2C_Mem_Read>
|
|
}
|
|
80058ea: 46c0 nop ; (mov r8, r8)
|
|
80058ec: 46bd mov sp, r7
|
|
80058ee: b003 add sp, #12
|
|
80058f0: bd90 pop {r4, r7, pc}
|
|
80058f2: 46c0 nop ; (mov r8, r8)
|
|
80058f4: 2000000d .word 0x2000000d
|
|
80058f8: 200000d8 .word 0x200000d8
|
|
|
|
080058fc <initVL53L0X>:
|
|
// (VL53L0X_PerformRefSpadManagement()), since the API user manual says that it
|
|
// is performed by ST on the bare modules; it seems like that should work well
|
|
// enough unless a cover glass is added.
|
|
// If io_2v8 (optional) is true or not given, the sensor is configured for 2V8
|
|
// mode.
|
|
bool initVL53L0X( bool io_2v8 ){
|
|
80058fc: b590 push {r4, r7, lr}
|
|
80058fe: b087 sub sp, #28
|
|
8005900: af00 add r7, sp, #0
|
|
8005902: 0002 movs r2, r0
|
|
8005904: 1dfb adds r3, r7, #7
|
|
8005906: 701a strb r2, [r3, #0]
|
|
// VL53L0X_DataInit() begin
|
|
|
|
// sensor uses 1V8 mode for I/O by default; switch to 2V8 mode if necessary
|
|
if (io_2v8)
|
|
8005908: 1dfb adds r3, r7, #7
|
|
800590a: 781b ldrb r3, [r3, #0]
|
|
800590c: 2b00 cmp r3, #0
|
|
800590e: d00b beq.n 8005928 <initVL53L0X+0x2c>
|
|
{
|
|
writeReg(VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV,
|
|
readReg(VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV) | 0x01); // set bit 0
|
|
8005910: 2089 movs r0, #137 ; 0x89
|
|
8005912: f7ff ff4f bl 80057b4 <readReg>
|
|
8005916: 0003 movs r3, r0
|
|
8005918: 001a movs r2, r3
|
|
writeReg(VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV,
|
|
800591a: 2301 movs r3, #1
|
|
800591c: 4313 orrs r3, r2
|
|
800591e: b2db uxtb r3, r3
|
|
8005920: 0019 movs r1, r3
|
|
8005922: 2089 movs r0, #137 ; 0x89
|
|
8005924: f7ff fec0 bl 80056a8 <writeReg>
|
|
}
|
|
|
|
// "Set I2C standard mode"
|
|
writeReg(0x88, 0x00);
|
|
8005928: 2100 movs r1, #0
|
|
800592a: 2088 movs r0, #136 ; 0x88
|
|
800592c: f7ff febc bl 80056a8 <writeReg>
|
|
|
|
writeReg(0x80, 0x01);
|
|
8005930: 2101 movs r1, #1
|
|
8005932: 2080 movs r0, #128 ; 0x80
|
|
8005934: f7ff feb8 bl 80056a8 <writeReg>
|
|
writeReg(0xFF, 0x01);
|
|
8005938: 2101 movs r1, #1
|
|
800593a: 20ff movs r0, #255 ; 0xff
|
|
800593c: f7ff feb4 bl 80056a8 <writeReg>
|
|
writeReg(0x00, 0x00);
|
|
8005940: 2100 movs r1, #0
|
|
8005942: 2000 movs r0, #0
|
|
8005944: f7ff feb0 bl 80056a8 <writeReg>
|
|
g_stopVariable = readReg(0x91);
|
|
8005948: 2091 movs r0, #145 ; 0x91
|
|
800594a: f7ff ff33 bl 80057b4 <readReg>
|
|
800594e: 0003 movs r3, r0
|
|
8005950: 001a movs r2, r3
|
|
8005952: 4b44 ldr r3, [pc, #272] ; (8005a64 <initVL53L0X+0x168>)
|
|
8005954: 701a strb r2, [r3, #0]
|
|
writeReg(0x00, 0x01);
|
|
8005956: 2101 movs r1, #1
|
|
8005958: 2000 movs r0, #0
|
|
800595a: f7ff fea5 bl 80056a8 <writeReg>
|
|
writeReg(0xFF, 0x00);
|
|
800595e: 2100 movs r1, #0
|
|
8005960: 20ff movs r0, #255 ; 0xff
|
|
8005962: f7ff fea1 bl 80056a8 <writeReg>
|
|
writeReg(0x80, 0x00);
|
|
8005966: 2100 movs r1, #0
|
|
8005968: 2080 movs r0, #128 ; 0x80
|
|
800596a: f7ff fe9d bl 80056a8 <writeReg>
|
|
|
|
// disable SIGNAL_RATE_MSRC (bit 1) and SIGNAL_RATE_PRE_RANGE (bit 4) limit checks
|
|
writeReg(MSRC_CONFIG_CONTROL, readReg(MSRC_CONFIG_CONTROL) | 0x12);
|
|
800596e: 2060 movs r0, #96 ; 0x60
|
|
8005970: f7ff ff20 bl 80057b4 <readReg>
|
|
8005974: 0003 movs r3, r0
|
|
8005976: 001a movs r2, r3
|
|
8005978: 2312 movs r3, #18
|
|
800597a: 4313 orrs r3, r2
|
|
800597c: b2db uxtb r3, r3
|
|
800597e: 0019 movs r1, r3
|
|
8005980: 2060 movs r0, #96 ; 0x60
|
|
8005982: f7ff fe91 bl 80056a8 <writeReg>
|
|
|
|
// set final range signal rate limit to 0.25 MCPS (million counts per second)
|
|
setSignalRateLimit(0.25);
|
|
8005986: 23fa movs r3, #250 ; 0xfa
|
|
8005988: 059b lsls r3, r3, #22
|
|
800598a: 1c18 adds r0, r3, #0
|
|
800598c: f000 fa1c bl 8005dc8 <setSignalRateLimit>
|
|
|
|
writeReg(SYSTEM_SEQUENCE_CONFIG, 0xFF);
|
|
8005990: 21ff movs r1, #255 ; 0xff
|
|
8005992: 2001 movs r0, #1
|
|
8005994: f7ff fe88 bl 80056a8 <writeReg>
|
|
|
|
// VL53L0X_StaticInit() begin
|
|
|
|
uint8_t spad_count;
|
|
bool spad_type_is_aperture;
|
|
if (!getSpadInfo(&spad_count, &spad_type_is_aperture)) { return false; }
|
|
8005998: 2313 movs r3, #19
|
|
800599a: 18fa adds r2, r7, r3
|
|
800599c: 2314 movs r3, #20
|
|
800599e: 18fb adds r3, r7, r3
|
|
80059a0: 0011 movs r1, r2
|
|
80059a2: 0018 movs r0, r3
|
|
80059a4: f000 fc9a bl 80062dc <getSpadInfo>
|
|
80059a8: 1e03 subs r3, r0, #0
|
|
80059aa: d101 bne.n 80059b0 <initVL53L0X+0xb4>
|
|
80059ac: 2300 movs r3, #0
|
|
80059ae: e204 b.n 8005dba <initVL53L0X+0x4be>
|
|
|
|
// The SPAD map (RefGoodSpadMap) is read by VL53L0X_get_info_from_device() in
|
|
// the API, but the same data seems to be more easily readable from
|
|
// GLOBAL_CONFIG_SPAD_ENABLES_REF_0 through _6, so read it from there
|
|
uint8_t ref_spad_map[6];
|
|
readMulti(GLOBAL_CONFIG_SPAD_ENABLES_REF_0, ref_spad_map, 6);
|
|
80059b0: 230c movs r3, #12
|
|
80059b2: 18fb adds r3, r7, r3
|
|
80059b4: 2206 movs r2, #6
|
|
80059b6: 0019 movs r1, r3
|
|
80059b8: 20b0 movs r0, #176 ; 0xb0
|
|
80059ba: f7ff ff77 bl 80058ac <readMulti>
|
|
|
|
// -- VL53L0X_set_reference_spads() begin (assume NVM values are valid)
|
|
|
|
writeReg(0xFF, 0x01);
|
|
80059be: 2101 movs r1, #1
|
|
80059c0: 20ff movs r0, #255 ; 0xff
|
|
80059c2: f7ff fe71 bl 80056a8 <writeReg>
|
|
writeReg(DYNAMIC_SPAD_REF_EN_START_OFFSET, 0x00);
|
|
80059c6: 2100 movs r1, #0
|
|
80059c8: 204f movs r0, #79 ; 0x4f
|
|
80059ca: f7ff fe6d bl 80056a8 <writeReg>
|
|
writeReg(DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD, 0x2C);
|
|
80059ce: 212c movs r1, #44 ; 0x2c
|
|
80059d0: 204e movs r0, #78 ; 0x4e
|
|
80059d2: f7ff fe69 bl 80056a8 <writeReg>
|
|
writeReg(0xFF, 0x00);
|
|
80059d6: 2100 movs r1, #0
|
|
80059d8: 20ff movs r0, #255 ; 0xff
|
|
80059da: f7ff fe65 bl 80056a8 <writeReg>
|
|
writeReg(GLOBAL_CONFIG_REF_EN_START_SELECT, 0xB4);
|
|
80059de: 21b4 movs r1, #180 ; 0xb4
|
|
80059e0: 20b6 movs r0, #182 ; 0xb6
|
|
80059e2: f7ff fe61 bl 80056a8 <writeReg>
|
|
|
|
uint8_t first_spad_to_enable = spad_type_is_aperture ? 12 : 0; // 12 is the first aperture spad
|
|
80059e6: 2313 movs r3, #19
|
|
80059e8: 18fb adds r3, r7, r3
|
|
80059ea: 781b ldrb r3, [r3, #0]
|
|
80059ec: 2b00 cmp r3, #0
|
|
80059ee: d001 beq.n 80059f4 <initVL53L0X+0xf8>
|
|
80059f0: 220c movs r2, #12
|
|
80059f2: e000 b.n 80059f6 <initVL53L0X+0xfa>
|
|
80059f4: 2200 movs r2, #0
|
|
80059f6: 2315 movs r3, #21
|
|
80059f8: 18fb adds r3, r7, r3
|
|
80059fa: 701a strb r2, [r3, #0]
|
|
uint8_t spads_enabled = 0;
|
|
80059fc: 2317 movs r3, #23
|
|
80059fe: 18fb adds r3, r7, r3
|
|
8005a00: 2200 movs r2, #0
|
|
8005a02: 701a strb r2, [r3, #0]
|
|
|
|
for (uint8_t i = 0; i < 48; i++)
|
|
8005a04: 2316 movs r3, #22
|
|
8005a06: 18fb adds r3, r7, r3
|
|
8005a08: 2200 movs r2, #0
|
|
8005a0a: 701a strb r2, [r3, #0]
|
|
8005a0c: e04b b.n 8005aa6 <initVL53L0X+0x1aa>
|
|
{
|
|
if (i < first_spad_to_enable || spads_enabled == spad_count)
|
|
8005a0e: 2316 movs r3, #22
|
|
8005a10: 18fa adds r2, r7, r3
|
|
8005a12: 2315 movs r3, #21
|
|
8005a14: 18fb adds r3, r7, r3
|
|
8005a16: 7812 ldrb r2, [r2, #0]
|
|
8005a18: 781b ldrb r3, [r3, #0]
|
|
8005a1a: 429a cmp r2, r3
|
|
8005a1c: d307 bcc.n 8005a2e <initVL53L0X+0x132>
|
|
8005a1e: 2314 movs r3, #20
|
|
8005a20: 18fb adds r3, r7, r3
|
|
8005a22: 781b ldrb r3, [r3, #0]
|
|
8005a24: 2217 movs r2, #23
|
|
8005a26: 18ba adds r2, r7, r2
|
|
8005a28: 7812 ldrb r2, [r2, #0]
|
|
8005a2a: 429a cmp r2, r3
|
|
8005a2c: d11c bne.n 8005a68 <initVL53L0X+0x16c>
|
|
{
|
|
// This bit is lower than the first one that should be enabled, or
|
|
// (reference_spad_count) bits have already been enabled, so zero this bit
|
|
ref_spad_map[i / 8] &= ~(1 << (i % 8));
|
|
8005a2e: 2116 movs r1, #22
|
|
8005a30: 187b adds r3, r7, r1
|
|
8005a32: 781b ldrb r3, [r3, #0]
|
|
8005a34: 08db lsrs r3, r3, #3
|
|
8005a36: b2d8 uxtb r0, r3
|
|
8005a38: 0002 movs r2, r0
|
|
8005a3a: 240c movs r4, #12
|
|
8005a3c: 193b adds r3, r7, r4
|
|
8005a3e: 5c9b ldrb r3, [r3, r2]
|
|
8005a40: b25b sxtb r3, r3
|
|
8005a42: 187a adds r2, r7, r1
|
|
8005a44: 7812 ldrb r2, [r2, #0]
|
|
8005a46: 2107 movs r1, #7
|
|
8005a48: 400a ands r2, r1
|
|
8005a4a: 2101 movs r1, #1
|
|
8005a4c: 4091 lsls r1, r2
|
|
8005a4e: 000a movs r2, r1
|
|
8005a50: b252 sxtb r2, r2
|
|
8005a52: 43d2 mvns r2, r2
|
|
8005a54: b252 sxtb r2, r2
|
|
8005a56: 4013 ands r3, r2
|
|
8005a58: b25b sxtb r3, r3
|
|
8005a5a: 0002 movs r2, r0
|
|
8005a5c: b2d9 uxtb r1, r3
|
|
8005a5e: 193b adds r3, r7, r4
|
|
8005a60: 5499 strb r1, [r3, r2]
|
|
8005a62: e01a b.n 8005a9a <initVL53L0X+0x19e>
|
|
8005a64: 2000025e .word 0x2000025e
|
|
}
|
|
else if ((ref_spad_map[i / 8] >> (i % 8)) & 0x1)
|
|
8005a68: 2016 movs r0, #22
|
|
8005a6a: 183b adds r3, r7, r0
|
|
8005a6c: 781b ldrb r3, [r3, #0]
|
|
8005a6e: 08db lsrs r3, r3, #3
|
|
8005a70: b2db uxtb r3, r3
|
|
8005a72: 001a movs r2, r3
|
|
8005a74: 230c movs r3, #12
|
|
8005a76: 18fb adds r3, r7, r3
|
|
8005a78: 5c9b ldrb r3, [r3, r2]
|
|
8005a7a: 0019 movs r1, r3
|
|
8005a7c: 183b adds r3, r7, r0
|
|
8005a7e: 781b ldrb r3, [r3, #0]
|
|
8005a80: 2207 movs r2, #7
|
|
8005a82: 4013 ands r3, r2
|
|
8005a84: 4119 asrs r1, r3
|
|
8005a86: 000b movs r3, r1
|
|
8005a88: 2201 movs r2, #1
|
|
8005a8a: 4013 ands r3, r2
|
|
8005a8c: d005 beq.n 8005a9a <initVL53L0X+0x19e>
|
|
{
|
|
spads_enabled++;
|
|
8005a8e: 2117 movs r1, #23
|
|
8005a90: 187b adds r3, r7, r1
|
|
8005a92: 781a ldrb r2, [r3, #0]
|
|
8005a94: 187b adds r3, r7, r1
|
|
8005a96: 3201 adds r2, #1
|
|
8005a98: 701a strb r2, [r3, #0]
|
|
for (uint8_t i = 0; i < 48; i++)
|
|
8005a9a: 2116 movs r1, #22
|
|
8005a9c: 187b adds r3, r7, r1
|
|
8005a9e: 781a ldrb r2, [r3, #0]
|
|
8005aa0: 187b adds r3, r7, r1
|
|
8005aa2: 3201 adds r2, #1
|
|
8005aa4: 701a strb r2, [r3, #0]
|
|
8005aa6: 2316 movs r3, #22
|
|
8005aa8: 18fb adds r3, r7, r3
|
|
8005aaa: 781b ldrb r3, [r3, #0]
|
|
8005aac: 2b2f cmp r3, #47 ; 0x2f
|
|
8005aae: d9ae bls.n 8005a0e <initVL53L0X+0x112>
|
|
}
|
|
}
|
|
|
|
writeMulti(GLOBAL_CONFIG_SPAD_ENABLES_REF_0, ref_spad_map, 6);
|
|
8005ab0: 230c movs r3, #12
|
|
8005ab2: 18fb adds r3, r7, r3
|
|
8005ab4: 2206 movs r2, #6
|
|
8005ab6: 0019 movs r1, r3
|
|
8005ab8: 20b0 movs r0, #176 ; 0xb0
|
|
8005aba: f7ff fecf bl 800585c <writeMulti>
|
|
// -- VL53L0X_set_reference_spads() end
|
|
|
|
// -- VL53L0X_load_tuning_settings() begin
|
|
// DefaultTuningSettings from vl53l0x_tuning.h
|
|
|
|
writeReg(0xFF, 0x01);
|
|
8005abe: 2101 movs r1, #1
|
|
8005ac0: 20ff movs r0, #255 ; 0xff
|
|
8005ac2: f7ff fdf1 bl 80056a8 <writeReg>
|
|
writeReg(0x00, 0x00);
|
|
8005ac6: 2100 movs r1, #0
|
|
8005ac8: 2000 movs r0, #0
|
|
8005aca: f7ff fded bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x00);
|
|
8005ace: 2100 movs r1, #0
|
|
8005ad0: 20ff movs r0, #255 ; 0xff
|
|
8005ad2: f7ff fde9 bl 80056a8 <writeReg>
|
|
writeReg(0x09, 0x00);
|
|
8005ad6: 2100 movs r1, #0
|
|
8005ad8: 2009 movs r0, #9
|
|
8005ada: f7ff fde5 bl 80056a8 <writeReg>
|
|
writeReg(0x10, 0x00);
|
|
8005ade: 2100 movs r1, #0
|
|
8005ae0: 2010 movs r0, #16
|
|
8005ae2: f7ff fde1 bl 80056a8 <writeReg>
|
|
writeReg(0x11, 0x00);
|
|
8005ae6: 2100 movs r1, #0
|
|
8005ae8: 2011 movs r0, #17
|
|
8005aea: f7ff fddd bl 80056a8 <writeReg>
|
|
|
|
writeReg(0x24, 0x01);
|
|
8005aee: 2101 movs r1, #1
|
|
8005af0: 2024 movs r0, #36 ; 0x24
|
|
8005af2: f7ff fdd9 bl 80056a8 <writeReg>
|
|
writeReg(0x25, 0xFF);
|
|
8005af6: 21ff movs r1, #255 ; 0xff
|
|
8005af8: 2025 movs r0, #37 ; 0x25
|
|
8005afa: f7ff fdd5 bl 80056a8 <writeReg>
|
|
writeReg(0x75, 0x00);
|
|
8005afe: 2100 movs r1, #0
|
|
8005b00: 2075 movs r0, #117 ; 0x75
|
|
8005b02: f7ff fdd1 bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x01);
|
|
8005b06: 2101 movs r1, #1
|
|
8005b08: 20ff movs r0, #255 ; 0xff
|
|
8005b0a: f7ff fdcd bl 80056a8 <writeReg>
|
|
writeReg(0x4E, 0x2C);
|
|
8005b0e: 212c movs r1, #44 ; 0x2c
|
|
8005b10: 204e movs r0, #78 ; 0x4e
|
|
8005b12: f7ff fdc9 bl 80056a8 <writeReg>
|
|
writeReg(0x48, 0x00);
|
|
8005b16: 2100 movs r1, #0
|
|
8005b18: 2048 movs r0, #72 ; 0x48
|
|
8005b1a: f7ff fdc5 bl 80056a8 <writeReg>
|
|
writeReg(0x30, 0x20);
|
|
8005b1e: 2120 movs r1, #32
|
|
8005b20: 2030 movs r0, #48 ; 0x30
|
|
8005b22: f7ff fdc1 bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x00);
|
|
8005b26: 2100 movs r1, #0
|
|
8005b28: 20ff movs r0, #255 ; 0xff
|
|
8005b2a: f7ff fdbd bl 80056a8 <writeReg>
|
|
writeReg(0x30, 0x09);
|
|
8005b2e: 2109 movs r1, #9
|
|
8005b30: 2030 movs r0, #48 ; 0x30
|
|
8005b32: f7ff fdb9 bl 80056a8 <writeReg>
|
|
writeReg(0x54, 0x00);
|
|
8005b36: 2100 movs r1, #0
|
|
8005b38: 2054 movs r0, #84 ; 0x54
|
|
8005b3a: f7ff fdb5 bl 80056a8 <writeReg>
|
|
writeReg(0x31, 0x04);
|
|
8005b3e: 2104 movs r1, #4
|
|
8005b40: 2031 movs r0, #49 ; 0x31
|
|
8005b42: f7ff fdb1 bl 80056a8 <writeReg>
|
|
writeReg(0x32, 0x03);
|
|
8005b46: 2103 movs r1, #3
|
|
8005b48: 2032 movs r0, #50 ; 0x32
|
|
8005b4a: f7ff fdad bl 80056a8 <writeReg>
|
|
writeReg(0x40, 0x83);
|
|
8005b4e: 2183 movs r1, #131 ; 0x83
|
|
8005b50: 2040 movs r0, #64 ; 0x40
|
|
8005b52: f7ff fda9 bl 80056a8 <writeReg>
|
|
writeReg(0x46, 0x25);
|
|
8005b56: 2125 movs r1, #37 ; 0x25
|
|
8005b58: 2046 movs r0, #70 ; 0x46
|
|
8005b5a: f7ff fda5 bl 80056a8 <writeReg>
|
|
writeReg(0x60, 0x00);
|
|
8005b5e: 2100 movs r1, #0
|
|
8005b60: 2060 movs r0, #96 ; 0x60
|
|
8005b62: f7ff fda1 bl 80056a8 <writeReg>
|
|
writeReg(0x27, 0x00);
|
|
8005b66: 2100 movs r1, #0
|
|
8005b68: 2027 movs r0, #39 ; 0x27
|
|
8005b6a: f7ff fd9d bl 80056a8 <writeReg>
|
|
writeReg(0x50, 0x06);
|
|
8005b6e: 2106 movs r1, #6
|
|
8005b70: 2050 movs r0, #80 ; 0x50
|
|
8005b72: f7ff fd99 bl 80056a8 <writeReg>
|
|
writeReg(0x51, 0x00);
|
|
8005b76: 2100 movs r1, #0
|
|
8005b78: 2051 movs r0, #81 ; 0x51
|
|
8005b7a: f7ff fd95 bl 80056a8 <writeReg>
|
|
writeReg(0x52, 0x96);
|
|
8005b7e: 2196 movs r1, #150 ; 0x96
|
|
8005b80: 2052 movs r0, #82 ; 0x52
|
|
8005b82: f7ff fd91 bl 80056a8 <writeReg>
|
|
writeReg(0x56, 0x08);
|
|
8005b86: 2108 movs r1, #8
|
|
8005b88: 2056 movs r0, #86 ; 0x56
|
|
8005b8a: f7ff fd8d bl 80056a8 <writeReg>
|
|
writeReg(0x57, 0x30);
|
|
8005b8e: 2130 movs r1, #48 ; 0x30
|
|
8005b90: 2057 movs r0, #87 ; 0x57
|
|
8005b92: f7ff fd89 bl 80056a8 <writeReg>
|
|
writeReg(0x61, 0x00);
|
|
8005b96: 2100 movs r1, #0
|
|
8005b98: 2061 movs r0, #97 ; 0x61
|
|
8005b9a: f7ff fd85 bl 80056a8 <writeReg>
|
|
writeReg(0x62, 0x00);
|
|
8005b9e: 2100 movs r1, #0
|
|
8005ba0: 2062 movs r0, #98 ; 0x62
|
|
8005ba2: f7ff fd81 bl 80056a8 <writeReg>
|
|
writeReg(0x64, 0x00);
|
|
8005ba6: 2100 movs r1, #0
|
|
8005ba8: 2064 movs r0, #100 ; 0x64
|
|
8005baa: f7ff fd7d bl 80056a8 <writeReg>
|
|
writeReg(0x65, 0x00);
|
|
8005bae: 2100 movs r1, #0
|
|
8005bb0: 2065 movs r0, #101 ; 0x65
|
|
8005bb2: f7ff fd79 bl 80056a8 <writeReg>
|
|
writeReg(0x66, 0xA0);
|
|
8005bb6: 21a0 movs r1, #160 ; 0xa0
|
|
8005bb8: 2066 movs r0, #102 ; 0x66
|
|
8005bba: f7ff fd75 bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x01);
|
|
8005bbe: 2101 movs r1, #1
|
|
8005bc0: 20ff movs r0, #255 ; 0xff
|
|
8005bc2: f7ff fd71 bl 80056a8 <writeReg>
|
|
writeReg(0x22, 0x32);
|
|
8005bc6: 2132 movs r1, #50 ; 0x32
|
|
8005bc8: 2022 movs r0, #34 ; 0x22
|
|
8005bca: f7ff fd6d bl 80056a8 <writeReg>
|
|
writeReg(0x47, 0x14);
|
|
8005bce: 2114 movs r1, #20
|
|
8005bd0: 2047 movs r0, #71 ; 0x47
|
|
8005bd2: f7ff fd69 bl 80056a8 <writeReg>
|
|
writeReg(0x49, 0xFF);
|
|
8005bd6: 21ff movs r1, #255 ; 0xff
|
|
8005bd8: 2049 movs r0, #73 ; 0x49
|
|
8005bda: f7ff fd65 bl 80056a8 <writeReg>
|
|
writeReg(0x4A, 0x00);
|
|
8005bde: 2100 movs r1, #0
|
|
8005be0: 204a movs r0, #74 ; 0x4a
|
|
8005be2: f7ff fd61 bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x00);
|
|
8005be6: 2100 movs r1, #0
|
|
8005be8: 20ff movs r0, #255 ; 0xff
|
|
8005bea: f7ff fd5d bl 80056a8 <writeReg>
|
|
writeReg(0x7A, 0x0A);
|
|
8005bee: 210a movs r1, #10
|
|
8005bf0: 207a movs r0, #122 ; 0x7a
|
|
8005bf2: f7ff fd59 bl 80056a8 <writeReg>
|
|
writeReg(0x7B, 0x00);
|
|
8005bf6: 2100 movs r1, #0
|
|
8005bf8: 207b movs r0, #123 ; 0x7b
|
|
8005bfa: f7ff fd55 bl 80056a8 <writeReg>
|
|
writeReg(0x78, 0x21);
|
|
8005bfe: 2121 movs r1, #33 ; 0x21
|
|
8005c00: 2078 movs r0, #120 ; 0x78
|
|
8005c02: f7ff fd51 bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x01);
|
|
8005c06: 2101 movs r1, #1
|
|
8005c08: 20ff movs r0, #255 ; 0xff
|
|
8005c0a: f7ff fd4d bl 80056a8 <writeReg>
|
|
writeReg(0x23, 0x34);
|
|
8005c0e: 2134 movs r1, #52 ; 0x34
|
|
8005c10: 2023 movs r0, #35 ; 0x23
|
|
8005c12: f7ff fd49 bl 80056a8 <writeReg>
|
|
writeReg(0x42, 0x00);
|
|
8005c16: 2100 movs r1, #0
|
|
8005c18: 2042 movs r0, #66 ; 0x42
|
|
8005c1a: f7ff fd45 bl 80056a8 <writeReg>
|
|
writeReg(0x44, 0xFF);
|
|
8005c1e: 21ff movs r1, #255 ; 0xff
|
|
8005c20: 2044 movs r0, #68 ; 0x44
|
|
8005c22: f7ff fd41 bl 80056a8 <writeReg>
|
|
writeReg(0x45, 0x26);
|
|
8005c26: 2126 movs r1, #38 ; 0x26
|
|
8005c28: 2045 movs r0, #69 ; 0x45
|
|
8005c2a: f7ff fd3d bl 80056a8 <writeReg>
|
|
writeReg(0x46, 0x05);
|
|
8005c2e: 2105 movs r1, #5
|
|
8005c30: 2046 movs r0, #70 ; 0x46
|
|
8005c32: f7ff fd39 bl 80056a8 <writeReg>
|
|
writeReg(0x40, 0x40);
|
|
8005c36: 2140 movs r1, #64 ; 0x40
|
|
8005c38: 2040 movs r0, #64 ; 0x40
|
|
8005c3a: f7ff fd35 bl 80056a8 <writeReg>
|
|
writeReg(0x0E, 0x06);
|
|
8005c3e: 2106 movs r1, #6
|
|
8005c40: 200e movs r0, #14
|
|
8005c42: f7ff fd31 bl 80056a8 <writeReg>
|
|
writeReg(0x20, 0x1A);
|
|
8005c46: 211a movs r1, #26
|
|
8005c48: 2020 movs r0, #32
|
|
8005c4a: f7ff fd2d bl 80056a8 <writeReg>
|
|
writeReg(0x43, 0x40);
|
|
8005c4e: 2140 movs r1, #64 ; 0x40
|
|
8005c50: 2043 movs r0, #67 ; 0x43
|
|
8005c52: f7ff fd29 bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x00);
|
|
8005c56: 2100 movs r1, #0
|
|
8005c58: 20ff movs r0, #255 ; 0xff
|
|
8005c5a: f7ff fd25 bl 80056a8 <writeReg>
|
|
writeReg(0x34, 0x03);
|
|
8005c5e: 2103 movs r1, #3
|
|
8005c60: 2034 movs r0, #52 ; 0x34
|
|
8005c62: f7ff fd21 bl 80056a8 <writeReg>
|
|
writeReg(0x35, 0x44);
|
|
8005c66: 2144 movs r1, #68 ; 0x44
|
|
8005c68: 2035 movs r0, #53 ; 0x35
|
|
8005c6a: f7ff fd1d bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x01);
|
|
8005c6e: 2101 movs r1, #1
|
|
8005c70: 20ff movs r0, #255 ; 0xff
|
|
8005c72: f7ff fd19 bl 80056a8 <writeReg>
|
|
writeReg(0x31, 0x04);
|
|
8005c76: 2104 movs r1, #4
|
|
8005c78: 2031 movs r0, #49 ; 0x31
|
|
8005c7a: f7ff fd15 bl 80056a8 <writeReg>
|
|
writeReg(0x4B, 0x09);
|
|
8005c7e: 2109 movs r1, #9
|
|
8005c80: 204b movs r0, #75 ; 0x4b
|
|
8005c82: f7ff fd11 bl 80056a8 <writeReg>
|
|
writeReg(0x4C, 0x05);
|
|
8005c86: 2105 movs r1, #5
|
|
8005c88: 204c movs r0, #76 ; 0x4c
|
|
8005c8a: f7ff fd0d bl 80056a8 <writeReg>
|
|
writeReg(0x4D, 0x04);
|
|
8005c8e: 2104 movs r1, #4
|
|
8005c90: 204d movs r0, #77 ; 0x4d
|
|
8005c92: f7ff fd09 bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x00);
|
|
8005c96: 2100 movs r1, #0
|
|
8005c98: 20ff movs r0, #255 ; 0xff
|
|
8005c9a: f7ff fd05 bl 80056a8 <writeReg>
|
|
writeReg(0x44, 0x00);
|
|
8005c9e: 2100 movs r1, #0
|
|
8005ca0: 2044 movs r0, #68 ; 0x44
|
|
8005ca2: f7ff fd01 bl 80056a8 <writeReg>
|
|
writeReg(0x45, 0x20);
|
|
8005ca6: 2120 movs r1, #32
|
|
8005ca8: 2045 movs r0, #69 ; 0x45
|
|
8005caa: f7ff fcfd bl 80056a8 <writeReg>
|
|
writeReg(0x47, 0x08);
|
|
8005cae: 2108 movs r1, #8
|
|
8005cb0: 2047 movs r0, #71 ; 0x47
|
|
8005cb2: f7ff fcf9 bl 80056a8 <writeReg>
|
|
writeReg(0x48, 0x28);
|
|
8005cb6: 2128 movs r1, #40 ; 0x28
|
|
8005cb8: 2048 movs r0, #72 ; 0x48
|
|
8005cba: f7ff fcf5 bl 80056a8 <writeReg>
|
|
writeReg(0x67, 0x00);
|
|
8005cbe: 2100 movs r1, #0
|
|
8005cc0: 2067 movs r0, #103 ; 0x67
|
|
8005cc2: f7ff fcf1 bl 80056a8 <writeReg>
|
|
writeReg(0x70, 0x04);
|
|
8005cc6: 2104 movs r1, #4
|
|
8005cc8: 2070 movs r0, #112 ; 0x70
|
|
8005cca: f7ff fced bl 80056a8 <writeReg>
|
|
writeReg(0x71, 0x01);
|
|
8005cce: 2101 movs r1, #1
|
|
8005cd0: 2071 movs r0, #113 ; 0x71
|
|
8005cd2: f7ff fce9 bl 80056a8 <writeReg>
|
|
writeReg(0x72, 0xFE);
|
|
8005cd6: 21fe movs r1, #254 ; 0xfe
|
|
8005cd8: 2072 movs r0, #114 ; 0x72
|
|
8005cda: f7ff fce5 bl 80056a8 <writeReg>
|
|
writeReg(0x76, 0x00);
|
|
8005cde: 2100 movs r1, #0
|
|
8005ce0: 2076 movs r0, #118 ; 0x76
|
|
8005ce2: f7ff fce1 bl 80056a8 <writeReg>
|
|
writeReg(0x77, 0x00);
|
|
8005ce6: 2100 movs r1, #0
|
|
8005ce8: 2077 movs r0, #119 ; 0x77
|
|
8005cea: f7ff fcdd bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x01);
|
|
8005cee: 2101 movs r1, #1
|
|
8005cf0: 20ff movs r0, #255 ; 0xff
|
|
8005cf2: f7ff fcd9 bl 80056a8 <writeReg>
|
|
writeReg(0x0D, 0x01);
|
|
8005cf6: 2101 movs r1, #1
|
|
8005cf8: 200d movs r0, #13
|
|
8005cfa: f7ff fcd5 bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x00);
|
|
8005cfe: 2100 movs r1, #0
|
|
8005d00: 20ff movs r0, #255 ; 0xff
|
|
8005d02: f7ff fcd1 bl 80056a8 <writeReg>
|
|
writeReg(0x80, 0x01);
|
|
8005d06: 2101 movs r1, #1
|
|
8005d08: 2080 movs r0, #128 ; 0x80
|
|
8005d0a: f7ff fccd bl 80056a8 <writeReg>
|
|
writeReg(0x01, 0xF8);
|
|
8005d0e: 21f8 movs r1, #248 ; 0xf8
|
|
8005d10: 2001 movs r0, #1
|
|
8005d12: f7ff fcc9 bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x01);
|
|
8005d16: 2101 movs r1, #1
|
|
8005d18: 20ff movs r0, #255 ; 0xff
|
|
8005d1a: f7ff fcc5 bl 80056a8 <writeReg>
|
|
writeReg(0x8E, 0x01);
|
|
8005d1e: 2101 movs r1, #1
|
|
8005d20: 208e movs r0, #142 ; 0x8e
|
|
8005d22: f7ff fcc1 bl 80056a8 <writeReg>
|
|
writeReg(0x00, 0x01);
|
|
8005d26: 2101 movs r1, #1
|
|
8005d28: 2000 movs r0, #0
|
|
8005d2a: f7ff fcbd bl 80056a8 <writeReg>
|
|
writeReg(0xFF, 0x00);
|
|
8005d2e: 2100 movs r1, #0
|
|
8005d30: 20ff movs r0, #255 ; 0xff
|
|
8005d32: f7ff fcb9 bl 80056a8 <writeReg>
|
|
writeReg(0x80, 0x00);
|
|
8005d36: 2100 movs r1, #0
|
|
8005d38: 2080 movs r0, #128 ; 0x80
|
|
8005d3a: f7ff fcb5 bl 80056a8 <writeReg>
|
|
// -- VL53L0X_load_tuning_settings() end
|
|
|
|
// "Set interrupt config to new sample ready"
|
|
// -- VL53L0X_SetGpioConfig() begin
|
|
|
|
writeReg(SYSTEM_INTERRUPT_CONFIG_GPIO, 0x04);
|
|
8005d3e: 2104 movs r1, #4
|
|
8005d40: 200a movs r0, #10
|
|
8005d42: f7ff fcb1 bl 80056a8 <writeReg>
|
|
writeReg(GPIO_HV_MUX_ACTIVE_HIGH, readReg(GPIO_HV_MUX_ACTIVE_HIGH) & ~0x10); // active low
|
|
8005d46: 2084 movs r0, #132 ; 0x84
|
|
8005d48: f7ff fd34 bl 80057b4 <readReg>
|
|
8005d4c: 0003 movs r3, r0
|
|
8005d4e: 001a movs r2, r3
|
|
8005d50: 2310 movs r3, #16
|
|
8005d52: 439a bics r2, r3
|
|
8005d54: 0013 movs r3, r2
|
|
8005d56: b2db uxtb r3, r3
|
|
8005d58: 0019 movs r1, r3
|
|
8005d5a: 2084 movs r0, #132 ; 0x84
|
|
8005d5c: f7ff fca4 bl 80056a8 <writeReg>
|
|
writeReg(SYSTEM_INTERRUPT_CLEAR, 0x01);
|
|
8005d60: 2101 movs r1, #1
|
|
8005d62: 200b movs r0, #11
|
|
8005d64: f7ff fca0 bl 80056a8 <writeReg>
|
|
|
|
// -- VL53L0X_SetGpioConfig() end
|
|
|
|
g_measTimBudUs = getMeasurementTimingBudget();
|
|
8005d68: f000 f924 bl 8005fb4 <getMeasurementTimingBudget>
|
|
8005d6c: 0002 movs r2, r0
|
|
8005d6e: 4b15 ldr r3, [pc, #84] ; (8005dc4 <initVL53L0X+0x4c8>)
|
|
8005d70: 601a str r2, [r3, #0]
|
|
// "Disable MSRC and TCC by default"
|
|
// MSRC = Minimum Signal Rate Check
|
|
// TCC = Target CentreCheck
|
|
// -- VL53L0X_SetSequenceStepEnable() begin
|
|
|
|
writeReg(SYSTEM_SEQUENCE_CONFIG, 0xE8);
|
|
8005d72: 21e8 movs r1, #232 ; 0xe8
|
|
8005d74: 2001 movs r0, #1
|
|
8005d76: f7ff fc97 bl 80056a8 <writeReg>
|
|
|
|
// -- VL53L0X_SetSequenceStepEnable() end
|
|
|
|
// "Recalculate timing budget"
|
|
setMeasurementTimingBudget(g_measTimBudUs);
|
|
8005d7a: 4b12 ldr r3, [pc, #72] ; (8005dc4 <initVL53L0X+0x4c8>)
|
|
8005d7c: 681b ldr r3, [r3, #0]
|
|
8005d7e: 0018 movs r0, r3
|
|
8005d80: f000 f850 bl 8005e24 <setMeasurementTimingBudget>
|
|
|
|
// VL53L0X_PerformRefCalibration() begin (VL53L0X_perform_ref_calibration())
|
|
|
|
// -- VL53L0X_perform_vhv_calibration() begin
|
|
|
|
writeReg(SYSTEM_SEQUENCE_CONFIG, 0x01);
|
|
8005d84: 2101 movs r1, #1
|
|
8005d86: 2001 movs r0, #1
|
|
8005d88: f7ff fc8e bl 80056a8 <writeReg>
|
|
if (!performSingleRefCalibration(0x40)) { return false; }
|
|
8005d8c: 2040 movs r0, #64 ; 0x40
|
|
8005d8e: f000 fc89 bl 80066a4 <performSingleRefCalibration>
|
|
8005d92: 1e03 subs r3, r0, #0
|
|
8005d94: d101 bne.n 8005d9a <initVL53L0X+0x49e>
|
|
8005d96: 2300 movs r3, #0
|
|
8005d98: e00f b.n 8005dba <initVL53L0X+0x4be>
|
|
|
|
// -- VL53L0X_perform_vhv_calibration() end
|
|
|
|
// -- VL53L0X_perform_phase_calibration() begin
|
|
|
|
writeReg(SYSTEM_SEQUENCE_CONFIG, 0x02);
|
|
8005d9a: 2102 movs r1, #2
|
|
8005d9c: 2001 movs r0, #1
|
|
8005d9e: f7ff fc83 bl 80056a8 <writeReg>
|
|
if (!performSingleRefCalibration(0x00)) { return false; }
|
|
8005da2: 2000 movs r0, #0
|
|
8005da4: f000 fc7e bl 80066a4 <performSingleRefCalibration>
|
|
8005da8: 1e03 subs r3, r0, #0
|
|
8005daa: d101 bne.n 8005db0 <initVL53L0X+0x4b4>
|
|
8005dac: 2300 movs r3, #0
|
|
8005dae: e004 b.n 8005dba <initVL53L0X+0x4be>
|
|
|
|
// -- VL53L0X_perform_phase_calibration() end
|
|
|
|
// "restore the previous Sequence Config"
|
|
writeReg(SYSTEM_SEQUENCE_CONFIG, 0xE8);
|
|
8005db0: 21e8 movs r1, #232 ; 0xe8
|
|
8005db2: 2001 movs r0, #1
|
|
8005db4: f7ff fc78 bl 80056a8 <writeReg>
|
|
|
|
// VL53L0X_PerformRefCalibration() end
|
|
|
|
return true;
|
|
8005db8: 2301 movs r3, #1
|
|
}
|
|
8005dba: 0018 movs r0, r3
|
|
8005dbc: 46bd mov sp, r7
|
|
8005dbe: b007 add sp, #28
|
|
8005dc0: bd90 pop {r4, r7, pc}
|
|
8005dc2: 46c0 nop ; (mov r8, r8)
|
|
8005dc4: 20000260 .word 0x20000260
|
|
|
|
08005dc8 <setSignalRateLimit>:
|
|
// Setting a lower limit increases the potential range of the sensor but also
|
|
// seems to increase the likelihood of getting an inaccurate reading because of
|
|
// unwanted reflections from objects other than the intended target.
|
|
// Defaults to 0.25 MCPS as initialized by the ST API and this library.
|
|
bool setSignalRateLimit(float limit_Mcps)
|
|
{
|
|
8005dc8: b580 push {r7, lr}
|
|
8005dca: b082 sub sp, #8
|
|
8005dcc: af00 add r7, sp, #0
|
|
8005dce: 6078 str r0, [r7, #4]
|
|
if (limit_Mcps < 0 || limit_Mcps > 511.99) { return false; }
|
|
8005dd0: 2100 movs r1, #0
|
|
8005dd2: 6878 ldr r0, [r7, #4]
|
|
8005dd4: f7fa fb5e bl 8000494 <__aeabi_fcmplt>
|
|
8005dd8: 1e03 subs r3, r0, #0
|
|
8005dda: d108 bne.n 8005dee <setSignalRateLimit+0x26>
|
|
8005ddc: 6878 ldr r0, [r7, #4]
|
|
8005dde: f7fb f849 bl 8000e74 <__aeabi_f2d>
|
|
8005de2: 4a0e ldr r2, [pc, #56] ; (8005e1c <setSignalRateLimit+0x54>)
|
|
8005de4: 4b0e ldr r3, [pc, #56] ; (8005e20 <setSignalRateLimit+0x58>)
|
|
8005de6: f7fa fb2f bl 8000448 <__aeabi_dcmpgt>
|
|
8005dea: 1e03 subs r3, r0, #0
|
|
8005dec: d001 beq.n 8005df2 <setSignalRateLimit+0x2a>
|
|
8005dee: 2300 movs r3, #0
|
|
8005df0: e00f b.n 8005e12 <setSignalRateLimit+0x4a>
|
|
|
|
// Q9.7 fixed point format (9 integer bits, 7 fractional bits)
|
|
writeReg16Bit(FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT, limit_Mcps * (1 << 7));
|
|
8005df2: 2186 movs r1, #134 ; 0x86
|
|
8005df4: 05c9 lsls r1, r1, #23
|
|
8005df6: 6878 ldr r0, [r7, #4]
|
|
8005df8: f7fa fc3c bl 8000674 <__aeabi_fmul>
|
|
8005dfc: 1c03 adds r3, r0, #0
|
|
8005dfe: 1c18 adds r0, r3, #0
|
|
8005e00: f7fa fb70 bl 80004e4 <__aeabi_f2uiz>
|
|
8005e04: 0003 movs r3, r0
|
|
8005e06: b29b uxth r3, r3
|
|
8005e08: 0019 movs r1, r3
|
|
8005e0a: 2044 movs r0, #68 ; 0x44
|
|
8005e0c: f7ff fc6e bl 80056ec <writeReg16Bit>
|
|
return true;
|
|
8005e10: 2301 movs r3, #1
|
|
}
|
|
8005e12: 0018 movs r0, r3
|
|
8005e14: 46bd mov sp, r7
|
|
8005e16: b002 add sp, #8
|
|
8005e18: bd80 pop {r7, pc}
|
|
8005e1a: 46c0 nop ; (mov r8, r8)
|
|
8005e1c: 0a3d70a4 .word 0x0a3d70a4
|
|
8005e20: 407fffd7 .word 0x407fffd7
|
|
|
|
08005e24 <setMeasurementTimingBudget>:
|
|
// budget allows for more accurate measurements. Increasing the budget by a
|
|
// factor of N decreases the range measurement standard deviation by a factor of
|
|
// sqrt(N). Defaults to about 33 milliseconds; the minimum is 20 ms.
|
|
// based on VL53L0X_set_measurement_timing_budget_micro_seconds()
|
|
bool setMeasurementTimingBudget(uint32_t budget_us)
|
|
{
|
|
8005e24: b5b0 push {r4, r5, r7, lr}
|
|
8005e26: b092 sub sp, #72 ; 0x48
|
|
8005e28: af00 add r7, sp, #0
|
|
8005e2a: 6078 str r0, [r7, #4]
|
|
SequenceStepEnables enables;
|
|
SequenceStepTimeouts timeouts;
|
|
|
|
uint16_t const StartOverhead = 1320; // note that this is different than the value in get_
|
|
8005e2c: 2340 movs r3, #64 ; 0x40
|
|
8005e2e: 18fb adds r3, r7, r3
|
|
8005e30: 22a5 movs r2, #165 ; 0xa5
|
|
8005e32: 00d2 lsls r2, r2, #3
|
|
8005e34: 801a strh r2, [r3, #0]
|
|
uint16_t const EndOverhead = 960;
|
|
8005e36: 233e movs r3, #62 ; 0x3e
|
|
8005e38: 18fb adds r3, r7, r3
|
|
8005e3a: 22f0 movs r2, #240 ; 0xf0
|
|
8005e3c: 0092 lsls r2, r2, #2
|
|
8005e3e: 801a strh r2, [r3, #0]
|
|
uint16_t const MsrcOverhead = 660;
|
|
8005e40: 233c movs r3, #60 ; 0x3c
|
|
8005e42: 18fb adds r3, r7, r3
|
|
8005e44: 22a5 movs r2, #165 ; 0xa5
|
|
8005e46: 0092 lsls r2, r2, #2
|
|
8005e48: 801a strh r2, [r3, #0]
|
|
uint16_t const TccOverhead = 590;
|
|
8005e4a: 233a movs r3, #58 ; 0x3a
|
|
8005e4c: 18fb adds r3, r7, r3
|
|
8005e4e: 4a54 ldr r2, [pc, #336] ; (8005fa0 <setMeasurementTimingBudget+0x17c>)
|
|
8005e50: 801a strh r2, [r3, #0]
|
|
uint16_t const DssOverhead = 690;
|
|
8005e52: 2338 movs r3, #56 ; 0x38
|
|
8005e54: 18fb adds r3, r7, r3
|
|
8005e56: 4a53 ldr r2, [pc, #332] ; (8005fa4 <setMeasurementTimingBudget+0x180>)
|
|
8005e58: 801a strh r2, [r3, #0]
|
|
uint16_t const PreRangeOverhead = 660;
|
|
8005e5a: 2336 movs r3, #54 ; 0x36
|
|
8005e5c: 18fb adds r3, r7, r3
|
|
8005e5e: 22a5 movs r2, #165 ; 0xa5
|
|
8005e60: 0092 lsls r2, r2, #2
|
|
8005e62: 801a strh r2, [r3, #0]
|
|
uint16_t const FinalRangeOverhead = 550;
|
|
8005e64: 2334 movs r3, #52 ; 0x34
|
|
8005e66: 18fb adds r3, r7, r3
|
|
8005e68: 4a4f ldr r2, [pc, #316] ; (8005fa8 <setMeasurementTimingBudget+0x184>)
|
|
8005e6a: 801a strh r2, [r3, #0]
|
|
|
|
uint32_t const MinTimingBudget = 20000;
|
|
8005e6c: 4b4f ldr r3, [pc, #316] ; (8005fac <setMeasurementTimingBudget+0x188>)
|
|
8005e6e: 633b str r3, [r7, #48] ; 0x30
|
|
|
|
if (budget_us < MinTimingBudget) { return false; }
|
|
8005e70: 687a ldr r2, [r7, #4]
|
|
8005e72: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8005e74: 429a cmp r2, r3
|
|
8005e76: d201 bcs.n 8005e7c <setMeasurementTimingBudget+0x58>
|
|
8005e78: 2300 movs r3, #0
|
|
8005e7a: e08c b.n 8005f96 <setMeasurementTimingBudget+0x172>
|
|
|
|
uint32_t used_budget_us = StartOverhead + EndOverhead;
|
|
8005e7c: 2340 movs r3, #64 ; 0x40
|
|
8005e7e: 18fb adds r3, r7, r3
|
|
8005e80: 881a ldrh r2, [r3, #0]
|
|
8005e82: 233e movs r3, #62 ; 0x3e
|
|
8005e84: 18fb adds r3, r7, r3
|
|
8005e86: 881b ldrh r3, [r3, #0]
|
|
8005e88: 18d3 adds r3, r2, r3
|
|
8005e8a: 647b str r3, [r7, #68] ; 0x44
|
|
|
|
getSequenceStepEnables(&enables);
|
|
8005e8c: 2424 movs r4, #36 ; 0x24
|
|
8005e8e: 193b adds r3, r7, r4
|
|
8005e90: 0018 movs r0, r3
|
|
8005e92: f000 fabd bl 8006410 <getSequenceStepEnables>
|
|
getSequenceStepTimeouts(&enables, &timeouts);
|
|
8005e96: 250c movs r5, #12
|
|
8005e98: 197a adds r2, r7, r5
|
|
8005e9a: 193b adds r3, r7, r4
|
|
8005e9c: 0011 movs r1, r2
|
|
8005e9e: 0018 movs r0, r3
|
|
8005ea0: f000 faf0 bl 8006484 <getSequenceStepTimeouts>
|
|
|
|
if (enables.tcc)
|
|
8005ea4: 193b adds r3, r7, r4
|
|
8005ea6: 781b ldrb r3, [r3, #0]
|
|
8005ea8: 2b00 cmp r3, #0
|
|
8005eaa: d008 beq.n 8005ebe <setMeasurementTimingBudget+0x9a>
|
|
{
|
|
used_budget_us += (timeouts.msrc_dss_tcc_us + TccOverhead);
|
|
8005eac: 197b adds r3, r7, r5
|
|
8005eae: 68da ldr r2, [r3, #12]
|
|
8005eb0: 233a movs r3, #58 ; 0x3a
|
|
8005eb2: 18fb adds r3, r7, r3
|
|
8005eb4: 881b ldrh r3, [r3, #0]
|
|
8005eb6: 18d3 adds r3, r2, r3
|
|
8005eb8: 6c7a ldr r2, [r7, #68] ; 0x44
|
|
8005eba: 18d3 adds r3, r2, r3
|
|
8005ebc: 647b str r3, [r7, #68] ; 0x44
|
|
}
|
|
|
|
if (enables.dss)
|
|
8005ebe: 2324 movs r3, #36 ; 0x24
|
|
8005ec0: 18fb adds r3, r7, r3
|
|
8005ec2: 789b ldrb r3, [r3, #2]
|
|
8005ec4: 2b00 cmp r3, #0
|
|
8005ec6: d00b beq.n 8005ee0 <setMeasurementTimingBudget+0xbc>
|
|
{
|
|
used_budget_us += 2 * (timeouts.msrc_dss_tcc_us + DssOverhead);
|
|
8005ec8: 230c movs r3, #12
|
|
8005eca: 18fb adds r3, r7, r3
|
|
8005ecc: 68da ldr r2, [r3, #12]
|
|
8005ece: 2338 movs r3, #56 ; 0x38
|
|
8005ed0: 18fb adds r3, r7, r3
|
|
8005ed2: 881b ldrh r3, [r3, #0]
|
|
8005ed4: 18d3 adds r3, r2, r3
|
|
8005ed6: 005b lsls r3, r3, #1
|
|
8005ed8: 6c7a ldr r2, [r7, #68] ; 0x44
|
|
8005eda: 18d3 adds r3, r2, r3
|
|
8005edc: 647b str r3, [r7, #68] ; 0x44
|
|
8005ede: e00e b.n 8005efe <setMeasurementTimingBudget+0xda>
|
|
}
|
|
else if (enables.msrc)
|
|
8005ee0: 2324 movs r3, #36 ; 0x24
|
|
8005ee2: 18fb adds r3, r7, r3
|
|
8005ee4: 785b ldrb r3, [r3, #1]
|
|
8005ee6: 2b00 cmp r3, #0
|
|
8005ee8: d009 beq.n 8005efe <setMeasurementTimingBudget+0xda>
|
|
{
|
|
used_budget_us += (timeouts.msrc_dss_tcc_us + MsrcOverhead);
|
|
8005eea: 230c movs r3, #12
|
|
8005eec: 18fb adds r3, r7, r3
|
|
8005eee: 68da ldr r2, [r3, #12]
|
|
8005ef0: 233c movs r3, #60 ; 0x3c
|
|
8005ef2: 18fb adds r3, r7, r3
|
|
8005ef4: 881b ldrh r3, [r3, #0]
|
|
8005ef6: 18d3 adds r3, r2, r3
|
|
8005ef8: 6c7a ldr r2, [r7, #68] ; 0x44
|
|
8005efa: 18d3 adds r3, r2, r3
|
|
8005efc: 647b str r3, [r7, #68] ; 0x44
|
|
}
|
|
|
|
if (enables.pre_range)
|
|
8005efe: 2324 movs r3, #36 ; 0x24
|
|
8005f00: 18fb adds r3, r7, r3
|
|
8005f02: 78db ldrb r3, [r3, #3]
|
|
8005f04: 2b00 cmp r3, #0
|
|
8005f06: d009 beq.n 8005f1c <setMeasurementTimingBudget+0xf8>
|
|
{
|
|
used_budget_us += (timeouts.pre_range_us + PreRangeOverhead);
|
|
8005f08: 230c movs r3, #12
|
|
8005f0a: 18fb adds r3, r7, r3
|
|
8005f0c: 691a ldr r2, [r3, #16]
|
|
8005f0e: 2336 movs r3, #54 ; 0x36
|
|
8005f10: 18fb adds r3, r7, r3
|
|
8005f12: 881b ldrh r3, [r3, #0]
|
|
8005f14: 18d3 adds r3, r2, r3
|
|
8005f16: 6c7a ldr r2, [r7, #68] ; 0x44
|
|
8005f18: 18d3 adds r3, r2, r3
|
|
8005f1a: 647b str r3, [r7, #68] ; 0x44
|
|
}
|
|
|
|
if (enables.final_range)
|
|
8005f1c: 2324 movs r3, #36 ; 0x24
|
|
8005f1e: 18fb adds r3, r7, r3
|
|
8005f20: 791b ldrb r3, [r3, #4]
|
|
8005f22: 2b00 cmp r3, #0
|
|
8005f24: d036 beq.n 8005f94 <setMeasurementTimingBudget+0x170>
|
|
{
|
|
used_budget_us += FinalRangeOverhead;
|
|
8005f26: 2334 movs r3, #52 ; 0x34
|
|
8005f28: 18fb adds r3, r7, r3
|
|
8005f2a: 881b ldrh r3, [r3, #0]
|
|
8005f2c: 6c7a ldr r2, [r7, #68] ; 0x44
|
|
8005f2e: 18d3 adds r3, r2, r3
|
|
8005f30: 647b str r3, [r7, #68] ; 0x44
|
|
// budget and the sum of all other timeouts within the sequence.
|
|
// If there is no room for the final range timeout, then an error
|
|
// will be set. Otherwise the remaining time will be applied to
|
|
// the final range."
|
|
|
|
if (used_budget_us > budget_us)
|
|
8005f32: 6c7a ldr r2, [r7, #68] ; 0x44
|
|
8005f34: 687b ldr r3, [r7, #4]
|
|
8005f36: 429a cmp r2, r3
|
|
8005f38: d901 bls.n 8005f3e <setMeasurementTimingBudget+0x11a>
|
|
{
|
|
// "Requested timeout too big."
|
|
return false;
|
|
8005f3a: 2300 movs r3, #0
|
|
8005f3c: e02b b.n 8005f96 <setMeasurementTimingBudget+0x172>
|
|
}
|
|
|
|
uint32_t final_range_timeout_us = budget_us - used_budget_us;
|
|
8005f3e: 687a ldr r2, [r7, #4]
|
|
8005f40: 6c7b ldr r3, [r7, #68] ; 0x44
|
|
8005f42: 1ad3 subs r3, r2, r3
|
|
8005f44: 62fb str r3, [r7, #44] ; 0x2c
|
|
// timeouts must be expressed in macro periods MClks
|
|
// because they have different vcsel periods."
|
|
|
|
uint16_t final_range_timeout_mclks =
|
|
timeoutMicrosecondsToMclks(final_range_timeout_us,
|
|
timeouts.final_range_vcsel_period_pclks);
|
|
8005f46: 240c movs r4, #12
|
|
8005f48: 193b adds r3, r7, r4
|
|
8005f4a: 885b ldrh r3, [r3, #2]
|
|
timeoutMicrosecondsToMclks(final_range_timeout_us,
|
|
8005f4c: b2da uxtb r2, r3
|
|
8005f4e: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8005f50: 0011 movs r1, r2
|
|
8005f52: 0018 movs r0, r3
|
|
8005f54: f000 fb75 bl 8006642 <timeoutMicrosecondsToMclks>
|
|
8005f58: 0002 movs r2, r0
|
|
uint16_t final_range_timeout_mclks =
|
|
8005f5a: 2042 movs r0, #66 ; 0x42
|
|
8005f5c: 183b adds r3, r7, r0
|
|
8005f5e: 801a strh r2, [r3, #0]
|
|
|
|
if (enables.pre_range)
|
|
8005f60: 2324 movs r3, #36 ; 0x24
|
|
8005f62: 18fb adds r3, r7, r3
|
|
8005f64: 78db ldrb r3, [r3, #3]
|
|
8005f66: 2b00 cmp r3, #0
|
|
8005f68: d006 beq.n 8005f78 <setMeasurementTimingBudget+0x154>
|
|
{
|
|
final_range_timeout_mclks += timeouts.pre_range_mclks;
|
|
8005f6a: 193b adds r3, r7, r4
|
|
8005f6c: 88d9 ldrh r1, [r3, #6]
|
|
8005f6e: 183b adds r3, r7, r0
|
|
8005f70: 183a adds r2, r7, r0
|
|
8005f72: 8812 ldrh r2, [r2, #0]
|
|
8005f74: 188a adds r2, r1, r2
|
|
8005f76: 801a strh r2, [r3, #0]
|
|
}
|
|
|
|
writeReg16Bit(FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI,
|
|
8005f78: 2342 movs r3, #66 ; 0x42
|
|
8005f7a: 18fb adds r3, r7, r3
|
|
8005f7c: 881b ldrh r3, [r3, #0]
|
|
8005f7e: 0018 movs r0, r3
|
|
8005f80: f000 fafc bl 800657c <encodeTimeout>
|
|
8005f84: 0003 movs r3, r0
|
|
8005f86: 0019 movs r1, r3
|
|
8005f88: 2071 movs r0, #113 ; 0x71
|
|
8005f8a: f7ff fbaf bl 80056ec <writeReg16Bit>
|
|
encodeTimeout(final_range_timeout_mclks));
|
|
|
|
// set_sequence_step_timeout() end
|
|
|
|
g_measTimBudUs = budget_us; // store for internal reuse
|
|
8005f8e: 4b08 ldr r3, [pc, #32] ; (8005fb0 <setMeasurementTimingBudget+0x18c>)
|
|
8005f90: 687a ldr r2, [r7, #4]
|
|
8005f92: 601a str r2, [r3, #0]
|
|
}
|
|
return true;
|
|
8005f94: 2301 movs r3, #1
|
|
}
|
|
8005f96: 0018 movs r0, r3
|
|
8005f98: 46bd mov sp, r7
|
|
8005f9a: b012 add sp, #72 ; 0x48
|
|
8005f9c: bdb0 pop {r4, r5, r7, pc}
|
|
8005f9e: 46c0 nop ; (mov r8, r8)
|
|
8005fa0: 0000024e .word 0x0000024e
|
|
8005fa4: 000002b2 .word 0x000002b2
|
|
8005fa8: 00000226 .word 0x00000226
|
|
8005fac: 00004e20 .word 0x00004e20
|
|
8005fb0: 20000260 .word 0x20000260
|
|
|
|
08005fb4 <getMeasurementTimingBudget>:
|
|
|
|
// Get the measurement timing budget in microseconds
|
|
// based on VL53L0X_get_measurement_timing_budget_micro_seconds()
|
|
// in us
|
|
uint32_t getMeasurementTimingBudget(void)
|
|
{
|
|
8005fb4: b5b0 push {r4, r5, r7, lr}
|
|
8005fb6: b08c sub sp, #48 ; 0x30
|
|
8005fb8: af00 add r7, sp, #0
|
|
SequenceStepEnables enables;
|
|
SequenceStepTimeouts timeouts;
|
|
|
|
uint16_t const StartOverhead = 1910; // note that this is different than the value in set_
|
|
8005fba: 212a movs r1, #42 ; 0x2a
|
|
8005fbc: 187b adds r3, r7, r1
|
|
8005fbe: 4a3e ldr r2, [pc, #248] ; (80060b8 <getMeasurementTimingBudget+0x104>)
|
|
8005fc0: 801a strh r2, [r3, #0]
|
|
uint16_t const EndOverhead = 960;
|
|
8005fc2: 2028 movs r0, #40 ; 0x28
|
|
8005fc4: 183b adds r3, r7, r0
|
|
8005fc6: 22f0 movs r2, #240 ; 0xf0
|
|
8005fc8: 0092 lsls r2, r2, #2
|
|
8005fca: 801a strh r2, [r3, #0]
|
|
uint16_t const MsrcOverhead = 660;
|
|
8005fcc: 2326 movs r3, #38 ; 0x26
|
|
8005fce: 18fb adds r3, r7, r3
|
|
8005fd0: 22a5 movs r2, #165 ; 0xa5
|
|
8005fd2: 0092 lsls r2, r2, #2
|
|
8005fd4: 801a strh r2, [r3, #0]
|
|
uint16_t const TccOverhead = 590;
|
|
8005fd6: 2524 movs r5, #36 ; 0x24
|
|
8005fd8: 197b adds r3, r7, r5
|
|
8005fda: 4a38 ldr r2, [pc, #224] ; (80060bc <getMeasurementTimingBudget+0x108>)
|
|
8005fdc: 801a strh r2, [r3, #0]
|
|
uint16_t const DssOverhead = 690;
|
|
8005fde: 2322 movs r3, #34 ; 0x22
|
|
8005fe0: 18fb adds r3, r7, r3
|
|
8005fe2: 4a37 ldr r2, [pc, #220] ; (80060c0 <getMeasurementTimingBudget+0x10c>)
|
|
8005fe4: 801a strh r2, [r3, #0]
|
|
uint16_t const PreRangeOverhead = 660;
|
|
8005fe6: 2320 movs r3, #32
|
|
8005fe8: 18fb adds r3, r7, r3
|
|
8005fea: 22a5 movs r2, #165 ; 0xa5
|
|
8005fec: 0092 lsls r2, r2, #2
|
|
8005fee: 801a strh r2, [r3, #0]
|
|
uint16_t const FinalRangeOverhead = 550;
|
|
8005ff0: 231e movs r3, #30
|
|
8005ff2: 18fb adds r3, r7, r3
|
|
8005ff4: 4a33 ldr r2, [pc, #204] ; (80060c4 <getMeasurementTimingBudget+0x110>)
|
|
8005ff6: 801a strh r2, [r3, #0]
|
|
|
|
// "Start and end overhead times always present"
|
|
uint32_t budget_us = StartOverhead + EndOverhead;
|
|
8005ff8: 187b adds r3, r7, r1
|
|
8005ffa: 881a ldrh r2, [r3, #0]
|
|
8005ffc: 183b adds r3, r7, r0
|
|
8005ffe: 881b ldrh r3, [r3, #0]
|
|
8006000: 18d3 adds r3, r2, r3
|
|
8006002: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
|
getSequenceStepEnables(&enables);
|
|
8006004: 2418 movs r4, #24
|
|
8006006: 193b adds r3, r7, r4
|
|
8006008: 0018 movs r0, r3
|
|
800600a: f000 fa01 bl 8006410 <getSequenceStepEnables>
|
|
getSequenceStepTimeouts(&enables, &timeouts);
|
|
800600e: 003a movs r2, r7
|
|
8006010: 193b adds r3, r7, r4
|
|
8006012: 0011 movs r1, r2
|
|
8006014: 0018 movs r0, r3
|
|
8006016: f000 fa35 bl 8006484 <getSequenceStepTimeouts>
|
|
|
|
if (enables.tcc)
|
|
800601a: 193b adds r3, r7, r4
|
|
800601c: 781b ldrb r3, [r3, #0]
|
|
800601e: 2b00 cmp r3, #0
|
|
8006020: d007 beq.n 8006032 <getMeasurementTimingBudget+0x7e>
|
|
{
|
|
budget_us += (timeouts.msrc_dss_tcc_us + TccOverhead);
|
|
8006022: 003b movs r3, r7
|
|
8006024: 68da ldr r2, [r3, #12]
|
|
8006026: 197b adds r3, r7, r5
|
|
8006028: 881b ldrh r3, [r3, #0]
|
|
800602a: 18d3 adds r3, r2, r3
|
|
800602c: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
800602e: 18d3 adds r3, r2, r3
|
|
8006030: 62fb str r3, [r7, #44] ; 0x2c
|
|
}
|
|
|
|
if (enables.dss)
|
|
8006032: 2318 movs r3, #24
|
|
8006034: 18fb adds r3, r7, r3
|
|
8006036: 789b ldrb r3, [r3, #2]
|
|
8006038: 2b00 cmp r3, #0
|
|
800603a: d00a beq.n 8006052 <getMeasurementTimingBudget+0x9e>
|
|
{
|
|
budget_us += 2 * (timeouts.msrc_dss_tcc_us + DssOverhead);
|
|
800603c: 003b movs r3, r7
|
|
800603e: 68da ldr r2, [r3, #12]
|
|
8006040: 2322 movs r3, #34 ; 0x22
|
|
8006042: 18fb adds r3, r7, r3
|
|
8006044: 881b ldrh r3, [r3, #0]
|
|
8006046: 18d3 adds r3, r2, r3
|
|
8006048: 005b lsls r3, r3, #1
|
|
800604a: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
800604c: 18d3 adds r3, r2, r3
|
|
800604e: 62fb str r3, [r7, #44] ; 0x2c
|
|
8006050: e00d b.n 800606e <getMeasurementTimingBudget+0xba>
|
|
}
|
|
else if (enables.msrc)
|
|
8006052: 2318 movs r3, #24
|
|
8006054: 18fb adds r3, r7, r3
|
|
8006056: 785b ldrb r3, [r3, #1]
|
|
8006058: 2b00 cmp r3, #0
|
|
800605a: d008 beq.n 800606e <getMeasurementTimingBudget+0xba>
|
|
{
|
|
budget_us += (timeouts.msrc_dss_tcc_us + MsrcOverhead);
|
|
800605c: 003b movs r3, r7
|
|
800605e: 68da ldr r2, [r3, #12]
|
|
8006060: 2326 movs r3, #38 ; 0x26
|
|
8006062: 18fb adds r3, r7, r3
|
|
8006064: 881b ldrh r3, [r3, #0]
|
|
8006066: 18d3 adds r3, r2, r3
|
|
8006068: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
800606a: 18d3 adds r3, r2, r3
|
|
800606c: 62fb str r3, [r7, #44] ; 0x2c
|
|
}
|
|
|
|
if (enables.pre_range)
|
|
800606e: 2318 movs r3, #24
|
|
8006070: 18fb adds r3, r7, r3
|
|
8006072: 78db ldrb r3, [r3, #3]
|
|
8006074: 2b00 cmp r3, #0
|
|
8006076: d008 beq.n 800608a <getMeasurementTimingBudget+0xd6>
|
|
{
|
|
budget_us += (timeouts.pre_range_us + PreRangeOverhead);
|
|
8006078: 003b movs r3, r7
|
|
800607a: 691a ldr r2, [r3, #16]
|
|
800607c: 2320 movs r3, #32
|
|
800607e: 18fb adds r3, r7, r3
|
|
8006080: 881b ldrh r3, [r3, #0]
|
|
8006082: 18d3 adds r3, r2, r3
|
|
8006084: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
8006086: 18d3 adds r3, r2, r3
|
|
8006088: 62fb str r3, [r7, #44] ; 0x2c
|
|
}
|
|
|
|
if (enables.final_range)
|
|
800608a: 2318 movs r3, #24
|
|
800608c: 18fb adds r3, r7, r3
|
|
800608e: 791b ldrb r3, [r3, #4]
|
|
8006090: 2b00 cmp r3, #0
|
|
8006092: d008 beq.n 80060a6 <getMeasurementTimingBudget+0xf2>
|
|
{
|
|
budget_us += (timeouts.final_range_us + FinalRangeOverhead);
|
|
8006094: 003b movs r3, r7
|
|
8006096: 695a ldr r2, [r3, #20]
|
|
8006098: 231e movs r3, #30
|
|
800609a: 18fb adds r3, r7, r3
|
|
800609c: 881b ldrh r3, [r3, #0]
|
|
800609e: 18d3 adds r3, r2, r3
|
|
80060a0: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
80060a2: 18d3 adds r3, r2, r3
|
|
80060a4: 62fb str r3, [r7, #44] ; 0x2c
|
|
}
|
|
|
|
g_measTimBudUs = budget_us; // store for internal reuse
|
|
80060a6: 4b08 ldr r3, [pc, #32] ; (80060c8 <getMeasurementTimingBudget+0x114>)
|
|
80060a8: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
80060aa: 601a str r2, [r3, #0]
|
|
return budget_us;
|
|
80060ac: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
}
|
|
80060ae: 0018 movs r0, r3
|
|
80060b0: 46bd mov sp, r7
|
|
80060b2: b00c add sp, #48 ; 0x30
|
|
80060b4: bdb0 pop {r4, r5, r7, pc}
|
|
80060b6: 46c0 nop ; (mov r8, r8)
|
|
80060b8: 00000776 .word 0x00000776
|
|
80060bc: 0000024e .word 0x0000024e
|
|
80060c0: 000002b2 .word 0x000002b2
|
|
80060c4: 00000226 .word 0x00000226
|
|
80060c8: 20000260 .word 0x20000260
|
|
|
|
080060cc <getVcselPulsePeriod>:
|
|
}
|
|
|
|
// Get the VCSEL pulse period in PCLKs for the given period type.
|
|
// based on VL53L0X_get_vcsel_pulse_period()
|
|
uint8_t getVcselPulsePeriod(vcselPeriodType type)
|
|
{
|
|
80060cc: b580 push {r7, lr}
|
|
80060ce: b082 sub sp, #8
|
|
80060d0: af00 add r7, sp, #0
|
|
80060d2: 0002 movs r2, r0
|
|
80060d4: 1dfb adds r3, r7, #7
|
|
80060d6: 701a strb r2, [r3, #0]
|
|
if (type == VcselPeriodPreRange)
|
|
80060d8: 1dfb adds r3, r7, #7
|
|
80060da: 781b ldrb r3, [r3, #0]
|
|
80060dc: 2b00 cmp r3, #0
|
|
80060de: d108 bne.n 80060f2 <getVcselPulsePeriod+0x26>
|
|
{
|
|
return decodeVcselPeriod(readReg(PRE_RANGE_CONFIG_VCSEL_PERIOD));
|
|
80060e0: 2050 movs r0, #80 ; 0x50
|
|
80060e2: f7ff fb67 bl 80057b4 <readReg>
|
|
80060e6: 0003 movs r3, r0
|
|
80060e8: 3301 adds r3, #1
|
|
80060ea: b2db uxtb r3, r3
|
|
80060ec: 18db adds r3, r3, r3
|
|
80060ee: b2db uxtb r3, r3
|
|
80060f0: e00d b.n 800610e <getVcselPulsePeriod+0x42>
|
|
}
|
|
else if (type == VcselPeriodFinalRange)
|
|
80060f2: 1dfb adds r3, r7, #7
|
|
80060f4: 781b ldrb r3, [r3, #0]
|
|
80060f6: 2b01 cmp r3, #1
|
|
80060f8: d108 bne.n 800610c <getVcselPulsePeriod+0x40>
|
|
{
|
|
return decodeVcselPeriod(readReg(FINAL_RANGE_CONFIG_VCSEL_PERIOD));
|
|
80060fa: 2070 movs r0, #112 ; 0x70
|
|
80060fc: f7ff fb5a bl 80057b4 <readReg>
|
|
8006100: 0003 movs r3, r0
|
|
8006102: 3301 adds r3, #1
|
|
8006104: b2db uxtb r3, r3
|
|
8006106: 18db adds r3, r3, r3
|
|
8006108: b2db uxtb r3, r3
|
|
800610a: e000 b.n 800610e <getVcselPulsePeriod+0x42>
|
|
}
|
|
else { return 255; }
|
|
800610c: 23ff movs r3, #255 ; 0xff
|
|
}
|
|
800610e: 0018 movs r0, r3
|
|
8006110: 46bd mov sp, r7
|
|
8006112: b002 add sp, #8
|
|
8006114: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08006118 <startContinuous>:
|
|
// often as possible); otherwise, continuous timed mode is used, with the given
|
|
// inter-measurement period in milliseconds determining how often the sensor
|
|
// takes a measurement.
|
|
// based on VL53L0X_StartMeasurement()
|
|
void startContinuous(uint32_t period_ms)
|
|
{
|
|
8006118: b5b0 push {r4, r5, r7, lr}
|
|
800611a: b084 sub sp, #16
|
|
800611c: af00 add r7, sp, #0
|
|
800611e: 6078 str r0, [r7, #4]
|
|
writeReg(0x80, 0x01);
|
|
8006120: 2101 movs r1, #1
|
|
8006122: 2080 movs r0, #128 ; 0x80
|
|
8006124: f7ff fac0 bl 80056a8 <writeReg>
|
|
writeReg(0xFF, 0x01);
|
|
8006128: 2101 movs r1, #1
|
|
800612a: 20ff movs r0, #255 ; 0xff
|
|
800612c: f7ff fabc bl 80056a8 <writeReg>
|
|
writeReg(0x00, 0x00);
|
|
8006130: 2100 movs r1, #0
|
|
8006132: 2000 movs r0, #0
|
|
8006134: f7ff fab8 bl 80056a8 <writeReg>
|
|
writeReg(0x91, g_stopVariable);
|
|
8006138: 4b1b ldr r3, [pc, #108] ; (80061a8 <startContinuous+0x90>)
|
|
800613a: 781b ldrb r3, [r3, #0]
|
|
800613c: 0019 movs r1, r3
|
|
800613e: 2091 movs r0, #145 ; 0x91
|
|
8006140: f7ff fab2 bl 80056a8 <writeReg>
|
|
writeReg(0x00, 0x01);
|
|
8006144: 2101 movs r1, #1
|
|
8006146: 2000 movs r0, #0
|
|
8006148: f7ff faae bl 80056a8 <writeReg>
|
|
writeReg(0xFF, 0x00);
|
|
800614c: 2100 movs r1, #0
|
|
800614e: 20ff movs r0, #255 ; 0xff
|
|
8006150: f7ff faaa bl 80056a8 <writeReg>
|
|
writeReg(0x80, 0x00);
|
|
8006154: 2100 movs r1, #0
|
|
8006156: 2080 movs r0, #128 ; 0x80
|
|
8006158: f7ff faa6 bl 80056a8 <writeReg>
|
|
|
|
if (period_ms != 0)
|
|
800615c: 687b ldr r3, [r7, #4]
|
|
800615e: 2b00 cmp r3, #0
|
|
8006160: d019 beq.n 8006196 <startContinuous+0x7e>
|
|
{
|
|
// continuous timed mode
|
|
|
|
// VL53L0X_SetInterMeasurementPeriodMilliSeconds() begin
|
|
|
|
uint16_t osc_calibrate_val = readReg16Bit(OSC_CALIBRATE_VAL);
|
|
8006162: 250e movs r5, #14
|
|
8006164: 197c adds r4, r7, r5
|
|
8006166: 20f8 movs r0, #248 ; 0xf8
|
|
8006168: f7ff fb46 bl 80057f8 <readReg16Bit>
|
|
800616c: 0003 movs r3, r0
|
|
800616e: 8023 strh r3, [r4, #0]
|
|
|
|
if (osc_calibrate_val != 0)
|
|
8006170: 197b adds r3, r7, r5
|
|
8006172: 881b ldrh r3, [r3, #0]
|
|
8006174: 2b00 cmp r3, #0
|
|
8006176: d004 beq.n 8006182 <startContinuous+0x6a>
|
|
{
|
|
period_ms *= osc_calibrate_val;
|
|
8006178: 197b adds r3, r7, r5
|
|
800617a: 881a ldrh r2, [r3, #0]
|
|
800617c: 687b ldr r3, [r7, #4]
|
|
800617e: 4353 muls r3, r2
|
|
8006180: 607b str r3, [r7, #4]
|
|
}
|
|
|
|
writeReg32Bit(SYSTEM_INTERMEASUREMENT_PERIOD, period_ms);
|
|
8006182: 687b ldr r3, [r7, #4]
|
|
8006184: 0019 movs r1, r3
|
|
8006186: 2004 movs r0, #4
|
|
8006188: f7ff fae0 bl 800574c <writeReg32Bit>
|
|
|
|
// VL53L0X_SetInterMeasurementPeriodMilliSeconds() end
|
|
|
|
writeReg(SYSRANGE_START, 0x04); // VL53L0X_REG_SYSRANGE_MODE_TIMED
|
|
800618c: 2104 movs r1, #4
|
|
800618e: 2000 movs r0, #0
|
|
8006190: f7ff fa8a bl 80056a8 <writeReg>
|
|
else
|
|
{
|
|
// continuous back-to-back mode
|
|
writeReg(SYSRANGE_START, 0x02); // VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK
|
|
}
|
|
}
|
|
8006194: e003 b.n 800619e <startContinuous+0x86>
|
|
writeReg(SYSRANGE_START, 0x02); // VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK
|
|
8006196: 2102 movs r1, #2
|
|
8006198: 2000 movs r0, #0
|
|
800619a: f7ff fa85 bl 80056a8 <writeReg>
|
|
}
|
|
800619e: 46c0 nop ; (mov r8, r8)
|
|
80061a0: 46bd mov sp, r7
|
|
80061a2: b004 add sp, #16
|
|
80061a4: bdb0 pop {r4, r5, r7, pc}
|
|
80061a6: 46c0 nop ; (mov r8, r8)
|
|
80061a8: 2000025e .word 0x2000025e
|
|
|
|
080061ac <readRangeContinuousMillimeters>:
|
|
|
|
// Returns a range reading in millimeters when continuous mode is active
|
|
// (readRangeSingleMillimeters() also calls this function after starting a
|
|
// single-shot range measurement)
|
|
// extraStats provides additional info for this measurment. Set to 0 if not needed.
|
|
uint16_t readRangeContinuousMillimeters( statInfo_t *extraStats ) {
|
|
80061ac: b590 push {r4, r7, lr}
|
|
80061ae: b087 sub sp, #28
|
|
80061b0: af00 add r7, sp, #0
|
|
80061b2: 6078 str r0, [r7, #4]
|
|
uint8_t tempBuffer[12];
|
|
uint16_t temp;
|
|
startTimeout();
|
|
80061b4: f7fb fdda bl 8001d6c <HAL_GetTick>
|
|
80061b8: 0003 movs r3, r0
|
|
80061ba: b29a uxth r2, r3
|
|
80061bc: 4b3b ldr r3, [pc, #236] ; (80062ac <readRangeContinuousMillimeters+0x100>)
|
|
80061be: 801a strh r2, [r3, #0]
|
|
while ((readReg(RESULT_INTERRUPT_STATUS) & 0x07) == 0) {
|
|
80061c0: e014 b.n 80061ec <readRangeContinuousMillimeters+0x40>
|
|
if (checkTimeoutExpired())
|
|
80061c2: 4b3b ldr r3, [pc, #236] ; (80062b0 <readRangeContinuousMillimeters+0x104>)
|
|
80061c4: 881b ldrh r3, [r3, #0]
|
|
80061c6: 2b00 cmp r3, #0
|
|
80061c8: d010 beq.n 80061ec <readRangeContinuousMillimeters+0x40>
|
|
80061ca: f7fb fdcf bl 8001d6c <HAL_GetTick>
|
|
80061ce: 0003 movs r3, r0
|
|
80061d0: b29b uxth r3, r3
|
|
80061d2: 001a movs r2, r3
|
|
80061d4: 4b35 ldr r3, [pc, #212] ; (80062ac <readRangeContinuousMillimeters+0x100>)
|
|
80061d6: 881b ldrh r3, [r3, #0]
|
|
80061d8: 1ad3 subs r3, r2, r3
|
|
80061da: 4a35 ldr r2, [pc, #212] ; (80062b0 <readRangeContinuousMillimeters+0x104>)
|
|
80061dc: 8812 ldrh r2, [r2, #0]
|
|
80061de: 4293 cmp r3, r2
|
|
80061e0: dd04 ble.n 80061ec <readRangeContinuousMillimeters+0x40>
|
|
{
|
|
g_isTimeout = true;
|
|
80061e2: 4b34 ldr r3, [pc, #208] ; (80062b4 <readRangeContinuousMillimeters+0x108>)
|
|
80061e4: 2201 movs r2, #1
|
|
80061e6: 701a strb r2, [r3, #0]
|
|
return 65535;
|
|
80061e8: 4b33 ldr r3, [pc, #204] ; (80062b8 <readRangeContinuousMillimeters+0x10c>)
|
|
80061ea: e05b b.n 80062a4 <readRangeContinuousMillimeters+0xf8>
|
|
while ((readReg(RESULT_INTERRUPT_STATUS) & 0x07) == 0) {
|
|
80061ec: 2013 movs r0, #19
|
|
80061ee: f7ff fae1 bl 80057b4 <readReg>
|
|
80061f2: 0003 movs r3, r0
|
|
80061f4: 001a movs r2, r3
|
|
80061f6: 2307 movs r3, #7
|
|
80061f8: 4013 ands r3, r2
|
|
80061fa: d0e2 beq.n 80061c2 <readRangeContinuousMillimeters+0x16>
|
|
}
|
|
}
|
|
if( extraStats == 0 ){
|
|
80061fc: 687b ldr r3, [r7, #4]
|
|
80061fe: 2b00 cmp r3, #0
|
|
8006200: d107 bne.n 8006212 <readRangeContinuousMillimeters+0x66>
|
|
// assumptions: Linearity Corrective Gain is 1000 (default);
|
|
// fractional ranging is not enabled
|
|
temp = readReg16Bit(RESULT_RANGE_STATUS + 10);
|
|
8006202: 2316 movs r3, #22
|
|
8006204: 18fc adds r4, r7, r3
|
|
8006206: 201e movs r0, #30
|
|
8006208: f7ff faf6 bl 80057f8 <readReg16Bit>
|
|
800620c: 0003 movs r3, r0
|
|
800620e: 8023 strh r3, [r4, #0]
|
|
8006210: e041 b.n 8006296 <readRangeContinuousMillimeters+0xea>
|
|
// 4: 0 ?
|
|
// 5: ???
|
|
// 6,7: signal count rate [mcps], uint16_t, fixpoint9.7
|
|
// 9,8: AmbientRateRtnMegaCps [mcps], uint16_t, fixpoimt9.7
|
|
// A,B: uncorrected distance [mm], uint16_t
|
|
readMulti(0x14, tempBuffer, 12);
|
|
8006212: 2408 movs r4, #8
|
|
8006214: 193b adds r3, r7, r4
|
|
8006216: 220c movs r2, #12
|
|
8006218: 0019 movs r1, r3
|
|
800621a: 2014 movs r0, #20
|
|
800621c: f7ff fb46 bl 80058ac <readMulti>
|
|
extraStats->rangeStatus = tempBuffer[0x00]>>3;
|
|
8006220: 0021 movs r1, r4
|
|
8006222: 187b adds r3, r7, r1
|
|
8006224: 781b ldrb r3, [r3, #0]
|
|
8006226: 08db lsrs r3, r3, #3
|
|
8006228: b2da uxtb r2, r3
|
|
800622a: 687b ldr r3, [r7, #4]
|
|
800622c: 721a strb r2, [r3, #8]
|
|
extraStats->spadCnt = (tempBuffer[0x02]<<8) | tempBuffer[0x03];
|
|
800622e: 187b adds r3, r7, r1
|
|
8006230: 789b ldrb r3, [r3, #2]
|
|
8006232: 021b lsls r3, r3, #8
|
|
8006234: b21a sxth r2, r3
|
|
8006236: 187b adds r3, r7, r1
|
|
8006238: 78db ldrb r3, [r3, #3]
|
|
800623a: b21b sxth r3, r3
|
|
800623c: 4313 orrs r3, r2
|
|
800623e: b21b sxth r3, r3
|
|
8006240: b29a uxth r2, r3
|
|
8006242: 687b ldr r3, [r7, #4]
|
|
8006244: 80da strh r2, [r3, #6]
|
|
extraStats->signalCnt = (tempBuffer[0x06]<<8) | tempBuffer[0x07];
|
|
8006246: 187b adds r3, r7, r1
|
|
8006248: 799b ldrb r3, [r3, #6]
|
|
800624a: 021b lsls r3, r3, #8
|
|
800624c: b21a sxth r2, r3
|
|
800624e: 187b adds r3, r7, r1
|
|
8006250: 79db ldrb r3, [r3, #7]
|
|
8006252: b21b sxth r3, r3
|
|
8006254: 4313 orrs r3, r2
|
|
8006256: b21b sxth r3, r3
|
|
8006258: b29a uxth r2, r3
|
|
800625a: 687b ldr r3, [r7, #4]
|
|
800625c: 805a strh r2, [r3, #2]
|
|
extraStats->ambientCnt = (tempBuffer[0x08]<<8) | tempBuffer[0x09];
|
|
800625e: 187b adds r3, r7, r1
|
|
8006260: 7a1b ldrb r3, [r3, #8]
|
|
8006262: 021b lsls r3, r3, #8
|
|
8006264: b21a sxth r2, r3
|
|
8006266: 187b adds r3, r7, r1
|
|
8006268: 7a5b ldrb r3, [r3, #9]
|
|
800626a: b21b sxth r3, r3
|
|
800626c: 4313 orrs r3, r2
|
|
800626e: b21b sxth r3, r3
|
|
8006270: b29a uxth r2, r3
|
|
8006272: 687b ldr r3, [r7, #4]
|
|
8006274: 809a strh r2, [r3, #4]
|
|
temp = (tempBuffer[0x0A]<<8) | tempBuffer[0x0B];
|
|
8006276: 187b adds r3, r7, r1
|
|
8006278: 7a9b ldrb r3, [r3, #10]
|
|
800627a: 021b lsls r3, r3, #8
|
|
800627c: b21a sxth r2, r3
|
|
800627e: 187b adds r3, r7, r1
|
|
8006280: 7adb ldrb r3, [r3, #11]
|
|
8006282: b21b sxth r3, r3
|
|
8006284: 4313 orrs r3, r2
|
|
8006286: b21a sxth r2, r3
|
|
8006288: 2116 movs r1, #22
|
|
800628a: 187b adds r3, r7, r1
|
|
800628c: 801a strh r2, [r3, #0]
|
|
extraStats->rawDistance = temp;
|
|
800628e: 687b ldr r3, [r7, #4]
|
|
8006290: 187a adds r2, r7, r1
|
|
8006292: 8812 ldrh r2, [r2, #0]
|
|
8006294: 801a strh r2, [r3, #0]
|
|
}
|
|
writeReg(SYSTEM_INTERRUPT_CLEAR, 0x01);
|
|
8006296: 2101 movs r1, #1
|
|
8006298: 200b movs r0, #11
|
|
800629a: f7ff fa05 bl 80056a8 <writeReg>
|
|
return temp;
|
|
800629e: 2316 movs r3, #22
|
|
80062a0: 18fb adds r3, r7, r3
|
|
80062a2: 881b ldrh r3, [r3, #0]
|
|
}
|
|
80062a4: 0018 movs r0, r3
|
|
80062a6: 46bd mov sp, r7
|
|
80062a8: b007 add sp, #28
|
|
80062aa: bd90 pop {r4, r7, pc}
|
|
80062ac: 2000025c .word 0x2000025c
|
|
80062b0: 20000258 .word 0x20000258
|
|
80062b4: 2000025a .word 0x2000025a
|
|
80062b8: 0000ffff .word 0x0000ffff
|
|
|
|
080062bc <setTimeout>:
|
|
bool tmp = g_isTimeout;
|
|
g_isTimeout = false;
|
|
return tmp;
|
|
}
|
|
|
|
void setTimeout(uint16_t timeout){
|
|
80062bc: b580 push {r7, lr}
|
|
80062be: b082 sub sp, #8
|
|
80062c0: af00 add r7, sp, #0
|
|
80062c2: 0002 movs r2, r0
|
|
80062c4: 1dbb adds r3, r7, #6
|
|
80062c6: 801a strh r2, [r3, #0]
|
|
g_ioTimeout = timeout;
|
|
80062c8: 4b03 ldr r3, [pc, #12] ; (80062d8 <setTimeout+0x1c>)
|
|
80062ca: 1dba adds r2, r7, #6
|
|
80062cc: 8812 ldrh r2, [r2, #0]
|
|
80062ce: 801a strh r2, [r3, #0]
|
|
}
|
|
80062d0: 46c0 nop ; (mov r8, r8)
|
|
80062d2: 46bd mov sp, r7
|
|
80062d4: b002 add sp, #8
|
|
80062d6: bd80 pop {r7, pc}
|
|
80062d8: 20000258 .word 0x20000258
|
|
|
|
080062dc <getSpadInfo>:
|
|
|
|
// Get reference SPAD (single photon avalanche diode) count and type
|
|
// based on VL53L0X_get_info_from_device(),
|
|
// but only gets reference SPAD count and type
|
|
bool getSpadInfo(uint8_t * count, bool * type_is_aperture)
|
|
{
|
|
80062dc: b5b0 push {r4, r5, r7, lr}
|
|
80062de: b084 sub sp, #16
|
|
80062e0: af00 add r7, sp, #0
|
|
80062e2: 6078 str r0, [r7, #4]
|
|
80062e4: 6039 str r1, [r7, #0]
|
|
uint8_t tmp;
|
|
|
|
writeReg(0x80, 0x01);
|
|
80062e6: 2101 movs r1, #1
|
|
80062e8: 2080 movs r0, #128 ; 0x80
|
|
80062ea: f7ff f9dd bl 80056a8 <writeReg>
|
|
writeReg(0xFF, 0x01);
|
|
80062ee: 2101 movs r1, #1
|
|
80062f0: 20ff movs r0, #255 ; 0xff
|
|
80062f2: f7ff f9d9 bl 80056a8 <writeReg>
|
|
writeReg(0x00, 0x00);
|
|
80062f6: 2100 movs r1, #0
|
|
80062f8: 2000 movs r0, #0
|
|
80062fa: f7ff f9d5 bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x06);
|
|
80062fe: 2106 movs r1, #6
|
|
8006300: 20ff movs r0, #255 ; 0xff
|
|
8006302: f7ff f9d1 bl 80056a8 <writeReg>
|
|
writeReg(0x83, readReg(0x83) | 0x04);
|
|
8006306: 2083 movs r0, #131 ; 0x83
|
|
8006308: f7ff fa54 bl 80057b4 <readReg>
|
|
800630c: 0003 movs r3, r0
|
|
800630e: 001a movs r2, r3
|
|
8006310: 2304 movs r3, #4
|
|
8006312: 4313 orrs r3, r2
|
|
8006314: b2db uxtb r3, r3
|
|
8006316: 0019 movs r1, r3
|
|
8006318: 2083 movs r0, #131 ; 0x83
|
|
800631a: f7ff f9c5 bl 80056a8 <writeReg>
|
|
writeReg(0xFF, 0x07);
|
|
800631e: 2107 movs r1, #7
|
|
8006320: 20ff movs r0, #255 ; 0xff
|
|
8006322: f7ff f9c1 bl 80056a8 <writeReg>
|
|
writeReg(0x81, 0x01);
|
|
8006326: 2101 movs r1, #1
|
|
8006328: 2081 movs r0, #129 ; 0x81
|
|
800632a: f7ff f9bd bl 80056a8 <writeReg>
|
|
|
|
writeReg(0x80, 0x01);
|
|
800632e: 2101 movs r1, #1
|
|
8006330: 2080 movs r0, #128 ; 0x80
|
|
8006332: f7ff f9b9 bl 80056a8 <writeReg>
|
|
|
|
writeReg(0x94, 0x6b);
|
|
8006336: 216b movs r1, #107 ; 0x6b
|
|
8006338: 2094 movs r0, #148 ; 0x94
|
|
800633a: f7ff f9b5 bl 80056a8 <writeReg>
|
|
writeReg(0x83, 0x00);
|
|
800633e: 2100 movs r1, #0
|
|
8006340: 2083 movs r0, #131 ; 0x83
|
|
8006342: f7ff f9b1 bl 80056a8 <writeReg>
|
|
startTimeout();
|
|
8006346: f7fb fd11 bl 8001d6c <HAL_GetTick>
|
|
800634a: 0003 movs r3, r0
|
|
800634c: b29a uxth r2, r3
|
|
800634e: 4b2e ldr r3, [pc, #184] ; (8006408 <getSpadInfo+0x12c>)
|
|
8006350: 801a strh r2, [r3, #0]
|
|
while (readReg(0x83) == 0x00)
|
|
8006352: e011 b.n 8006378 <getSpadInfo+0x9c>
|
|
{
|
|
if (checkTimeoutExpired()) { return false; }
|
|
8006354: 4b2d ldr r3, [pc, #180] ; (800640c <getSpadInfo+0x130>)
|
|
8006356: 881b ldrh r3, [r3, #0]
|
|
8006358: 2b00 cmp r3, #0
|
|
800635a: d00d beq.n 8006378 <getSpadInfo+0x9c>
|
|
800635c: f7fb fd06 bl 8001d6c <HAL_GetTick>
|
|
8006360: 0003 movs r3, r0
|
|
8006362: b29b uxth r3, r3
|
|
8006364: 001a movs r2, r3
|
|
8006366: 4b28 ldr r3, [pc, #160] ; (8006408 <getSpadInfo+0x12c>)
|
|
8006368: 881b ldrh r3, [r3, #0]
|
|
800636a: 1ad3 subs r3, r2, r3
|
|
800636c: 4a27 ldr r2, [pc, #156] ; (800640c <getSpadInfo+0x130>)
|
|
800636e: 8812 ldrh r2, [r2, #0]
|
|
8006370: 4293 cmp r3, r2
|
|
8006372: dd01 ble.n 8006378 <getSpadInfo+0x9c>
|
|
8006374: 2300 movs r3, #0
|
|
8006376: e043 b.n 8006400 <getSpadInfo+0x124>
|
|
while (readReg(0x83) == 0x00)
|
|
8006378: 2083 movs r0, #131 ; 0x83
|
|
800637a: f7ff fa1b bl 80057b4 <readReg>
|
|
800637e: 1e03 subs r3, r0, #0
|
|
8006380: d0e8 beq.n 8006354 <getSpadInfo+0x78>
|
|
}
|
|
writeReg(0x83, 0x01);
|
|
8006382: 2101 movs r1, #1
|
|
8006384: 2083 movs r0, #131 ; 0x83
|
|
8006386: f7ff f98f bl 80056a8 <writeReg>
|
|
tmp = readReg(0x92);
|
|
800638a: 250f movs r5, #15
|
|
800638c: 197c adds r4, r7, r5
|
|
800638e: 2092 movs r0, #146 ; 0x92
|
|
8006390: f7ff fa10 bl 80057b4 <readReg>
|
|
8006394: 0003 movs r3, r0
|
|
8006396: 7023 strb r3, [r4, #0]
|
|
|
|
*count = tmp & 0x7f;
|
|
8006398: 0029 movs r1, r5
|
|
800639a: 187b adds r3, r7, r1
|
|
800639c: 781b ldrb r3, [r3, #0]
|
|
800639e: 227f movs r2, #127 ; 0x7f
|
|
80063a0: 4013 ands r3, r2
|
|
80063a2: b2da uxtb r2, r3
|
|
80063a4: 687b ldr r3, [r7, #4]
|
|
80063a6: 701a strb r2, [r3, #0]
|
|
*type_is_aperture = (tmp >> 7) & 0x01;
|
|
80063a8: 187b adds r3, r7, r1
|
|
80063aa: 781b ldrb r3, [r3, #0]
|
|
80063ac: 09db lsrs r3, r3, #7
|
|
80063ae: b2da uxtb r2, r3
|
|
80063b0: 683b ldr r3, [r7, #0]
|
|
80063b2: 701a strb r2, [r3, #0]
|
|
|
|
writeReg(0x81, 0x00);
|
|
80063b4: 2100 movs r1, #0
|
|
80063b6: 2081 movs r0, #129 ; 0x81
|
|
80063b8: f7ff f976 bl 80056a8 <writeReg>
|
|
writeReg(0xFF, 0x06);
|
|
80063bc: 2106 movs r1, #6
|
|
80063be: 20ff movs r0, #255 ; 0xff
|
|
80063c0: f7ff f972 bl 80056a8 <writeReg>
|
|
writeReg(0x83, readReg(0x83) & ~0x04);
|
|
80063c4: 2083 movs r0, #131 ; 0x83
|
|
80063c6: f7ff f9f5 bl 80057b4 <readReg>
|
|
80063ca: 0003 movs r3, r0
|
|
80063cc: 001a movs r2, r3
|
|
80063ce: 2304 movs r3, #4
|
|
80063d0: 439a bics r2, r3
|
|
80063d2: 0013 movs r3, r2
|
|
80063d4: b2db uxtb r3, r3
|
|
80063d6: 0019 movs r1, r3
|
|
80063d8: 2083 movs r0, #131 ; 0x83
|
|
80063da: f7ff f965 bl 80056a8 <writeReg>
|
|
writeReg(0xFF, 0x01);
|
|
80063de: 2101 movs r1, #1
|
|
80063e0: 20ff movs r0, #255 ; 0xff
|
|
80063e2: f7ff f961 bl 80056a8 <writeReg>
|
|
writeReg(0x00, 0x01);
|
|
80063e6: 2101 movs r1, #1
|
|
80063e8: 2000 movs r0, #0
|
|
80063ea: f7ff f95d bl 80056a8 <writeReg>
|
|
|
|
writeReg(0xFF, 0x00);
|
|
80063ee: 2100 movs r1, #0
|
|
80063f0: 20ff movs r0, #255 ; 0xff
|
|
80063f2: f7ff f959 bl 80056a8 <writeReg>
|
|
writeReg(0x80, 0x00);
|
|
80063f6: 2100 movs r1, #0
|
|
80063f8: 2080 movs r0, #128 ; 0x80
|
|
80063fa: f7ff f955 bl 80056a8 <writeReg>
|
|
|
|
return true;
|
|
80063fe: 2301 movs r3, #1
|
|
}
|
|
8006400: 0018 movs r0, r3
|
|
8006402: 46bd mov sp, r7
|
|
8006404: b004 add sp, #16
|
|
8006406: bdb0 pop {r4, r5, r7, pc}
|
|
8006408: 2000025c .word 0x2000025c
|
|
800640c: 20000258 .word 0x20000258
|
|
|
|
08006410 <getSequenceStepEnables>:
|
|
|
|
// Get sequence step enables
|
|
// based on VL53L0X_GetSequenceStepEnables()
|
|
void getSequenceStepEnables(SequenceStepEnables * enables)
|
|
{
|
|
8006410: b5b0 push {r4, r5, r7, lr}
|
|
8006412: b084 sub sp, #16
|
|
8006414: af00 add r7, sp, #0
|
|
8006416: 6078 str r0, [r7, #4]
|
|
uint8_t sequence_config = readReg(SYSTEM_SEQUENCE_CONFIG);
|
|
8006418: 250f movs r5, #15
|
|
800641a: 197c adds r4, r7, r5
|
|
800641c: 2001 movs r0, #1
|
|
800641e: f7ff f9c9 bl 80057b4 <readReg>
|
|
8006422: 0003 movs r3, r0
|
|
8006424: 7023 strb r3, [r4, #0]
|
|
|
|
enables->tcc = (sequence_config >> 4) & 0x1;
|
|
8006426: 0029 movs r1, r5
|
|
8006428: 187b adds r3, r7, r1
|
|
800642a: 781b ldrb r3, [r3, #0]
|
|
800642c: 091b lsrs r3, r3, #4
|
|
800642e: b2db uxtb r3, r3
|
|
8006430: 2201 movs r2, #1
|
|
8006432: 4013 ands r3, r2
|
|
8006434: b2da uxtb r2, r3
|
|
8006436: 687b ldr r3, [r7, #4]
|
|
8006438: 701a strb r2, [r3, #0]
|
|
enables->dss = (sequence_config >> 3) & 0x1;
|
|
800643a: 187b adds r3, r7, r1
|
|
800643c: 781b ldrb r3, [r3, #0]
|
|
800643e: 08db lsrs r3, r3, #3
|
|
8006440: b2db uxtb r3, r3
|
|
8006442: 2201 movs r2, #1
|
|
8006444: 4013 ands r3, r2
|
|
8006446: b2da uxtb r2, r3
|
|
8006448: 687b ldr r3, [r7, #4]
|
|
800644a: 709a strb r2, [r3, #2]
|
|
enables->msrc = (sequence_config >> 2) & 0x1;
|
|
800644c: 187b adds r3, r7, r1
|
|
800644e: 781b ldrb r3, [r3, #0]
|
|
8006450: 089b lsrs r3, r3, #2
|
|
8006452: b2db uxtb r3, r3
|
|
8006454: 2201 movs r2, #1
|
|
8006456: 4013 ands r3, r2
|
|
8006458: b2da uxtb r2, r3
|
|
800645a: 687b ldr r3, [r7, #4]
|
|
800645c: 705a strb r2, [r3, #1]
|
|
enables->pre_range = (sequence_config >> 6) & 0x1;
|
|
800645e: 187b adds r3, r7, r1
|
|
8006460: 781b ldrb r3, [r3, #0]
|
|
8006462: 099b lsrs r3, r3, #6
|
|
8006464: b2db uxtb r3, r3
|
|
8006466: 2201 movs r2, #1
|
|
8006468: 4013 ands r3, r2
|
|
800646a: b2da uxtb r2, r3
|
|
800646c: 687b ldr r3, [r7, #4]
|
|
800646e: 70da strb r2, [r3, #3]
|
|
enables->final_range = (sequence_config >> 7) & 0x1;
|
|
8006470: 187b adds r3, r7, r1
|
|
8006472: 781b ldrb r3, [r3, #0]
|
|
8006474: 09db lsrs r3, r3, #7
|
|
8006476: b2da uxtb r2, r3
|
|
8006478: 687b ldr r3, [r7, #4]
|
|
800647a: 711a strb r2, [r3, #4]
|
|
}
|
|
800647c: 46c0 nop ; (mov r8, r8)
|
|
800647e: 46bd mov sp, r7
|
|
8006480: b004 add sp, #16
|
|
8006482: bdb0 pop {r4, r5, r7, pc}
|
|
|
|
08006484 <getSequenceStepTimeouts>:
|
|
// Get sequence step timeouts
|
|
// based on get_sequence_step_timeout(),
|
|
// but gets all timeouts instead of just the requested one, and also stores
|
|
// intermediate values
|
|
void getSequenceStepTimeouts(SequenceStepEnables const * enables, SequenceStepTimeouts * timeouts)
|
|
{
|
|
8006484: b580 push {r7, lr}
|
|
8006486: b082 sub sp, #8
|
|
8006488: af00 add r7, sp, #0
|
|
800648a: 6078 str r0, [r7, #4]
|
|
800648c: 6039 str r1, [r7, #0]
|
|
timeouts->pre_range_vcsel_period_pclks = getVcselPulsePeriod(VcselPeriodPreRange);
|
|
800648e: 2000 movs r0, #0
|
|
8006490: f7ff fe1c bl 80060cc <getVcselPulsePeriod>
|
|
8006494: 0003 movs r3, r0
|
|
8006496: b29a uxth r2, r3
|
|
8006498: 683b ldr r3, [r7, #0]
|
|
800649a: 801a strh r2, [r3, #0]
|
|
|
|
timeouts->msrc_dss_tcc_mclks = readReg(MSRC_CONFIG_TIMEOUT_MACROP) + 1;
|
|
800649c: 2046 movs r0, #70 ; 0x46
|
|
800649e: f7ff f989 bl 80057b4 <readReg>
|
|
80064a2: 0003 movs r3, r0
|
|
80064a4: b29b uxth r3, r3
|
|
80064a6: 3301 adds r3, #1
|
|
80064a8: b29a uxth r2, r3
|
|
80064aa: 683b ldr r3, [r7, #0]
|
|
80064ac: 809a strh r2, [r3, #4]
|
|
timeouts->msrc_dss_tcc_us =
|
|
timeoutMclksToMicroseconds(timeouts->msrc_dss_tcc_mclks,
|
|
80064ae: 683b ldr r3, [r7, #0]
|
|
80064b0: 889a ldrh r2, [r3, #4]
|
|
timeouts->pre_range_vcsel_period_pclks);
|
|
80064b2: 683b ldr r3, [r7, #0]
|
|
80064b4: 881b ldrh r3, [r3, #0]
|
|
timeoutMclksToMicroseconds(timeouts->msrc_dss_tcc_mclks,
|
|
80064b6: b2db uxtb r3, r3
|
|
80064b8: 0019 movs r1, r3
|
|
80064ba: 0010 movs r0, r2
|
|
80064bc: f000 f892 bl 80065e4 <timeoutMclksToMicroseconds>
|
|
80064c0: 0002 movs r2, r0
|
|
timeouts->msrc_dss_tcc_us =
|
|
80064c2: 683b ldr r3, [r7, #0]
|
|
80064c4: 60da str r2, [r3, #12]
|
|
|
|
timeouts->pre_range_mclks =
|
|
decodeTimeout(readReg16Bit(PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI));
|
|
80064c6: 2051 movs r0, #81 ; 0x51
|
|
80064c8: f7ff f996 bl 80057f8 <readReg16Bit>
|
|
80064cc: 0003 movs r3, r0
|
|
80064ce: 0018 movs r0, r3
|
|
80064d0: f000 f83e bl 8006550 <decodeTimeout>
|
|
80064d4: 0003 movs r3, r0
|
|
80064d6: 001a movs r2, r3
|
|
timeouts->pre_range_mclks =
|
|
80064d8: 683b ldr r3, [r7, #0]
|
|
80064da: 80da strh r2, [r3, #6]
|
|
timeouts->pre_range_us =
|
|
timeoutMclksToMicroseconds(timeouts->pre_range_mclks,
|
|
80064dc: 683b ldr r3, [r7, #0]
|
|
80064de: 88da ldrh r2, [r3, #6]
|
|
timeouts->pre_range_vcsel_period_pclks);
|
|
80064e0: 683b ldr r3, [r7, #0]
|
|
80064e2: 881b ldrh r3, [r3, #0]
|
|
timeoutMclksToMicroseconds(timeouts->pre_range_mclks,
|
|
80064e4: b2db uxtb r3, r3
|
|
80064e6: 0019 movs r1, r3
|
|
80064e8: 0010 movs r0, r2
|
|
80064ea: f000 f87b bl 80065e4 <timeoutMclksToMicroseconds>
|
|
80064ee: 0002 movs r2, r0
|
|
timeouts->pre_range_us =
|
|
80064f0: 683b ldr r3, [r7, #0]
|
|
80064f2: 611a str r2, [r3, #16]
|
|
|
|
timeouts->final_range_vcsel_period_pclks = getVcselPulsePeriod(VcselPeriodFinalRange);
|
|
80064f4: 2001 movs r0, #1
|
|
80064f6: f7ff fde9 bl 80060cc <getVcselPulsePeriod>
|
|
80064fa: 0003 movs r3, r0
|
|
80064fc: b29a uxth r2, r3
|
|
80064fe: 683b ldr r3, [r7, #0]
|
|
8006500: 805a strh r2, [r3, #2]
|
|
|
|
timeouts->final_range_mclks =
|
|
decodeTimeout(readReg16Bit(FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI));
|
|
8006502: 2071 movs r0, #113 ; 0x71
|
|
8006504: f7ff f978 bl 80057f8 <readReg16Bit>
|
|
8006508: 0003 movs r3, r0
|
|
800650a: 0018 movs r0, r3
|
|
800650c: f000 f820 bl 8006550 <decodeTimeout>
|
|
8006510: 0003 movs r3, r0
|
|
8006512: 001a movs r2, r3
|
|
timeouts->final_range_mclks =
|
|
8006514: 683b ldr r3, [r7, #0]
|
|
8006516: 811a strh r2, [r3, #8]
|
|
|
|
if (enables->pre_range)
|
|
8006518: 687b ldr r3, [r7, #4]
|
|
800651a: 78db ldrb r3, [r3, #3]
|
|
800651c: 2b00 cmp r3, #0
|
|
800651e: d007 beq.n 8006530 <getSequenceStepTimeouts+0xac>
|
|
{
|
|
timeouts->final_range_mclks -= timeouts->pre_range_mclks;
|
|
8006520: 683b ldr r3, [r7, #0]
|
|
8006522: 891a ldrh r2, [r3, #8]
|
|
8006524: 683b ldr r3, [r7, #0]
|
|
8006526: 88db ldrh r3, [r3, #6]
|
|
8006528: 1ad3 subs r3, r2, r3
|
|
800652a: b29a uxth r2, r3
|
|
800652c: 683b ldr r3, [r7, #0]
|
|
800652e: 811a strh r2, [r3, #8]
|
|
}
|
|
|
|
timeouts->final_range_us =
|
|
timeoutMclksToMicroseconds(timeouts->final_range_mclks,
|
|
8006530: 683b ldr r3, [r7, #0]
|
|
8006532: 891a ldrh r2, [r3, #8]
|
|
timeouts->final_range_vcsel_period_pclks);
|
|
8006534: 683b ldr r3, [r7, #0]
|
|
8006536: 885b ldrh r3, [r3, #2]
|
|
timeoutMclksToMicroseconds(timeouts->final_range_mclks,
|
|
8006538: b2db uxtb r3, r3
|
|
800653a: 0019 movs r1, r3
|
|
800653c: 0010 movs r0, r2
|
|
800653e: f000 f851 bl 80065e4 <timeoutMclksToMicroseconds>
|
|
8006542: 0002 movs r2, r0
|
|
timeouts->final_range_us =
|
|
8006544: 683b ldr r3, [r7, #0]
|
|
8006546: 615a str r2, [r3, #20]
|
|
}
|
|
8006548: 46c0 nop ; (mov r8, r8)
|
|
800654a: 46bd mov sp, r7
|
|
800654c: b002 add sp, #8
|
|
800654e: bd80 pop {r7, pc}
|
|
|
|
08006550 <decodeTimeout>:
|
|
// Decode sequence step timeout in MCLKs from register value
|
|
// based on VL53L0X_decode_timeout()
|
|
// Note: the original function returned a uint32_t, but the return value is
|
|
// always stored in a uint16_t.
|
|
uint16_t decodeTimeout(uint16_t reg_val)
|
|
{
|
|
8006550: b580 push {r7, lr}
|
|
8006552: b082 sub sp, #8
|
|
8006554: af00 add r7, sp, #0
|
|
8006556: 0002 movs r2, r0
|
|
8006558: 1dbb adds r3, r7, #6
|
|
800655a: 801a strh r2, [r3, #0]
|
|
// format: "(LSByte * 2^MSByte) + 1"
|
|
return (uint16_t)((reg_val & 0x00FF) <<
|
|
800655c: 1dbb adds r3, r7, #6
|
|
800655e: 881b ldrh r3, [r3, #0]
|
|
8006560: 22ff movs r2, #255 ; 0xff
|
|
8006562: 4013 ands r3, r2
|
|
(uint16_t)((reg_val & 0xFF00) >> 8)) + 1;
|
|
8006564: 1dba adds r2, r7, #6
|
|
8006566: 8812 ldrh r2, [r2, #0]
|
|
8006568: 0a12 lsrs r2, r2, #8
|
|
800656a: b292 uxth r2, r2
|
|
return (uint16_t)((reg_val & 0x00FF) <<
|
|
800656c: 4093 lsls r3, r2
|
|
800656e: b29b uxth r3, r3
|
|
(uint16_t)((reg_val & 0xFF00) >> 8)) + 1;
|
|
8006570: 3301 adds r3, #1
|
|
8006572: b29b uxth r3, r3
|
|
}
|
|
8006574: 0018 movs r0, r3
|
|
8006576: 46bd mov sp, r7
|
|
8006578: b002 add sp, #8
|
|
800657a: bd80 pop {r7, pc}
|
|
|
|
0800657c <encodeTimeout>:
|
|
// Encode sequence step timeout register value from timeout in MCLKs
|
|
// based on VL53L0X_encode_timeout()
|
|
// Note: the original function took a uint16_t, but the argument passed to it
|
|
// is always a uint16_t.
|
|
uint16_t encodeTimeout(uint16_t timeout_mclks)
|
|
{
|
|
800657c: b580 push {r7, lr}
|
|
800657e: b084 sub sp, #16
|
|
8006580: af00 add r7, sp, #0
|
|
8006582: 0002 movs r2, r0
|
|
8006584: 1dbb adds r3, r7, #6
|
|
8006586: 801a strh r2, [r3, #0]
|
|
// format: "(LSByte * 2^MSByte) + 1"
|
|
|
|
uint32_t ls_byte = 0;
|
|
8006588: 2300 movs r3, #0
|
|
800658a: 60fb str r3, [r7, #12]
|
|
uint16_t ms_byte = 0;
|
|
800658c: 230a movs r3, #10
|
|
800658e: 18fb adds r3, r7, r3
|
|
8006590: 2200 movs r2, #0
|
|
8006592: 801a strh r2, [r3, #0]
|
|
|
|
if (timeout_mclks > 0)
|
|
8006594: 1dbb adds r3, r7, #6
|
|
8006596: 881b ldrh r3, [r3, #0]
|
|
8006598: 2b00 cmp r3, #0
|
|
800659a: d01e beq.n 80065da <encodeTimeout+0x5e>
|
|
{
|
|
ls_byte = timeout_mclks - 1;
|
|
800659c: 1dbb adds r3, r7, #6
|
|
800659e: 881b ldrh r3, [r3, #0]
|
|
80065a0: 3b01 subs r3, #1
|
|
80065a2: 60fb str r3, [r7, #12]
|
|
|
|
while ((ls_byte & 0xFFFFFF00) > 0)
|
|
80065a4: e008 b.n 80065b8 <encodeTimeout+0x3c>
|
|
{
|
|
ls_byte >>= 1;
|
|
80065a6: 68fb ldr r3, [r7, #12]
|
|
80065a8: 085b lsrs r3, r3, #1
|
|
80065aa: 60fb str r3, [r7, #12]
|
|
ms_byte++;
|
|
80065ac: 210a movs r1, #10
|
|
80065ae: 187b adds r3, r7, r1
|
|
80065b0: 881a ldrh r2, [r3, #0]
|
|
80065b2: 187b adds r3, r7, r1
|
|
80065b4: 3201 adds r2, #1
|
|
80065b6: 801a strh r2, [r3, #0]
|
|
while ((ls_byte & 0xFFFFFF00) > 0)
|
|
80065b8: 68fb ldr r3, [r7, #12]
|
|
80065ba: 22ff movs r2, #255 ; 0xff
|
|
80065bc: 4393 bics r3, r2
|
|
80065be: d1f2 bne.n 80065a6 <encodeTimeout+0x2a>
|
|
}
|
|
|
|
return (ms_byte << 8) | (ls_byte & 0xFF);
|
|
80065c0: 230a movs r3, #10
|
|
80065c2: 18fb adds r3, r7, r3
|
|
80065c4: 881b ldrh r3, [r3, #0]
|
|
80065c6: 021b lsls r3, r3, #8
|
|
80065c8: b29a uxth r2, r3
|
|
80065ca: 68fb ldr r3, [r7, #12]
|
|
80065cc: b29b uxth r3, r3
|
|
80065ce: 21ff movs r1, #255 ; 0xff
|
|
80065d0: 400b ands r3, r1
|
|
80065d2: b29b uxth r3, r3
|
|
80065d4: 4313 orrs r3, r2
|
|
80065d6: b29b uxth r3, r3
|
|
80065d8: e000 b.n 80065dc <encodeTimeout+0x60>
|
|
}
|
|
else { return 0; }
|
|
80065da: 2300 movs r3, #0
|
|
}
|
|
80065dc: 0018 movs r0, r3
|
|
80065de: 46bd mov sp, r7
|
|
80065e0: b004 add sp, #16
|
|
80065e2: bd80 pop {r7, pc}
|
|
|
|
080065e4 <timeoutMclksToMicroseconds>:
|
|
|
|
// Convert sequence step timeout from MCLKs to microseconds with given VCSEL period in PCLKs
|
|
// based on VL53L0X_calc_timeout_us()
|
|
uint32_t timeoutMclksToMicroseconds(uint16_t timeout_period_mclks, uint8_t vcsel_period_pclks)
|
|
{
|
|
80065e4: b580 push {r7, lr}
|
|
80065e6: b084 sub sp, #16
|
|
80065e8: af00 add r7, sp, #0
|
|
80065ea: 0002 movs r2, r0
|
|
80065ec: 1dbb adds r3, r7, #6
|
|
80065ee: 801a strh r2, [r3, #0]
|
|
80065f0: 1d7b adds r3, r7, #5
|
|
80065f2: 1c0a adds r2, r1, #0
|
|
80065f4: 701a strb r2, [r3, #0]
|
|
uint32_t macro_period_ns = calcMacroPeriod(vcsel_period_pclks);
|
|
80065f6: 1d7b adds r3, r7, #5
|
|
80065f8: 781a ldrb r2, [r3, #0]
|
|
80065fa: 0013 movs r3, r2
|
|
80065fc: 015b lsls r3, r3, #5
|
|
80065fe: 1a9b subs r3, r3, r2
|
|
8006600: 015b lsls r3, r3, #5
|
|
8006602: 189b adds r3, r3, r2
|
|
8006604: 011a lsls r2, r3, #4
|
|
8006606: 1ad2 subs r2, r2, r3
|
|
8006608: 0213 lsls r3, r2, #8
|
|
800660a: 001a movs r2, r3
|
|
800660c: 0013 movs r3, r2
|
|
800660e: 33f5 adds r3, #245 ; 0xf5
|
|
8006610: 33ff adds r3, #255 ; 0xff
|
|
8006612: 22fa movs r2, #250 ; 0xfa
|
|
8006614: 0091 lsls r1, r2, #2
|
|
8006616: 0018 movs r0, r3
|
|
8006618: f7f9 fd76 bl 8000108 <__udivsi3>
|
|
800661c: 0003 movs r3, r0
|
|
800661e: 60fb str r3, [r7, #12]
|
|
|
|
return ((timeout_period_mclks * macro_period_ns) + (macro_period_ns / 2)) / 1000;
|
|
8006620: 1dbb adds r3, r7, #6
|
|
8006622: 881b ldrh r3, [r3, #0]
|
|
8006624: 68fa ldr r2, [r7, #12]
|
|
8006626: 435a muls r2, r3
|
|
8006628: 68fb ldr r3, [r7, #12]
|
|
800662a: 085b lsrs r3, r3, #1
|
|
800662c: 18d3 adds r3, r2, r3
|
|
800662e: 22fa movs r2, #250 ; 0xfa
|
|
8006630: 0091 lsls r1, r2, #2
|
|
8006632: 0018 movs r0, r3
|
|
8006634: f7f9 fd68 bl 8000108 <__udivsi3>
|
|
8006638: 0003 movs r3, r0
|
|
}
|
|
800663a: 0018 movs r0, r3
|
|
800663c: 46bd mov sp, r7
|
|
800663e: b004 add sp, #16
|
|
8006640: bd80 pop {r7, pc}
|
|
|
|
08006642 <timeoutMicrosecondsToMclks>:
|
|
|
|
// Convert sequence step timeout from microseconds to MCLKs with given VCSEL period in PCLKs
|
|
// based on VL53L0X_calc_timeout_mclks()
|
|
uint32_t timeoutMicrosecondsToMclks(uint32_t timeout_period_us, uint8_t vcsel_period_pclks)
|
|
{
|
|
8006642: b580 push {r7, lr}
|
|
8006644: b084 sub sp, #16
|
|
8006646: af00 add r7, sp, #0
|
|
8006648: 6078 str r0, [r7, #4]
|
|
800664a: 000a movs r2, r1
|
|
800664c: 1cfb adds r3, r7, #3
|
|
800664e: 701a strb r2, [r3, #0]
|
|
uint32_t macro_period_ns = calcMacroPeriod(vcsel_period_pclks);
|
|
8006650: 1cfb adds r3, r7, #3
|
|
8006652: 781a ldrb r2, [r3, #0]
|
|
8006654: 0013 movs r3, r2
|
|
8006656: 015b lsls r3, r3, #5
|
|
8006658: 1a9b subs r3, r3, r2
|
|
800665a: 015b lsls r3, r3, #5
|
|
800665c: 189b adds r3, r3, r2
|
|
800665e: 011a lsls r2, r3, #4
|
|
8006660: 1ad2 subs r2, r2, r3
|
|
8006662: 0213 lsls r3, r2, #8
|
|
8006664: 001a movs r2, r3
|
|
8006666: 0013 movs r3, r2
|
|
8006668: 33f5 adds r3, #245 ; 0xf5
|
|
800666a: 33ff adds r3, #255 ; 0xff
|
|
800666c: 22fa movs r2, #250 ; 0xfa
|
|
800666e: 0091 lsls r1, r2, #2
|
|
8006670: 0018 movs r0, r3
|
|
8006672: f7f9 fd49 bl 8000108 <__udivsi3>
|
|
8006676: 0003 movs r3, r0
|
|
8006678: 60fb str r3, [r7, #12]
|
|
|
|
return (((timeout_period_us * 1000) + (macro_period_ns / 2)) / macro_period_ns);
|
|
800667a: 687a ldr r2, [r7, #4]
|
|
800667c: 0013 movs r3, r2
|
|
800667e: 015b lsls r3, r3, #5
|
|
8006680: 1a9b subs r3, r3, r2
|
|
8006682: 009b lsls r3, r3, #2
|
|
8006684: 189b adds r3, r3, r2
|
|
8006686: 00db lsls r3, r3, #3
|
|
8006688: 001a movs r2, r3
|
|
800668a: 68fb ldr r3, [r7, #12]
|
|
800668c: 085b lsrs r3, r3, #1
|
|
800668e: 18d3 adds r3, r2, r3
|
|
8006690: 68f9 ldr r1, [r7, #12]
|
|
8006692: 0018 movs r0, r3
|
|
8006694: f7f9 fd38 bl 8000108 <__udivsi3>
|
|
8006698: 0003 movs r3, r0
|
|
}
|
|
800669a: 0018 movs r0, r3
|
|
800669c: 46bd mov sp, r7
|
|
800669e: b004 add sp, #16
|
|
80066a0: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080066a4 <performSingleRefCalibration>:
|
|
|
|
|
|
// based on VL53L0X_perform_single_ref_calibration()
|
|
bool performSingleRefCalibration(uint8_t vhv_init_byte)
|
|
{
|
|
80066a4: b580 push {r7, lr}
|
|
80066a6: b082 sub sp, #8
|
|
80066a8: af00 add r7, sp, #0
|
|
80066aa: 0002 movs r2, r0
|
|
80066ac: 1dfb adds r3, r7, #7
|
|
80066ae: 701a strb r2, [r3, #0]
|
|
writeReg(SYSRANGE_START, 0x01 | vhv_init_byte); // VL53L0X_REG_SYSRANGE_MODE_START_STOP
|
|
80066b0: 1dfb adds r3, r7, #7
|
|
80066b2: 781b ldrb r3, [r3, #0]
|
|
80066b4: 2201 movs r2, #1
|
|
80066b6: 4313 orrs r3, r2
|
|
80066b8: b2db uxtb r3, r3
|
|
80066ba: 0019 movs r1, r3
|
|
80066bc: 2000 movs r0, #0
|
|
80066be: f7fe fff3 bl 80056a8 <writeReg>
|
|
|
|
startTimeout();
|
|
80066c2: f7fb fb53 bl 8001d6c <HAL_GetTick>
|
|
80066c6: 0003 movs r3, r0
|
|
80066c8: b29a uxth r2, r3
|
|
80066ca: 4b15 ldr r3, [pc, #84] ; (8006720 <performSingleRefCalibration+0x7c>)
|
|
80066cc: 801a strh r2, [r3, #0]
|
|
while ((readReg(RESULT_INTERRUPT_STATUS) & 0x07) == 0)
|
|
80066ce: e011 b.n 80066f4 <performSingleRefCalibration+0x50>
|
|
{
|
|
if (checkTimeoutExpired()) { return false; }
|
|
80066d0: 4b14 ldr r3, [pc, #80] ; (8006724 <performSingleRefCalibration+0x80>)
|
|
80066d2: 881b ldrh r3, [r3, #0]
|
|
80066d4: 2b00 cmp r3, #0
|
|
80066d6: d00d beq.n 80066f4 <performSingleRefCalibration+0x50>
|
|
80066d8: f7fb fb48 bl 8001d6c <HAL_GetTick>
|
|
80066dc: 0003 movs r3, r0
|
|
80066de: b29b uxth r3, r3
|
|
80066e0: 001a movs r2, r3
|
|
80066e2: 4b0f ldr r3, [pc, #60] ; (8006720 <performSingleRefCalibration+0x7c>)
|
|
80066e4: 881b ldrh r3, [r3, #0]
|
|
80066e6: 1ad3 subs r3, r2, r3
|
|
80066e8: 4a0e ldr r2, [pc, #56] ; (8006724 <performSingleRefCalibration+0x80>)
|
|
80066ea: 8812 ldrh r2, [r2, #0]
|
|
80066ec: 4293 cmp r3, r2
|
|
80066ee: dd01 ble.n 80066f4 <performSingleRefCalibration+0x50>
|
|
80066f0: 2300 movs r3, #0
|
|
80066f2: e010 b.n 8006716 <performSingleRefCalibration+0x72>
|
|
while ((readReg(RESULT_INTERRUPT_STATUS) & 0x07) == 0)
|
|
80066f4: 2013 movs r0, #19
|
|
80066f6: f7ff f85d bl 80057b4 <readReg>
|
|
80066fa: 0003 movs r3, r0
|
|
80066fc: 001a movs r2, r3
|
|
80066fe: 2307 movs r3, #7
|
|
8006700: 4013 ands r3, r2
|
|
8006702: d0e5 beq.n 80066d0 <performSingleRefCalibration+0x2c>
|
|
}
|
|
|
|
writeReg(SYSTEM_INTERRUPT_CLEAR, 0x01);
|
|
8006704: 2101 movs r1, #1
|
|
8006706: 200b movs r0, #11
|
|
8006708: f7fe ffce bl 80056a8 <writeReg>
|
|
|
|
writeReg(SYSRANGE_START, 0x00);
|
|
800670c: 2100 movs r1, #0
|
|
800670e: 2000 movs r0, #0
|
|
8006710: f7fe ffca bl 80056a8 <writeReg>
|
|
|
|
return true;
|
|
8006714: 2301 movs r3, #1
|
|
}
|
|
8006716: 0018 movs r0, r3
|
|
8006718: 46bd mov sp, r7
|
|
800671a: b002 add sp, #8
|
|
800671c: bd80 pop {r7, pc}
|
|
800671e: 46c0 nop ; (mov r8, r8)
|
|
8006720: 2000025c .word 0x2000025c
|
|
8006724: 20000258 .word 0x20000258
|
|
|
|
08006728 <__libc_init_array>:
|
|
8006728: b570 push {r4, r5, r6, lr}
|
|
800672a: 2600 movs r6, #0
|
|
800672c: 4d0c ldr r5, [pc, #48] ; (8006760 <__libc_init_array+0x38>)
|
|
800672e: 4c0d ldr r4, [pc, #52] ; (8006764 <__libc_init_array+0x3c>)
|
|
8006730: 1b64 subs r4, r4, r5
|
|
8006732: 10a4 asrs r4, r4, #2
|
|
8006734: 42a6 cmp r6, r4
|
|
8006736: d109 bne.n 800674c <__libc_init_array+0x24>
|
|
8006738: 2600 movs r6, #0
|
|
800673a: f000 f821 bl 8006780 <_init>
|
|
800673e: 4d0a ldr r5, [pc, #40] ; (8006768 <__libc_init_array+0x40>)
|
|
8006740: 4c0a ldr r4, [pc, #40] ; (800676c <__libc_init_array+0x44>)
|
|
8006742: 1b64 subs r4, r4, r5
|
|
8006744: 10a4 asrs r4, r4, #2
|
|
8006746: 42a6 cmp r6, r4
|
|
8006748: d105 bne.n 8006756 <__libc_init_array+0x2e>
|
|
800674a: bd70 pop {r4, r5, r6, pc}
|
|
800674c: 00b3 lsls r3, r6, #2
|
|
800674e: 58eb ldr r3, [r5, r3]
|
|
8006750: 4798 blx r3
|
|
8006752: 3601 adds r6, #1
|
|
8006754: e7ee b.n 8006734 <__libc_init_array+0xc>
|
|
8006756: 00b3 lsls r3, r6, #2
|
|
8006758: 58eb ldr r3, [r5, r3]
|
|
800675a: 4798 blx r3
|
|
800675c: 3601 adds r6, #1
|
|
800675e: e7f2 b.n 8006746 <__libc_init_array+0x1e>
|
|
8006760: 0800687c .word 0x0800687c
|
|
8006764: 0800687c .word 0x0800687c
|
|
8006768: 0800687c .word 0x0800687c
|
|
800676c: 08006880 .word 0x08006880
|
|
|
|
08006770 <memset>:
|
|
8006770: 0003 movs r3, r0
|
|
8006772: 1882 adds r2, r0, r2
|
|
8006774: 4293 cmp r3, r2
|
|
8006776: d100 bne.n 800677a <memset+0xa>
|
|
8006778: 4770 bx lr
|
|
800677a: 7019 strb r1, [r3, #0]
|
|
800677c: 3301 adds r3, #1
|
|
800677e: e7f9 b.n 8006774 <memset+0x4>
|
|
|
|
08006780 <_init>:
|
|
8006780: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8006782: 46c0 nop ; (mov r8, r8)
|
|
8006784: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8006786: bc08 pop {r3}
|
|
8006788: 469e mov lr, r3
|
|
800678a: 4770 bx lr
|
|
|
|
0800678c <_fini>:
|
|
800678c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800678e: 46c0 nop ; (mov r8, r8)
|
|
8006790: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8006792: bc08 pop {r3}
|
|
8006794: 469e mov lr, r3
|
|
8006796: 4770 bx lr
|
|
|
|
08006798 <__FLASH_Program_Fast_veneer>:
|
|
8006798: b401 push {r0}
|
|
800679a: 4802 ldr r0, [pc, #8] ; (80067a4 <__FLASH_Program_Fast_veneer+0xc>)
|
|
800679c: 4684 mov ip, r0
|
|
800679e: bc01 pop {r0}
|
|
80067a0: 4760 bx ip
|
|
80067a2: bf00 nop
|
|
80067a4: 20000011 .word 0x20000011
|
|
|
|
Disassembly of section .data:
|
|
|
|
20000000 <needConfig>:
|
|
20000000: .
|
|
|
|
20000001 <dLevel>:
|
|
20000001: ...
|
|
|
|
20000004 <SystemCoreClock>:
|
|
20000004: 00f42400 .$..
|
|
|
|
20000008 <uwTickPrio>:
|
|
20000008: 00000004 ....
|
|
|
|
2000000c <uwTickFreq>:
|
|
2000000c: .
|
|
|
|
2000000d <g_i2cAddr>:
|
|
2000000d: R..
|
|
|
|
20000010 <FLASH_Program_Fast>:
|
|
* @param Address Specifies the address to be programmed.
|
|
* @param DataAddress Specifies the address where the data are stored.
|
|
* @retval None
|
|
*/
|
|
static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
|
|
{
|
|
20000010: b580 push {r7, lr}
|
|
20000012: b088 sub sp, #32
|
|
20000014: af00 add r7, sp, #0
|
|
20000016: 6078 str r0, [r7, #4]
|
|
20000018: 6039 str r1, [r7, #0]
|
|
uint8_t index = 0;
|
|
2000001a: 231f movs r3, #31
|
|
2000001c: 18fb adds r3, r7, r3
|
|
2000001e: 2200 movs r2, #0
|
|
20000020: 701a strb r2, [r3, #0]
|
|
uint32_t dest = Address;
|
|
20000022: 687b ldr r3, [r7, #4]
|
|
20000024: 61bb str r3, [r7, #24]
|
|
uint32_t src = DataAddress;
|
|
20000026: 683b ldr r3, [r7, #0]
|
|
20000028: 617b str r3, [r7, #20]
|
|
uint32_t primask_bit;
|
|
|
|
/* Set FSTPG bit */
|
|
SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
|
|
2000002a: 4b1a ldr r3, [pc, #104] ; (20000094 <FLASH_Program_Fast+0x84>)
|
|
2000002c: 695a ldr r2, [r3, #20]
|
|
2000002e: 4b19 ldr r3, [pc, #100] ; (20000094 <FLASH_Program_Fast+0x84>)
|
|
20000030: 2180 movs r1, #128 ; 0x80
|
|
20000032: 02c9 lsls r1, r1, #11
|
|
20000034: 430a orrs r2, r1
|
|
20000036: 615a str r2, [r3, #20]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
20000038: f3ef 8310 mrs r3, PRIMASK
|
|
2000003c: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
2000003e: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Enter critical section: row programming should not be longer than 7 ms */
|
|
primask_bit = __get_PRIMASK();
|
|
20000040: 613b str r3, [r7, #16]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
20000042: b672 cpsid i
|
|
}
|
|
20000044: 46c0 nop ; (mov r8, r8)
|
|
__disable_irq();
|
|
|
|
/* Fast Program : 64 words */
|
|
while (index < 64U)
|
|
20000046: e00f b.n 20000068 <FLASH_Program_Fast+0x58>
|
|
{
|
|
*(uint32_t *)dest = *(uint32_t *)src;
|
|
20000048: 697a ldr r2, [r7, #20]
|
|
2000004a: 69bb ldr r3, [r7, #24]
|
|
2000004c: 6812 ldr r2, [r2, #0]
|
|
2000004e: 601a str r2, [r3, #0]
|
|
src += 4U;
|
|
20000050: 697b ldr r3, [r7, #20]
|
|
20000052: 3304 adds r3, #4
|
|
20000054: 617b str r3, [r7, #20]
|
|
dest += 4U;
|
|
20000056: 69bb ldr r3, [r7, #24]
|
|
20000058: 3304 adds r3, #4
|
|
2000005a: 61bb str r3, [r7, #24]
|
|
index++;
|
|
2000005c: 211f movs r1, #31
|
|
2000005e: 187b adds r3, r7, r1
|
|
20000060: 781a ldrb r2, [r3, #0]
|
|
20000062: 187b adds r3, r7, r1
|
|
20000064: 3201 adds r2, #1
|
|
20000066: 701a strb r2, [r3, #0]
|
|
while (index < 64U)
|
|
20000068: 231f movs r3, #31
|
|
2000006a: 18fb adds r3, r7, r3
|
|
2000006c: 781b ldrb r3, [r3, #0]
|
|
2000006e: 2b3f cmp r3, #63 ; 0x3f
|
|
20000070: d9ea bls.n 20000048 <FLASH_Program_Fast+0x38>
|
|
be anyway done later */
|
|
|
|
#if defined(FLASH_DBANK_SUPPORT)
|
|
while ((FLASH->SR & (FLASH_SR_BSY1 | FLASH_SR_BSY2)) != 0x00U)
|
|
#else
|
|
while ((FLASH->SR & FLASH_SR_BSY1) != 0x00U)
|
|
20000072: 46c0 nop ; (mov r8, r8)
|
|
20000074: 4b07 ldr r3, [pc, #28] ; (20000094 <FLASH_Program_Fast+0x84>)
|
|
20000076: 691a ldr r2, [r3, #16]
|
|
20000078: 2380 movs r3, #128 ; 0x80
|
|
2000007a: 025b lsls r3, r3, #9
|
|
2000007c: 4013 ands r3, r2
|
|
2000007e: d1f9 bne.n 20000074 <FLASH_Program_Fast+0x64>
|
|
20000080: 693b ldr r3, [r7, #16]
|
|
20000082: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
20000084: 68bb ldr r3, [r7, #8]
|
|
20000086: f383 8810 msr PRIMASK, r3
|
|
}
|
|
2000008a: 46c0 nop ; (mov r8, r8)
|
|
{
|
|
}
|
|
|
|
/* Exit critical section: restore previous priority mask */
|
|
__set_PRIMASK(primask_bit);
|
|
}
|
|
2000008c: 46c0 nop ; (mov r8, r8)
|
|
2000008e: 46bd mov sp, r7
|
|
20000090: b008 add sp, #32
|
|
20000092: bd80 pop {r7, pc}
|
|
20000094: 40022000 .word 0x40022000
|