From 03e8a184a2a405e134b892cf5260de36935cb948 Mon Sep 17 00:00:00 2001 From: wagiminator Date: Sun, 11 Sep 2022 11:42:08 +0200 Subject: [PATCH] Initial commit --- LICENSE | 3 + README.md | 95 +- documentation/USB_PD_Adapter_hardware.png | Bin 0 -> 912564 bytes documentation/USB_PD_Adapter_operation.png | Bin 0 -> 420735 bytes documentation/USB_PD_Adapter_pic1.jpg | Bin 0 -> 101006 bytes documentation/USB_PD_Adapter_pic2.jpg | Bin 0 -> 114036 bytes documentation/USB_PD_Adapter_pic3.jpg | Bin 0 -> 147913 bytes documentation/USB_PD_Adapter_pic4.jpg | Bin 0 -> 129649 bytes documentation/USB_PD_Adapter_wiring.png | Bin 0 -> 164426 bytes hardware/USB_PD_Adapter_BOM.tsv | Bin 0 -> 2912 bytes hardware/USB_PD_Adapter_gerber.zip | Bin 0 -> 55327 bytes hardware/USB_PD_Adapter_schematic.pdf | 6141 ++++++ software/USB_PD_Adapter.ino | 526 + software/makefile | 109 + software/tools/avr-gcc/download.txt | 4 + software/tools/avrdude/avrdude.conf | 16284 ++++++++++++++++ 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licensed under the Creative Commons Attribution-ShareAlike 3.0 Unported License. +To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/3.0/ or send +a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA. diff --git a/README.md b/README.md index 19a2438..7323f0e 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,93 @@ -# ATtiny814-USB-PD-Adapter -USB Type-C Power Delivery Trigger and Monitoring Board +# USB PD Adapter based on ATtiny814 or compatible +The USB PD Adapter is a USB Power Delivery trigger and monitoring board, with which you can use almost any USB Type-C PD power supply to power your projects with different selectable voltages and high currents. Important values such as voltage, current, power and energy are displayed on the OLED. The USB PD Adapter is based on the cheap and easy-to-use CH224K multi fast charging protocol power receiving chip, the INA219 voltage and current sensor IC, and an ATtiny204, 214, 404, 414, 804, 814, 1604 or 1614 microcontroller. + +- Design Files (EasyEDA): + +![pic1.jpg](https://raw.githubusercontent.com/wagiminator/ATtiny814-USB-PD-Adapter/master/documentation/USB_PD_Adapter_pic1.jpg) + +# Hardware +## Schematic +![wiring.png](https://raw.githubusercontent.com/wagiminator/ATtiny814-USB-PD-Adapter/master/documentation/USB_PD_Adapter_wiring.png) + +## 78L33 Voltage Regulator +The 78L33 is a simple and inexpensive voltage regulator that can convert input voltages up to 30V to an output voltage of 3.3V with an output current of up to 200mA and a dropout voltage of 1.7V. The 78L33 supplies all elements of the circuit with 3.3V. + +## CH224K USB PD Power Receiving Chip +The CH224K is a USB PD power receiving protocol chip, which integrates PD3.0/2.0, BC1.2 and other fast charging protocols, automatically detects VCONN and analog E-Mark chips, supports up to 100W power, and has built-in PD communication module. It also integrates output voltage detection internally to support overheating and overvoltage protection. It features: + +- 4V to 22V input voltage +- PD3.0/2.0, BC1.2 and other fast charging protocols +- USB Type-C PD, positive and negative insertion detection and automatic switching +- E-Mark simulation, automatically detects VCONN, supports 100W power PD request +- requested voltage can be dynamically adjusted through a variety of methods +- high integration of single chip, simplified peripheral and low cost +- built-in over-voltage and over-temperature protection module + +The output voltage is selected via three configuration pins of the CH224K, which are connected directly to the ATtiny and is set according to the following table: + +|Output Voltage|CFG1|CFG2|CFG3| +|-|-|-|-| +|5V|1|-|-| +|9V|0|0|0| +|12V|0|0|1| +|15V|0|1|1| +|20V|0|1|0| + +The CH224K's PG pin is open-drain, pulling the input to ground when the requested voltage has been successfully negotiated with the USB PD power supply. It can be used to drive an indicator LED or a high-side P-channel MOSFET for power path control. Here this pin is connected directly to the ATtiny, which can query the status with the help of an internal pull-up resistor. + +## INA219 Current/Power Monitor +The INA219 is a current shunt and power monitor with an I²C-compatible interface. The device monitors both shunt voltage drop and bus supply voltage, with programmable conversion times and filtering. A programmable calibration value, combined with an internal multiplier, enables direct readouts of current in amperes. The selected shunt resistance of 10mΩ enables both a very small influence on the circuit and a measurement with a resolution of 1mA. For an accurate measurement, a shunt resistor with a low tolerance (1% or better) should be selected. The INA219 is used here to measure the output voltage and output current. It communicates with the ATtiny via I²C. + +## ATtiny Microcontroller +The ATtiny microcontroller handles the user interface, the control of the CH224K and INA219, and the calculation and display of the measured values. The user interface utilizes two buttons and an [SSD1306 128x64 pixels OLED display](http://aliexpress.com/wholesale?SearchText=128+64+0.96+oled+new+4pin). In this application, the ATtiny runs at only 1MHz to keep power consumption low and thus avoid overheating of the 78L33 voltage regulator, especially at 20V output voltage. + +The following microcontrollers can be used: ATtiny204, 214, 404, 414, 804, 814, 1604 or 1614. However, since the firmware in the current version already requires almost 2KB of SRAM (depending on the compiler settings), the use of an ATtiny202 or ATtiny212 is not recommended, since there are hardly any reserves left for future upgrades. + +![hardware.png](https://raw.githubusercontent.com/wagiminator/ATtiny814-USB-PD-Adapter/master/documentation/USB_PD_Adapter_hardware.png) + +# Compiling and Uploading the Firmware +## If using the Arduino IDE +- Open your Arduino IDE. +- Make sure you have installed [megaTinyCore](https://github.com/SpenceKonde/megaTinyCore). +- Go to **Tools -> Board -> megaTinyCore** and select **ATtiny1614/1604/814/804/414/404/214/204**. +- Go to **Tools** and choose the following board options: + - **Chip:** choose the chip you have installed + - **Clock:** 1 MHz internal + - Leave the rest at the default settings. +- Connect your programmer to your PC and to the UPDI header on the board. +- Go to **Tools -> Programmer** and select your UPDI programmer. +- Go to **Tools -> Burn Bootloader** to burn the fuses. +- Open the sketch and click **Upload**. + +## If using the makefile (Linux/Mac) +- Connect your [programmer](https://github.com/wagiminator/AVR-Programmer) (jtag2updi or SerialUPDI) to your PC and to the UPDI header on the board. +- Download [AVR 8-bit Toolchain](https://www.microchip.com/mplab/avr-support/avr-and-arm-toolchains-c-compilers) and extract the sub-folders (avr, bin, include, ...) to /software/tools/avr-gcc. To do this, you have to register for free with Microchip on the download site. +- Open a terminal. +- Navigate to the folder with the makefile and the sketch. +- Run `DEVICE=attiny814 PROGRMR=serialupdi PORT=/dev/ttyUSB0 make install` to compile, burn the fuses and upload the firmware (change DEVICE, PROGRMR and PORT accordingly). + +# Operating Instructions +1. Connect the USB PD Adapter to a USB Type-C PD power supply using a USB-C cable. +2. Use the SET button to select the desired output voltage. An hourglass appears on the display while the device is communicating with the power supply. If the negotiation was successful, a tick is displayed and the desired voltage is present at the output. +3. Connect the device to the power consumer via the output screw terminal. +4. Use the RESET button to clear the energy counter. + +![operation.png](https://raw.githubusercontent.com/wagiminator/ATtiny814-USB-PD-Adapter/master/documentation/USB_PD_Adapter_operation.png) + +# References, Links and Notes +1. [78L33 Datasheet](https://datasheet.lcsc.com/lcsc/2204181745_Shikues-78L33_C2999140.pdf) +2. [CH224K Datasheet](https://datasheet.lcsc.com/lcsc/2204251615_WCH-Jiangsu-Qin-Heng-CH224K_C970725.pdf) +3. [INA219 Datasheet](https://www.ti.com/lit/ds/symlink/ina219.pdf?ts=1662832146107) +4. [ATtiny814 Datasheet](https://ww1.microchip.com/downloads/aemDocuments/documents/MCU08/ProductDocuments/DataSheets/ATtiny417-814-816-817-DataSheet-DS40002288A.pdf) +5. [SSD1306 Datasheet](https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf) +6. [CH224K USB PD Decoy](https://github.com/wagiminator/Power-Boards/tree/master/USB-PD_Decoy_CH224K) +7. [TI Primer on USB PD](https://www.ti.com/lit/wp/slyy109b/slyy109b.pdf) + +![pic2.jpg](https://raw.githubusercontent.com/wagiminator/ATtiny814-USB-PD-Adapter/master/documentation/USB_PD_Adapter_pic2.jpg) +![pic3.jpg](https://raw.githubusercontent.com/wagiminator/ATtiny814-USB-PD-Adapter/master/documentation/USB_PD_Adapter_pic3.jpg) + +# License +![license.png](https://i.creativecommons.org/l/by-sa/3.0/88x31.png) + +This work is licensed under Creative Commons Attribution-ShareAlike 3.0 Unported License. +(http://creativecommons.org/licenses/by-sa/3.0/) diff --git a/documentation/USB_PD_Adapter_hardware.png b/documentation/USB_PD_Adapter_hardware.png new file mode 100644 index 0000000000000000000000000000000000000000..cd5292c038ee47132dc2dc547bda1b4e43fda487 GIT binary patch literal 912564 zcmdSBhd-A6|2}RfBzt8<$ezi}%F5m$*@TG5-YYAS6=g;C-g}3Pj6$->ifq~A_dM^< z_wyTn!tecf^uF&~m+Lyu^Yt9Z^Ei&@6|Sx-e*=dK2L%P?#v=t8O%xQ2G87cFVQeh; zi9cp|Df|P&S^AMSHvG>U+ae79`?{lozB3Anlq~WGwQ#Z&6@EzhN>=ZcmV?zRH&Z7| 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623.500 m +530.000 615.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +530.000 745.500 m +530.000 695.500 l +540.000 695.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +620.000 655.500 m +650.000 655.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +620.000 665.500 m +650.000 665.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +620.000 675.500 m +630.000 675.500 l +630.000 705.500 l +S +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +636.83 717.32 Td +(10k) Tj +ET +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +638.04 726.34 Td +(R1) Tj +ET +2 J +0 j +100 M +1.00 w +0.63 0.00 0.00 RG +[] 0 d +625.00 735.50 10.00 -20.00 re +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +630.000 735.500 m +630.000 745.500 l +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +630.000 715.500 m +630.000 705.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +580.000 635.500 m +580.000 605.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 567.00 579.50 Tm +(GND) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +580.000 595.500 m +580.000 605.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +571.000 595.500 m +589.000 595.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +574.000 593.500 m +586.000 593.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +577.000 591.500 m +583.000 591.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +579.000 589.500 m +581.000 589.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 480.25 651.80 Tm +(DM) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +520.000 655.500 m +515.000 650.500 l +500.000 650.500 l +500.000 660.500 l +515.000 660.500 l +520.000 655.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 483.62 661.80 Tm +(DP) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +520.000 665.500 m +515.000 660.500 l +500.000 660.500 l +500.000 670.500 l +515.000 670.500 l +520.000 665.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 673.10 651.80 Tm +(CC2) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +650.000 655.500 m +655.000 660.500 l +670.000 660.500 l +670.000 650.500 l +655.000 650.500 l +650.000 655.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 673.10 661.80 Tm +(CC1) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +650.000 665.500 m +655.000 670.500 l +670.000 670.500 l +670.000 660.500 l +655.000 660.500 l +650.000 665.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 614.13 757.42 Tm +(VBUS) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +630.000 755.500 m +630.000 745.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +625.000 755.500 m +635.000 755.500 l +S +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +564.14 711.16 Td +(CH224K) Tj +ET +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +573.95 720.66 Td +(U2) Tj +ET +2 J +0 j +100 M +1.00 w +0.60 0.00 0.00 RG +[] 0 d +553.000 708.500 m +607.000 708.500 l +608.657 708.500 610.000 707.157 610.000 705.500 c +610.000 648.500 l +610.000 646.843 608.343 645.500 607.000 645.500 c +553.000 645.500 l +551.343 645.500 550.000 647.157 550.000 648.500 c +550.000 705.500 l +550.000 707.157 551.657 708.500 553.000 708.500 c +S +BT +/F1 9 Tf +9.00 TL +1.000 0.000 0.000 rg +1.00 -0.00 0.00 1.00 552.00 692.50 Tm +(VDD) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 543.28 696.50 Tm +(1) Tj +ET +1 J +1 j +1.00 w +1.00 0.00 0.00 RG +[] 0 d +540.000 695.500 m +550.000 695.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 552.00 682.50 Tm +(CFG2) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 543.28 686.50 Tm +(2) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +540.000 685.500 m +550.000 685.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 552.00 672.50 Tm +(CFG3) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 543.28 676.50 Tm +(3) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +540.000 675.500 m +550.000 675.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 552.00 662.50 Tm +(DP) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 543.28 666.50 Tm +(4) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +540.000 665.500 m +550.000 665.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 552.00 652.50 Tm +(DM) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 543.28 656.50 Tm +(5) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +540.000 655.500 m +550.000 655.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 589.72 652.50 Tm +(CC2) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 611.00 656.50 Tm +(6) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +620.000 655.500 m +610.000 655.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 589.72 662.50 Tm +(CC1) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 611.00 666.50 Tm +(7) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +620.000 665.500 m +610.000 665.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 582.96 672.50 Tm +(VBUS) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 611.00 676.50 Tm +(8) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +620.000 675.500 m +610.000 675.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 583.86 682.50 Tm +(CFG1) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 611.00 686.50 Tm +(9) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +620.000 685.500 m +610.000 685.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 595.60 692.50 Tm +(PG) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 610.00 696.50 Tm +(10) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +620.000 695.500 m +610.000 695.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 g +0.00 1.00 -1.00 0.00 583.00 647.50 Tm +(GND) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +0.00 1.00 -1.00 0.00 578.00 634.07 Tm +(11) Tj +ET +1 J +1 j +1.00 w +0.00 G +[] 0 d +580.000 635.500 m +580.000 645.500 l +S +1.00 w +0.60 0.00 0.00 RG +0.60 0.00 0.00 rg +[] 0 d +557.00 703.50 m 557.00 704.60 556.10 705.50 555.00 705.50 c +553.90 705.50 553.00 704.60 553.00 703.50 c +553.00 702.40 553.90 701.50 555.00 701.50 c +556.10 701.50 557.00 702.40 557.00 703.50 c +B +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +540.000 685.500 m +520.000 685.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +540.000 675.500 m +520.000 675.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 471.32 681.91 Tm +(CFG2) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +520.000 685.500 m +515.000 680.500 l +500.000 680.500 l +500.000 690.500 l +515.000 690.500 l +520.000 685.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 471.32 671.91 Tm +(CFG3) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +520.000 675.500 m +515.000 670.500 l +500.000 670.500 l +500.000 680.500 l +515.000 680.500 l +520.000 675.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 673.14 682.00 Tm +(CFG1) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +650.000 685.500 m +655.000 690.500 l +670.000 690.500 l +670.000 680.500 l +655.000 680.500 l +650.000 685.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +620.000 685.500 m +650.000 685.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 515.29 757.44 Tm +(+3V3) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +530.000 755.500 m +530.000 745.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +525.000 755.500 m +535.000 755.500 l +S +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +132.03 488.26 Td +(78L33) Tj +ET +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +139.13 497.50 Td +(U4) Tj +ET +2 J +0 j +100 M +1.00 w +0.00 G +[] 0 d +132.000 485.500 m +158.000 485.500 l +159.105 485.500 160.000 484.605 160.000 483.500 c +160.000 447.500 l +160.000 446.395 158.895 445.500 158.000 445.500 c +132.000 445.500 l +130.895 445.500 130.000 446.605 130.000 447.500 c +130.000 483.500 l +130.000 484.605 131.105 485.500 132.000 485.500 c +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 132.00 472.50 Tm +(Vout) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 122.28 477.50 Tm +(1) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +120.000 475.500 m +130.000 475.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 132.00 452.50 Tm +(Vin) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 122.28 457.50 Tm +(3) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +120.000 455.500 m +130.000 455.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 g +1.00 -0.00 0.00 1.00 137.36 462.50 Tm +(GND) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 162.00 467.50 Tm +(2) Tj +ET +1 J +1 j +1.00 w +0.00 G +[] 0 d +170.000 465.500 m +160.000 465.500 l +S +10.00 w +BT +/F1 12 Tf +12.00 TL +0.000 0.000 1.000 rg +40.00 535.50 Td +(3V3 Voltage Regulator) Tj +ET +2 J +0 j +100 M +1.00 w +0.00 G +[] 0 d +30.00 555.50 175.00 -225.00 re +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +170.000 465.500 m +180.000 465.500 l +180.000 370.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +110.000 385.500 m +110.000 370.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +75.000 385.500 m +75.000 370.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 167.00 344.50 Tm +(GND) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +180.000 360.500 m +180.000 370.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +171.000 360.500 m +189.000 360.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +174.000 358.500 m +186.000 358.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +177.000 356.500 m +183.000 356.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +179.000 354.500 m +181.000 354.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 97.00 344.50 Tm +(GND) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +110.000 360.500 m +110.000 370.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +101.000 360.500 m +119.000 360.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +104.000 358.500 m +116.000 358.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +107.000 356.500 m +113.000 356.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +109.000 354.500 m +111.000 354.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 62.00 344.50 Tm +(GND) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +75.000 360.500 m +75.000 370.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +66.000 360.500 m +84.000 360.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +69.000 358.500 m +81.000 358.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +72.000 356.500 m +78.000 356.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +74.000 354.500 m +76.000 354.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +75.000 425.500 m +75.000 455.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +110.000 425.500 m +110.000 475.500 l +S +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +121.80 397.16 Td +(100n) Tj +ET +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +122.03 406.16 Td +(C5) Tj +ET +1 J +1 j +1.00 w +0.63 0.00 0.00 RG +0.00 g +[] 0 d +118.000 403.500 m +102.000 403.500 l +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +110.000 395.500 m +110.000 385.500 l +S +1 J +1 j +1.00 w +0.63 0.00 0.00 RG +0.00 g +[] 0 d +110.000 415.500 m +110.000 407.500 l +S +1 J +1 j +1.00 w +0.63 0.00 0.00 RG +0.00 g +[] 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+0.000 g +1.00 -0.00 0.00 1.00 915.50 676.50 Tm +(6) Tj +ET +1 J +1 j +1.00 w +0.00 G +[] 0 d +925.000 675.500 m +915.000 675.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 890.55 681.50 Tm +(VIN-) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 915.50 686.50 Tm +(7) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +925.000 685.500 m +915.000 685.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 887.28 691.50 Tm +(VIN+) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 915.50 696.50 Tm +(8) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +925.000 695.500 m +915.000 695.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 919.13 757.42 Tm +(VBUS) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +935.000 755.500 m +935.000 745.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +930.000 755.500 m +940.000 755.500 l +S +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 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695.500 m +935.000 695.500 l +935.000 715.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 1000.29 757.44 Tm +(+3V3) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +1015.000 755.500 m +1015.000 745.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +1010.000 755.500 m +1020.000 755.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +1015.000 745.500 m +1015.000 665.500 l +925.000 665.500 l +S +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +1025.00 623.25 Td +(100n) Tj +ET +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +1025.50 632.25 Td +(C6) Tj +ET +1 J +1 j +1.00 w +0.63 0.00 0.00 RG +0.00 g +[] 0 d +1023.000 633.500 m +1007.000 633.500 l +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +1015.000 625.500 m +1015.000 615.500 l +S +1 J +1 j +1.00 w +0.63 0.00 0.00 RG +0.00 g +[] 0 d +1015.000 645.500 m +1015.000 637.500 l +S +1 J +1 j +1.00 w +0.63 0.00 0.00 RG +0.00 g +[] 0 d +1007.000 637.500 m +1023.000 637.500 l +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +1015.000 645.500 m +1015.000 655.500 l +S +1 J +1 j +1.00 w +0.63 0.00 0.00 RG +0.00 g +[] 0 d +1015.000 633.500 m +1015.000 625.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 1002.00 579.50 Tm +(GND) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +1015.000 595.500 m +1015.000 605.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +1006.000 595.500 m +1024.000 595.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +1009.000 593.500 m +1021.000 593.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +1012.000 591.500 m +1018.000 591.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +1014.000 589.500 m +1016.000 589.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 922.00 579.50 Tm +(GND) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +935.000 595.500 m +935.000 605.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +926.000 595.500 m +944.000 595.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +929.000 593.500 m +941.000 593.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +932.000 591.500 m +938.000 591.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +934.000 589.500 m +936.000 589.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +935.000 605.500 m +935.000 675.500 l +925.000 675.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +1015.000 605.500 m +1015.000 615.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +1015.000 655.500 m +1015.000 665.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 739.57 672.12 Tm +(SDA) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +785.000 675.500 m +780.000 670.500 l +765.000 670.500 l +765.000 680.500 l +780.000 680.500 l +785.000 675.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 741.77 662.10 Tm +(SCL) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +785.000 665.500 m +780.000 660.500 l +765.000 660.500 l +765.000 670.500 l +780.000 670.500 l +785.000 665.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 822.00 579.50 Tm +(GND) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +835.000 595.500 m +835.000 605.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +826.000 595.500 m +844.000 595.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +829.000 593.500 m +841.000 593.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +832.000 591.500 m +838.000 591.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +834.000 589.500 m +836.000 589.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +835.000 605.500 m +835.000 695.500 l +845.000 695.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +845.000 685.500 m +835.000 685.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 51.53 636.86 Tm +(CFG1) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +100.000 640.500 m +95.000 635.500 l +80.000 635.500 l +80.000 645.500 l +95.000 645.500 l +100.000 640.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 291.71 666.71 Tm +(CFG2) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +270.000 670.500 m +275.000 675.500 l +290.000 675.500 l +290.000 665.500 l +275.000 665.500 l +270.000 670.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 291.96 656.67 Tm +(CFG3) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +270.000 660.500 m +275.000 665.500 l +290.000 665.500 l +290.000 655.500 l +275.000 655.500 l +270.000 660.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 62.05 646.96 Tm +(PG) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +100.000 650.500 m +95.000 645.500 l +80.000 645.500 l +80.000 655.500 l +95.000 655.500 l +100.000 650.500 l +S +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +772.49 707.26 Td +(10k) Tj +ET +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +776.04 716.27 Td +(R3) Tj +ET +2 J +0 j +100 M +1.00 w +0.63 0.00 0.00 RG +[] 0 d +790.00 725.50 10.00 -20.00 re +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +795.000 725.500 m +795.000 735.500 l +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +795.000 705.500 m +795.000 695.500 l +S +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +831.83 707.32 Td +(10k) Tj +ET +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +833.04 716.34 Td +(R4) Tj +ET +2 J +0 j +100 M +1.00 w +0.63 0.00 0.00 RG +[] 0 d +820.00 725.50 10.00 -20.00 re +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +825.000 725.500 m +825.000 735.500 l +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +825.000 705.500 m +825.000 695.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 780.29 757.44 Tm +(+3V3) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +795.000 755.500 m +795.000 745.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +790.000 755.500 m +800.000 755.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 810.29 757.44 Tm +(+3V3) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +825.000 755.500 m +825.000 745.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +820.000 755.500 m +830.000 755.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +785.000 675.500 m +845.000 675.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +785.000 665.500 m +845.000 665.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +825.000 695.500 m +825.000 675.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +795.000 695.500 m +795.000 665.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +795.000 745.500 m +795.000 735.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +825.000 745.500 m +825.000 735.500 l +S +2 J +0 j +100 M +1.00 w +0.00 G +[] 0 d +725.00 795.50 340.00 -230.00 re +S +10.00 w +BT +/F1 12 Tf +12.00 TL +0.000 0.000 1.000 rg +735.00 775.50 Td +(Voltage and Current Sensor) Tj +ET +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +505.92 473.50 Td +(OLED 0.91) Tj +ET +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +506.42 482.50 Td +(OLED1) Tj +ET +2 J +0 j +100 M +1.00 w +0.00 G +[] 0 d +500.00 470.50 60.00 -70.00 re +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 502.00 417.50 Tm +(GND) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 489.29 421.50 Tm +(1) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +480.000 420.500 m +500.000 420.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 502.00 427.50 Tm +(VCC) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 489.29 431.50 Tm +(2) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +480.000 430.500 m +500.000 430.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 502.00 437.50 Tm +(SCK) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 489.29 441.50 Tm +(3) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +480.000 440.500 m +500.000 440.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 502.00 447.50 Tm +(SDA) Tj +ET +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 489.29 451.50 Tm +(4) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +480.000 450.500 m +500.000 450.500 l +S +2 J +0 j +100 M +1.00 w +0.00 G +[] 0 d +525.00 465.50 30.00 -60.00 re +S +10.00 w +BT +/F1 12 Tf +12.00 TL +0.000 0.000 1.000 rg +0.00 1.00 -1.00 0.00 545.00 420.50 Tm +(OLED) Tj +ET +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 414.57 447.12 Tm +(SDA) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +460.000 450.500 m +455.000 445.500 l +440.000 445.500 l +440.000 455.500 l +455.000 455.500 l +460.000 450.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 416.77 437.10 Tm +(SCL) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +460.000 440.500 m +455.000 435.500 l +440.000 435.500 l +440.000 445.500 l +455.000 445.500 l +460.000 440.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 455.29 512.44 Tm +(+3V3) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +470.000 510.500 m +470.000 500.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +465.000 510.500 m +475.000 510.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 457.00 344.50 Tm +(GND) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +470.000 360.500 m +470.000 370.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +461.000 360.500 m +479.000 360.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +464.000 358.500 m +476.000 358.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +467.000 356.500 m +473.000 356.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +469.000 354.500 m +471.000 354.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +470.000 500.500 m +470.000 430.500 l +480.000 430.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +470.000 370.500 m +470.000 420.500 l +480.000 420.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +460.000 440.500 m +480.000 440.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +460.000 450.500 m +480.000 450.500 l +S +2 J +0 j +100 M +1.00 w +0.00 G +[] 0 d +400.00 555.50 175.00 -225.00 re +S +10.00 w +BT +/F1 12 Tf +12.00 TL +0.000 0.000 1.000 rg +410.00 535.50 Td +(Display) Tj +ET +2 J +0 j +100 M +1.00 w +0.00 G +[] 0 d +215.00 555.50 175.00 -225.00 re +S +10.00 w +BT +/F1 12 Tf +12.00 TL +0.000 0.000 1.000 rg +225.00 535.50 Td +(Control Buttons) Tj +ET +10.00 w +BT +/F4 12 Tf +12.00 TL +0.000 0.600 0.690 rg +1068.00 116.50 Td +(CC-BY-SA) Tj +ET +q +70.00 0 0 70.00 1065.00 130.50 cm +/I0 Do +Q +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +310.53 497.35 Td +(SET) Tj +ET +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +308.93 508.35 Td +(KEY1) Tj +ET +1.00 w +0.53 0.00 0.00 RG +[] 0 d +332.00 470.50 m 332.00 471.60 331.10 472.50 330.00 472.50 c +328.90 472.50 328.00 471.60 328.00 470.50 c +328.00 469.40 328.90 468.50 330.00 468.50 c +331.10 468.50 332.00 469.40 332.00 470.50 c +S +1.00 w +0.53 0.00 0.00 RG +[] 0 d +312.00 470.50 m 312.00 471.60 311.10 472.50 310.00 472.50 c +308.90 472.50 308.00 471.60 308.00 470.50 c +308.00 469.40 308.90 468.50 310.00 468.50 c +311.10 468.50 312.00 469.40 312.00 470.50 c +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +0.00 g +[] 0 d +330.000 472.500 m +310.000 478.500 l +310.000 478.500 l +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +0.00 g +[] 0 d +308.000 470.500 m +300.000 470.500 l +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +0.00 g +[] 0 d +332.000 470.500 m +340.000 470.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 340.00 491.50 Tm +(1) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +350.000 490.500 m +340.000 490.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 294.29 491.50 Tm +(2) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +290.000 490.500 m +300.000 490.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 340.00 471.50 Tm +(3) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +350.000 470.500 m +340.000 470.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 294.29 471.50 Tm +(4) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +290.000 470.500 m +300.000 470.500 l +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +0.00 g +[] 0 d +340.000 490.500 m +300.000 490.500 l +S +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +306.15 433.26 Td +(RESET) Tj +ET +10.00 w +BT +/F3 9 Tf +9.00 TL +0.000 0.000 0.502 rg +308.93 443.35 Td +(KEY2) Tj +ET +1.00 w +0.53 0.00 0.00 RG +[] 0 d +332.00 405.50 m 332.00 406.60 331.10 407.50 330.00 407.50 c +328.90 407.50 328.00 406.60 328.00 405.50 c +328.00 404.40 328.90 403.50 330.00 403.50 c +331.10 403.50 332.00 404.40 332.00 405.50 c +S +1.00 w +0.53 0.00 0.00 RG +[] 0 d +312.00 405.50 m 312.00 406.60 311.10 407.50 310.00 407.50 c +308.90 407.50 308.00 406.60 308.00 405.50 c +308.00 404.40 308.90 403.50 310.00 403.50 c +311.10 403.50 312.00 404.40 312.00 405.50 c +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +0.00 g +[] 0 d +330.000 407.500 m +310.000 413.500 l +310.000 413.500 l +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +0.00 g +[] 0 d +308.000 405.500 m +300.000 405.500 l +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +0.00 g +[] 0 d +332.000 405.500 m +340.000 405.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 340.00 426.50 Tm +(1) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +350.000 425.500 m +340.000 425.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 294.29 426.50 Tm +(2) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +290.000 425.500 m +300.000 425.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 340.00 406.50 Tm +(3) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +350.000 405.500 m +340.000 405.500 l +S +BT +/F1 9 Tf +9.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 294.29 406.50 Tm +(4) Tj +ET +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +[] 0 d +290.000 405.500 m +300.000 405.500 l +S +1 J +1 j +1.00 w +0.53 0.00 0.00 RG +0.00 g +[] 0 d +340.000 425.500 m +300.000 425.500 l +S +BT +/F2 12 Tf +12.00 TL +0.000 g +1.00 -0.00 0.00 1.00 347.00 344.50 Tm +(GND) Tj +ET +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +360.000 360.500 m +360.000 370.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +351.000 360.500 m +369.000 360.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +354.000 358.500 m +366.000 358.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +357.000 356.500 m +363.000 356.500 l +S +1 J +1 j +1.00 w +0.00 G +0.00 g +[] 0 d +359.000 354.500 m +361.000 354.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +360.000 370.500 m +360.000 405.500 l +350.000 405.500 l +S +1 J +1 j +1.00 w +0.00 0.53 0.00 RG +0.00 g +[] 0 d +350.000 470.500 m +360.000 470.500 l +360.000 405.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 48.59 696.89 Tm +(KEY1) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +100.000 700.500 m +95.000 695.500 l +80.000 695.500 l +80.000 705.500 l +95.000 705.500 l +100.000 700.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 48.59 686.89 Tm +(KEY2) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +100.000 690.500 m +95.000 685.500 l +80.000 685.500 l +80.000 695.500 l +95.000 695.500 l +100.000 690.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 228.59 466.89 Tm +(KEY1) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +280.000 470.500 m +275.000 465.500 l +260.000 465.500 l +260.000 475.500 l +275.000 475.500 l +280.000 470.500 l +S +BT +/F2 11 Tf +11.00 TL +0.000 0.000 1.000 rg +1.00 -0.00 0.00 1.00 228.59 401.89 Tm +(KEY2) Tj +ET +1 J +1 j +1.00 w +0.00 0.00 1.00 RG +0.00 g +[] 0 d +280.000 405.500 m +275.000 400.500 l +260.000 400.500 l +260.000 410.500 l +275.000 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Important +// values such as voltage, current, power and energy are displayed on the OLED. +// The USB PD Adapter is based on the cheap and easy-to-use CH224K multi fast +// charging protocol power receiving chip, the INA219 voltage and current sensor IC, +// and an ATtiny204, 214, 404, 414, 804, 814, 1604 or 1614 microcontroller. +// +// Wiring: +// ------- +// +-\/-+ +// Vcc 1|° |14 GND +// --- !SS AIN4 PA4 2| |13 PA3 AIN3 SCK ---- +// ------- AIN5 PA5 3| |12 PA2 AIN2 MISO --- KEY2 +// CH224K PG --- DAC AIN6 PA6 4| |11 PA1 AIN1 MOSI --- KEY1 +// CH224K CFG1 ------- AIN7 PA7 5| |10 PA0 AIN0 UPDI --- UPDI +// CH224K CFG3 -------- RXD PB3 6| |9 PB0 AIN11 SCL --- INA219/OLED +// CH224K CFG2 ---------TXD PB2 7| |8 PB1 AIN10 SDA --- INA219/OLED +// +----+ +// +// Compilation Settings: +// --------------------- +// Core: megaTinyCore (https://github.com/SpenceKonde/megaTinyCore) +// Board: ATtiny1614/1604/814/804/414/404/214/204 +// Chip: choose the chip you have installed +// Clock: 1 MHz internal +// +// Leave the rest on default settings. Don't forget to "Burn bootloader"! +// Compile and upload the code. +// +// No Arduino core functions or libraries are used. To compile and upload without +// Arduino IDE download AVR 8-bit toolchain at: +// https://www.microchip.com/mplab/avr-support/avr-and-arm-toolchains-c-compilers +// and extract to tools/avr-gcc. Use the makefile to compile and upload. +// +// Fuse Settings: 0:0x00 1:0x00 2:0x01 4:0x00 5:0xC5 6:0x04 7:0x00 8:0x00 +// +// Operating Instructions: +// ----------------------- +// 1. Connect the USB PD Adapter to a USB Type-C PD power supply using a USB-C cable. +// 2. Use the SET button to select the desired output voltage. An hourglass appears +// on the display while the device is communicating with the power supply. If +// the negotiation was successful, a tick is displayed and the desired voltage +// is present at the output. +// 3. Connect the device to the power consumer via the output screw terminal. +// 4. Use the RESET button to clear the energy counter. + + +// =================================================================================== +// Libraries, Definitions and Macros +// =================================================================================== + +// Libraries +#include // for GPIO +#include // for interrupts +#include // for delays + +// Pin definitions +#define PIN_SCL PB0 // I2C SCL, connected to INA219 and OLED +#define PIN_SDA PB1 // I2C SDA, connected to INA219 and OLED +#define PIN_CFG1 PA7 // CFG1 of CH224K +#define PIN_CFG2 PB2 // CFG2 of CH224K +#define PIN_CFG3 PB3 // CFG3 of CH224K +#define PIN_PG PA6 // Power Good of CH224K +#define PIN_KEY1 PA1 // Key 1 +#define PIN_KEY2 PA2 // Key 2 + +// Pin manipulation macros +enum {PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PB2, PB3}; // enumerate pin designators +#define pinInput(x) (&VPORTA.DIR)[((x)&8)>>1] &= ~(1<<((x)&7)) // set pin to INPUT +#define pinOutput(x) (&VPORTA.DIR)[((x)&8)>>1] |= (1<<((x)&7)) // set pin to OUTPUT +#define pinLow(x) (&VPORTA.OUT)[((x)&8)>>1] &= ~(1<<((x)&7)) // set pin to LOW +#define pinHigh(x) (&VPORTA.OUT)[((x)&8)>>1] |= (1<<((x)&7)) // set pin to HIGH +#define pinToggle(x) (&VPORTA.IN )[((x)&8)>>1] |= (1<<((x)&7)) // TOGGLE pin +#define pinRead(x) ((&VPORTA.IN)[((x)&8)>>1] & (1<<((x)&7))) // READ pin +#define pinDisable(x) (&PORTA.PIN0CTRL)[(((x)&8)<<2)+((x)&7)] |= PORT_ISC_INPUT_DISABLE_gc +#define pinPullup(x) (&PORTA.PIN0CTRL)[(((x)&8)<<2)+((x)&7)] |= PORT_PULLUPEN_bm + +// =================================================================================== +// I2C Master Implementation (Read/Write, Conservative) +// =================================================================================== + +#define I2C_FREQ 100000 // I2C clock frequency in Hz +#define I2C_BAUD ((F_CPU / I2C_FREQ) - 10) / 2; // simplified BAUD calculation + +// I2C init function +void I2C_init(void) { + TWI0.MBAUD = I2C_BAUD; // set TWI master BAUD rate + TWI0.MCTRLA = TWI_ENABLE_bm; // enable TWI master + TWI0.MSTATUS = TWI_BUSSTATE_IDLE_gc; // set bus state to idle +} + +// I2C start transmission +void I2C_start(uint8_t addr) { + TWI0.MADDR = addr; // start sending address + while(!(TWI0.MSTATUS&(TWI_WIF_bm|TWI_RIF_bm))); // wait for transfer to complete +} + +// I2C restart transmission +void I2C_restart(uint8_t addr) { + I2C_start(addr); // start sending address +} + +// I2C stop transmission +void I2C_stop(void) { + TWI0.MCTRLB = TWI_MCMD_STOP_gc; // send stop condition +} + +// I2C transmit one data byte to the slave, ignore ACK bit +void I2C_write(uint8_t data) { + TWI0.MDATA = data; // start sending data byte + while(~TWI0.MSTATUS & TWI_WIF_bm); // wait for transfer to complete +} + +// I2C receive one data byte from slave; ack=0: last byte, ack>0: more bytes to follow +uint8_t I2C_read(uint8_t ack) { + while(~TWI0.MSTATUS & TWI_RIF_bm); // wait for transfer to complete + uint8_t data = TWI0.MDATA; // get received data byte + if(ack) TWI0.MCTRLB = TWI_MCMD_RECVTRANS_gc; // ACK: read more bytes + else TWI0.MCTRLB = TWI_ACKACT_NACK_gc; // NACK: this was the last byte + return data; // return received byte +} + +// =================================================================================== +// INA219 Implementation +// =================================================================================== + +// INA219 register values +#define INA_ADDR 0x80 // I2C write address of INA219 +#define INA_CONFIG 0b0010011111111111 // INA config register according to datasheet +#define INA_CALIB 4096 // INA calibration register according to R_SHUNT +#define INA_REG_CONFIG 0x00 // INA configuration register address +#define INA_REG_CALIB 0x05 // INA calibration register address +#define INA_REG_SHUNT 0x01 // INA shunt voltage register address +#define INA_REG_VOLTAGE 0x02 // INA bus voltage register address +#define INA_REG_POWER 0x03 // INA power register address +#define INA_REG_CURRENT 0x04 // INA current register address + +// INA219 write a register value +void INA_write(uint8_t reg, uint16_t value) { + I2C_start(INA_ADDR); // start transmission to INA219 + I2C_write(reg); // write register address + I2C_write(value >> 8); // write register content high byte + I2C_write(value); // write register content low byte + I2C_stop(); // stop transmission +} + +// INA219 read a register +uint16_t INA_read(uint8_t reg) { + uint16_t result; // result variable + I2C_start(INA_ADDR); // start transmission to INA219 + I2C_write(reg); // write register address + I2C_restart(INA_ADDR | 0x01); // restart for reading + result = (uint16_t)(I2C_read(1) << 8) | I2C_read(0); // read register content + I2C_stop(); // stop transmission + return result; // return result +} + +// INA219 write inital configuration and calibration values +void INA_init(void) { + INA_write(INA_REG_CONFIG, INA_CONFIG); // write INA219 configuration + INA_write(INA_REG_CALIB, INA_CALIB); // write INA219 calibration +} + +// INA219 read voltage +uint16_t INA_readVoltage(void) { + return((INA_read(INA_REG_VOLTAGE) >> 1) & 0xFFFC); +} + +// INA219 read sensor values +uint16_t INA_readCurrent(void) { + uint16_t result = INA_read(INA_REG_CURRENT); // read current from INA + if(result > 32767) result = 0; // ignore nagtive currents + return result; // return result +} + +// =================================================================================== +// OLED Implementation +// =================================================================================== + +// OLED definitions +#define OLED_ADDR 0x78 // OLED write address +#define OLED_CMD_MODE 0x00 // set command mode +#define OLED_DAT_MODE 0x40 // set data mode + +// OLED init settings +const uint8_t OLED_INIT_CMD[] = { + 0xA8, 0x1F, // set multiplex for 128x32 + 0x20, 0x01, // set vertical memory addressing mode + 0xDA, 0x02, // set COM pins hardware configuration to sequential + 0x8D, 0x14, // enable charge pump + 0xAF // switch on OLED +}; + +// OLED 5x16 font +const uint8_t OLED_FONT[] = { + 0x7C, 0x1F, 0x02, 0x20, 0x02, 0x20, 0x02, 0x20, 0x7C, 0x1F, // 0 0 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x1F, // 1 1 + 0x00, 0x1F, 0x82, 0x20, 0x82, 0x20, 0x82, 0x20, 0x7C, 0x00, // 2 2 + 0x00, 0x00, 0x82, 0x20, 0x82, 0x20, 0x82, 0x20, 0x7C, 0x1F, // 3 3 + 0x7C, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x7C, 0x1F, // 4 4 + 0x7C, 0x00, 0x82, 0x20, 0x82, 0x20, 0x82, 0x20, 0x00, 0x1F, // 5 5 + 0x7C, 0x1F, 0x82, 0x20, 0x82, 0x20, 0x82, 0x20, 0x00, 0x1F, // 6 6 + 0x7C, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7C, 0x1F, // 7 7 + 0x7C, 0x1F, 0x82, 0x20, 0x82, 0x20, 0x82, 0x20, 0x7C, 0x1F, // 8 8 + 0x7C, 0x00, 0x82, 0x20, 0x82, 0x20, 0x82, 0x20, 0x7C, 0x1F, // 9 9 + 0x7C, 0x3F, 0x82, 0x00, 0x82, 0x00, 0x82, 0x00, 0x7C, 0x3F, // A 10 + 0x7C, 0x03, 0x00, 0x0C, 0x00, 0x30, 0x00, 0x0C, 0x7C, 0x03, // V 11 + 0x7C, 0x1F, 0x00, 0x20, 0x00, 0x3F, 0x00, 0x20, 0x7C, 0x1F, // W 12 + 0x7C, 0x3F, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x3F, // h 13 + 0x00, 0x3F, 0x80, 0x00, 0x80, 0x3F, 0x80, 0x00, 0x00, 0x3F, // m 14 + 0x7C, 0x1F, 0x82, 0x20, 0x82, 0x20, 0x82, 0x20, 0x00, 0x00, // E 15 + 0x02, 0x00, 0x02, 0x00, 0x7E, 0x3F, 0x02, 0x00, 0x02, 0x00, // T 16 + 0x00, 0x00, 0x30, 0x06, 0x30, 0x06, 0x00, 0x00, 0x00, 0x00, // : 17 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 18 SPACE + 0x3E, 0x3E, 0x72, 0x39, 0xE2, 0x3C, 0x72, 0x39, 0x3E, 0x3E, // 19 hourglass + 0x60, 0x00, 0x80, 0x01, 0x00, 0x06, 0x80, 0x01, 0x60, 0x00 // 20 checkmark +}; + +// Character definitions +#define COLON 17 +#define SPACE 18 +#define GLASS 19 +#define CHECK 20 + +// BCD conversion array +const uint16_t DIVIDER[] = {1, 10, 100, 1000, 10000}; + +// OLED init function +void OLED_init(void) { + I2C_start(OLED_ADDR); // start transmission to OLED + I2C_write(OLED_CMD_MODE); // set command mode + for (uint8_t i = 0; i < sizeof(OLED_INIT_CMD); i++) + I2C_write(OLED_INIT_CMD[i]); // send the command bytes + I2C_stop(); // stop transmission +} + +// OLED set the cursor +void OLED_setCursor(uint8_t xpos, uint8_t ypos) { + I2C_start(OLED_ADDR); // start transmission to OLED + I2C_write(OLED_CMD_MODE); // set command mode + I2C_write(0x22); // command for min/max page + I2C_write(ypos); I2C_write(ypos+1); // min: ypos; max: ypos+1 + I2C_write(xpos & 0x0F); // set low nibble of start column + I2C_write(0x10 | (xpos >> 4)); // set high nibble of start column + I2C_write(0xB0 | (ypos)); // set start page + I2C_stop(); // stop transmission +} + +// OLED clear a line +void OLED_clearLine(uint8_t ypos) { + OLED_setCursor(0, ypos); // set cursor at line start + I2C_start(OLED_ADDR); // start transmission to OLED + I2C_write(OLED_DAT_MODE); // set data mode + uint8_t i = 0; // count variable + do {I2C_write(0x00);} while(--i); // clear upper half + I2C_stop(); // stop transmission +} + +// OLED clear screen +void OLED_clearScreen(void) { + OLED_clearLine(0); OLED_clearLine(2); // clear both lines +} + +// OLED plot a single character +void OLED_plotChar(uint8_t ch) { + ch = (ch << 1) + (ch << 3); // calculate position of character in font array + I2C_write(0x00); I2C_write(0x00); // print spacing between characters + I2C_write(0x00); I2C_write(0x00); + for(uint8_t i=10; i; i--) I2C_write(OLED_FONT[ch++]); // print character +} + +// OLED print a character +void OLED_printChar(uint8_t ch) { + I2C_start(OLED_ADDR); // start transmission to OLED + I2C_write(OLED_DAT_MODE); // set data mode + OLED_plotChar(ch); // plot the character + I2C_stop(); // stop transmission +} + +// OLED print a "string"; terminator: 255 +void OLED_printStr(const uint8_t* p) { + I2C_start(OLED_ADDR); // start transmission to OLED + I2C_write(OLED_DAT_MODE); // set data mode + while(*p < 255) OLED_plotChar(*p++); // plot each character of the string + I2C_stop(); // stop transmission +} + +// OLED print value (BCD conversion by substraction method) +void OLED_printVal(uint16_t value) { + uint8_t digits = 5; // print 5 digits + uint8_t leadflag = 0; // flag for leading spaces + I2C_start(OLED_ADDR); // start transmission to OLED + I2C_write(OLED_DAT_MODE); // set data mode + while(digits--) { // for all digits digits + uint8_t digitval = 0; // start with digit value 0 + uint16_t divider = DIVIDER[digits]; // read current divider + while(value >= divider) { // if current divider fits into the value + leadflag = 1; // end of leading spaces + digitval++; // increase digit value + value -= divider; // decrease value by divider + } + if(!digits) leadflag++; // least digit has to be printed + if(leadflag) OLED_plotChar(digitval); // print the digit + else OLED_plotChar(SPACE); // or print leading space + } + I2C_stop(); // stop transmission +} + +// OLED print 8-bit value as 2-digit decimal (BCD conversion by substraction method) +void OLED_printDec(uint8_t value, uint8_t lead) { + I2C_start(OLED_ADDR); // start transmission to OLED + I2C_write(OLED_DAT_MODE); // set data mode + uint8_t digitval = 0; // start with digit value 0 + while(value >= 10) { // if current divider fits into the value + digitval++; // increase digit value + value -= 10; // decrease value by divider + } + if(digitval) OLED_plotChar(digitval); // print first digit + else OLED_plotChar(lead); + OLED_plotChar(value); // print second digit + I2C_stop(); // stop transmission +} + +// =================================================================================== +// Millis Counter Implementation for TCB0 +// =================================================================================== + +volatile uint32_t MIL_counter = 0; // millis counter variable + +// Init millis counter +void MIL_init(void) { + TCB0.CCMP = (F_CPU / 1000) - 1; // set TOP value (period) + TCB0.CTRLA = TCB_ENABLE_bm; // enable timer/counter + TCB0.INTCTRL = TCB_CAPT_bm; // enable periodic interrupt +} + +// Read millis counter +uint32_t MIL_read(void) { + cli(); // disable interrupt for atomic read + uint32_t result = MIL_counter; // read millis counter + sei(); // enable interrupt again + return result; // return millis counter value +} + +// TCB0 interrupt service routine (every millisecond) +ISR(TCB0_INT_vect) { + TCB0.INTFLAGS = TCB_CAPT_bm; // clear interrupt flag + MIL_counter++; // increase millis counter +} + +// =================================================================================== +// CH224K Implementation +// =================================================================================== + +// Some variables +enum {SET_5V, SET_9V, SET_12V, SET_15V, SET_20V}; +const uint8_t VOLTAGES[] = {5, 9, 12, 15, 20}; +uint8_t CH224K_volt = 0; // current voltage pointer + +// Some macros +#define CH224K_getVolt() (VOLTAGES[CH224K_volt]) // get voltage +#define CH224K_isGood() (!pinRead(PIN_PG)) // power good? + +// CH224K init +void CH224K_init(void) { + pinHigh(PIN_CFG1); // start with 5V + pinOutput(PIN_CFG1); // CFG pins as output... + pinOutput(PIN_CFG2); + pinOutput(PIN_CFG3); + pinPullup(PIN_PG); // pullup for Power Good pin +} + +// CH224K set voltage +void CH224K_setVolt(uint8_t volt) { + CH224K_volt = volt; + switch(CH224K_volt) { // set CFG pins according to voltage + case SET_5V: pinHigh(PIN_CFG1); break; + case SET_9V: pinLow (PIN_CFG1); pinLow (PIN_CFG2); pinLow (PIN_CFG3); break; + case SET_12V: pinLow (PIN_CFG1); pinLow (PIN_CFG2); pinHigh(PIN_CFG3); break; + case SET_15V: pinLow (PIN_CFG1); pinHigh(PIN_CFG2); pinHigh(PIN_CFG3); break; + case SET_20V: pinLow (PIN_CFG1); pinHigh(PIN_CFG2); pinLow (PIN_CFG3); break; + default: break; + } +} + +// CH224K set next voltage +void CH224K_nextVolt(void) { + if(++CH224K_volt > SET_20V) CH224K_volt = SET_5V; // next voltage + switch(CH224K_volt) { // change pins according to voltage + case SET_5V: pinHigh(PIN_CFG1); pinLow(PIN_CFG2); break; + case SET_9V: pinLow (PIN_CFG1); break; + case SET_12V: pinHigh(PIN_CFG3); break; + case SET_15V: pinHigh(PIN_CFG2); break; + case SET_20V: pinLow (PIN_CFG3); break; + default: break; + } +} + +// =================================================================================== +// Main Function +// =================================================================================== + +// Some "strings" +const uint8_t mA[] = { 14, 10, 255 }; // "mA" +const uint8_t mV[] = { 14, 11, 255 }; // "mV" +const uint8_t mW[] = { 14, 12, 18, 255 }; // "mW " +const uint8_t Ah[] = { 10, 13, 18, 255 }; // "Ah " +const uint8_t mAh[] = { 14, 10, 13, 255 }; // "mAh" +const uint8_t Wt[] = { 12, 18, 18, 255 }; // "W " +const uint8_t Wh[] = { 12, 13, 18, 255 }; // "Wh " +const uint8_t mWh[] = { 14, 12, 13, 255 }; // "mWh" +const uint8_t SET[] = { 5, 15, 16, 17, 18, 255 }; // "SET: " +const uint8_t HGL[] = { 11, SPACE, GLASS, SPACE, 255}; // hourglass +const uint8_t CMK[] = { 11, SPACE, CHECK, SPACE, 255}; // checkmark +const uint8_t SEP[] = { SPACE, SPACE, SPACE, 255}; // seperator + +// Main function +int main(void) { + // Setup + _PROTECTED_WRITE(CLKCTRL.MCLKCTRLB, 7); // set clock frequency to 1 MHz + CH224K_init(); // init CH224K + I2C_init(); // init I2C + INA_init(); // init INA219 + OLED_init(); // init OLED + MIL_init(); // init TCB for millis counter + sei(); // enable interrupts + pinPullup(PIN_KEY1); pinPullup(PIN_KEY2); // pullup for keys + OLED_clearScreen(); // clear OLED + + // Local variables + uint16_t volt, curr; // voltage in mV, current in mA + uint32_t power; // power in mW + uint32_t energy = 0, charge = 0; // counter for energy and charge + uint32_t interval, nowmillis, lastmillis = 0; // for timing calculation in millis + uint32_t duration = 0; // total duration in ms + uint16_t seconds = 0; // total duration in seconds + uint8_t lastkey1 = 0, lastkey2 = 0; // for key pressed dectection + + // Loop + while(1) { // loop until forever + // Read sensor values + volt = INA_readVoltage(); // read voltage in mV from INA219 + curr = INA_readCurrent(); // read current in mA from INA219 + + // Calculate timings + nowmillis = MIL_read(); // read millis counter + interval = nowmillis - lastmillis; // calculate recent time interval + lastmillis = nowmillis; // reset lastmillis + duration += interval; // calculate total duration in millis + seconds = duration / 1000; // calculate total duration in seconds + + // Calculate power, capacity and energy + power = (uint32_t)volt * curr / 1000; // calculate power in mW + energy += interval * power / 3600; // calculate energy in uWh + charge += interval * curr / 3600; // calculate charge in uAh + + // Check SET button + if(pinRead(PIN_KEY1)) lastkey1 = 0; + else if(!lastkey1) { + CH224K_nextVolt(); + lastkey1++; + } + + // Check RESET button + if(pinRead(PIN_KEY2)) lastkey2 = 0; + else if(!lastkey2) { + duration = 0; seconds = 0; energy = 0; charge = 0; + lastkey2++; + } + + // Display values on the OLED + OLED_setCursor(0,0); + OLED_printStr(SET); OLED_printDec(CH224K_getVolt(), SPACE); + OLED_printStr(CH224K_isGood() ? CMK : HGL); + OLED_printVal(volt); OLED_printStr(mV); + + OLED_setCursor(0,2); + switch(seconds & 0x0C) { + case 0x00: if(power > 65535) { + OLED_printVal(power / 1000); + OLED_printStr(Wt); + } else { + OLED_printVal(power); + OLED_printStr(mW); + } + break; + case 0x04: if(energy > 65535) { + OLED_printVal(energy / 1000000); + OLED_printStr(Wh); + } else { + OLED_printVal(energy / 1000); + OLED_printStr(mWh); + } + break; + case 0x08: if(charge > 65535) { + OLED_printVal(charge / 1000000); + OLED_printStr(Ah); + } else { + OLED_printVal(charge / 1000); + OLED_printStr(mAh); + } + break; + case 0x0C: OLED_printDec(seconds / 3600, 0); OLED_printChar(COLON); + seconds %= 3600; + OLED_printDec(seconds / 60 , 0); OLED_printChar(COLON); + OLED_printDec(seconds % 60 , 0); + break; + default: break; + } + OLED_printStr(SEP); + OLED_printVal(curr); OLED_printStr(mA); + _delay_ms(50); + } +} diff --git a/software/makefile b/software/makefile new file mode 100755 index 0000000..56cc3d5 --- /dev/null +++ b/software/makefile @@ -0,0 +1,109 @@ +# Project: USB PD Adapter +# Author: Stefan Wagner +# Year: 2022 +# URL: https://github.com/wagiminator +# +# Download AVR 8-bit Toolchain: +# https://www.microchip.com/mplab/avr-support/avr-and-arm-toolchains-c-compilers +# and extract to ./tools/avr-gcc +# Type "make help" in the command line. + +# Input and Output File Names +SKETCH = USB_PD_Adapter.ino +TARGET = usb_pd_adapter + +# Microcontroller Options +DEVICE ?= attiny814 +CLOCK = 1000000 +FUSE0 = 0x00 +FUSE1 = 0x00 +FUSE2 = 0x01 +FUSE4 = 0x00 +FUSE5 = 0xC5 +FUSE6 = 0x04 +FUSE7 = 0x00 +FUSE8 = 0x00 + +# Programmer Options (serialupdi or jtag2updi) +PROGRMR ?= serialupdi +PORT ?= /dev/ttyUSB0 + +# Paths +GCCPATH = ./tools/avr-gcc +DFPPATH = ./tools/dfp +PYMPATH = ./tools/pymcuprog +ADCPATH = ./tools/avrdude + +# Commands +DFPINCL = -B $(DFPPATH)/gcc/dev/$(DEVICE)/ -I $(DFPPATH)/include/ +COMPILE = $(GCCPATH)/bin/avr-gcc $(DFPINCL) -flto -Wall -Os -mmcu=$(DEVICE) -DF_CPU=$(CLOCK)UL -x c++ $(SKETCH) +PYPROG = python3 -u $(PYMPATH)/prog.py -t uart -u $(PORT) -b 230400 -d $(DEVICE) +AVRDUDE = avrdude -C $(ADCPATH)/avrdude.conf -c jtag2updi -P $(PORT) -p $(DEVICE) +CLEAN = rm -f *.lst *.obj *.cof *.list *.map *.eep.hex *.o *.s *.d + +# Symbolic Targets +help: + @echo "Use the following commands:" + @echo "make all compile and build $(TARGET).bin/.hex/.asm for $(DEVICE)" + @echo "make hex compile and build $(TARGET).hex for $(DEVICE)" + @echo "make asm compile and disassemble to $(TARGET).asm for $(DEVICE)" + @echo "make bin compile and build $(TARGET).bin for $(DEVICE)" + @echo "make upload compile and upload to $(DEVICE) using $(PROGRMR)" + @echo "make fuses burn fuses of $(DEVICE) using $(PROGRMR) programmer" + @echo "make install compile, upload and burn fuses for $(DEVICE)" + @echo "make clean remove all build files" + +all: buildbin buildhex buildasm removetemp size + +bin: buildbin removetemp size + +hex: buildbin buildhex removetemp size removebin + +asm: buildbin buildasm removetemp size removebin + +install: fuses upload + +upload: hex + @echo "Uploading to $(DEVICE) ..." +ifeq ($(PROGRMR),serialupdi) + @$(PYPROG) --fuses 2:$(FUSE2) 6:$(FUSE6) 8:$(FUSE8) -f $(TARGET).hex -a write +else + @$(AVRDUDE) -U fuse2:w:$(FUSE2):m -U fuse6:w:$(FUSE6):m -U fuse8:w:$(FUSE8):m -U flash:w:$(TARGET).hex:i +endif + +fuses: + @echo "Burning fuses of $(DEVICE) ..." +ifeq ($(PROGRMR),serialupdi) + @$(PYPROG) --fuses 0:$(FUSE0) 1:$(FUSE1) 2:$(FUSE2) 4:$(FUSE4) 5:$(FUSE5) 6:$(FUSE6) 7:$(FUSE7) 8:$(FUSE8) -a erase +else + @$(AVRDUDE) -e -Ufuse0:w:$(FUSE0):m -Ufuse1:w:$(FUSE1):m -Ufuse2:w:$(FUSE2):m -Ufuse4:w:$(FUSE4):m -Ufuse5:w:$(FUSE5):m -Ufuse6:w:$(FUSE6):m -Ufuse7:w:$(FUSE7):m -Ufuse8:w:$(FUSE8):m +endif + +clean: + @echo "Cleaning all up ..." + @$(CLEAN) + @rm -f $(TARGET).bin $(TARGET).hex $(TARGET).asm + +buildbin: + @echo "Building $(TARGET).bin for $(DEVICE) @ $(CLOCK)Hz ..." + @$(COMPILE) -o $(TARGET).bin + +buildhex: + @echo "Building $(TARGET).hex ..." + @$(GCCPATH)/bin/avr-objcopy -O ihex -R .eeprom $(TARGET).bin $(TARGET).hex + +buildasm: + @echo "Disassembling to $(TARGET).asm ..." + @$(GCCPATH)/bin/avr-objdump -d $(TARGET).bin > $(TARGET).asm + +size: + @echo "FLASH: $(shell $(GCCPATH)/bin/avr-size -d $(TARGET).bin | awk '/[0-9]/ {print $$1 + $$2}') bytes" + @echo "SRAM: $(shell $(GCCPATH)/bin/avr-size -d $(TARGET).bin | awk '/[0-9]/ {print $$2 + $$3}') bytes" + +removetemp: + @echo "Removing temporary files ..." + @$(CLEAN) + +removebin: + @echo "Removing $(TARGET).bin ..." + @rm -f $(TARGET).bin diff --git a/software/tools/avr-gcc/download.txt b/software/tools/avr-gcc/download.txt new file mode 100644 index 0000000..efa5d96 --- /dev/null +++ b/software/tools/avr-gcc/download.txt @@ -0,0 +1,4 @@ +Download AVR 8-bit Toolchain: +https://www.microchip.com/mplab/avr-support/avr-and-arm-toolchains-c-compilers +To do this, you have to register for free with Microchip on the site. +Extract the sub-folders (avr, bin, include, ...) here. diff --git a/software/tools/avrdude/avrdude.conf b/software/tools/avrdude/avrdude.conf new file mode 100644 index 0000000..b53dcc4 --- /dev/null +++ b/software/tools/avrdude/avrdude.conf @@ -0,0 +1,16284 @@ +# $Id$ -*- text -*- +# +# AVRDUDE Configuration File +# +# This file contains configuration data used by AVRDUDE which describes +# the programming hardware pinouts and also provides part definitions. +# AVRDUDE's "-C" command line option specifies the location of the +# configuration file. The "-c" option names the programmer configuration +# which must match one of the entry's "id" parameter. The "-p" option +# identifies which part AVRDUDE is going to be programming and must match +# one of the parts' "id" parameter. +# +# DO NOT MODIFY THIS FILE. Modifications will be overwritten the next +# time a "make install" is run. For user-specific additions, use the +# "-C +filename" commandline option. +# +# Possible entry formats are: +# +# programmer +# parent # optional parent +# id = [, [, ] ...] ; # are quoted strings +# desc = ; # quoted string +# type = ; # programmer type, quoted string +# # supported programmer types can be listed by "-c ?type" +# connection_type = parallel | serial | usb +# baudrate = ; # baudrate for avr910-programmer +# vcc = [, ... ] ; # pin number(s) +# buff = [, ... ] ; # pin number(s) +# reset = ; # pin number +# sck = ; # pin number +# mosi = ; # pin number +# miso = ; # pin number +# errled = ; # pin number +# rdyled = ; # pin number +# pgmled = ; # pin number +# vfyled = ; # pin number +# usbvid = ; # USB VID (Vendor ID) +# usbpid = [, ...] # USB PID (Product ID) (1) +# usbdev = ; # USB interface or other device info +# usbvendor = ; # USB Vendor Name +# usbproduct = ; # USB Product Name +# usbsn = ; # USB Serial Number +# +# To invert a bit, use = ~ , the spaces are important. +# For a pin list all pins must be inverted. +# A single pin can be specified as usual = ~ , for lists +# specify it as follows = ~ ( [, ... ] ) . +# +# (1) Not all programmer types can process a list of PIDs. +# ; +# +# part +# id = ; # quoted string +# desc = ; # quoted string +# has_jtag = ; # part has JTAG i/f +# has_debugwire = ; # part has debugWire i/f +# has_pdi = ; # part has PDI i/f +# has_updi = ; # part has UPDI i/f +# has_tpi = ; # part has TPI i/f +# devicecode = ; # deprecated, use stk500_devcode +# stk500_devcode = ; # numeric +# avr910_devcode = ; # numeric +# signature = ; # signature bytes +# usbpid = ; # DFU USB PID +# chip_erase_delay = ; # micro-seconds +# reset = dedicated | io; +# retry_pulse = reset | sck; +# pgm_enable = ; +# chip_erase = ; +# chip_erase_delay = ; # chip erase delay (us) +# # STK500 parameters (parallel programming IO lines) +# pagel = ; # pin name in hex, i.e., 0xD7 +# bs2 = ; # pin name in hex, i.e., 0xA0 +# serial = ; # can use serial downloading +# parallel = ; # can use par. programming +# # STK500v2 parameters, to be taken from Atmel's XML files +# timeout = ; +# stabdelay = ; +# cmdexedelay = ; +# synchloops = ; +# bytedelay = ; +# pollvalue = ; +# pollindex = ; +# predelay = ; +# postdelay = ; +# pollmethod = ; +# mode = ; +# delay = ; +# blocksize = ; +# readsize = ; +# hvspcmdexedelay = ; +# # STK500v2 HV programming parameters, from XML +# pp_controlstack = , , ...; # PP only +# hvsp_controlstack = , , ...; # HVSP only +# hventerstabdelay = ; +# progmodedelay = ; # PP only +# latchcycles = ; +# togglevtg = ; +# poweroffdelay = ; +# resetdelayms = ; +# resetdelayus = ; +# hvleavestabdelay = ; +# resetdelay = ; +# synchcycles = ; # HVSP only +# chiperasepulsewidth = ; # PP only +# chiperasepolltimeout = ; +# chiperasetime = ; # HVSP only +# programfusepulsewidth = ; # PP only +# programfusepolltimeout = ; +# programlockpulsewidth = ; # PP only +# programlockpolltimeout = ; +# # JTAG ICE mkII parameters, also from XML files +# allowfullpagebitstream = ; +# enablepageprogramming = ; +# idr = ; # IO addr of IDR (OCD) reg. +# rampz = ; # IO addr of RAMPZ reg. +# spmcr = ; # mem addr of SPMC[S]R reg. +# eecr = ; # mem addr of EECR reg. +# # (only when != 0x3c) +# is_at90s1200 = ; # AT90S1200 part +# is_avr32 = ; # AVR32 part +# +# memory +# paged = ; # yes / no +# size = ; # bytes +# page_size = ; # bytes +# num_pages = ; # numeric +# min_write_delay = ; # micro-seconds +# max_write_delay = ; # micro-seconds +# readback_p1 = ; # byte value +# readback_p2 = ; # byte value +# pwroff_after_write = ; # yes / no +# read = ; +# write = ; +# read_lo = ; +# read_hi = ; +# write_lo = ; +# write_hi = ; +# loadpage_lo = ; +# loadpage_hi = ; +# writepage = ; +# ; +# ; +# +# If any of the above parameters are not specified, the default value +# of 0 is used for numerics or the empty string ("") for string +# values. If a required parameter is left empty, AVRDUDE will +# complain. +# +# Parts can also inherit parameters from previously defined parts +# using the following syntax. In this case specified integer and +# string values override parameter values from the parent part. New +# memory definitions are added to the definitions inherited from the +# parent. +# +# part parent # quoted string +# id = ; # quoted string +# +# ; +# +# NOTES: +# * 'devicecode' is the device code used by the STK500 (see codes +# listed below) +# * Not all memory types will implement all instructions. +# * AVR Fuse bits and Lock bits are implemented as a type of memory. +# * Example memory types are: +# "flash", "eeprom", "fuse", "lfuse" (low fuse), "hfuse" (high +# fuse), "signature", "calibration", "lock" +# * The memory type specified on the avrdude command line must match +# one of the memory types defined for the specified chip. +# * The pwroff_after_write flag causes avrdude to attempt to +# power the device off and back on after an unsuccessful write to +# the affected memory area if VCC programmer pins are defined. If +# VCC pins are not defined for the programmer, a message +# indicating that the device needs a power-cycle is printed out. +# This flag was added to work around a problem with the +# at90s4433/2333's; see the at90s4433 errata at: +# +# http://www.atmel.com/dyn/resources/prod_documents/doc1280.pdf +# +# INSTRUCTION FORMATS +# +# Instruction formats are specified as a comma seperated list of +# string values containing information (bit specifiers) about each +# of the 32 bits of the instruction. Bit specifiers may be one of +# the following formats: +# +# '1' = the bit is always set on input as well as output +# +# '0' = the bit is always clear on input as well as output +# +# 'x' = the bit is ignored on input and output +# +# 'a' = the bit is an address bit, the bit-number matches this bit +# specifier's position within the current instruction byte +# +# 'aN' = the bit is the Nth address bit, bit-number = N, i.e., a12 +# is address bit 12 on input, a0 is address bit 0. +# +# 'i' = the bit is an input data bit +# +# 'o' = the bit is an output data bit +# +# Each instruction must be composed of 32 bit specifiers. The +# instruction specification closely follows the instruction data +# provided in Atmel's data sheets for their parts. +# +# See below for some examples. +# +# +# The following are STK500 part device codes to use for the +# "devicecode" field of the part. These came from Atmel's software +# section avr061.zip which accompanies the application note +# AVR061 available from: +# +# http://www.atmel.com/dyn/resources/prod_documents/doc2525.pdf +# + +#define ATTINY10 0x10 /* the _old_ one that never existed! */ +#define ATTINY11 0x11 +#define ATTINY12 0x12 +#define ATTINY15 0x13 +#define ATTINY13 0x14 + +#define ATTINY22 0x20 +#define ATTINY26 0x21 +#define ATTINY28 0x22 +#define ATTINY2313 0x23 + +#define AT90S1200 0x33 + +#define AT90S2313 0x40 +#define AT90S2323 0x41 +#define AT90S2333 0x42 +#define AT90S2343 0x43 + +#define AT90S4414 0x50 +#define AT90S4433 0x51 +#define AT90S4434 0x52 +#define ATMEGA48 0x59 + +#define AT90S8515 0x60 +#define AT90S8535 0x61 +#define AT90C8534 0x62 +#define ATMEGA8515 0x63 +#define ATMEGA8535 0x64 + +#define ATMEGA8 0x70 +#define ATMEGA88 0x73 +#define ATMEGA168 0x86 + +#define ATMEGA161 0x80 +#define ATMEGA163 0x81 +#define ATMEGA16 0x82 +#define ATMEGA162 0x83 +#define ATMEGA169 0x84 + +#define ATMEGA323 0x90 +#define ATMEGA32 0x91 + +#define ATMEGA64 0xA0 + +#define ATMEGA103 0xB1 +#define ATMEGA128 0xB2 +#define AT90CAN128 0xB3 +#define AT90CAN64 0xB3 +#define AT90CAN32 0xB3 + +#define AT86RF401 0xD0 + +#define AT89START 0xE0 +#define AT89S51 0xE0 +#define AT89S52 0xE1 + +# The following table lists the devices in the original AVR910 +# appnote: +# |Device |Signature | Code | +# +-------+----------+------+ +# |tiny12 | 1E 90 05 | 0x55 | +# |tiny15 | 1E 90 06 | 0x56 | +# | | | | +# | S1200 | 1E 90 01 | 0x13 | +# | | | | +# | S2313 | 1E 91 01 | 0x20 | +# | S2323 | 1E 91 02 | 0x48 | +# | S2333 | 1E 91 05 | 0x34 | +# | S2343 | 1E 91 03 | 0x4C | +# | | | | +# | S4414 | 1E 92 01 | 0x28 | +# | S4433 | 1E 92 03 | 0x30 | +# | S4434 | 1E 92 02 | 0x6C | +# | | | | +# | S8515 | 1E 93 01 | 0x38 | +# | S8535 | 1E 93 03 | 0x68 | +# | | | | +# |mega32 | 1E 95 01 | 0x72 | +# |mega83 | 1E 93 05 | 0x65 | +# |mega103| 1E 97 01 | 0x41 | +# |mega161| 1E 94 01 | 0x60 | +# |mega163| 1E 94 02 | 0x64 | + +# Appnote AVR109 also has a table of AVR910 device codes, which +# lists: +# dev avr910 signature +# ATmega8 0x77 0x1E 0x93 0x07 +# ATmega8515 0x3B 0x1E 0x93 0x06 +# ATmega8535 0x6A 0x1E 0x93 0x08 +# ATmega16 0x75 0x1E 0x94 0x03 +# ATmega162 0x63 0x1E 0x94 0x04 +# ATmega163 0x66 0x1E 0x94 0x02 +# ATmega169 0x79 0x1E 0x94 0x05 +# ATmega32 0x7F 0x1E 0x95 0x02 +# ATmega323 0x73 0x1E 0x95 0x01 +# ATmega64 0x46 0x1E 0x96 0x02 +# ATmega128 0x44 0x1E 0x97 0x02 +# +# These codes refer to "BOOT" device codes which are apparently +# different than standard device codes, for whatever reasons +# (often one above the standard code). + +# There are several extended versions of AVR910 implementations around +# in the Internet. These add the following codes (only devices that +# actually exist are listed): + +# ATmega8515 0x3A +# ATmega128 0x43 +# ATmega64 0x45 +# ATtiny26 0x5E +# ATmega8535 0x69 +# ATmega32 0x72 +# ATmega16 0x74 +# ATmega8 0x76 +# ATmega169 0x78 + +# +# Overall avrdude defaults; suitable for ~/.avrduderc +# +default_parallel = "@DEFAULT_PAR_PORT@"; +default_serial = "@DEFAULT_SER_PORT@"; +# default_bitclock = 2.5; + +# Turn off safemode by default +#default_safemode = no; + + +# +# PROGRAMMER DEFINITIONS +# + +# http://wiring.org.co/ +# Basically STK500v2 protocol, with some glue to trigger the +# bootloader. +programmer + id = "wiring"; + desc = "Wiring"; + type = "wiring"; + connection_type = serial; +; + +programmer + id = "arduino"; + desc = "Arduino"; + type = "arduino"; + connection_type = serial; +; +# this will interface with the chips on these programmers: +# +# http://real.kiev.ua/old/avreal/en/adapters +# http://www.amontec.com/jtagkey.shtml, jtagkey-tiny.shtml +# http://www.olimex.com/dev/arm-usb-ocd.html, arm-usb-tiny.html +# http://www.ethernut.de/en/hardware/turtelizer/index.html +# http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html +# http://dangerousprototypes.com/docs/FT2232_breakout_board +# http://www.ftdichip.com/Products/Modules/DLPModules.htm,DLP-2232*,DLP-USB1232H +# http://flashrom.org/FT2232SPI_Programmer +# +# The drivers will look for a specific device and use the first one found. +# If you have mulitple devices, then look for unique information (like SN) +# And fill that in here. +# +# Note that the pin numbers for the main ISP signals (reset, sck, +# mosi, miso) are fixed and cannot be changed, since they must match +# the way the Multi-Protocol Synchronous Serial Engine (MPSSE) of +# these FTDI ICs has been designed. + +programmer + id = "avrftdi"; + desc = "FT2232D based generic programmer"; + type = "avrftdi"; + connection_type = usb; + usbvid = 0x0403; + usbpid = 0x6010; + usbvendor = ""; + usbproduct = ""; + usbdev = "A"; + usbsn = ""; +#ISP-signals - lower ADBUS-Nibble (default) + reset = 3; + sck = 0; + mosi = 1; + miso = 2; +#LED SIGNALs - higher ADBUS-Nibble +# errled = 4; +# rdyled = 5; +# pgmled = 6; +# vfyled = 7; +#Buffer Signal - ACBUS - Nibble +# buff = 8; +; +# This is an implementation of the above with a buffer IC (74AC244) and +# 4 LEDs directly attached, all active low. +programmer + id = "2232HIO"; + desc = "FT2232H based generic programmer"; + type = "avrftdi"; + connection_type = usb; + usbvid = 0x0403; +# Note: This PID is reserved for generic H devices and +# should be programmed into the EEPROM +# usbpid = 0x8A48; + usbpid = 0x6010; + usbdev = "A"; + usbvendor = ""; + usbproduct = ""; + usbsn = ""; +#ISP-signals + reset = 3; + sck = 0; + mosi = 1; + miso = 2; + buff = ~4; +#LED SIGNALs + errled = ~ 11; + rdyled = ~ 14; + pgmled = ~ 13; + vfyled = ~ 12; +; + +#The FT4232H can be treated as FT2232H, but it has a different USB +#device ID of 0x6011. +programmer parent "avrftdi" + id = "4232h"; + desc = "FT4232H based generic programmer"; + usbpid = 0x6011; +; + +programmer + id = "jtagkey"; + desc = "Amontec JTAGKey, JTAGKey-Tiny and JTAGKey2"; + type = "avrftdi"; + connection_type = usb; + usbvid = 0x0403; +# Note: This PID is used in all JTAGKey variants + usbpid = 0xCFF8; + usbdev = "A"; + usbvendor = ""; + usbproduct = ""; + usbsn = ""; +#ISP-signals => 20 - Pin connector on JTAGKey + reset = 3; # TMS 7 violet + sck = 0; # TCK 9 white + mosi = 1; # TDI 5 green + miso = 2; # TDO 13 orange + buff = ~4; +# VTG VREF 1 brown with red tip +# GND GND 20 black +# The colors are on the 20 pin breakout cable +# from Amontec +; + +# UM232H module from FTDI and Glyn.com.au. +# See helix.air.net.au for detailed usage information. +# J1: Connect pin 2 and 3 for USB power. +# J2: Connect pin 2 and 3 for USB power. +# J2: Pin 7 is SCK +# : Pin 8 is MOSI +# : Pin 9 is MISO +# : Pin 11 is RST +# : Pin 6 is ground +# Use the -b flag to set the SPI clock rate eg -b 3750000 is the fastest I could get +# a 16MHz Atmega1280 to program reliably. The 232H is conveniently 5V tolerant. +programmer + id = "UM232H"; + desc = "FT232H based module from FTDI and Glyn.com.au"; + type = "avrftdi"; + usbvid = 0x0403; +# Note: This PID is reserved for generic 232H devices and +# should be programmed into the EEPROM + usbpid = 0x6014; + usbdev = "A"; + usbvendor = ""; + usbproduct = ""; + usbsn = ""; +#ISP-signals + sck = 0; + mosi = 1; + miso = 2; + reset = 3; +; + +# C232HM module from FTDI and Glyn.com.au. +# : Orange is SCK +# : Yellow is MOSI +# : Green is MISO +# : Brown is RST +# : Black is ground +# Use the -b flag to set the SPI clock rate eg -b 3750000 is the fastest I could get +# a 16MHz Atmega1280 to program reliably. The 232H is conveniently 5V tolerant. +programmer + id = "C232HM"; + desc = "FT232H based module from FTDI and Glyn.com.au"; + type = "avrftdi"; + usbvid = 0x0403; +# Note: This PID is reserved for generic 232H devices and +# should be programmed into the EEPROM + usbpid = 0x6014; + usbdev = "A"; + usbvendor = ""; + usbproduct = ""; + usbsn = ""; +#ISP-signals + sck = 0; + mosi = 1; + miso = 2; + reset = 3; +; + + +# On the adapter you can read "O-Link". On the PCB is printed "OpenJTAG v3.1" +# You can find it as "OpenJTAG ARM JTAG USB" in the internet. +# (But there are also several projects called Open JTAG, eg. +# http://www.openjtag.org, which are completely different.) +# http://www.100ask.net/shop/english.html (website seems to be outdated) +# http://item.taobao.com/item.htm?id=1559277013 +# http://www.micro4you.com/store/openjtag-arm-jtag-usb.html (schematics!) +# some other sources which call it O-Link +# http://www.andahammer.com/olink/ +# http://www.developmentboard.net/31-o-link-debugger.html +# http://armwerks.com/catalog/o-link-debugger-copy/ +# or just have a look at ebay ... +# It is basically the same entry as jtagkey with different usb ids. +programmer parent "jtagkey" + id = "o-link"; + desc = "O-Link, OpenJTAG from www.100ask.net"; + usbvid = 0x1457; + usbpid = 0x5118; + usbvendor = "www.100ask.net"; + usbproduct = "USB<=>JTAG&RS232"; +; + +# http://wiki.openmoko.org/wiki/Debug_Board_v3 +programmer + id = "openmoko"; + desc = "Openmoko debug board (v3)"; + type = "avrftdi"; + usbvid = 0x1457; + usbpid = 0x5118; + usbdev = "A"; + usbvendor = ""; + usbproduct = ""; + usbsn = ""; + reset = 3; # TMS 7 + sck = 0; # TCK 9 + mosi = 1; # TDI 5 + miso = 2; # TDO 13 +; + +# Only Rev. A boards. +# Schematic and user manual: http://www.cs.put.poznan.pl/wswitala/download/pdf/811EVBK.pdf +programmer + id = "lm3s811"; + desc = "Luminary Micro LM3S811 Eval Board (Rev. A)"; + type = "avrftdi"; + connection_type = usb; + usbvid = 0x0403; + usbpid = 0xbcd9; + usbvendor = "LMI"; + usbproduct = "LM3S811 Evaluation Board"; + usbdev = "A"; + usbsn = ""; +#ISP-signals - lower ACBUS-Nibble (default) + reset = 3; + sck = 0; + mosi = 1; + miso = 2; +# Enable correct buffers + buff = 7; +; + +# submitted as bug #46020 +programmer + id = "tumpa"; + desc = "TIAO USB Multi-Protocol Adapter"; + type = "avrftdi"; + connection_type = usb; + usbvid = 0x0403; + usbpid = 0x8A98; + usbdev = "A"; + usbvendor = "TIAO"; + usbproduct = ""; + usbsn = ""; + sck = 0; # TCK 9 + mosi = 1; # TDI 5 + miso = 2; # TDO 13 + reset = 3; # TMS 7 +; + +programmer + id = "avrisp"; + desc = "Atmel AVR ISP"; + type = "stk500"; + connection_type = serial; +; + +programmer + id = "avrispv2"; + desc = "Atmel AVR ISP V2"; + type = "stk500v2"; + connection_type = serial; +; + +programmer + id = "avrispmkII"; + desc = "Atmel AVR ISP mkII"; + type = "stk500v2"; + connection_type = usb; +; + +programmer parent "avrispmkII" + id = "avrisp2"; +; + +programmer + id = "buspirate"; + desc = "The Bus Pirate"; + type = "buspirate"; + connection_type = serial; +; + +programmer + id = "buspirate_bb"; + desc = "The Bus Pirate (bitbang interface, supports TPI)"; + type = "buspirate_bb"; + connection_type = serial; + # pins are bits in bitbang byte (numbers are 87654321) + # 1|POWER|PULLUP|AUX|MOSI|CLK|MISO|CS + reset = 1; + sck = 3; + mosi = 4; + miso = 2; + #vcc = 7; This is internally set independent of this setting. +; + +# This is supposed to be the "default" STK500 entry. +# Attempts to select the correct firmware version +# by probing for it. Better use one of the entries +# below instead. +programmer + id = "stk500"; + desc = "Atmel STK500"; + type = "stk500generic"; + connection_type = serial; +; + +programmer + id = "stk500v1"; + desc = "Atmel STK500 Version 1.x firmware"; + type = "stk500"; + connection_type = serial; +; + +programmer + id = "mib510"; + desc = "Crossbow MIB510 programming board"; + type = "stk500"; + connection_type = serial; +; + +programmer + id = "stk500v2"; + desc = "Atmel STK500 Version 2.x firmware"; + type = "stk500v2"; + connection_type = serial; +; + +programmer + id = "stk500pp"; + desc = "Atmel STK500 V2 in parallel programming mode"; + type = "stk500pp"; + connection_type = serial; +; + +programmer + id = "stk500hvsp"; + desc = "Atmel STK500 V2 in high-voltage serial programming mode"; + type = "stk500hvsp"; + connection_type = serial; +; + +programmer + id = "stk600"; + desc = "Atmel STK600"; + type = "stk600"; + connection_type = usb; +; + +programmer + id = "stk600pp"; + desc = "Atmel STK600 in parallel programming mode"; + type = "stk600pp"; + connection_type = usb; +; + +programmer + id = "stk600hvsp"; + desc = "Atmel STK600 in high-voltage serial programming mode"; + type = "stk600hvsp"; + connection_type = usb; +; + +programmer + id = "avr910"; + desc = "Atmel Low Cost Serial Programmer"; + type = "avr910"; + connection_type = serial; +; + +programmer + id = "ft245r"; + desc = "FT245R Synchronous BitBang"; + type = "ftdi_syncbb"; + connection_type = usb; + miso = 1; # D1 + sck = 0; # D0 + mosi = 2; # D2 + reset = 4; # D4 +; + +programmer + id = "ft232r"; + desc = "FT232R Synchronous BitBang"; + type = "ftdi_syncbb"; + connection_type = usb; + miso = 1; # RxD + sck = 0; # TxD + mosi = 2; # RTS + reset = 4; # DTR +; + +# see http://www.bitwizard.nl/wiki/index.php/FTDI_ATmega +programmer + id = "bwmega"; + desc = "BitWizard ftdi_atmega builtin programmer"; + type = "ftdi_syncbb"; + connection_type = usb; + miso = 5; # DSR + sck = 6; # DCD + mosi = 3; # CTS + reset = 7; # RI +; + +# see http://www.geocities.jp/arduino_diecimila/bootloader/index_en.html +# Note: pins are numbered from 1! +programmer + id = "arduino-ft232r"; + desc = "Arduino: FT232R connected to ISP"; + type = "ftdi_syncbb"; + connection_type = usb; + miso = 3; # CTS X3(1) + sck = 5; # DSR X3(2) + mosi = 6; # DCD X3(3) + reset = 7; # RI X3(4) +; + +# website mentioned above uses this id +programmer parent "arduino-ft232r" + id = "diecimila"; + desc = "alias for arduino-ft232r"; +; + +# There is a ATmega328P kit PCB called "uncompatino". +# This board allows ISP via its on-board FT232R. +# This is designed like Arduino Duemilanove but has no standard ICPS header. +# Its 4 pairs of pins are shorted to enable ftdi_syncbb. +# http://akizukidenshi.com/catalog/g/gP-07487/ +# http://akizukidenshi.com/download/ds/akizuki/k6096_manual_20130816.pdf +programmer + id = "uncompatino"; + desc = "uncompatino with all pairs of pins shorted"; + type = "ftdi_syncbb"; + connection_type = usb; + miso = 3; # cts + sck = 5; # dsr + mosi = 6; # dcd + reset = 7; # ri +; + +# FTDI USB to serial cable TTL-232R-5V with a custom adapter for ICSP +# http://www.ftdichip.com/Products/Cables/USBTTLSerial.htm +# http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232R_CABLES.pdf +# For ICSP pinout see for example http://www.atmel.com/images/doc2562.pdf +# (Figure 1. ISP6PIN header pinout and Table 1. Connections required for ISP ...) +# TTL-232R GND 1 Black -> ICPS GND (pin 6) +# TTL-232R CTS 2 Brown -> ICPS MOSI (pin 4) +# TTL-232R VCC 3 Red -> ICPS VCC (pin 2) +# TTL-232R TXD 4 Orange -> ICPS RESET (pin 5) +# TTL-232R RXD 5 Yellow -> ICPS SCK (pin 3) +# TTL-232R RTS 6 Green -> ICPS MISO (pin 1) +# Except for VCC and GND, you can connect arbitual pairs as long as +# the following table is adjusted. +programmer + id = "ttl232r"; + desc = "FTDI TTL232R-5V with ICSP adapter"; + type = "ftdi_syncbb"; + connection_type = usb; + miso = 2; # rts + sck = 1; # rxd + mosi = 3; # cts + reset = 0; # txd +; + +programmer + id = "usbasp"; + desc = "USBasp, http://www.fischl.de/usbasp/"; + type = "usbasp"; + connection_type = usb; + usbvid = 0x16C0; # VOTI + usbpid = 0x05DC; # Obdev's free shared PID + usbvendor = "www.fischl.de"; + usbproduct = "USBasp"; + + # following variants are autodetected for id "usbasp" + + # original usbasp from fischl.de + # see above "usbasp" + + # old usbasp from fischl.de + #usbvid = 0x03EB; # ATMEL + #usbpid = 0xC7B4; # (unoffical) USBasp + #usbvendor = "www.fischl.de"; + #usbproduct = "USBasp"; + + # NIBObee (only if -P nibobee is given on command line) + # see below "nibobee" +; + +programmer + id = "nibobee"; + desc = "NIBObee"; + type = "usbasp"; + connection_type = usb; + usbvid = 0x16C0; # VOTI + usbpid = 0x092F; # NIBObee PID + usbvendor = "www.nicai-systems.com"; + usbproduct = "NIBObee"; +; + +programmer + id = "usbasp-clone"; + desc = "Any usbasp clone with correct VID/PID"; + type = "usbasp"; + connection_type = usb; + usbvid = 0x16C0; # VOTI + usbpid = 0x05DC; # Obdev's free shared PID + #usbvendor = ""; + #usbproduct = ""; +; + +# USBtiny can also be used for TPI programming. +# In that case, a resistor of 1 kOhm is needed between MISO and MOSI +# pins of the connector, and MISO (pin 1 of the 6-pin connector) +# connects to TPIDATA. +programmer + id = "usbtiny"; + desc = "USBtiny simple USB programmer, https://learn.adafruit.com/usbtinyisp"; + type = "usbtiny"; + connection_type = usb; + usbvid = 0x1781; + usbpid = 0x0c9f; +; + +# commercial version of USBtiny, using a separate VID/PID +programmer + id = "ehajo-isp"; + desc = "avr-isp-programmer from eHaJo, http://www.eHaJo.de"; + type = "usbtiny"; + connection_type = usb; + usbvid = 0x16D0; + usbpid = 0x0BA5; +; + +programmer + id = "butterfly"; + desc = "Atmel Butterfly Development Board"; + type = "butterfly"; + connection_type = serial; +; + +programmer + id = "avr109"; + desc = "Atmel AppNote AVR109 Boot Loader"; + type = "butterfly"; + connection_type = serial; +; + +programmer + id = "avr911"; + desc = "Atmel AppNote AVR911 AVROSP"; + type = "butterfly"; + connection_type = serial; +; + +# suggested in http://forum.mikrokopter.de/topic-post48317.html +programmer + id = "mkbutterfly"; + desc = "Mikrokopter.de Butterfly"; + type = "butterfly_mk"; + connection_type = serial; +; + +programmer parent "mkbutterfly" + id = "butterfly_mk"; +; + +programmer + id = "jtagmkI"; + desc = "Atmel JTAG ICE (mkI)"; + baudrate = 115200; # default is 115200 + type = "jtagmki"; + connection_type = serial; +; + +# easier to type +programmer parent "jtagmkI" + id = "jtag1"; +; + +# easier to type +programmer parent "jtag1" + id = "jtag1slow"; + baudrate = 19200; +; + +# The JTAG ICE mkII has both, serial and USB connectivity. As it is +# mostly used through USB these days (AVR Studio 5 only supporting it +# that way), we make connection_type = usb the default. Users are +# still free to use a serial port with the -P option. + +programmer + id = "jtagmkII"; + desc = "Atmel JTAG ICE mkII"; + baudrate = 19200; # default is 19200 + type = "jtagmkii"; + connection_type = usb; +; + +# easier to type +programmer parent "jtagmkII" + id = "jtag2slow"; +; + +# JTAG ICE mkII @ 115200 Bd +programmer parent "jtag2slow" + id = "jtag2fast"; + baudrate = 115200; +; + +# make the fast one the default, people will love that +programmer parent "jtag2fast" + id = "jtag2"; +; + +# JTAG ICE mkII in ISP mode +programmer + id = "jtag2isp"; + desc = "Atmel JTAG ICE mkII in ISP mode"; + baudrate = 115200; + type = "jtagmkii_isp"; + connection_type = usb; +; + +# JTAG ICE mkII in debugWire mode +programmer + id = "jtag2dw"; + desc = "Atmel JTAG ICE mkII in debugWire mode"; + baudrate = 115200; + type = "jtagmkii_dw"; + connection_type = usb; +; + +# JTAG ICE mkII in AVR32 mode +programmer + id = "jtagmkII_avr32"; + desc = "Atmel JTAG ICE mkII im AVR32 mode"; + baudrate = 115200; + type = "jtagmkii_avr32"; + connection_type = usb; +; + +# JTAG ICE mkII in AVR32 mode +programmer + id = "jtag2avr32"; + desc = "Atmel JTAG ICE mkII im AVR32 mode"; + baudrate = 115200; + type = "jtagmkii_avr32"; + connection_type = usb; +; + +# JTAG ICE mkII in PDI mode +programmer + id = "jtag2pdi"; + desc = "Atmel JTAG ICE mkII PDI mode"; + baudrate = 115200; + type = "jtagmkii_pdi"; + connection_type = usb; +; + +# AVR Dragon in JTAG mode +programmer + id = "dragon_jtag"; + desc = "Atmel AVR Dragon in JTAG mode"; + baudrate = 115200; + type = "dragon_jtag"; + connection_type = usb; +; + +# AVR Dragon in ISP mode +programmer + id = "dragon_isp"; + desc = "Atmel AVR Dragon in ISP mode"; + baudrate = 115200; + type = "dragon_isp"; + connection_type = usb; +; + +# AVR Dragon in PP mode +programmer + id = "dragon_pp"; + desc = "Atmel AVR Dragon in PP mode"; + baudrate = 115200; + type = "dragon_pp"; + connection_type = usb; +; + +# AVR Dragon in HVSP mode +programmer + id = "dragon_hvsp"; + desc = "Atmel AVR Dragon in HVSP mode"; + baudrate = 115200; + type = "dragon_hvsp"; + connection_type = usb; +; + +# AVR Dragon in debugWire mode +programmer + id = "dragon_dw"; + desc = "Atmel AVR Dragon in debugWire mode"; + baudrate = 115200; + type = "dragon_dw"; + connection_type = usb; +; + +# AVR Dragon in PDI mode +programmer + id = "dragon_pdi"; + desc = "Atmel AVR Dragon in PDI mode"; + baudrate = 115200; + type = "dragon_pdi"; + connection_type = usb; +; + +programmer + id = "jtag3"; + desc = "Atmel AVR JTAGICE3 in JTAG mode"; + type = "jtagice3"; + connection_type = usb; + usbpid = 0x2110, 0x2140; +; + +programmer + id = "jtag3pdi"; + desc = "Atmel AVR JTAGICE3 in PDI mode"; + type = "jtagice3_pdi"; + connection_type = usb; + usbpid = 0x2110, 0x2140; +; + +programmer + id = "jtag3dw"; + desc = "Atmel AVR JTAGICE3 in debugWIRE mode"; + type = "jtagice3_dw"; + connection_type = usb; + usbpid = 0x2110, 0x2140; +; + +programmer + id = "jtag3isp"; + desc = "Atmel AVR JTAGICE3 in ISP mode"; + type = "jtagice3_isp"; + connection_type = usb; + usbpid = 0x2110, 0x2140; +; + +programmer + id = "xplainedpro"; + desc = "Atmel AVR XplainedPro in JTAG mode"; + type = "jtagice3"; + connection_type = usb; + usbpid = 0x2111; +; + +programmer + id = "xplainedmini"; + desc = "Atmel AVR XplainedMini in ISP mode"; + type = "jtagice3_isp"; + connection_type = usb; + usbpid = 0x2145; +; + +programmer + id = "xplainedmini_dw"; + desc = "Atmel AVR XplainedMini in debugWIRE mode"; + type = "jtagice3_dw"; + connection_type = usb; + usbpid = 0x2145; +; + +programmer + id = "atmelice"; + desc = "Atmel-ICE (ARM/AVR) in JTAG mode"; + type = "jtagice3"; + connection_type = usb; + usbpid = 0x2141; +; + +programmer + id = "atmelice_pdi"; + desc = "Atmel-ICE (ARM/AVR) in PDI mode"; + type = "jtagice3_pdi"; + connection_type = usb; + usbpid = 0x2141; +; + +programmer + id = "atmelice_dw"; + desc = "Atmel-ICE (ARM/AVR) in debugWIRE mode"; + type = "jtagice3_dw"; + connection_type = usb; + usbpid = 0x2141; +; + +programmer + id = "atmelice_isp"; + desc = "Atmel-ICE (ARM/AVR) in ISP mode"; + type = "jtagice3_isp"; + connection_type = usb; + usbpid = 0x2141; +; + +programmer + id = "powerdebugger"; + desc = "Atmel PowerDebugger (ARM/AVR) in JTAG mode"; + type = "jtagice3"; + connection_type = usb; + usbpid = 0x2144; +; + +programmer + id = "powerdebugger_pdi"; + desc = "Atmel PowerDebugger (ARM/AVR) in PDI mode"; + type = "jtagice3_pdi"; + connection_type = usb; + usbpid = 0x2144; +; + +programmer + id = "powerdebugger_dw"; + desc = "Atmel PowerDebugger (ARM/AVR) in debugWire mode"; + type = "jtagice3_dw"; + connection_type = usb; + usbpid = 0x2144; +; + +programmer + id = "powerdebugger_isp"; + desc = "Atmel PowerDebugger (ARM/AVR) in ISP mode"; + type = "jtagice3_isp"; + connection_type = usb; + usbpid = 0x2144; +; + +programmer + id = "pavr"; + desc = "Jason Kyle's pAVR Serial Programmer"; + type = "avr910"; + connection_type = serial; +; + +programmer + id = "pickit2"; + desc = "MicroChip's PICkit2 Programmer"; + type = "pickit2"; + connection_type = usb; +; + +programmer + id = "flip1"; + desc = "FLIP USB DFU protocol version 1 (doc7618)"; + type = "flip1"; + connection_type = usb; +; + +programmer + id = "flip2"; + desc = "FLIP USB DFU protocol version 2 (AVR4023)"; + type = "flip2"; + connection_type = usb; +; + +#@HAVE_PARPORT_BEGIN@ Inclusion of the following depends on --enable-parport +# Parallel port programmers. + +programmer + id = "bsd"; + desc = "Brian Dean's Programmer, http://www.bsdhome.com/avrdude/"; + type = "par"; + connection_type = parallel; + vcc = 2, 3, 4, 5; + reset = 7; + sck = 8; + mosi = 9; + miso = 10; +; + +programmer + id = "stk200"; + desc = "STK200"; + type = "par"; + connection_type = parallel; + buff = 4, 5; + sck = 6; + mosi = 7; + reset = 9; + miso = 10; +; + +# The programming dongle used by the popular Ponyprog +# utility. It is almost similar to the STK200 one, +# except that there is a LED indicating that the +# programming is currently in progress. + +programmer parent "stk200" + id = "pony-stk200"; + desc = "Pony Prog STK200"; + pgmled = 8; +; + +programmer + id = "dt006"; + desc = "Dontronics DT006"; + type = "par"; + connection_type = parallel; + reset = 4; + sck = 5; + mosi = 2; + miso = 11; +; + +programmer parent "dt006" + id = "bascom"; + desc = "Bascom SAMPLE programming cable"; +; + +programmer + id = "alf"; + desc = "Nightshade ALF-PgmAVR, http://nightshade.homeip.net/"; + type = "par"; + connection_type = parallel; + vcc = 2, 3, 4, 5; + buff = 6; + reset = 7; + sck = 8; + mosi = 9; + miso = 10; + errled = 1; + rdyled = 14; + pgmled = 16; + vfyled = 17; +; + +programmer + id = "sp12"; + desc = "Steve Bolt's Programmer"; + type = "par"; + connection_type = parallel; + vcc = 4,5,6,7,8; + reset = 3; + sck = 2; + mosi = 9; + miso = 11; +; + +programmer + id = "picoweb"; + desc = "Picoweb Programming Cable, http://www.picoweb.net/"; + type = "par"; + connection_type = parallel; + reset = 2; + sck = 3; + mosi = 4; + miso = 13; +; + +programmer + id = "abcmini"; + desc = "ABCmini Board, aka Dick Smith HOTCHIP"; + type = "par"; + connection_type = parallel; + reset = 4; + sck = 3; + mosi = 2; + miso = 10; +; + +programmer + id = "futurlec"; + desc = "Futurlec.com programming cable."; + type = "par"; + connection_type = parallel; + reset = 3; + sck = 2; + mosi = 1; + miso = 10; +; + + +# From the contributor of the "xil" jtag cable: +# The "vcc" definition isn't really vcc (the cable gets its power from +# the programming circuit) but is necessary to switch one of the +# buffer lines (trying to add it to the "buff" lines doesn't work in +# avrdude versions before 5.5j). +# With this, TMS connects to RESET, TDI to MOSI, TDO to MISO and TCK +# to SCK (plus vcc/gnd of course) +programmer + id = "xil"; + desc = "Xilinx JTAG cable"; + type = "par"; + connection_type = parallel; + mosi = 2; + sck = 3; + reset = 4; + buff = 5; + miso = 13; + vcc = 6; +; + + +programmer + id = "dapa"; + desc = "Direct AVR Parallel Access cable"; + type = "par"; + connection_type = parallel; + vcc = 3; + reset = 16; + sck = 1; + mosi = 2; + miso = 11; +; + +programmer + id = "atisp"; + desc = "AT-ISP V1.1 programming cable for AVR-SDK1 from micro-research.co.th"; + type = "par"; + connection_type = parallel; + reset = ~6; + sck = ~8; + mosi = ~7; + miso = ~10; +; + +programmer + id = "ere-isp-avr"; + desc = "ERE ISP-AVR "; + type = "par"; + connection_type = parallel; + reset = ~4; + sck = 3; + mosi = 2; + miso = 10; +; + +programmer + id = "blaster"; + desc = "Altera ByteBlaster"; + type = "par"; + connection_type = parallel; + sck = 2; + miso = 11; + reset = 3; + mosi = 8; + buff = 14; +; + +# It is almost same as pony-stk200, except vcc on pin 5 to auto +# disconnect port (download on http://electropol.free.fr/spip/spip.php?article27) +programmer parent "pony-stk200" + id = "frank-stk200"; + desc = "Frank STK200"; + buff = ; # delete buff pin assignment + vcc = 5; +; + +# The AT98ISP Cable is a simple parallel dongle for AT89 family. +# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=2877 +programmer + id = "89isp"; + desc = "Atmel at89isp cable"; + type = "par"; + connection_type = parallel; + reset = 17; + sck = 1; + mosi = 2; + miso = 10; +; + +#@HAVE_PARPORT_END@ + +#This programmer bitbangs GPIO lines using the Linux sysfs GPIO interface +# +#To enable it set the configuration below to match the GPIO lines connected to the +#relevant ISP header pins and uncomment the entry definition. In case you don't +#have the required permissions to edit this system wide config file put the +#entry in a separate .conf file and use it with -C+.conf +#on the command line. +# +#To check if your avrdude build has support for the linuxgpio programmer compiled in, +#use -c?type on the command line and look for linuxgpio in the list. If it's not available +#you need pass the --enable-linuxgpio=yes option to configure and recompile avrdude. +# +#programmer +# id = "linuxgpio"; +# desc = "Use the Linux sysfs interface to bitbang GPIO lines"; +# type = "linuxgpio"; +# reset = ?; +# sck = ?; +# mosi = ?; +# miso = ?; +#; + +# some ultra cheap programmers use bitbanging on the +# serialport. +# +# PC - DB9 - Pins for RS232: +# +# GND 5 -- |O +# | O| <- 9 RI +# DTR 4 <- |O | +# | O| <- 8 CTS +# TXD 3 <- |O | +# | O| -> 7 RTS +# RXD 2 -> |O | +# | O| <- 6 DSR +# DCD 1 -> |O +# +# Using RXD is currently not supported. +# Using RI is not supported under Win32 but is supported under Posix. + +# serial ponyprog design (dasa2 in uisp) +# reset=!txd sck=rts mosi=dtr miso=cts + +programmer + id = "ponyser"; + desc = "design ponyprog serial, reset=!txd sck=rts mosi=dtr miso=cts"; + type = "serbb"; + connection_type = serial; + reset = ~3; + sck = 7; + mosi = 4; + miso = 8; +; + +# Same as above, different name +# reset=!txd sck=rts mosi=dtr miso=cts + +programmer parent "ponyser" + id = "siprog"; + desc = "Lancos SI-Prog "; +; + +# unknown (dasa in uisp) +# reset=rts sck=dtr mosi=txd miso=cts + +programmer + id = "dasa"; + desc = "serial port banging, reset=rts sck=dtr mosi=txd miso=cts"; + type = "serbb"; + connection_type = serial; + reset = 7; + sck = 4; + mosi = 3; + miso = 8; +; + +# unknown (dasa3 in uisp) +# reset=!dtr sck=rts mosi=txd miso=cts + +programmer + id = "dasa3"; + desc = "serial port banging, reset=!dtr sck=rts mosi=txd miso=cts"; + type = "serbb"; + connection_type = serial; + reset = ~4; + sck = 7; + mosi = 3; + miso = 8; +; + +# C2N232i (jumper configuration "auto") +# reset=dtr sck=!rts mosi=!txd miso=!cts + +programmer + id = "c2n232i"; + desc = "serial port banging, reset=dtr sck=!rts mosi=!txd miso=!cts"; + type = "serbb"; + connection_type = serial; + reset = 4; + sck = ~7; + mosi = ~3; + miso = ~8; +; + +# +# PART DEFINITIONS +# + +#------------------------------------------------------------ +# ATtiny11 +#------------------------------------------------------------ + +# This is an HVSP-only device. + +part + id = "t11"; + desc = "ATtiny11"; + stk500_devcode = 0x11; + signature = 0x1e 0x90 0x04; + chip_erase_delay = 20000; + + timeout = 200; + hvsp_controlstack = + 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x00, + 0x68, 0x78, 0x68, 0x68, 0x00, 0x00, 0x68, 0x78, + 0x78, 0x00, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, + 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + hvspcmdexedelay = 0; + synchcycles = 6; + latchcycles = 1; + togglevtg = 1; + poweroffdelay = 25; + resetdelayms = 0; + resetdelayus = 50; + hvleavestabdelay = 100; + resetdelay = 25; + chiperasepolltimeout = 40; + chiperasetime = 0; + programfusepolltimeout = 25; + programlockpolltimeout = 25; + + memory "eeprom" + size = 64; + blocksize = 64; + readsize = 256; + delay = 5; + ; + + memory "flash" + size = 1024; + blocksize = 128; + readsize = 256; + delay = 3; + ; + + memory "signature" + size = 3; + ; + + memory "lock" + size = 1; + ; + + memory "calibration" + size = 1; + ; + + memory "fuse" + size = 1; + ; +; + +#------------------------------------------------------------ +# ATtiny12 +#------------------------------------------------------------ + +part + id = "t12"; + desc = "ATtiny12"; + stk500_devcode = 0x12; + avr910_devcode = 0x55; + signature = 0x1e 0x90 0x05; + chip_erase_delay = 20000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + hvsp_controlstack = + 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x00, + 0x68, 0x78, 0x68, 0x68, 0x00, 0x00, 0x68, 0x78, + 0x78, 0x00, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, + 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; + hventerstabdelay = 100; + hvspcmdexedelay = 0; + synchcycles = 6; + latchcycles = 1; + togglevtg = 1; + poweroffdelay = 25; + resetdelayms = 0; + resetdelayus = 50; + hvleavestabdelay = 100; + resetdelay = 25; + chiperasepolltimeout = 40; + chiperasetime = 0; + programfusepolltimeout = 25; + programlockpolltimeout = 25; + + memory "eeprom" + size = 64; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 x x x x x x x x", + "x x a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 x x x x x x x x", + "x x a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + mode = 0x04; + delay = 8; + blocksize = 64; + readsize = 256; + ; + + memory "flash" + size = 1024; + min_write_delay = 4500; + max_write_delay = 20000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + write_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 5; + blocksize = 128; + readsize = 256; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x x x x x x o o x"; + + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "fuse" + size = 1; + read = "0 1 0 1 0 0 0 0 x x x x x x x x", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 x x x x x", + "x x x x x x x x i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; +; + +#------------------------------------------------------------ +# ATtiny13 +#------------------------------------------------------------ + +part + id = "t13"; + desc = "ATtiny13"; + has_debugwire = yes; + flash_instr = 0xB4, 0x0E, 0x1E; + eeprom_instr = 0xBB, 0xFE, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBC, 0x0E, 0xB4, 0x0E, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; + stk500_devcode = 0x14; + signature = 0x1e 0x90 0x07; + chip_erase_delay = 4000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + hvsp_controlstack = + 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, + 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, + 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, + 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + hvspcmdexedelay = 0; + synchcycles = 6; + latchcycles = 1; + togglevtg = 1; + poweroffdelay = 25; + resetdelayms = 0; + resetdelayus = 90; + hvleavestabdelay = 100; + resetdelay = 25; + chiperasepolltimeout = 40; + chiperasetime = 0; + programfusepolltimeout = 25; + programlockpolltimeout = 25; + + ocdrev = 0; + + memory "eeprom" + size = 64; + page_size = 4; + min_write_delay = 4000; + max_write_delay = 4000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", + "x x a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", + "x x a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " x x a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 5; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 1024; + page_size = 32; + num_pages = 32; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 0 0 0 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 0 0 0 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x x a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x x a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 0 0 0 a8", + " a7 a6 a5 a4 x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 32; + readsize = 256; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + + memory "lock" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "calibration" + size = 2; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 a0 o o o o o o o o"; + ; + + memory "lfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + ; + +; + + +#------------------------------------------------------------ +# ATtiny15 +#------------------------------------------------------------ + +part + id = "t15"; + desc = "ATtiny15"; + stk500_devcode = 0x13; + avr910_devcode = 0x56; + signature = 0x1e 0x90 0x06; + chip_erase_delay = 8200; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + hvsp_controlstack = + 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x00, + 0x68, 0x78, 0x68, 0x68, 0x00, 0x00, 0x68, 0x78, + 0x78, 0x00, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, + 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; + hventerstabdelay = 100; + hvspcmdexedelay = 5; + synchcycles = 6; + latchcycles = 16; + togglevtg = 1; + poweroffdelay = 25; + resetdelayms = 0; + resetdelayus = 50; + hvleavestabdelay = 100; + resetdelay = 25; + chiperasepolltimeout = 40; + chiperasetime = 0; + programfusepolltimeout = 25; + programlockpolltimeout = 25; + + memory "eeprom" + size = 64; + min_write_delay = 8200; + max_write_delay = 8200; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 x x x x x x x x", + "x x a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 x x x x x x x x", + "x x a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + mode = 0x04; + delay = 10; + blocksize = 64; + readsize = 256; + ; + + memory "flash" + size = 1024; + min_write_delay = 4100; + max_write_delay = 4100; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + write_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 5; + blocksize = 128; + readsize = 256; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x x x x x x o o x"; + + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "fuse" + size = 1; + read = "0 1 0 1 0 0 0 0 x x x x x x x x", + "x x x x x x x x o o o o x x o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 x x x x x", + "x x x x x x x x i i i i 1 1 i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; +; + +#------------------------------------------------------------ +# AT90s1200 +#------------------------------------------------------------ + +part + id = "1200"; + desc = "AT90S1200"; + is_at90s1200 = yes; + stk500_devcode = 0x33; + avr910_devcode = 0x13; + signature = 0x1e 0x90 0x01; + pagel = 0xd7; + bs2 = 0xa0; + chip_erase_delay = 20000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 1; + bytedelay = 0; + pollindex = 0; + pollvalue = 0xFF; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 0; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 15; + chiperasepolltimeout = 0; + programfusepulsewidth = 2; + programfusepolltimeout = 0; + programlockpulsewidth = 0; + programlockpolltimeout = 1; + + memory "eeprom" + size = 64; + min_write_delay = 4000; + max_write_delay = 9000; + readback_p1 = 0x00; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 x x x x x x x x", + "x x a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 x x x x x x x x", + "x x a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + mode = 0x04; + delay = 20; + blocksize = 32; + readsize = 256; + ; + memory "flash" + size = 1024; + min_write_delay = 4000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + write_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x02; + delay = 15; + blocksize = 128; + readsize = 256; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "fuse" + size = 1; + ; + memory "lock" + size = 1; + min_write_delay = 9000; + max_write_delay = 20000; + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", + "x x x x x x x x x x x x x x x x"; + ; + ; + +#------------------------------------------------------------ +# AT90s4414 +#------------------------------------------------------------ + +part + id = "4414"; + desc = "AT90S4414"; + stk500_devcode = 0x50; + avr910_devcode = 0x28; + signature = 0x1e 0x92 0x01; + chip_erase_delay = 20000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 0; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 15; + chiperasepolltimeout = 0; + programfusepulsewidth = 2; + programfusepolltimeout = 0; + programlockpulsewidth = 0; + programlockpolltimeout = 1; + + memory "eeprom" + size = 256; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0x80; + readback_p2 = 0x7f; + read = " 1 0 1 0 0 0 0 0 x x x x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0 x x x x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 64; + readsize = 256; + ; + memory "flash" + size = 4096; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0x7f; + readback_p2 = 0x7f; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write_lo = " 0 1 0 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + write_hi = " 0 1 0 0 1 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 64; + readsize = 256; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "fuse" + size = 1; + ; + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + ; + +#------------------------------------------------------------ +# AT90s2313 +#------------------------------------------------------------ + +part + id = "2313"; + desc = "AT90S2313"; + stk500_devcode = 0x40; + avr910_devcode = 0x20; + signature = 0x1e 0x91 0x01; + chip_erase_delay = 20000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 0; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 15; + chiperasepolltimeout = 0; + programfusepulsewidth = 2; + programfusepolltimeout = 0; + programlockpulsewidth = 0; + programlockpolltimeout = 1; + + memory "eeprom" + size = 128; + min_write_delay = 4000; + max_write_delay = 9000; + readback_p1 = 0x80; + readback_p2 = 0x7f; + read = "1 0 1 0 0 0 0 0 x x x x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 x x x x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 64; + readsize = 256; + ; + memory "flash" + size = 2048; + min_write_delay = 4000; + max_write_delay = 9000; + readback_p1 = 0x7f; + readback_p2 = 0x7f; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + write_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 128; + readsize = 256; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "fuse" + size = 1; + ; + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 x x i i x", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + ; + +#------------------------------------------------------------ +# AT90s2333 +#------------------------------------------------------------ + +part + id = "2333"; +##### WARNING: No XML file for device 'AT90S2333'! ##### + desc = "AT90S2333"; + stk500_devcode = 0x42; + avr910_devcode = 0x34; + signature = 0x1e 0x91 0x05; + chip_erase_delay = 20000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 0; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 15; + chiperasepolltimeout = 0; + programfusepulsewidth = 2; + programfusepolltimeout = 0; + programlockpulsewidth = 0; + programlockpolltimeout = 1; + + memory "eeprom" + size = 128; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0x00; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 x x x x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 x x x x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 128; + readsize = 256; + ; + + memory "flash" + size = 2048; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + write_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 128; + readsize = 256; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "fuse" + size = 1; + min_write_delay = 9000; + max_write_delay = 20000; + pwroff_after_write = yes; + read = "0 1 0 1 0 0 0 0 x x x x x x x x", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 i i i i i", + "x x x x x x x x x x x x x x x x"; + ; + memory "lock" + size = 1; + min_write_delay = 9000; + max_write_delay = 20000; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x x x x x x o o x"; + + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", + "x x x x x x x x x x x x x x x x"; + ; + ; + + +#------------------------------------------------------------ +# AT90s2343 (also AT90s2323 and ATtiny22) +#------------------------------------------------------------ + +part + id = "2343"; + desc = "AT90S2343"; + stk500_devcode = 0x43; + avr910_devcode = 0x4c; + signature = 0x1e 0x91 0x03; + chip_erase_delay = 18000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + hvsp_controlstack = + 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x00, + 0x68, 0x78, 0x68, 0x68, 0x00, 0x00, 0x68, 0x78, + 0x78, 0x00, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, + 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; + hventerstabdelay = 100; + hvspcmdexedelay = 0; + synchcycles = 6; + latchcycles = 1; + togglevtg = 0; + poweroffdelay = 25; + resetdelayms = 0; + resetdelayus = 50; + hvleavestabdelay = 100; + resetdelay = 25; + chiperasepolltimeout = 40; + chiperasetime = 0; + programfusepolltimeout = 25; + programlockpolltimeout = 25; + + memory "eeprom" + size = 128; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0x00; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0", + "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0", + "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 64; + readsize = 256; + ; + memory "flash" + size = 2048; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + write_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 128; + readsize = 128; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "fuse" + size = 1; + min_write_delay = 9000; + max_write_delay = 20000; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x o o o x x x x o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 i", + "x x x x x x x x x x x x x x x x"; + ; + memory "lock" + size = 1; + min_write_delay = 9000; + max_write_delay = 20000; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x o o o x x x x o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", + "x x x x x x x x x x x x x x x x"; + ; + ; + + +#------------------------------------------------------------ +# AT90s4433 +#------------------------------------------------------------ + +part + id = "4433"; + desc = "AT90S4433"; + stk500_devcode = 0x51; + avr910_devcode = 0x30; + signature = 0x1e 0x92 0x03; + chip_erase_delay = 20000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 0; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 15; + chiperasepolltimeout = 0; + programfusepulsewidth = 2; + programfusepolltimeout = 0; + programlockpulsewidth = 0; + programlockpolltimeout = 1; + + memory "eeprom" + size = 256; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0x00; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0 x x x x x x x x", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0 x x x x x x x x", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 128; + readsize = 256; + ; + memory "flash" + size = 4096; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write_lo = " 0 1 0 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + write_hi = " 0 1 0 0 1 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 128; + readsize = 256; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "fuse" + size = 1; + min_write_delay = 9000; + max_write_delay = 20000; + pwroff_after_write = yes; + read = "0 1 0 1 0 0 0 0 x x x x x x x x", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 i i i i i", + "x x x x x x x x x x x x x x x x"; + ; + memory "lock" + size = 1; + min_write_delay = 9000; + max_write_delay = 20000; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x x x x x x o o x"; + + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", + "x x x x x x x x x x x x x x x x"; + ; + ; + +#------------------------------------------------------------ +# AT90s4434 +#------------------------------------------------------------ + +part + id = "4434"; +##### WARNING: No XML file for device 'AT90S4434'! ##### + desc = "AT90S4434"; + stk500_devcode = 0x52; + avr910_devcode = 0x6c; + signature = 0x1e 0x92 0x02; + chip_erase_delay = 20000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + memory "eeprom" + size = 256; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0x00; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0 x x x x x x x x", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0 x x x x x x x x", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + ; + memory "flash" + size = 4096; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write_lo = " 0 1 0 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + write_hi = " 0 1 0 0 1 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "fuse" + size = 1; + min_write_delay = 9000; + max_write_delay = 20000; + read = "0 1 0 1 0 0 0 0 x x x x x x x x", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 i i i i i", + "x x x x x x x x x x x x x x x x"; + ; + memory "lock" + size = 1; + min_write_delay = 9000; + max_write_delay = 20000; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x x x x x x o o x"; + + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", + "x x x x x x x x x x x x x x x x"; + ; + ; + +#------------------------------------------------------------ +# AT90s8515 +#------------------------------------------------------------ + +part + id = "8515"; + desc = "AT90S8515"; + stk500_devcode = 0x60; + avr910_devcode = 0x38; + signature = 0x1e 0x93 0x01; + chip_erase_delay = 20000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 0; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + resetdelay = 15; + chiperasepulsewidth = 15; + chiperasepolltimeout = 0; + programfusepulsewidth = 2; + programfusepolltimeout = 0; + programlockpulsewidth = 0; + programlockpolltimeout = 1; + + memory "eeprom" + size = 512; + min_write_delay = 4000; + max_write_delay = 9000; + readback_p1 = 0x80; + readback_p2 = 0x7f; + read = " 1 0 1 0 0 0 0 0 x x x x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0 x x x x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 128; + readsize = 256; + ; + memory "flash" + size = 8192; + min_write_delay = 4000; + max_write_delay = 9000; + readback_p1 = 0x7f; + readback_p2 = 0x7f; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write_lo = " 0 1 0 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + write_hi = " 0 1 0 0 1 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 128; + readsize = 256; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "fuse" + size = 1; + ; + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + ; + +#------------------------------------------------------------ +# AT90s8535 +#------------------------------------------------------------ + +part + id = "8535"; + desc = "AT90S8535"; + stk500_devcode = 0x61; + avr910_devcode = 0x68; + signature = 0x1e 0x93 0x03; + chip_erase_delay = 20000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 0; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 15; + chiperasepolltimeout = 0; + programfusepulsewidth = 2; + programfusepolltimeout = 0; + programlockpulsewidth = 0; + programlockpolltimeout = 1; + + memory "eeprom" + size = 512; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0x00; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0 x x x x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0 x x x x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 128; + readsize = 256; + ; + memory "flash" + size = 8192; + min_write_delay = 9000; + max_write_delay = 20000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write_lo = " 0 1 0 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + write_hi = " 0 1 0 0 1 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 128; + readsize = 256; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "fuse" + size = 1; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x x x x x x x x o"; + write = "1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 i", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x o o x x x x x x"; + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + ; + +#------------------------------------------------------------ +# ATmega103 +#------------------------------------------------------------ + +part + id = "m103"; + desc = "ATmega103"; + stk500_devcode = 0xB1; + avr910_devcode = 0x41; + signature = 0x1e 0x97 0x01; + chip_erase_delay = 112000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x8E, 0x9E, 0x2E, 0x3E, 0xAE, 0xBE, + 0x4E, 0x5E, 0xCE, 0xDE, 0x6E, 0x7E, 0xEE, 0xDE, + 0x66, 0x76, 0xE6, 0xF6, 0x6A, 0x7A, 0xEA, 0x7A, + 0x7F, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 0; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 15; + chiperasepolltimeout = 0; + programfusepulsewidth = 2; + programfusepolltimeout = 0; + programlockpulsewidth = 0; + programlockpolltimeout = 10; + + memory "eeprom" + size = 4096; + min_write_delay = 4000; + max_write_delay = 9000; + readback_p1 = 0x80; + readback_p2 = 0x7f; + read = " 1 0 1 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 64; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 131072; + page_size = 256; + num_pages = 512; + min_write_delay = 22000; + max_write_delay = 56000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x11; + delay = 70; + blocksize = 256; + readsize = 256; + ; + + memory "fuse" + size = 1; + read = "0 1 0 1 0 0 0 0 x x x x x x x x", + "x x x x x x x x x x o x o 1 o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 1 i 1 i i", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x x x x x x o o x"; + + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + + +#------------------------------------------------------------ +# ATmega64 +#------------------------------------------------------------ + +part + id = "m64"; + desc = "ATmega64"; + has_jtag = yes; + stk500_devcode = 0xA0; + avr910_devcode = 0x45; + signature = 0x1e 0x96 0x02; + chip_erase_delay = 9000; + pagel = 0xD7; + bs2 = 0xA0; + reset = dedicated; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 6; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x22; + spmcr = 0x68; + allowfullpagebitstream = yes; + + ocdrev = 2; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 2048; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 20; + blocksize = 64; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 65536; + page_size = 256; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " x a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x21; + delay = 6; + blocksize = 128; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 4; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + + + + +#------------------------------------------------------------ +# ATmega128 +#------------------------------------------------------------ + +part + id = "m128"; + desc = "ATmega128"; + has_jtag = yes; + stk500_devcode = 0xB2; + avr910_devcode = 0x43; + signature = 0x1e 0x97 0x02; + chip_erase_delay = 9000; + pagel = 0xD7; + bs2 = 0xA0; + reset = dedicated; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 6; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x22; + spmcr = 0x68; + rampz = 0x3b; + allowfullpagebitstream = yes; + + ocdrev = 1; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 4096; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 12; + blocksize = 64; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 131072; + page_size = 256; + num_pages = 512; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x21; + delay = 6; + blocksize = 128; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 4; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# AT90CAN128 +#------------------------------------------------------------ + +part + id = "c128"; + desc = "AT90CAN128"; + has_jtag = yes; + stk500_devcode = 0xB3; +# avr910_devcode = 0x43; + signature = 0x1e 0x97 0x81; + chip_erase_delay = 9000; + pagel = 0xD7; + bs2 = 0xA0; + reset = dedicated; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 6; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + rampz = 0x3b; + eecr = 0x3f; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 4096; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + + mode = 0x41; + delay = 20; + blocksize = 8; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 131072; + page_size = 256; + num_pages = 512; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 256; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# AT90CAN64 +#------------------------------------------------------------ + +part + id = "c64"; + desc = "AT90CAN64"; + has_jtag = yes; + stk500_devcode = 0xB3; +# avr910_devcode = 0x43; + signature = 0x1e 0x96 0x81; + chip_erase_delay = 9000; + pagel = 0xD7; + bs2 = 0xA0; + reset = dedicated; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 6; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + rampz = 0x3b; + eecr = 0x3f; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 2048; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + + mode = 0x41; + delay = 20; + blocksize = 8; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 65536; + page_size = 256; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 256; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# AT90CAN32 +#------------------------------------------------------------ + +part + id = "c32"; + desc = "AT90CAN32"; + has_jtag = yes; + stk500_devcode = 0xB3; +# avr910_devcode = 0x43; + signature = 0x1e 0x95 0x81; + chip_erase_delay = 9000; + pagel = 0xD7; + bs2 = 0xA0; + reset = dedicated; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 6; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + rampz = 0x3b; + eecr = 0x3f; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 1024; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + + mode = 0x41; + delay = 20; + blocksize = 8; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 32768; + page_size = 256; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 256; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + + +#------------------------------------------------------------ +# ATmega16 +#------------------------------------------------------------ + +part + id = "m16"; + desc = "ATmega16"; + has_jtag = yes; + stk500_devcode = 0x82; + avr910_devcode = 0x74; + signature = 0x1e 0x94 0x03; + pagel = 0xd7; + bs2 = 0xa0; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 100; + latchcycles = 6; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + resetdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + allowfullpagebitstream = yes; + + ocdrev = 2; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 512; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x04; + delay = 10; + blocksize = 128; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 16384; + page_size = 128; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x21; + delay = 6; + blocksize = 128; + readsize = 256; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "calibration" + size = 4; + + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + ; + + +#------------------------------------------------------------ +# ATmega164P +#------------------------------------------------------------ + +# close to ATmega16 + +part parent "m16" + id = "m164p"; + desc = "ATmega164P"; + signature = 0x1e 0x94 0x0a; + + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + allowfullpagebitstream = no; + chip_erase_delay = 55000; + + ocdrev = 3; + ; + + +#------------------------------------------------------------ +# ATmega324P +#------------------------------------------------------------ + +# similar to ATmega164P + +part + id = "m324p"; + desc = "ATmega324P"; + has_jtag = yes; + stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one + avr910_devcode = 0x74; + signature = 0x1e 0x95 0x08; + pagel = 0xd7; + bs2 = 0xa0; + chip_erase_delay = 55000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 1024; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 128; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 32768; + page_size = 128; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x21; + delay = 6; + blocksize = 256; + readsize = 256; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x 1 1 1 1 1 i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + + memory "calibration" + size = 1; + + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + ; + + +#------------------------------------------------------------ +# ATmega324PA +#------------------------------------------------------------ + +# similar to ATmega324P + +part parent "m324p" + id = "m324pa"; + desc = "ATmega324PA"; + signature = 0x1e 0x95 0x11; + + ocdrev = 3; + ; + + +#------------------------------------------------------------ +# ATmega644 +#------------------------------------------------------------ + +# similar to ATmega164 + +part + id = "m644"; + desc = "ATmega644"; + has_jtag = yes; + stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one + avr910_devcode = 0x74; + signature = 0x1e 0x96 0x09; + pagel = 0xd7; + bs2 = 0xa0; + chip_erase_delay = 55000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 6; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 2048; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 128; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 65536; + page_size = 256; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x21; + delay = 6; + blocksize = 256; + readsize = 256; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x 1 1 1 1 1 i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + + memory "calibration" + size = 1; + + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega644P +#------------------------------------------------------------ + +# similar to ATmega164p + +part parent "m644" + id = "m644p"; + desc = "ATmega644P"; + signature = 0x1e 0x96 0x0a; + + ocdrev = 3; + ; + + + +#------------------------------------------------------------ +# ATmega1284 +#------------------------------------------------------------ + +# similar to ATmega164 + +part + id = "m1284"; + desc = "ATmega1284"; + has_jtag = yes; + stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one + avr910_devcode = 0x74; + signature = 0x1e 0x97 0x06; + pagel = 0xd7; + bs2 = 0xa0; + chip_erase_delay = 55000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 6; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 4096; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 128; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 131072; + page_size = 256; + num_pages = 512; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 256; + readsize = 256; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x 1 1 1 1 1 i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + + memory "calibration" + size = 1; + + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + ; + + + +#------------------------------------------------------------ +# ATmega1284P +#------------------------------------------------------------ + +# similar to ATmega164p + +part + id = "m1284p"; + desc = "ATmega1284P"; + has_jtag = yes; + stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one + avr910_devcode = 0x74; + signature = 0x1e 0x97 0x05; + pagel = 0xd7; + bs2 = 0xa0; + chip_erase_delay = 55000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 6; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 4096; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 128; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 131072; + page_size = 256; + num_pages = 512; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 256; + readsize = 256; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x 1 1 1 1 1 i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + + memory "calibration" + size = 1; + + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + ; + + + +#------------------------------------------------------------ +# ATmega162 +#------------------------------------------------------------ + +part + id = "m162"; + desc = "ATmega162"; + has_jtag = yes; + stk500_devcode = 0x83; + avr910_devcode = 0x63; + signature = 0x1e 0x94 0x04; + chip_erase_delay = 9000; + pagel = 0xd7; + bs2 = 0xa0; + + idr = 0x04; + spmcr = 0x57; + allowfullpagebitstream = yes; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + ocdrev = 2; + + memory "flash" + paged = yes; + size = 16384; + page_size = 128; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + mode = 0x41; + delay = 10; + blocksize = 128; + readsize = 256; + + ; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 6; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 512; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + + read = " 1 0 1 0 0 0 0 0", + " 0 0 x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + + memory "lfuse" + size = 1; + min_write_delay = 16000; + max_write_delay = 16000; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 16000; + max_write_delay = 16000; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "efuse" + size = 1; + min_write_delay = 16000; + max_write_delay = 16000; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x 1 1 1 1 1 i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 16000; + max_write_delay = 16000; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "signature" + size = 3; + + read = "0 0 1 1 0 0 0 0 0 0 x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + + memory "calibration" + size = 1; + + read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; +; + + + +#------------------------------------------------------------ +# ATmega163 +#------------------------------------------------------------ + +part + id = "m163"; + desc = "ATmega163"; + stk500_devcode = 0x81; + avr910_devcode = 0x64; + signature = 0x1e 0x94 0x02; + chip_erase_delay = 32000; + pagel = 0xd7; + bs2 = 0xa0; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 0; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 30; + programfusepulsewidth = 0; + programfusepolltimeout = 2; + programlockpulsewidth = 0; + programlockpolltimeout = 2; + + + memory "eeprom" + size = 512; + min_write_delay = 4000; + max_write_delay = 4000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 16384; + page_size = 128; + num_pages = 128; + min_write_delay = 16000; + max_write_delay = 16000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x11; + delay = 20; + blocksize = 128; + readsize = 256; + ; + + memory "lfuse" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o x x o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i 1 1 i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x x x x x 1 o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x 1 1 1 1 1 i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x 0 x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega169 +#------------------------------------------------------------ + +part + id = "m169"; + desc = "ATmega169"; + has_jtag = yes; + stk500_devcode = 0x85; + avr910_devcode = 0x78; + signature = 0x1e 0x94 0x05; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + + ocdrev = 2; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 512; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 16384; + page_size = 128; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 128; + readsize = 256; + ; + + memory "lfuse" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + ; + + memory "lock" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega329 +#------------------------------------------------------------ + +part + id = "m329"; + desc = "ATmega329"; + has_jtag = yes; +# stk500_devcode = 0x85; # no STK500 support, only STK500v2 +# avr910_devcode = 0x?; # try the ATmega169 one: + avr910_devcode = 0x75; + signature = 0x1e 0x95 0x03; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 1024; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 8; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 32768; + page_size = 128; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 256; + readsize = 256; + ; + + memory "lfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "efuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega329P +#------------------------------------------------------------ +# Identical to ATmega329 except of the signature + +part parent "m329" + id = "m329p"; + desc = "ATmega329P"; + signature = 0x1e 0x95 0x0b; + + ocdrev = 3; + ; + +#------------------------------------------------------------ +# ATmega3290 +#------------------------------------------------------------ + +# identical to ATmega329 + +part parent "m329" + id = "m3290"; + desc = "ATmega3290"; + signature = 0x1e 0x95 0x04; + + ocdrev = 3; + ; + +#------------------------------------------------------------ +# ATmega3290P +#------------------------------------------------------------ + +# identical to ATmega3290 except of the signature + +part parent "m3290" + id = "m3290p"; + desc = "ATmega3290P"; + signature = 0x1e 0x95 0x0c; + + ocdrev = 3; + ; + +#------------------------------------------------------------ +# ATmega649 +#------------------------------------------------------------ + +part + id = "m649"; + desc = "ATmega649"; + has_jtag = yes; +# stk500_devcode = 0x85; # no STK500 support, only STK500v2 +# avr910_devcode = 0x?; # try the ATmega169 one: + avr910_devcode = 0x75; + signature = 0x1e 0x96 0x03; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 2048; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 8; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 65536; + page_size = 256; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 256; + readsize = 256; + ; + + memory "lfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "efuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega6490 +#------------------------------------------------------------ + +# identical to ATmega649 + +part parent "m649" + id = "m6490"; + desc = "ATmega6490"; + signature = 0x1e 0x96 0x04; + + ocdrev = 3; + ; + +#------------------------------------------------------------ +# ATmega32 +#------------------------------------------------------------ + +part + id = "m32"; + desc = "ATmega32"; + has_jtag = yes; + stk500_devcode = 0x91; + avr910_devcode = 0x72; + signature = 0x1e 0x95 0x02; + chip_erase_delay = 9000; + pagel = 0xd7; + bs2 = 0xa0; + reset = dedicated; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 6; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + allowfullpagebitstream = yes; + + ocdrev = 2; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 1024; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x04; + delay = 10; + blocksize = 64; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 32768; + page_size = 128; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x21; + delay = 6; + blocksize = 64; + readsize = 256; + ; + + memory "lfuse" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + + memory "calibration" + size = 4; + read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega161 +#------------------------------------------------------------ + +part + id = "m161"; + desc = "ATmega161"; + stk500_devcode = 0x80; + avr910_devcode = 0x60; + signature = 0x1e 0x94 0x01; + chip_erase_delay = 28000; + pagel = 0xd7; + bs2 = 0xa0; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 0; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 30; + programfusepulsewidth = 0; + programfusepolltimeout = 2; + programlockpulsewidth = 0; + programlockpolltimeout = 2; + + memory "eeprom" + size = 512; + min_write_delay = 3400; + max_write_delay = 3400; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 5; + blocksize = 128; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 16384; + page_size = 128; + num_pages = 128; + min_write_delay = 14000; + max_write_delay = 14000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x21; + delay = 16; + blocksize = 128; + readsize = 256; + ; + + memory "fuse" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 0 0 0 0 x x x x x x x x", + "x x x x x x x x x o x o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 x x x x x", + "x x x x x x x x 1 i 1 i i i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + + +#------------------------------------------------------------ +# ATmega8 +#------------------------------------------------------------ + +part + id = "m8"; + desc = "ATmega8"; + stk500_devcode = 0x70; + avr910_devcode = 0x76; + signature = 0x1e 0x93 0x07; + pagel = 0xd7; + bs2 = 0xc2; + chip_erase_delay = 10000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 2; + resetdelayus = 0; + hvleavestabdelay = 15; + resetdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + memory "eeprom" + size = 512; + page_size = 4; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 20; + blocksize = 128; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 8192; + page_size = 64; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 0 x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 0 x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x21; + delay = 10; + blocksize = 64; + readsize = 256; + ; + + memory "lfuse" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "calibration" + size = 4; + read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + + + +#------------------------------------------------------------ +# ATmega8515 +#------------------------------------------------------------ + +part + id = "m8515"; + desc = "ATmega8515"; + stk500_devcode = 0x63; + avr910_devcode = 0x3A; + signature = 0x1e 0x93 0x06; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 6; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + memory "eeprom" + size = 512; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 20; + blocksize = 128; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 8192; + page_size = 64; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 0 x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 0 x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x21; + delay = 6; + blocksize = 64; + readsize = 256; + ; + + memory "lfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "calibration" + size = 4; + read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + + + + +#------------------------------------------------------------ +# ATmega8535 +#------------------------------------------------------------ + +part + id = "m8535"; + desc = "ATmega8535"; + stk500_devcode = 0x64; + avr910_devcode = 0x69; + signature = 0x1e 0x93 0x08; + pagel = 0xd7; + bs2 = 0xa0; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 6; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + memory "eeprom" + size = 512; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 x x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + mode = 0x04; + delay = 20; + blocksize = 128; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 8192; + page_size = 64; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 0 x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 0 x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x21; + delay = 6; + blocksize = 64; + readsize = 256; + ; + + memory "lfuse" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 2000; + max_write_delay = 2000; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "calibration" + size = 4; + read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + + +#------------------------------------------------------------ +# ATtiny26 +#------------------------------------------------------------ + +part + id = "t26"; + desc = "ATtiny26"; + stk500_devcode = 0x21; + avr910_devcode = 0x5e; + signature = 0x1e 0x91 0x09; + pagel = 0xb3; + bs2 = 0xb2; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0xC4, 0xE4, 0xC4, 0xE4, 0xCC, 0xEC, 0xCC, 0xEC, + 0xD4, 0xF4, 0xD4, 0xF4, 0xDC, 0xFC, 0xDC, 0xFC, + 0xC8, 0xE8, 0xD8, 0xF8, 0x4C, 0x6C, 0x5C, 0x7C, + 0xEC, 0xBC, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 2; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + memory "eeprom" + size = 128; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 x x x x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 x x x x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + mode = 0x04; + delay = 10; + blocksize = 64; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 2048; + page_size = 32; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x x x a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x x x a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 x x x x", + " x x x x x x x x"; + + mode = 0x21; + delay = 6; + blocksize = 16; + readsize = 256; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x x x x x x x o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 1 i i", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x x x x i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 4; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + +; + + +#------------------------------------------------------------ +# ATtiny261 +#------------------------------------------------------------ +# Close to ATtiny26 + +part + id = "t261"; + desc = "ATtiny261"; + has_debugwire = yes; + flash_instr = 0xB4, 0x00, 0x10; + eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBC, 0x00, 0xB4, 0x00, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; +# stk500_devcode = 0x21; +# avr910_devcode = 0x5e; + signature = 0x1e 0x91 0x0c; + pagel = 0xb3; + bs2 = 0xb2; + chip_erase_delay = 4000; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0xC4, 0xE4, 0xC4, 0xE4, 0xCC, 0xEC, 0xCC, 0xEC, + 0xD4, 0xF4, 0xD4, 0xF4, 0xDC, 0xFC, 0xDC, 0xFC, + 0xC8, 0xE8, 0xD8, 0xF8, 0x4C, 0x6C, 0x5C, 0x7C, + 0xEC, 0xBC, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 2; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; + size = 128; + page_size = 4; + num_pages = 32; + min_write_delay = 4000; + max_write_delay = 4000; + readback_p1 = 0xff; + readback_p2 = 0xff; + + read = "1 0 1 0 0 0 0 0 x x x x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 x x x x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 2048; + page_size = 32; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x x x a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x x x a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " x x x x x x a9 a8", + " a7 a6 a5 a4 x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 32; + readsize = 256; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x x x x x x x o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 1 i i", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + +; + + +#------------------------------------------------------------ +# ATtiny461 +#------------------------------------------------------------ +# Close to ATtiny261 + +part + id = "t461"; + desc = "ATtiny461"; + has_debugwire = yes; + flash_instr = 0xB4, 0x00, 0x10; + eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBC, 0x00, 0xB4, 0x00, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; +# stk500_devcode = 0x21; +# avr910_devcode = 0x5e; + signature = 0x1e 0x92 0x08; + pagel = 0xb3; + bs2 = 0xb2; + chip_erase_delay = 4000; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0xC4, 0xE4, 0xC4, 0xE4, 0xCC, 0xEC, 0xCC, 0xEC, + 0xD4, 0xF4, 0xD4, 0xF4, 0xDC, 0xFC, 0xDC, 0xFC, + 0xC8, 0xE8, 0xD8, 0xF8, 0x4C, 0x6C, 0x5C, 0x7C, + 0xEC, 0xBC, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 2; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; + size = 256; + page_size = 4; + num_pages = 64; + min_write_delay = 4000; + max_write_delay = 4000; + readback_p1 = 0xff; + readback_p2 = 0xff; + + read = " 1 0 1 0 0 0 0 0 x x x x x x x x", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0 x x x x x x x x", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 4096; + page_size = 64; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 64; + readsize = 256; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x x x x x x x o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 1 i i", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + +; + + +#------------------------------------------------------------ +# ATtiny861 +#------------------------------------------------------------ +# Close to ATtiny461 + +part + id = "t861"; + desc = "ATtiny861"; + has_debugwire = yes; + flash_instr = 0xB4, 0x00, 0x10; + eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBC, 0x00, 0xB4, 0x00, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; +# stk500_devcode = 0x21; +# avr910_devcode = 0x5e; + signature = 0x1e 0x93 0x0d; + pagel = 0xb3; + bs2 = 0xb2; + chip_erase_delay = 4000; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 0; + + pp_controlstack = + 0xC4, 0xE4, 0xC4, 0xE4, 0xCC, 0xEC, 0xCC, 0xEC, + 0xD4, 0xF4, 0xD4, 0xF4, 0xDC, 0xFC, 0xDC, 0xFC, + 0xC8, 0xE8, 0xD8, 0xF8, 0x4C, 0x6C, 0x5C, 0x7C, + 0xEC, 0xBC, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 2; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; + size = 512; + num_pages = 128; + page_size = 4; + min_write_delay = 4000; + max_write_delay = 4000; + readback_p1 = 0xff; + readback_p2 = 0xff; + + read = " 1 0 1 0 0 0 0 0 x x x x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0 x x x x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 8192; + page_size = 64; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + + read_lo = " 0 0 1 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 64; + readsize = 256; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 x x x x x x x x", + "x x x x x x x x x x x x x x o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 1 1 1 i i", + "x x x x x x x x x x x x x x x x"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + +; + + +#------------------------------------------------------------ +# ATtiny28 +#------------------------------------------------------------ + +# This is an HVPP-only device. + +part + id = "t28"; + desc = "ATtiny28"; + stk500_devcode = 0x22; + avr910_devcode = 0x5c; + signature = 0x1e 0x91 0x07; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 0; + togglevtg = 0; + poweroffdelay = 0; + resetdelayms = 0; + resetdelayus = 0; + hvleavestabdelay = 15; + resetdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + memory "flash" + size = 2048; + page_size = 2; + readsize = 256; + delay = 5; + ; + + memory "signature" + size = 3; + ; + + memory "lock" + size = 1; + ; + + memory "calibration" + size = 1; + ; + + memory "fuse" + size = 1; + ; +; + + + +#------------------------------------------------------------ +# ATmega48 +#------------------------------------------------------------ + +part + id = "m48"; + desc = "ATmega48"; + has_debugwire = yes; + flash_instr = 0xB6, 0x01, 0x11; + eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, + 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, + 0x99, 0xF9, 0xBB, 0xAF; + stk500_devcode = 0x59; +# avr910_devcode = 0x; + signature = 0x1e 0x92 0x05; + pagel = 0xd7; + bs2 = 0xc2; + chip_erase_delay = 45000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + resetdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; + page_size = 4; + size = 256; + min_write_delay = 3600; + max_write_delay = 3600; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 x x x x x", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 4096; + page_size = 64; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 64; + readsize = 256; + ; + + memory "lfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "efuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + ; + + memory "lock" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega48P +#------------------------------------------------------------ + +part parent "m48" + id = "m48p"; + desc = "ATmega48P"; + signature = 0x1e 0x92 0x0a; + + ocdrev = 1; + ; + +#------------------------------------------------------------ +# ATmega48PB +#------------------------------------------------------------ + +part parent "m48" + id = "m48pb"; + desc = "ATmega48PB"; + signature = 0x1e 0x92 0x10; + + ocdrev = 1; + ; + +#------------------------------------------------------------ +# ATmega88 +#------------------------------------------------------------ + +part + id = "m88"; + desc = "ATmega88"; + has_debugwire = yes; + flash_instr = 0xB6, 0x01, 0x11; + eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, + 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, + 0x99, 0xF9, 0xBB, 0xAF; + stk500_devcode = 0x73; +# avr910_devcode = 0x; + signature = 0x1e 0x93 0x0a; + pagel = 0xd7; + bs2 = 0xc2; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + resetdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; + page_size = 4; + size = 512; + min_write_delay = 3600; + max_write_delay = 3600; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 8192; + page_size = 64; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 64; + readsize = 256; + ; + + memory "lfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "efuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega88P +#------------------------------------------------------------ + +part parent "m88" + id = "m88p"; + desc = "ATmega88P"; + signature = 0x1e 0x93 0x0f; + + ocdrev = 1; + ; + +#------------------------------------------------------------ +# ATmega88PB +#------------------------------------------------------------ + +part parent "m88" + id = "m88pb"; + desc = "ATmega88PB"; + signature = 0x1e 0x93 0x16; + + ocdrev = 1; + ; + +#------------------------------------------------------------ +# ATmega168 +#------------------------------------------------------------ + +part + id = "m168"; + desc = "ATmega168"; + has_debugwire = yes; + flash_instr = 0xB6, 0x01, 0x11; + eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, + 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, + 0x99, 0xF9, 0xBB, 0xAF; + stk500_devcode = 0x86; + # avr910_devcode = 0x; + signature = 0x1e 0x94 0x06; + pagel = 0xd7; + bs2 = 0xc2; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + resetdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; + page_size = 4; + size = 512; + min_write_delay = 3600; + max_write_delay = 3600; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 16384; + page_size = 128; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 128; + readsize = 256; + + ; + + memory "lfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "efuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; +; + +#------------------------------------------------------------ +# ATmega168P +#------------------------------------------------------------ + +part parent "m168" + id = "m168p"; + desc = "ATmega168P"; + signature = 0x1e 0x94 0x0b; + + ocdrev = 1; +; + +#------------------------------------------------------------ +# ATmega168PB +#------------------------------------------------------------ + +part parent "m168" + id = "m168pb"; + desc = "ATmega168PB"; + signature = 0x1e 0x94 0x15; + + ocdrev = 1; +; + +#------------------------------------------------------------ +# ATtiny88 +#------------------------------------------------------------ + +part + id = "t88"; + desc = "ATtiny88"; + has_debugwire = yes; + flash_instr = 0xB6, 0x01, 0x11; + eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, + 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, + 0x99, 0xF9, 0xBB, 0xAF; + stk500_devcode = 0x73; +# avr910_devcode = 0x; + signature = 0x1e 0x93 0x11; + pagel = 0xd7; + bs2 = 0xc2; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + resetdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; + page_size = 4; + size = 64; + min_write_delay = 3600; + max_write_delay = 3600; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 64; + ; + memory "flash" + paged = yes; + size = 8192; + page_size = 64; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 64; + readsize = 256; + ; + + memory "lfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "efuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + ; + + memory "lock" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega328 +#------------------------------------------------------------ + +part + id = "m328"; + desc = "ATmega328"; + has_debugwire = yes; + flash_instr = 0xB6, 0x01, 0x11; + eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, + 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, + 0x99, 0xF9, 0xBB, 0xAF; + stk500_devcode = 0x86; + # avr910_devcode = 0x; + signature = 0x1e 0x95 0x14; + pagel = 0xd7; + bs2 = 0xc2; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + resetdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; + page_size = 4; + size = 1024; + min_write_delay = 3600; + max_write_delay = 3600; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 x x x a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x a9 a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 32768; + page_size = 128; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 128; + readsize = 256; + + ; + + memory "lfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "efuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; +; + +part parent "m328" + id = "m328p"; + desc = "ATmega328P"; + signature = 0x1e 0x95 0x0F; + + ocdrev = 1; +; + +part parent "m328" + id = "m328pb"; + desc = "ATmega328PB"; + signature = 0x1e 0x95 0x16; + + ocdrev = 1; +; + +#------------------------------------------------------------ +# ATmega32m1 +#------------------------------------------------------------ + +part parent "m328" + id = "m32m1"; + desc = "ATmega32M1"; + # stk500_devcode = 0x; + # avr910_devcode = 0x; + signature = 0x1e 0x95 0x84; + bs2 = 0xe2; + + memory "efuse" + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x i i i i i i"; + ; +; + +#------------------------------------------------------------ +# ATmega64m1 +#------------------------------------------------------------ + +part parent "m328" + id = "m64m1"; + desc = "ATmega64M1"; + # stk500_devcode = 0x; + # avr910_devcode = 0x; + signature = 0x1e 0x96 0x84; + bs2 = 0xe2; + + memory "efuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x i i i i i i"; + ; +; + +#------------------------------------------------------------ +# ATtiny2313 +#------------------------------------------------------------ + +part + id = "t2313"; + desc = "ATtiny2313"; + has_debugwire = yes; + flash_instr = 0xB2, 0x0F, 0x1F; + eeprom_instr = 0xBB, 0xFE, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBA, 0x0F, 0xB2, 0x0F, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; + stk500_devcode = 0x23; +## Use the ATtiny26 devcode: + avr910_devcode = 0x5e; + signature = 0x1e 0x91 0x0a; + pagel = 0xD4; + bs2 = 0xD6; + reset = io; + chip_erase_delay = 9000; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0E, 0x1E, 0x2E, 0x3E, 0x2E, 0x3E, + 0x4E, 0x5E, 0x4E, 0x5E, 0x6E, 0x7E, 0x6E, 0x7E, + 0x26, 0x36, 0x66, 0x76, 0x2A, 0x3A, 0x6A, 0x7A, + 0x2E, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 0; + + memory "eeprom" + size = 128; + paged = no; + page_size = 4; + min_write_delay = 4000; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 4; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 2048; + page_size = 32; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 0 0 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 0 0 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + +# The information in the data sheet of April/2004 is wrong, this works: + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x x a3 a2 a1 a0", + " i i i i i i i i"; + +# The information in the data sheet of April/2004 is wrong, this works: + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x x a3 a2 a1 a0", + " i i i i i i i i"; + +# The information in the data sheet of April/2004 is wrong, this works: + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 0 0 a9 a8", + " a7 a6 a5 a4 x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 32; + readsize = 256; + ; +# ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A. + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; +# The Tiny2313 has calibration data for both 4 MHz and 8 MHz. +# The information in the data sheet of April/2004 is wrong, this works: + + memory "calibration" + size = 2; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATtiny4313 +#------------------------------------------------------------ + +part + id = "t4313"; + desc = "ATtiny4313"; + has_debugwire = yes; + flash_instr = 0xB2, 0x0F, 0x1F; + eeprom_instr = 0xBB, 0xFE, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBA, 0x0F, 0xB2, 0x0F, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; + stk500_devcode = 0x23; +## Use the ATtiny26 devcode: + avr910_devcode = 0x5e; + signature = 0x1e 0x92 0x0d; + pagel = 0xD4; + bs2 = 0xD6; + reset = io; + chip_erase_delay = 9000; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0E, 0x1E, 0x2E, 0x3E, 0x2E, 0x3E, + 0x4E, 0x5E, 0x4E, 0x5E, 0x6E, 0x7E, 0x6E, 0x7E, + 0x26, 0x36, 0x66, 0x76, 0x2A, 0x3A, 0x6A, 0x7A, + 0x2E, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 0; + + memory "eeprom" + size = 256; + paged = no; + page_size = 4; + min_write_delay = 4000; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 4; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 4096; + page_size = 64; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 32; + readsize = 256; + ; +# ATtiny4313 has Signature Bytes: 0x1E 0x92 0x0D. + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 2; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# AT90PWM2 +#------------------------------------------------------------ + +part + id = "pwm2"; + desc = "AT90PWM2"; + has_debugwire = yes; + flash_instr = 0xB6, 0x01, 0x11; + eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, + 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, + 0x99, 0xF9, 0xBB, 0xAF; + stk500_devcode = 0x65; +## avr910_devcode = ?; + signature = 0x1e 0x93 0x81; + pagel = 0xD8; + bs2 = 0xE2; + reset = io; + chip_erase_delay = 9000; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + memory "eeprom" + size = 512; + paged = no; + page_size = 4; + min_write_delay = 4000; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 0 0 0 x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 0 0 0 x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 4; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 8192; + page_size = 64; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 64; + readsize = 256; + ; +# AT90PWM2 has Signature Bytes: 0x1E 0x93 0x81. + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# AT90PWM3 +#------------------------------------------------------------ + +# Completely identical to AT90PWM2 (including the signature!) + +part parent "pwm2" + id = "pwm3"; + desc = "AT90PWM3"; + ; + +#------------------------------------------------------------ +# AT90PWM2B +#------------------------------------------------------------ +# Same as AT90PWM2 but different signature. + +part parent "pwm2" + id = "pwm2b"; + desc = "AT90PWM2B"; + signature = 0x1e 0x93 0x83; + + ocdrev = 1; + ; + +#------------------------------------------------------------ +# AT90PWM3B +#------------------------------------------------------------ + +# Completely identical to AT90PWM2B (including the signature!) + +part parent "pwm2b" + id = "pwm3b"; + desc = "AT90PWM3B"; + + ocdrev = 1; + ; + +#------------------------------------------------------------ +# AT90PWM316 +#------------------------------------------------------------ + +# Similar to AT90PWM3B, but with 16 kiB flash, 512 B EEPROM, and 1024 B SRAM. + +part parent "pwm3b" + id = "pwm316"; + desc = "AT90PWM316"; + signature = 0x1e 0x94 0x83; + + ocdrev = 1; + + memory "flash" + paged = yes; + size = 16384; + page_size = 128; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 a13 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x21; + delay = 6; + blocksize = 128; + readsize = 256; + ; + ; + +#------------------------------------------------------------ +# AT90PWM216 +#------------------------------------------------------------ +# Completely identical to AT90PWM316 (including the signature!) + +part parent "pwm316" + id = "pwm216"; + desc = "AT90PWM216"; + ; + +#------------------------------------------------------------ +# ATtiny25 +#------------------------------------------------------------ + +part + id = "t25"; + desc = "ATtiny25"; + has_debugwire = yes; + flash_instr = 0xB4, 0x02, 0x12; + eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBC, 0x02, 0xB4, 0x02, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; +## no STK500 devcode in XML file, use the ATtiny45 one + stk500_devcode = 0x14; +## avr910_devcode = ?; +## Try the AT90S2313 devcode: + avr910_devcode = 0x20; + signature = 0x1e 0x91 0x08; + reset = io; + chip_erase_delay = 4500; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + hvsp_controlstack = + 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, + 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, + 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, + 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; + hventerstabdelay = 100; + hvspcmdexedelay = 0; + synchcycles = 6; + latchcycles = 1; + togglevtg = 1; + poweroffdelay = 25; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 100; + resetdelay = 25; + chiperasepolltimeout = 40; + chiperasetime = 0; + programfusepolltimeout = 25; + programlockpolltimeout = 25; + + ocdrev = 1; + + memory "eeprom" + size = 128; + paged = no; + page_size = 4; + min_write_delay = 4000; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 4; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 2048; + page_size = 32; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 0 0 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 0 0 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x x a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x x a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 0 0 a9 a8", + " a7 a6 a5 a4 x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 32; + readsize = 256; + ; +# ATtiny25 has Signature Bytes: 0x1E 0x91 0x08. + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATtiny45 +#------------------------------------------------------------ + +part + id = "t45"; + desc = "ATtiny45"; + has_debugwire = yes; + flash_instr = 0xB4, 0x02, 0x12; + eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBC, 0x02, 0xB4, 0x02, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; + stk500_devcode = 0x14; +## avr910_devcode = ?; +## Try the AT90S2313 devcode: + avr910_devcode = 0x20; + signature = 0x1e 0x92 0x06; + reset = io; + chip_erase_delay = 4500; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + hvsp_controlstack = + 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, + 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, + 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, + 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + hvspcmdexedelay = 0; + synchcycles = 6; + latchcycles = 1; + togglevtg = 1; + poweroffdelay = 25; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 100; + resetdelay = 25; + chiperasepolltimeout = 40; + chiperasetime = 0; + programfusepolltimeout = 25; + programlockpolltimeout = 25; + + ocdrev = 1; + + memory "eeprom" + size = 256; + page_size = 4; + min_write_delay = 4000; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 4; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 4096; + page_size = 64; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 32; + readsize = 256; + ; +# ATtiny45 has Signature Bytes: 0x1E 0x92 0x08. (Data sheet 2586C-AVR-06/05 (doc2586.pdf) indicates otherwise!) + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATtiny85 +#------------------------------------------------------------ + +part + id = "t85"; + desc = "ATtiny85"; + has_debugwire = yes; + flash_instr = 0xB4, 0x02, 0x12; + eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBC, 0x02, 0xB4, 0x02, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; +## no STK500 devcode in XML file, use the ATtiny45 one + stk500_devcode = 0x14; +## avr910_devcode = ?; +## Try the AT90S2313 devcode: + avr910_devcode = 0x20; + signature = 0x1e 0x93 0x0b; + reset = io; + chip_erase_delay = 4500; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + hvsp_controlstack = + 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, + 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, + 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, + 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; + hventerstabdelay = 100; + hvspcmdexedelay = 0; + synchcycles = 6; + latchcycles = 1; + togglevtg = 1; + poweroffdelay = 25; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 100; + resetdelay = 25; + chiperasepolltimeout = 40; + chiperasetime = 0; + programfusepolltimeout = 25; + programlockpolltimeout = 25; + + ocdrev = 1; + + memory "eeprom" + size = 512; + paged = no; + page_size = 4; + min_write_delay = 4000; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 0 0 0 x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 0 0 0 x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 4; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 8192; + page_size = 64; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 32; + readsize = 256; + ; +# ATtiny85 has Signature Bytes: 0x1E 0x93 0x08. + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega640 +#------------------------------------------------------------ +# Almost same as ATmega1280, except for different memory sizes + +part + id = "m640"; + desc = "ATmega640"; + signature = 0x1e 0x96 0x08; + has_jtag = yes; +# stk500_devcode = 0xB2; +# avr910_devcode = 0x43; + chip_erase_delay = 9000; + pagel = 0xD7; + bs2 = 0xA0; + reset = dedicated; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + rampz = 0x3b; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 4096; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 8; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 65536; + page_size = 256; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 256; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega1280 +#------------------------------------------------------------ + +part + id = "m1280"; + desc = "ATmega1280"; + signature = 0x1e 0x97 0x03; + has_jtag = yes; +# stk500_devcode = 0xB2; +# avr910_devcode = 0x43; + chip_erase_delay = 9000; + pagel = 0xD7; + bs2 = 0xA0; + reset = dedicated; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + rampz = 0x3b; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 4096; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 8; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 131072; + page_size = 256; + num_pages = 512; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 256; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega1281 +#------------------------------------------------------------ +# Identical to ATmega1280 + +part parent "m1280" + id = "m1281"; + desc = "ATmega1281"; + signature = 0x1e 0x97 0x04; + + ocdrev = 3; + ; + +#------------------------------------------------------------ +# ATmega2560 +#------------------------------------------------------------ + +part + id = "m2560"; + desc = "ATmega2560"; + signature = 0x1e 0x98 0x01; + has_jtag = yes; + stk500_devcode = 0xB2; +# avr910_devcode = 0x43; + chip_erase_delay = 9000; + pagel = 0xD7; + bs2 = 0xA0; + reset = dedicated; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + rampz = 0x3b; + allowfullpagebitstream = no; + + ocdrev = 4; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 4096; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 8; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 262144; + page_size = 256; + num_pages = 1024; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + load_ext_addr = " 0 1 0 0 1 1 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 0 a16", + " 0 0 0 0 0 0 0 0"; + + mode = 0x41; + delay = 10; + blocksize = 256; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega2561 +#------------------------------------------------------------ + +part parent "m2560" + id = "m2561"; + desc = "ATmega2561"; + signature = 0x1e 0x98 0x02; + + ocdrev = 4; + ; + +#------------------------------------------------------------ +# ATmega128RFA1 +#------------------------------------------------------------ +# Identical to ATmega2561 but half the ROM + +part parent "m2561" + id = "m128rfa1"; + desc = "ATmega128RFA1"; + signature = 0x1e 0xa7 0x01; + chip_erase_delay = 55000; + bs2 = 0xE2; + + ocdrev = 3; + + memory "flash" + paged = yes; + size = 131072; + page_size = 256; + num_pages = 512; + min_write_delay = 50000; + max_write_delay = 50000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 256; + readsize = 256; + ; + ; + +#------------------------------------------------------------ +# ATmega256RFR2 +#------------------------------------------------------------ + +part parent "m2561" + id = "m256rfr2"; + desc = "ATmega256RFR2"; + signature = 0x1e 0xa8 0x02; + chip_erase_delay = 18500; + bs2 = 0xE2; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 8192; + min_write_delay = 13000; + max_write_delay = 13000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 8; + readsize = 256; + ; + + + ocdrev = 4; + ; + +#------------------------------------------------------------ +# ATmega128RFR2 +#------------------------------------------------------------ + +part parent "m128rfa1" + id = "m128rfr2"; + desc = "ATmega128RFR2"; + signature = 0x1e 0xa7 0x02; + + + ocdrev = 3; + ; + +#------------------------------------------------------------ +# ATmega64RFR2 +#------------------------------------------------------------ + +part parent "m128rfa1" + id = "m64rfr2"; + desc = "ATmega64RFR2"; + signature = 0x1e 0xa6 0x02; + + + ocdrev = 3; + + memory "flash" + paged = yes; + size = 65536; + page_size = 256; + num_pages = 256; + min_write_delay = 50000; + max_write_delay = 50000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 256; + readsize = 256; + ; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 2048; + min_write_delay = 13000; + max_write_delay = 13000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 8; + readsize = 256; + ; + + + ; + +#------------------------------------------------------------ +# ATmega2564RFR2 +#------------------------------------------------------------ + +part parent "m256rfr2" + id = "m2564rfr2"; + desc = "ATmega2564RFR2"; + signature = 0x1e 0xa8 0x03; + ; + +#------------------------------------------------------------ +# ATmega1284RFR2 +#------------------------------------------------------------ + +part parent "m128rfr2" + id = "m1284rfr2"; + desc = "ATmega1284RFR2"; + signature = 0x1e 0xa7 0x03; + ; + +#------------------------------------------------------------ +# ATmega644RFR2 +#------------------------------------------------------------ + +part parent "m64rfr2" + id = "m644rfr2"; + desc = "ATmega644RFR2"; + signature = 0x1e 0xa6 0x03; + ; + +#------------------------------------------------------------ +# ATtiny24 +#------------------------------------------------------------ + +part + id = "t24"; + desc = "ATtiny24"; + has_debugwire = yes; + flash_instr = 0xB4, 0x07, 0x17; + eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBC, 0x07, 0xB4, 0x07, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; +## no STK500 devcode in XML file, use the ATtiny45 one + stk500_devcode = 0x14; +## avr910_devcode = ?; +## Try the AT90S2313 devcode: + avr910_devcode = 0x20; + signature = 0x1e 0x91 0x0b; + reset = io; + chip_erase_delay = 4500; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + hvsp_controlstack = + 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, + 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, + 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, + 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x0F; + hventerstabdelay = 100; + hvspcmdexedelay = 0; + synchcycles = 6; + latchcycles = 1; + togglevtg = 1; + poweroffdelay = 25; + resetdelayms = 0; + resetdelayus = 70; + hvleavestabdelay = 100; + resetdelay = 25; + chiperasepolltimeout = 40; + chiperasetime = 0; + programfusepolltimeout = 25; + programlockpolltimeout = 25; + + ocdrev = 1; + + memory "eeprom" + size = 128; + paged = no; + page_size = 4; + min_write_delay = 4000; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", + "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 4; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 2048; + page_size = 32; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 0 0 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 0 0 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x x a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x x a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 0 0 a9 a8", + " a7 a6 a5 a4 x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 32; + readsize = 256; + ; +# ATtiny24 has Signature Bytes: 0x1E 0x91 0x0B. + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x x x x x x x i i"; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATtiny44 +#------------------------------------------------------------ + +part + id = "t44"; + desc = "ATtiny44"; + has_debugwire = yes; + flash_instr = 0xB4, 0x07, 0x17; + eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBC, 0x07, 0xB4, 0x07, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; +## no STK500 devcode in XML file, use the ATtiny45 one + stk500_devcode = 0x14; +## avr910_devcode = ?; +## Try the AT90S2313 devcode: + avr910_devcode = 0x20; + signature = 0x1e 0x92 0x07; + reset = io; + chip_erase_delay = 4500; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + hvsp_controlstack = + 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, + 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, + 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, + 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x0F; + hventerstabdelay = 100; + hvspcmdexedelay = 0; + synchcycles = 6; + latchcycles = 1; + togglevtg = 1; + poweroffdelay = 25; + resetdelayms = 0; + resetdelayus = 70; + hvleavestabdelay = 100; + resetdelay = 25; + chiperasepolltimeout = 40; + chiperasetime = 0; + programfusepolltimeout = 25; + programlockpolltimeout = 25; + + ocdrev = 1; + + memory "eeprom" + size = 256; + paged = no; + page_size = 4; + min_write_delay = 4000; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 4; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 4096; + page_size = 64; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 32; + readsize = 256; + ; +# ATtiny44 has Signature Bytes: 0x1E 0x92 0x07. + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x x x x x x x i i"; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATtiny84 +#------------------------------------------------------------ + +part + id = "t84"; + desc = "ATtiny84"; + has_debugwire = yes; + flash_instr = 0xB4, 0x07, 0x17; + eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBC, 0x07, 0xB4, 0x07, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; +## no STK500 devcode in XML file, use the ATtiny45 one + stk500_devcode = 0x14; +## avr910_devcode = ?; +## Try the AT90S2313 devcode: + avr910_devcode = 0x20; + signature = 0x1e 0x93 0x0c; + reset = io; + chip_erase_delay = 4500; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + hvsp_controlstack = + 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, + 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, + 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, + 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x0F; + hventerstabdelay = 100; + hvspcmdexedelay = 0; + synchcycles = 6; + latchcycles = 1; + togglevtg = 1; + poweroffdelay = 25; + resetdelayms = 0; + resetdelayus = 70; + hvleavestabdelay = 100; + resetdelay = 25; + chiperasepolltimeout = 40; + chiperasetime = 0; + programfusepolltimeout = 25; + programlockpolltimeout = 25; + + ocdrev = 1; + + memory "eeprom" + size = 512; + paged = no; + page_size = 4; + min_write_delay = 4000; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 0 0 0 x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 0 0 0 x x x x a8", + "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " x a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 4; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 8192; + page_size = 64; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 32; + readsize = 256; + ; +# ATtiny84 has Signature Bytes: 0x1E 0x93 0x0C. + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x x x x x x x i i"; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATtiny441 +#------------------------------------------------------------ + +part parent "t44" + id = "t441"; + desc = "ATtiny441"; + signature = 0x1e 0x92 0x15; + + memory "flash" + paged = yes; + size = 4096; + page_size = 16; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x x x a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x x x a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 16; + readsize = 256; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; +; + +#------------------------------------------------------------ +# ATtiny841 +#------------------------------------------------------------ + +part parent "t84" + id = "t841"; + desc = "ATtiny841"; + signature = 0x1e 0x93 0x15; + + memory "flash" + paged = yes; + size = 8192; + page_size = 16; + num_pages = 512; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x x x a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x x x a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 16; + readsize = 256; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; +; + +#------------------------------------------------------------ +# ATtiny43U +#------------------------------------------------------------ + +part + id = "t43u"; + desc = "ATtiny43u"; + has_debugwire = yes; + flash_instr = 0xB4, 0x07, 0x17; + eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, + 0xBC, 0x07, 0xB4, 0x07, 0xBA, 0x0D, 0xBB, 0xBC, + 0x99, 0xE1, 0xBB, 0xAC; + stk500_devcode = 0x14; +## avr910_devcode = ?; +## Try the AT90S2313 devcode: + avr910_devcode = 0x20; + signature = 0x1e 0x92 0x0C; + reset = io; + chip_erase_delay = 1000; + + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + pp_controlstack = 0x0E, 0x1E, 0x0E, 0x1E, 0x2E, 0x3E, 0x2E, 0x3E, 0x4E, 0x5E, + 0x4E, 0x5E, 0x6E, 0x7E, 0x6E, 0x7E, 0x06, 0x16, 0x46, 0x56, + 0x0A, 0x1A, 0x4A, 0x5A, 0x1E, 0x7C, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + hvspcmdexedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 20; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + resetdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + memory "eeprom" + size = 64; + paged = yes; + page_size = 4; + num_pages = 16; + min_write_delay = 4000; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", + "0 0 a4 a3 a2 a1 a0 o o o o o o o o"; + + write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", + "0 0 a5 a4 a3 a2 a1 a0 i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x x", + " 0 0 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 5; + blocksize = 4; + readsize = 256; + ; + memory "flash" + paged = yes; + size = 4096; + page_size = 64; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x x a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 64; + readsize = 256; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + memory "lock" + size = 1; + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x x x x i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 4500; + max_write_delay = 4500; + ; + + memory "calibration" + size = 2; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 a0 o o o o o o o o"; + ; +; + +#------------------------------------------------------------ +# ATmega32u4 +#------------------------------------------------------------ + +part + id = "m32u4"; + desc = "ATmega32U4"; + signature = 0x1e 0x95 0x87; + usbpid = 0x2ff4; + has_jtag = yes; +# stk500_devcode = 0xB2; +# avr910_devcode = 0x43; + chip_erase_delay = 9000; + pagel = 0xD7; + bs2 = 0xA0; + reset = dedicated; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + rampz = 0x3b; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 1024; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 32768; + page_size = 128; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 128; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# AT90USB646 +#------------------------------------------------------------ + +part + id = "usb646"; + desc = "AT90USB646"; + signature = 0x1e 0x96 0x82; + usbpid = 0x2ff9; + has_jtag = yes; +# stk500_devcode = 0xB2; +# avr910_devcode = 0x43; + chip_erase_delay = 9000; + pagel = 0xD7; + bs2 = 0xA0; + reset = dedicated; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + rampz = 0x3b; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 2048; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x x a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 8; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 65536; + page_size = 256; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 256; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# AT90USB647 +#------------------------------------------------------------ +# identical to AT90USB646 + +part parent "usb646" + id = "usb647"; + desc = "AT90USB647"; + signature = 0x1e 0x96 0x82; + + ocdrev = 3; + ; + +#------------------------------------------------------------ +# AT90USB1286 +#------------------------------------------------------------ + +part + id = "usb1286"; + desc = "AT90USB1286"; + signature = 0x1e 0x97 0x82; + usbpid = 0x2ffb; + has_jtag = yes; +# stk500_devcode = 0xB2; +# avr910_devcode = 0x43; + chip_erase_delay = 9000; + pagel = 0xD7; + bs2 = 0xA0; + reset = dedicated; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + rampz = 0x3b; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 4096; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " x x x x a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 8; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 131072; + page_size = 256; + num_pages = 512; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 x x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 256; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x x i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 x x x x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 x x x x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# AT90USB1287 +#------------------------------------------------------------ +# identical to AT90USB1286 + +part parent "usb1286" + id = "usb1287"; + desc = "AT90USB1287"; + signature = 0x1e 0x97 0x82; + + ocdrev = 3; + ; + +#------------------------------------------------------------ +# AT90USB162 +#------------------------------------------------------------ + +part + id = "usb162"; + desc = "AT90USB162"; + has_jtag = no; + has_debugwire = yes; + signature = 0x1e 0x94 0x82; + usbpid = 0x2ffa; + chip_erase_delay = 9000; + reset = io; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + pagel = 0xD7; + bs2 = 0xC6; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 512; + num_pages = 128; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 16384; + page_size = 128; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 128; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# AT90USB82 +#------------------------------------------------------------ +# Changes against AT90USB162 (beside IDs) +# memory "flash" +# size = 8192; +# num_pages = 64; + +part + id = "usb82"; + desc = "AT90USB82"; + has_jtag = no; + has_debugwire = yes; + signature = 0x1e 0x93 0x82; + usbpid = 0x2ff7; + chip_erase_delay = 9000; + reset = io; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + pagel = 0xD7; + bs2 = 0xC6; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 512; + num_pages = 128; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 8192; + page_size = 128; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 128; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega32U2 +#------------------------------------------------------------ +# Changes against AT90USB162 (beside IDs) +# memory "flash" +# size = 32768; +# num_pages = 256; +# memory "eeprom" +# size = 1024; +# num_pages = 256; +part + id = "m32u2"; + desc = "ATmega32U2"; + has_jtag = no; + has_debugwire = yes; + signature = 0x1e 0x95 0x8a; + usbpid = 0x2ff0; + chip_erase_delay = 9000; + reset = io; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + pagel = 0xD7; + bs2 = 0xC6; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 1024; + num_pages = 256; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 32768; + page_size = 128; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 128; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; +#------------------------------------------------------------ +# ATmega16U2 +#------------------------------------------------------------ +# Changes against ATmega32U2 (beside IDs) +# memory "flash" +# size = 16384; +# num_pages = 128; +# memory "eeprom" +# size = 512; +# num_pages = 128; +part + id = "m16u2"; + desc = "ATmega16U2"; + has_jtag = no; + has_debugwire = yes; + signature = 0x1e 0x94 0x89; + usbpid = 0x2fef; + chip_erase_delay = 9000; + reset = io; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + pagel = 0xD7; + bs2 = 0xC6; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 512; + num_pages = 128; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 16384; + page_size = 128; + num_pages = 128; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 128; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega8U2 +#------------------------------------------------------------ +# Changes against ATmega16U2 (beside IDs) +# memory "flash" +# size = 8192; +# page_size = 64; +# blocksize = 64; + +part + id = "m8u2"; + desc = "ATmega8U2"; + has_jtag = no; + has_debugwire = yes; + signature = 0x1e 0x93 0x89; + usbpid = 0x2fee; + chip_erase_delay = 9000; + reset = io; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + pagel = 0xD7; + bs2 = 0xC6; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + ocdrev = 1; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 512; + num_pages = 128; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0x00; + readback_p2 = 0x00; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 0 0 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 20; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 8192; + page_size = 128; + num_pages = 64; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0x00; + readback_p2 = 0x00; + read_lo = " 0 0 1 0 0 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " x x x x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + "a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 128; + readsize = 256; + ; + + memory "lfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x i i i i i i i i"; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; + ; +#------------------------------------------------------------ +# ATmega325 +#------------------------------------------------------------ + +part + id = "m325"; + desc = "ATmega325"; + signature = 0x1e 0x95 0x05; + has_jtag = yes; +# stk500_devcode = 0x??; # No STK500v1 support? +# avr910_devcode = 0x??; # Try the ATmega16 one + avr910_devcode = 0x74; + pagel = 0xd7; + bs2 = 0xa0; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 4; /* for parallel programming */ + size = 1024; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 0 0 0 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 0 0 0 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 0 0 0 0 a9 a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 32768; + page_size = 128; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 0 0 0 0 0", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 0 0 0 0 0", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 128; + readsize = 256; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 0 0 0 0 0", + "0 0 0 0 0 0 0 0 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "0 0 0 0 0 0 0 0 i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "0 0 0 0 0 0 0 0 i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "0 0 0 0 0 0 0 0 1 1 1 1 1 i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "calibration" + size = 1; + + read = "0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega645 +#------------------------------------------------------------ + +part + id = "m645"; + desc = "ATmega645"; + signature = 0x1E 0x96 0x05; + has_jtag = yes; +# stk500_devcode = 0x??; # No STK500v1 support? +# avr910_devcode = 0x??; # Try the ATmega16 one + avr910_devcode = 0x74; + pagel = 0xd7; + bs2 = 0xa0; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", + "0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, + 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, + 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, + 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 5; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + idr = 0x31; + spmcr = 0x57; + allowfullpagebitstream = no; + + ocdrev = 3; + + memory "eeprom" + paged = no; /* leave this "no" */ + page_size = 8; /* for parallel programming */ + size = 2048; + min_write_delay = 9000; + max_write_delay = 9000; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 0 0 0 a10 a9 a8", + " a7 a6 a5 a4 a3 0 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 10; + blocksize = 8; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 65536; + page_size = 256; + num_pages = 256; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 0 0 0 0 0", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 0 0 0 0 0", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " a15 a14 a13 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " 0 0 0 0 0 0 0 0"; + + mode = 0x41; + delay = 10; + blocksize = 128; + readsize = 256; + ; + + memory "lock" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 0 0 0 0 0", + "0 0 0 0 0 0 0 0 1 1 i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "lfuse" + size = 1; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "0 0 0 0 0 0 0 0 i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "hfuse" + size = 1; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "0 0 0 0 0 0 0 0 i i i i i i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "efuse" + size = 1; + + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "0 0 0 0 0 0 0 0 1 1 1 1 1 i i i"; + min_write_delay = 9000; + max_write_delay = 9000; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0", + "0 0 0 0 0 0 a1 a0 o o o o o o o o"; + ; + + memory "calibration" + size = 1; + + read = "0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + ; + +#------------------------------------------------------------ +# ATmega3250 +#------------------------------------------------------------ + +part parent "m325" + id = "m3250"; + desc = "ATmega3250"; + signature = 0x1E 0x95 0x06; + + ocdrev = 3; + ; + +#------------------------------------------------------------ +# ATmega6450 +#------------------------------------------------------------ + +part parent "m645" + id = "m6450"; + desc = "ATmega6450"; + signature = 0x1E 0x96 0x06; + + ocdrev = 3; + ; + +#------------------------------------------------------------ +# AVR XMEGA family common values +#------------------------------------------------------------ + +part + id = ".xmega"; + desc = "AVR XMEGA family common values"; + has_pdi = yes; + nvm_base = 0x01c0; + mcu_base = 0x0090; + + memory "signature" + size = 3; + offset = 0x1000090; + ; + + memory "prodsig" + size = 0x32; + offset = 0x8e0200; + page_size = 0x32; + readsize = 0x32; + ; + + memory "fuse1" + size = 1; + offset = 0x8f0021; + ; + + memory "fuse2" + size = 1; + offset = 0x8f0022; + ; + + memory "fuse4" + size = 1; + offset = 0x8f0024; + ; + + memory "fuse5" + size = 1; + offset = 0x8f0025; + ; + + memory "lock" + size = 1; + offset = 0x8f0027; + ; + + memory "data" + # SRAM, only used to supply the offset + offset = 0x1000000; + ; +; + +#------------------------------------------------------------ +# ATxmega16A4U +#------------------------------------------------------------ + +part parent ".xmega" + id = "x16a4u"; + desc = "ATxmega16A4U"; + signature = 0x1e 0x94 0x41; + usbpid = 0x2fe3; + + memory "eeprom" + size = 0x400; + offset = 0x8c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x4000; + offset = 0x800000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "apptable" + size = 0x1000; + offset = 0x803000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "boot" + size = 0x1000; + offset = 0x804000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "flash" + size = 0x5000; + offset = 0x800000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "usersig" + size = 0x100; + offset = 0x8e0400; + page_size = 0x100; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# ATxmega16C4 +#------------------------------------------------------------ + +part parent "x16a4u" + id = "x16c4"; + desc = "ATxmega16C4"; + signature = 0x1e 0x94 0x43; +; + +#------------------------------------------------------------ +# ATxmega16D4 +#------------------------------------------------------------ + +part parent "x16a4u" + id = "x16d4"; + desc = "ATxmega16D4"; + signature = 0x1e 0x94 0x42; +; + +#------------------------------------------------------------ +# ATxmega16A4 +#------------------------------------------------------------ + +part parent "x16a4u" + id = "x16a4"; + desc = "ATxmega16A4"; + signature = 0x1e 0x94 0x41; + has_jtag = yes; + + memory "fuse0" + size = 1; + offset = 0x8f0020; + ; +; + +#------------------------------------------------------------ +# ATxmega32A4U +#------------------------------------------------------------ + +part parent ".xmega" + id = "x32a4u"; + desc = "ATxmega32A4U"; + signature = 0x1e 0x95 0x41; + usbpid = 0x2fe4; + + memory "eeprom" + size = 0x400; + offset = 0x8c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x8000; + offset = 0x800000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "apptable" + size = 0x1000; + offset = 0x807000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "boot" + size = 0x1000; + offset = 0x808000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "flash" + size = 0x9000; + offset = 0x800000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "usersig" + size = 0x100; + offset = 0x8e0400; + page_size = 0x100; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# ATxmega32C4 +#------------------------------------------------------------ + +part parent "x32a4u" + id = "x32c4"; + desc = "ATxmega32C4"; + signature = 0x1e 0x95 0x44; +; + +#------------------------------------------------------------ +# ATxmega32D4 +#------------------------------------------------------------ + +part parent "x32a4u" + id = "x32d4"; + desc = "ATxmega32D4"; + signature = 0x1e 0x95 0x42; +; + +#------------------------------------------------------------ +# ATxmega32A4 +#------------------------------------------------------------ + +part parent "x32a4u" + id = "x32a4"; + desc = "ATxmega32A4"; + signature = 0x1e 0x95 0x41; + has_jtag = yes; + + memory "fuse0" + size = 1; + offset = 0x8f0020; + ; +; + +#------------------------------------------------------------ +# ATxmega64A4U +#------------------------------------------------------------ + +part parent ".xmega" + id = "x64a4u"; + desc = "ATxmega64A4U"; + signature = 0x1e 0x96 0x46; + usbpid = 0x2fe5; + + memory "eeprom" + size = 0x800; + offset = 0x8c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x10000; + offset = 0x800000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "apptable" + size = 0x1000; + offset = 0x80f000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "boot" + size = 0x1000; + offset = 0x810000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "flash" + size = 0x11000; + offset = 0x800000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "usersig" + size = 0x100; + offset = 0x8e0400; + page_size = 0x100; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# ATxmega64C3 +#------------------------------------------------------------ + +part parent "x64a4u" + id = "x64c3"; + desc = "ATxmega64C3"; + signature = 0x1e 0x96 0x49; + usbpid = 0x2fd6; +; + +#------------------------------------------------------------ +# ATxmega64D3 +#------------------------------------------------------------ + +part parent "x64a4u" + id = "x64d3"; + desc = "ATxmega64D3"; + signature = 0x1e 0x96 0x4a; +; + +#------------------------------------------------------------ +# ATxmega64D4 +#------------------------------------------------------------ + +part parent "x64a4u" + id = "x64d4"; + desc = "ATxmega64D4"; + signature = 0x1e 0x96 0x47; +; + +#------------------------------------------------------------ +# ATxmega64A1 +#------------------------------------------------------------ + +part parent "x64a4u" + id = "x64a1"; + desc = "ATxmega64A1"; + signature = 0x1e 0x96 0x4e; + has_jtag = yes; + + memory "fuse0" + size = 1; + offset = 0x8f0020; + ; +; + +#------------------------------------------------------------ +# ATxmega64A1U +#------------------------------------------------------------ + +part parent "x64a1" + id = "x64a1u"; + desc = "ATxmega64A1U"; + signature = 0x1e 0x96 0x4e; + usbpid = 0x2fe8; +; + +#------------------------------------------------------------ +# ATxmega64A3 +#------------------------------------------------------------ + +part parent "x64a1" + id = "x64a3"; + desc = "ATxmega64A3"; + signature = 0x1e 0x96 0x42; +; + +#------------------------------------------------------------ +# ATxmega64A3U +#------------------------------------------------------------ + +part parent "x64a1" + id = "x64a3u"; + desc = "ATxmega64A3U"; + signature = 0x1e 0x96 0x42; + usbpid = 0x2fe5; +; + +#------------------------------------------------------------ +# ATxmega64A4 +#------------------------------------------------------------ + +part parent "x64a1" + id = "x64a4"; + desc = "ATxmega64A4"; + signature = 0x1e 0x96 0x46; +; + +#------------------------------------------------------------ +# ATxmega64B1 +#------------------------------------------------------------ + +part parent "x64a1" + id = "x64b1"; + desc = "ATxmega64B1"; + signature = 0x1e 0x96 0x52; + usbpid = 0x2fe1; +; + +#------------------------------------------------------------ +# ATxmega64B3 +#------------------------------------------------------------ + +part parent "x64a1" + id = "x64b3"; + desc = "ATxmega64B3"; + signature = 0x1e 0x96 0x51; + usbpid = 0x2fdf; +; + +#------------------------------------------------------------ +# ATxmega128C3 +#------------------------------------------------------------ + +part parent ".xmega" + id = "x128c3"; + desc = "ATxmega128C3"; + signature = 0x1e 0x97 0x52; + usbpid = 0x2fd7; + + memory "eeprom" + size = 0x800; + offset = 0x8c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x20000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "apptable" + size = 0x2000; + offset = 0x81e000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "boot" + size = 0x2000; + offset = 0x820000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "flash" + size = 0x22000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "usersig" + size = 0x200; + offset = 0x8e0400; + page_size = 0x200; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# ATxmega128D3 +#------------------------------------------------------------ + +part parent "x128c3" + id = "x128d3"; + desc = "ATxmega128D3"; + signature = 0x1e 0x97 0x48; +; + +#------------------------------------------------------------ +# ATxmega128D4 +#------------------------------------------------------------ + +part parent "x128c3" + id = "x128d4"; + desc = "ATxmega128D4"; + signature = 0x1e 0x97 0x47; +; + +#------------------------------------------------------------ +# ATxmega128A1 +#------------------------------------------------------------ + +part parent "x128c3" + id = "x128a1"; + desc = "ATxmega128A1"; + signature = 0x1e 0x97 0x4c; + has_jtag = yes; + + memory "fuse0" + size = 1; + offset = 0x8f0020; + ; +; + +#------------------------------------------------------------ +# ATxmega128A1 revision D +#------------------------------------------------------------ + +part parent "x128a1" + id = "x128a1d"; + desc = "ATxmega128A1revD"; + signature = 0x1e 0x97 0x41; +; + +#------------------------------------------------------------ +# ATxmega128A1U +#------------------------------------------------------------ + +part parent "x128a1" + id = "x128a1u"; + desc = "ATxmega128A1U"; + signature = 0x1e 0x97 0x4c; + usbpid = 0x2fed; +; + +#------------------------------------------------------------ +# ATxmega128A3 +#------------------------------------------------------------ + +part parent "x128a1" + id = "x128a3"; + desc = "ATxmega128A3"; + signature = 0x1e 0x97 0x42; +; + +#------------------------------------------------------------ +# ATxmega128A3U +#------------------------------------------------------------ + +part parent "x128a1" + id = "x128a3u"; + desc = "ATxmega128A3U"; + signature = 0x1e 0x97 0x42; + usbpid = 0x2fe6; +; + +#------------------------------------------------------------ +# ATxmega128A4 +#------------------------------------------------------------ + +part parent ".xmega" + id = "x128a4"; + desc = "ATxmega128A4"; + signature = 0x1e 0x97 0x46; + has_jtag = yes; + + memory "eeprom" + size = 0x800; + offset = 0x8c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x20000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "apptable" + size = 0x1000; + offset = 0x81f000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "boot" + size = 0x2000; + offset = 0x820000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "flash" + size = 0x22000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "usersig" + size = 0x200; + offset = 0x8e0400; + page_size = 0x200; + readsize = 0x100; + ; + + memory "fuse0" + size = 1; + offset = 0x8f0020; + ; +; + +#------------------------------------------------------------ +# ATxmega128A4U +#------------------------------------------------------------ + +part parent ".xmega" + id = "x128a4u"; + desc = "ATxmega128A4U"; + signature = 0x1e 0x97 0x46; + usbpid = 0x2fde; + + memory "eeprom" + size = 0x800; + offset = 0x8c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x20000; + offset = 0x800000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "apptable" + size = 0x1000; + offset = 0x81f000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "boot" + size = 0x2000; + offset = 0x820000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "flash" + size = 0x22000; + offset = 0x800000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "usersig" + size = 0x100; + offset = 0x8e0400; + page_size = 0x100; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# ATxmega128B1 +#------------------------------------------------------------ + +part parent ".xmega" + id = "x128b1"; + desc = "ATxmega128B1"; + signature = 0x1e 0x97 0x4d; + usbpid = 0x2fea; + has_jtag = yes; + + memory "eeprom" + size = 0x800; + offset = 0x8c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x20000; + offset = 0x800000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "apptable" + size = 0x2000; + offset = 0x81e000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "boot" + size = 0x2000; + offset = 0x820000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "flash" + size = 0x22000; + offset = 0x800000; + page_size = 0x100; + readsize = 0x100; + ; + + memory "usersig" + size = 0x100; + offset = 0x8e0400; + page_size = 0x100; + readsize = 0x100; + ; + + memory "fuse0" + size = 1; + offset = 0x8f0020; + ; +; + +#------------------------------------------------------------ +# ATxmega128B3 +#------------------------------------------------------------ + +part parent "x128b1" + id = "x128b3"; + desc = "ATxmega128B3"; + signature = 0x1e 0x97 0x4b; + usbpid = 0x2fe0; +; + +#------------------------------------------------------------ +# ATxmega192C3 +#------------------------------------------------------------ + +part parent ".xmega" + id = "x192c3"; + desc = "ATxmega192C3"; + signature = 0x1e 0x97 0x51; + # usbpid = 0x2f??; + + memory "eeprom" + size = 0x800; + offset = 0x8c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x30000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "apptable" + size = 0x2000; + offset = 0x82e000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "boot" + size = 0x2000; + offset = 0x830000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "flash" + size = 0x32000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "usersig" + size = 0x200; + offset = 0x8e0400; + page_size = 0x200; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# ATxmega192D3 +#------------------------------------------------------------ + +part parent "x192c3" + id = "x192d3"; + desc = "ATxmega192D3"; + signature = 0x1e 0x97 0x49; +; + +#------------------------------------------------------------ +# ATxmega192A1 +#------------------------------------------------------------ + +part parent "x192c3" + id = "x192a1"; + desc = "ATxmega192A1"; + signature = 0x1e 0x97 0x4e; + has_jtag = yes; + + memory "fuse0" + size = 1; + offset = 0x8f0020; + ; +; + +#------------------------------------------------------------ +# ATxmega192A3 +#------------------------------------------------------------ + +part parent "x192a1" + id = "x192a3"; + desc = "ATxmega192A3"; + signature = 0x1e 0x97 0x44; +; + +#------------------------------------------------------------ +# ATxmega192A3U +#------------------------------------------------------------ + +part parent "x192a1" + id = "x192a3u"; + desc = "ATxmega192A3U"; + signature = 0x1e 0x97 0x44; + usbpid = 0x2fe7; +; + +#------------------------------------------------------------ +# ATxmega256C3 +#------------------------------------------------------------ + +part parent ".xmega" + id = "x256c3"; + desc = "ATxmega256C3"; + signature = 0x1e 0x98 0x46; + usbpid = 0x2fda; + + memory "eeprom" + size = 0x1000; + offset = 0x8c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x40000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "apptable" + size = 0x2000; + offset = 0x83e000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "boot" + size = 0x2000; + offset = 0x840000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "flash" + size = 0x42000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "usersig" + size = 0x200; + offset = 0x8e0400; + page_size = 0x200; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# ATxmega256D3 +#------------------------------------------------------------ + +part parent "x256c3" + id = "x256d3"; + desc = "ATxmega256D3"; + signature = 0x1e 0x98 0x44; +; + +#------------------------------------------------------------ +# ATxmega256A1 +#------------------------------------------------------------ + +part parent "x256c3" + id = "x256a1"; + desc = "ATxmega256A1"; + signature = 0x1e 0x98 0x46; + has_jtag = yes; + + memory "fuse0" + size = 1; + offset = 0x8f0020; + ; +; + +#------------------------------------------------------------ +# ATxmega256A3 +#------------------------------------------------------------ + +part parent "x256a1" + id = "x256a3"; + desc = "ATxmega256A3"; + signature = 0x1e 0x98 0x42; +; + +#------------------------------------------------------------ +# ATxmega256A3U +#------------------------------------------------------------ + +part parent "x256a1" + id = "x256a3u"; + desc = "ATxmega256A3U"; + signature = 0x1e 0x98 0x42; + usbpid = 0x2fec; +; + +#------------------------------------------------------------ +# ATxmega256A3B +#------------------------------------------------------------ + +part parent "x256a1" + id = "x256a3b"; + desc = "ATxmega256A3B"; + signature = 0x1e 0x98 0x43; +; + +#------------------------------------------------------------ +# ATxmega256A3BU +#------------------------------------------------------------ + +part parent "x256a1" + id = "x256a3bu"; + desc = "ATxmega256A3BU"; + signature = 0x1e 0x98 0x43; + usbpid = 0x2fe2; +; + +#------------------------------------------------------------ +# ATxmega384C3 +#------------------------------------------------------------ + +part parent ".xmega" + id = "x384c3"; + desc = "ATxmega384C3"; + signature = 0x1e 0x98 0x45; + usbpid = 0x2fdb; + + memory "eeprom" + size = 0x1000; + offset = 0x8c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x60000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "apptable" + size = 0x2000; + offset = 0x85e000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "boot" + size = 0x2000; + offset = 0x860000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "flash" + size = 0x62000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "usersig" + size = 0x200; + offset = 0x8e0400; + page_size = 0x200; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# ATxmega384D3 +#------------------------------------------------------------ + +part parent "x384c3" + id = "x384d3"; + desc = "ATxmega384D3"; + signature = 0x1e 0x98 0x47; +; + +#------------------------------------------------------------ +# ATxmega8E5 +#------------------------------------------------------------ + +part parent ".xmega" + id = "x8e5"; + desc = "ATxmega8E5"; + signature = 0x1e 0x93 0x41; + + memory "eeprom" + size = 0x0200; + offset = 0x08c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x2000; + offset = 0x0800000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "apptable" + size = 0x800; + offset = 0x00801800; + page_size = 0x80; + readsize = 0x100; + ; + + memory "boot" + size = 0x800; + offset = 0x00802000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "flash" + size = 0x2800; + offset = 0x0800000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "usersig" + size = 0x80; + offset = 0x8e0400; + page_size = 0x80; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# ATxmega16E5 +#------------------------------------------------------------ + +part parent ".xmega" + id = "x16e5"; + desc = "ATxmega16E5"; + signature = 0x1e 0x94 0x45; + + memory "eeprom" + size = 0x0200; + offset = 0x08c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x4000; + offset = 0x0800000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "apptable" + size = 0x1000; + offset = 0x00803000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "boot" + size = 0x1000; + offset = 0x00804000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "flash" + size = 0x5000; + offset = 0x0800000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "usersig" + size = 0x80; + offset = 0x8e0400; + page_size = 0x80; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# ATxmega32E5 +#------------------------------------------------------------ + +part parent ".xmega" + id = "x32e5"; + desc = "ATxmega32E5"; + signature = 0x1e 0x95 0x4c; + + memory "eeprom" + size = 0x0400; + offset = 0x08c0000; + page_size = 0x20; + readsize = 0x100; + ; + + memory "application" + size = 0x8000; + offset = 0x0800000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "apptable" + size = 0x1000; + offset = 0x00807000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "boot" + size = 0x1000; + offset = 0x00808000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "flash" + size = 0x9000; + offset = 0x0800000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "usersig" + size = 0x80; + offset = 0x8e0400; + page_size = 0x80; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# AVR32UC3A0512 +#------------------------------------------------------------ + +part + id = "uc3a0512"; + desc = "AT32UC3A0512"; + signature = 0xED 0xC0 0x3F; + has_jtag = yes; + is_avr32 = yes; + + memory "flash" + paged = yes; + page_size = 512; # bytes + readsize = 512; # bytes + num_pages = 1024; # could be set dynamicly + size = 0x00080000; # could be set dynamicly + offset = 0x80000000; + ; +; + +part parent "uc3a0512" + id = "ucr2"; + desc = "deprecated, use 'uc3a0512'"; +; + +#------------------------------------------------------------ +# ATtiny1634. +#------------------------------------------------------------ + +part + id = "t1634"; + desc = "ATtiny1634"; + has_debugwire = yes; + flash_instr = 0xB6, 0x01, 0x11; + eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, + 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, + 0x99, 0xF9, 0xBB, 0xAF; + stk500_devcode = 0x86; + # avr910_devcode = 0x; + signature = 0x1e 0x94 0x12; + pagel = 0xB3; + bs2 = 0xB1; + reset = io; + chip_erase_delay = 9000; + pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", + "x x x x x x x x x x x x x x x x"; + + chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", + "x x x x x x x x x x x x x x x x"; + + timeout = 200; + stabdelay = 100; + cmdexedelay = 25; + synchloops = 32; + bytedelay = 0; + pollindex = 3; + pollvalue = 0x53; + predelay = 1; + postdelay = 1; + pollmethod = 1; + + pp_controlstack = + 0x0E, 0x1E, 0x0E, 0x1E, 0x2E, 0x3E, 0x2E, 0x3E, + 0x4E, 0x5E, 0x4E, 0x5E, 0x6E, 0x7E, 0x6E, 0x7E, + 0x26, 0x36, 0x66, 0x76, 0x2A, 0x3A, 0x6A, 0x7A, + 0x2E, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + hventerstabdelay = 100; + progmodedelay = 0; + latchcycles = 0; + togglevtg = 1; + poweroffdelay = 15; + resetdelayms = 1; + resetdelayus = 0; + hvleavestabdelay = 15; + resetdelay = 15; + chiperasepulsewidth = 0; + chiperasepolltimeout = 10; + programfusepulsewidth = 0; + programfusepolltimeout = 5; + programlockpulsewidth = 0; + programlockpolltimeout = 5; + + memory "eeprom" + paged = no; + page_size = 4; + size = 256; + min_write_delay = 3600; + max_write_delay = 3600; + readback_p1 = 0xff; + readback_p2 = 0xff; + read = " 1 0 1 0 0 0 0 0", + " 0 0 0 x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + write = " 1 1 0 0 0 0 0 0", + " 0 0 0 x x x x a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_lo = " 1 1 0 0 0 0 0 1", + " 0 0 0 0 0 0 0 0", + " 0 0 0 0 0 0 a1 a0", + " i i i i i i i i"; + + writepage = " 1 1 0 0 0 0 1 0", + " 0 0 x x x x x a8", + " a7 a6 a5 a4 a3 a2 0 0", + " x x x x x x x x"; + + mode = 0x41; + delay = 5; + blocksize = 4; + readsize = 256; + ; + + memory "flash" + paged = yes; + size = 16384; + page_size = 32; + num_pages = 512; + min_write_delay = 4500; + max_write_delay = 4500; + readback_p1 = 0xff; + readback_p2 = 0xff; + read_lo = " 0 0 1 0 0 0 0 0", + " 0 0 0 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + read_hi = " 0 0 1 0 1 0 0 0", + " 0 0 0 a12 a11 a10 a9 a8", + " a7 a6 a5 a4 a3 a2 a1 a0", + " o o o o o o o o"; + + loadpage_lo = " 0 1 0 0 0 0 0 0", + " 0 0 0 x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + loadpage_hi = " 0 1 0 0 1 0 0 0", + " 0 0 0 x x x x x", + " x x a5 a4 a3 a2 a1 a0", + " i i i i i i i i"; + + writepage = " 0 1 0 0 1 1 0 0", + " 0 0 0 a12 a11 a10 a9 a8", + " a7 a6 x x x x x x", + " x x x x x x x x"; + + mode = 0x41; + delay = 6; + blocksize = 128; + readsize = 256; + + ; + + memory "lfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "hfuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", + "x x x x x x x x i i i i i i i i"; + ; + + memory "efuse" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", + "x x x x x x x x o o o o o o o o"; + + write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", + "x x x x x x x x x x x i i i i i"; + ; + + memory "lock" + size = 1; + min_write_delay = 4500; + max_write_delay = 4500; + read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", + "x x x x x x x x x x x x x x o o"; + + write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", + "x x x x x x x x 1 1 1 1 1 1 i i"; + ; + + memory "calibration" + size = 1; + read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", + "0 0 0 0 0 0 0 0 o o o o o o o o"; + ; + + memory "signature" + size = 3; + read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", + "x x x x x x a1 a0 o o o o o o o o"; + ; +; + +#------------------------------------------------------------ +# Common values for reduced core tinys (4/5/9/10/20/40) +#------------------------------------------------------------ + +part + id = ".reduced_core_tiny"; + desc = "Common values for reduced core tinys"; + has_tpi = yes; + + memory "signature" + size = 3; + offset = 0x3fc0; + page_size = 16; + ; + + memory "fuse" + size = 1; + offset = 0x3f40; + page_size = 16; + blocksize = 4; + ; + + memory "calibration" + size = 1; + offset = 0x3f80; + page_size = 16; + ; + + memory "lockbits" + size = 1; + offset = 0x3f00; + page_size = 16; + ; +; + +#------------------------------------------------------------ +# ATtiny4 +#------------------------------------------------------------ + +part parent ".reduced_core_tiny" + id = "t4"; + desc = "ATtiny4"; + signature = 0x1e 0x8f 0x0a; + + memory "flash" + size = 512; + offset = 0x4000; + page_size = 16; + blocksize = 128; + ; +; + +#------------------------------------------------------------ +# ATtiny5 +#------------------------------------------------------------ + +part parent "t4" + id = "t5"; + desc = "ATtiny5"; + signature = 0x1e 0x8f 0x09; +; + +#------------------------------------------------------------ +# ATtiny9 +#------------------------------------------------------------ + +part parent ".reduced_core_tiny" + id = "t9"; + desc = "ATtiny9"; + signature = 0x1e 0x90 0x08; + + memory "flash" + size = 1024; + offset = 0x4000; + page_size = 16; + blocksize = 128; + ; +; + +#------------------------------------------------------------ +# ATtiny10 +#------------------------------------------------------------ + +part parent "t9" + id = "t10"; + desc = "ATtiny10"; + signature = 0x1e 0x90 0x03; +; + +#------------------------------------------------------------ +# ATtiny20 +#------------------------------------------------------------ + +part parent ".reduced_core_tiny" + id = "t20"; + desc = "ATtiny20"; + signature = 0x1e 0x91 0x0F; + + memory "flash" + size = 2048; + offset = 0x4000; + page_size = 16; + blocksize = 128; + ; +; + +#------------------------------------------------------------ +# ATtiny40 +#------------------------------------------------------------ + +part parent ".reduced_core_tiny" + id = "t40"; + desc = "ATtiny40"; + signature = 0x1e 0x92 0x0E; + + memory "flash" + size = 4096; + offset = 0x4000; + page_size = 64; + blocksize = 128; + ; +; + +#------------------------------------------------------------ +# ATmega406 +#------------------------------------------------------------ + +part + id = "m406"; + desc = "ATMEGA406"; + has_jtag = yes; + signature = 0x1e 0x95 0x07; + + # STK500 parameters (parallel programming IO lines) + pagel = 0xa7; + bs2 = 0xa0; + serial = no; + parallel = yes; + + # STK500v2 HV programming parameters, from XML + pp_controlstack = 0x0e, 0x1e, 0x0f, 0x1f, 0x2e, 0x3e, 0x2f, 0x3f, + 0x4e, 0x5e, 0x4f, 0x5f, 0x6e, 0x7e, 0x6f, 0x7f, + 0x66, 0x76, 0x67, 0x77, 0x6a, 0x7a, 0x6b, 0x7b, + 0xbe, 0xfd, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; + + # JTAG ICE mkII parameters, also from XML files + allowfullpagebitstream = no; + enablepageprogramming = yes; + idr = 0x51; + rampz = 0x00; + spmcr = 0x57; + eecr = 0x3f; + + memory "eeprom" + paged = no; + size = 512; + page_size = 4; + blocksize = 4; + readsize = 4; + num_pages = 128; + ; + + memory "flash" + paged = yes; + size = 40960; + page_size = 128; + blocksize = 128; + readsize = 128; + num_pages = 320; + ; + + memory "hfuse" + size = 1; + ; + + memory "lfuse" + size = 1; + ; + + memory "lockbits" + size = 1; + ; + + memory "signature" + size = 3; + ; +; + +#------------------------------------------------------------ +# AVR8X class common values +#------------------------------------------------------------ + +part + id = ".avr8x"; + desc = "AVR8X class common values"; +# has_updi = yes; + has_pdi = yes; + nvm_base = 0x1000; +# ocd_base = 0x0F80; + + memory "signature" + size = 3; + offset = 0x1100; + ; + + memory "prodsig" + size = 0x3D; + offset = 0x1103; + page_size = 0x3D; + readsize = 0x3D; + ; + + memory "fuses" + size = 9; + offset = 0x1280; + ; + + memory "fuse0" + size = 1; + offset = 0x1280; + ; + + memory "fuse1" + size = 1; + offset = 0x1281; + ; + + memory "fuse2" + size = 1; + offset = 0x1282; + ; + + memory "fuse4" + size = 1; + offset = 0x1284; + ; + + memory "fuse5" + size = 1; + offset = 0x1285; + ; + + memory "fuse6" + size = 1; + offset = 0x1286; + ; + + memory "fuse7" + size = 1; + offset = 0x1287; + ; + + memory "fuse8" + size = 1; + offset = 0x1288; + ; + + memory "lock" + size = 1; + offset = 0x128a; + ; + + memory "data" + # SRAM, only used to supply the offset + offset = 0x1000000; + ; +; + +#------------------------------------------------------------ +# AVR8X tiny family common values +#------------------------------------------------------------ + +part parent ".avr8x" + id = ".avr8x_tiny"; + desc = "AVR8X tiny family common values"; +# family_id = "tinyAVR"; + + memory "usersig" + size = 0x20; + offset = 0x1300; + page_size = 0x20; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# AVR8X mega family common values +#------------------------------------------------------------ + +part parent ".avr8x" + id = ".avr8x_mega"; + desc = "AVR8X mega family common values"; +# family_id = "megaAVR"; + + memory "usersig" + size = 0x40; + offset = 0x1300; + page_size = 0x40; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# Tiny2XX sub-family common values +#------------------------------------------------------------ + +part parent ".avr8x_tiny" + id = ".tiny2xx"; + desc = "Tiny2XX sub-family common values"; +# family_id = "tiny2xx"; + + memory "flash" + size = 0x800; + offset = 0x8000; + page_size = 0x40; + readsize = 0x100; + ; + + memory "eeprom" + size = 0x40; + offset = 0x1400; + page_size = 0x20; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# Tiny4XX sub-family common values +#------------------------------------------------------------ + +part parent ".avr8x_tiny" + id = ".tiny4xx"; + desc = "Tiny4XX sub-family common values"; +# family_id = "tiny4xx"; + + memory "flash" + size = 0x1000; + offset = 0x8000; + page_size = 0x40; + readsize = 0x100; + ; + + memory "eeprom" + size = 0x80; + offset = 0x1400; + page_size = 0x20; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# Tiny8XX sub-family common values +#------------------------------------------------------------ + +part parent ".avr8x_tiny" + id = ".tiny8xx"; + desc = "Tiny8XX sub-family common values"; +# family_id = "tiny8xx"; + + memory "flash" + size = 0x2000; + offset = 0x8000; + page_size = 0x40; + readsize = 0x100; + ; + + memory "eeprom" + size = 0x80; + offset = 0x1400; + page_size = 0x20; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# Tiny16XX sub-family common values +#------------------------------------------------------------ + +part parent ".avr8x_tiny" + id = ".tiny16xx"; + desc = "Tiny16XX sub-family common values"; +# family_id = "tiny16xx"; + + memory "flash" + size = 0x4000; + offset = 0x8000; + page_size = 0x40; + readsize = 0x100; + ; + + memory "eeprom" + size = 0x100; + offset = 0x1400; + page_size = 0x20; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# Tiny32XX sub-family common values +#------------------------------------------------------------ + +part parent ".avr8x_mega" # yes, this is correct + id = ".tiny32xx"; + desc = "Tiny32XX sub-family common values"; +# family_id = "tiny32xx"; + + memory "flash" + size = 0x8000; + offset = 0x8000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "eeprom" + size = 0x100; + offset = 0x1400; + page_size = 0x40; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# Mega80X sub-family common values +#------------------------------------------------------------ + +part parent ".avr8x_tiny" # yes, this is correct + id = ".mega80x"; + desc = "Mega80X sub-family common values"; +# family_id = "mega80x"; + + memory "flash" + size = 0x2000; + offset = 0x4000; + page_size = 0x40; + readsize = 0x100; + ; + + memory "eeprom" + size = 0x100; + offset = 0x1400; + page_size = 0x20; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# Mega160X sub-family common values +#------------------------------------------------------------ + +part parent ".avr8x_tiny" # yes, this is correct + id = ".mega160x"; + desc = "Mega160X sub-family common values"; +# family_id = "mega160x"; + + memory "flash" + size = 0x4000; + offset = 0x4000; + page_size = 0x40; + readsize = 0x100; + ; + + memory "eeprom" + size = 0x100; + offset = 0x1400; + page_size = 0x20; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# Mega320X sub-family common values +#------------------------------------------------------------ + +part parent ".avr8x_mega" + id = ".mega320x"; + desc = "Mega320X sub-family common values"; +# family_id = "mega320x"; + + memory "flash" + size = 0x8000; + offset = 0x4000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "eeprom" + size = 0x100; + offset = 0x1400; + page_size = 0x40; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# Mega480X sub-family common values +#------------------------------------------------------------ + +part parent ".avr8x_mega" + id = ".mega480x"; + desc = "Mega480X sub-family common values"; +# family_id = "mega480x"; + + memory "flash" + size = 0xC000; + offset = 0x4000; + page_size = 0x80; + readsize = 0x100; + ; + + memory "eeprom" + size = 0x100; + offset = 0x1400; + page_size = 0x40; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# ATtiny202 +#------------------------------------------------------------ + +part parent ".tiny2xx" + id = "t202"; + desc = "ATtiny202"; + signature = 0x1E 0x91 0x23; +; + +#------------------------------------------------------------ +# ATtiny204 +#------------------------------------------------------------ + +part parent ".tiny2xx" + id = "t204"; + desc = "ATtiny204"; + signature = 0x1E 0x91 0x22; +; + +#------------------------------------------------------------ +# ATtiny402 +#------------------------------------------------------------ + +part parent ".tiny4xx" + id = "t402"; + desc = "ATtiny402"; + signature = 0x1E 0x92 0x27; +; + +#------------------------------------------------------------ +# ATtiny402w = workaround to address wrong device signature on some chips +#------------------------------------------------------------ + +part parent ".tiny4xx" + id = "t402w"; + desc = "ATtiny402w"; + signature = 0x1E 0x92 0x25; +; + +#------------------------------------------------------------ +# ATtiny404 +#------------------------------------------------------------ + +part parent ".tiny4xx" + id = "t404"; + desc = "ATtiny404"; + signature = 0x1E 0x92 0x26; +; + +#------------------------------------------------------------ +# ATtiny406 +#------------------------------------------------------------ + +part parent ".tiny4xx" + id = "t406"; + desc = "ATtiny406"; + signature = 0x1E 0x92 0x25; +; + +#------------------------------------------------------------ +# ATtiny804 +#------------------------------------------------------------ + +part parent ".tiny8xx" + id = "t804"; + desc = "ATtiny804"; + signature = 0x1E 0x93 0x25; +; + +#------------------------------------------------------------ +# ATtiny806 +#------------------------------------------------------------ + +part parent ".tiny8xx" + id = "t806"; + desc = "ATtiny806"; + signature = 0x1E 0x93 0x24; +; + +#------------------------------------------------------------ +# ATtiny807 +#------------------------------------------------------------ + +part parent ".tiny8xx" + id = "t807"; + desc = "ATtiny807"; + signature = 0x1E 0x93 0x23; +; + +#------------------------------------------------------------ +# ATtiny1604 +#------------------------------------------------------------ + +part parent ".tiny16xx" + id = "t1604"; + desc = "ATtiny1604"; + signature = 0x1E 0x94 0x25; +; + +#------------------------------------------------------------ +# ATtiny1606 +#------------------------------------------------------------ + +part parent ".tiny16xx" + id = "t1606"; + desc = "ATtiny1606"; + signature = 0x1E 0x94 0x24; +; + +#------------------------------------------------------------ +# ATtiny1607 +#------------------------------------------------------------ + +part parent ".tiny16xx" + id = "t1607"; + desc = "ATtiny1607"; + signature = 0x1E 0x94 0x23; +; + +#------------------------------------------------------------ +# ATtiny212 +#------------------------------------------------------------ + +part parent ".tiny2xx" + id = "t212"; + desc = "ATtiny212"; + signature = 0x1E 0x91 0x21; +; + +#------------------------------------------------------------ +# ATtiny214 +#------------------------------------------------------------ + +part parent ".tiny2xx" + id = "t214"; + desc = "ATtiny214"; + signature = 0x1E 0x91 0x20; +; + +#------------------------------------------------------------ +# ATtiny412 +#------------------------------------------------------------ + +part parent ".tiny4xx" + id = "t412"; + desc = "ATtiny412"; + signature = 0x1E 0x92 0x23; +; + + +#------------------------------------------------------------ +# ATtiny414 +#------------------------------------------------------------ + +part parent ".tiny4xx" + id = "t414"; + desc = "ATtiny414"; + signature = 0x1E 0x92 0x22; +; + +#------------------------------------------------------------ +# ATtiny416 +#------------------------------------------------------------ + +part parent ".tiny4xx" + id = "t416"; + desc = "ATtiny416"; + signature = 0x1E 0x92 0x21; +; + + +#------------------------------------------------------------ +# ATtiny417 +#------------------------------------------------------------ + +part parent ".tiny4xx" + id = "t417"; + desc = "ATtiny417"; + signature = 0x1E 0x92 0x20; +; + + +#------------------------------------------------------------ +# ATtiny814 +#------------------------------------------------------------ + +part parent ".tiny8xx" + id = "t814"; + desc = "ATtiny814"; + signature = 0x1E 0x93 0x22; +; + + +#------------------------------------------------------------ +# ATtiny816 +#------------------------------------------------------------ + +part parent ".tiny8xx" + id = "t816"; + desc = "ATtiny816"; + signature = 0x1E 0x93 0x21; +; + +#------------------------------------------------------------ +# ATtiny817 +#------------------------------------------------------------ + +part parent ".tiny8xx" + id = "t817"; + desc = "ATtiny817"; + signature = 0x1E 0x93 0x20; +; + +#------------------------------------------------------------ +# ATtiny1614 +#------------------------------------------------------------ + +part parent ".tiny16xx" + id = "t1614"; + desc = "ATtiny1614"; + signature = 0x1E 0x94 0x22; +; + +#------------------------------------------------------------ +# ATtiny1616 +#------------------------------------------------------------ + +part parent ".tiny16xx" + id = "t1616"; + desc = "ATtiny1616"; + signature = 0x1E 0x94 0x21; +; + +#------------------------------------------------------------ +# ATtiny1617 +#------------------------------------------------------------ + +part parent ".tiny16xx" + id = "t1617"; + desc = "ATtiny1617"; + signature = 0x1E 0x94 0x20; +; + +#------------------------------------------------------------ +# ATtiny3214 +#------------------------------------------------------------ + +part parent ".tiny32xx" + id = "t3214"; + desc = "ATtiny3214"; + signature = 0x1E 0x95 0x20; +; + +#------------------------------------------------------------ +# ATtiny3216 +#------------------------------------------------------------ + +part parent ".tiny32xx" + id = "t3216"; + desc = "ATtiny3216"; + signature = 0x1E 0x95 0x21; +; + +#------------------------------------------------------------ +# ATtiny3217 +#------------------------------------------------------------ + +part parent ".tiny32xx" + id = "t3217"; + desc = "ATtiny3217"; + signature = 0x1E 0x95 0x22; +; + +#------------------------------------------------------------ +# ATtiny424 +#------------------------------------------------------------ + +part parent ".tiny4xx" + id = "t424"; + desc = "ATtiny424"; + signature = 0x1E 0x92 0x2C; +; + +#------------------------------------------------------------ +# ATtiny426 +#------------------------------------------------------------ + +part parent ".tiny4xx" + id = "t426"; + desc = "ATtiny426"; + signature = 0x1E 0x92 0x2B; +; + + +#------------------------------------------------------------ +# ATtiny427 +#------------------------------------------------------------ + +part parent ".tiny4xx" + id = "t427"; + desc = "ATtiny427"; + signature = 0x1E 0x92 0x2A; +; + + +#------------------------------------------------------------ +# ATtiny824 +#------------------------------------------------------------ + +part parent ".tiny8xx" + id = "t824"; + desc = "ATtiny824"; + signature = 0x1E 0x93 0x29; +; + + +#------------------------------------------------------------ +# ATtiny826 +#------------------------------------------------------------ + +part parent ".tiny8xx" + id = "t826"; + desc = "ATtiny826"; + signature = 0x1E 0x93 0x28; +; + +#------------------------------------------------------------ +# ATtiny827 +#------------------------------------------------------------ + +part parent ".tiny8xx" + id = "t827"; + desc = "ATtiny827"; + signature = 0x1E 0x93 0x27; +; + +#------------------------------------------------------------ +# ATtiny1624 +#------------------------------------------------------------ + +part parent ".tiny16xx" + id = "t1624"; + desc = "ATtiny1624"; + signature = 0x1E 0x94 0x2A; +; + +#------------------------------------------------------------ +# ATtiny1626 +#------------------------------------------------------------ + +part parent ".tiny16xx" + id = "t1626"; + desc = "ATtiny1626"; + signature = 0x1E 0x94 0x29; +; + +#------------------------------------------------------------ +# ATtiny1627 +#------------------------------------------------------------ + +part parent ".tiny16xx" + id = "t1627"; + desc = "ATtiny1627"; + signature = 0x1E 0x94 0x28; +; + +#------------------------------------------------------------ +# ATmega808 +#------------------------------------------------------------ + +part parent ".mega80x" + id = "m808"; + desc = "ATmega808"; + signature = 0x1E 0x93 0x26; +; + +#------------------------------------------------------------ +# ATmega809 +#------------------------------------------------------------ + +part parent ".mega80x" + id = "m809"; + desc = "ATmega809"; + signature = 0x1E 0x93 0x2A; +; + +#------------------------------------------------------------ +# ATmega1608 +#------------------------------------------------------------ + +part parent ".mega160x" + id = "m1608"; + desc = "ATmega1608"; + signature = 0x1E 0x94 0x27; +; + +#------------------------------------------------------------ +# ATmega1609 +#------------------------------------------------------------ + +part parent ".mega160x" + id = "m1609"; + desc = "ATmega1609"; + signature = 0x1E 0x94 0x26; +; + +#------------------------------------------------------------ +# ATmega3208 +#------------------------------------------------------------ + +part parent ".mega320x" + id = "m3208"; + desc = "ATmega3208"; + signature = 0x1E 0x95 0x30; +; + +#------------------------------------------------------------ +# ATmega3209 +#------------------------------------------------------------ + +part parent ".mega320x" + id = "m3209"; + desc = "ATmega3209"; + signature = 0x1E 0x95 0x31; +; + +#------------------------------------------------------------ +# ATmega4808 +#------------------------------------------------------------ + +part parent ".mega480x" + id = "m4808"; + desc = "ATmega4808"; + signature = 0x1E 0x96 0x50; +; + +#------------------------------------------------------------ +# ATmega4809 +#------------------------------------------------------------ + +part parent ".mega480x" + id = "m4809"; + desc = "ATmega4809"; + signature = 0x1E 0x96 0x51; +; + +#------------------------------------------------------------ +# AVR-Dx class common values +#------------------------------------------------------------ + +part + id = ".avrdx"; + desc = "AVR-Dx class common values"; +# has_updi = yes; + has_pdi = yes; + nvm_base = 0x1000; +# ocd_base = 0x0F80; + + memory "signature" # these are the first 3 bytes of the USERROW memory area + size = 3; + offset = 0x1100; + ; + + memory "prodsig" # this is the name avrdude recognises for the USERROW memory area + size = 0x80; + offset = 0x1100; + page_size = 0x80; + readsize = 0x80; + ; + + memory "fuses" # first 9 bytes of fuse memory area, writing to undocumented fuses may be dangerous! + size = 9; + offset = 0x1050; + ; + + memory "fuse0" + size = 1; + offset = 0x1050; + ; + + memory "fuse1" + size = 1; + offset = 0x1051; + ; + + memory "fuse2" + size = 1; + offset = 0x1052; + ; + + memory "fuse5" + size = 1; + offset = 0x1055; + ; + + memory "fuse6" + size = 1; + offset = 0x1056; + ; + + memory "fuse7" + size = 1; + offset = 0x1057; + ; + + memory "fuse8" + size = 1; + offset = 0x1058; + ; + + memory "fuserow" # this is the entire fuse memory area, writing to undocumented fuses may be dangerous! + size = 0x10; + offset = 0x1050; + ; + + memory "lock" + size = 4; + offset = 0x1040; + ; + + memory "data" + # SRAM, only used to supply the offset + offset = 0x1000000; + ; + + memory "usersig" + size = 0x20; + offset = 0x1080; + page_size = 0x20; + readsize = 0x20; + ; + + memory "mmflash" # memory mapped flash window (aka MAPPED_PROGMEM). + size = 0x8000; + offset = 0x8000; + page_size = 0x200; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# AVR128DA sub-family common values +#------------------------------------------------------------ + +part parent ".avrdx" + id = ".avr128da"; + desc = "AVR-DA with 128KB flash common values"; + + memory "flash" + size = 0x20000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "eeprom" + size = 0x200; + offset = 0x1400; + page_size = 0x1; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# AVR64DA sub-family common values +#------------------------------------------------------------ + +part parent ".avrdx" + id = ".avr64da"; + desc = "AVR-DA with 64KB flash common values"; + + memory "flash" + size = 0x10000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "eeprom" + size = 0x200; + offset = 0x1400; + page_size = 0x1; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# AVR32DA sub-family common values +#------------------------------------------------------------ + +part parent ".avrdx" + id = ".avr32da"; + desc = "AVR-DA with 32KB flash common values"; + + memory "flash" + size = 0x8000; + offset = 0x800000; + page_size = 0x200; + readsize = 0x100; + ; + + memory "eeprom" + size = 0x200; + offset = 0x1400; + page_size = 0x1; + readsize = 0x100; + ; +; + +#------------------------------------------------------------ +# AVR128DB sub-family common values +#------------------------------------------------------------ + +part parent ".avr128da" # The AVR-DB have identical memory layout to AVR-DA + id = ".avr128db"; + desc = "AVR-DB with 128KB flash common values"; +; + +#------------------------------------------------------------ +# AVR128DA28 +#------------------------------------------------------------ + +part parent ".avr128da" + id = "avr128da28"; + desc = "AVR128DA28"; + signature = 0x1E 0x97 0x0A; +; + +#------------------------------------------------------------ +# AVR128DA32 +#------------------------------------------------------------ + +part parent ".avr128da" + id = "avr128da32"; + desc = "AVR128DA32"; + signature = 0x1E 0x97 0x09; +; + +#------------------------------------------------------------ +# AVR128DA48 +#------------------------------------------------------------ + +part parent ".avr128da" + id = "avr128da48"; + desc = "AVR128DA48"; + signature = 0x1E 0x97 0x08; +; + +#------------------------------------------------------------ +# AVR128DA64 +#------------------------------------------------------------ + +part parent ".avr128da" + id = "avr128da64"; + desc = "AVR128DA64"; + signature = 0x1E 0x97 0x07; +; + +#------------------------------------------------------------ +# AVR64DA28 +#------------------------------------------------------------ + +part parent ".avr64da" + id = "avr64da28"; + desc = "AVR64DA28"; + signature = 0x1E 0x96 0x15; +; + +#------------------------------------------------------------ +# AVR64DA32 +#------------------------------------------------------------ + +part parent ".avr64da" + id = "avr64da32"; + desc = "AVR64DA32"; + signature = 0x1E 0x96 0x14; +; + +#------------------------------------------------------------ +# AVR64DA48 +#------------------------------------------------------------ + +part parent ".avr64da" + id = "avr64da48"; + desc = "AVR64DA48"; + signature = 0x1E 0x96 0x13; +; + +#------------------------------------------------------------ +# AVR64DA64 +#------------------------------------------------------------ + +part parent ".avr64da" + id = "avr64da64"; + desc = "AVR64DA64"; + signature = 0x1E 0x96 0x12; +; + +#------------------------------------------------------------ +# AVR32DA28 +#------------------------------------------------------------ + +part parent ".avr32da" + id = "avr32da28"; + desc = "AVR32DA28"; + signature = 0x1E 0x95 0x34; +; + +#------------------------------------------------------------ +# AVR32DA32 +#------------------------------------------------------------ + +part parent ".avr32da" + id = "avr32da32"; + desc = "AVR32DA32"; + signature = 0x1E 0x95 0x33; +; + +#------------------------------------------------------------ +# AVR32DA48 +#------------------------------------------------------------ + +part parent ".avr32da" + id = "avr32da48"; + desc = "AVR32DA48"; + signature = 0x1E 0x95 0x32; +; + +#------------------------------------------------------------ +# AVR128DB28 +#------------------------------------------------------------ + +part parent ".avr128db" + id = "avr128db28"; + desc = "AVR128DB28"; + signature = 0x1E 0x97 0x0E; +; + +#------------------------------------------------------------ +# AVR128DB32 +#------------------------------------------------------------ + +part parent ".avr128db" + id = "avr128db32"; + desc = "AVR128DB32"; + signature = 0x1E 0x97 0x0D; +; + +#------------------------------------------------------------ +# AVR128DB48 +#------------------------------------------------------------ + +part parent ".avr128db" + id = "avr128db48"; + desc = "AVR128DB48"; + signature = 0x1E 0x97 0x0C; +; + +#------------------------------------------------------------ +# AVR128DB64 +#------------------------------------------------------------ + +part parent ".avr128db" + id = "avr128db64"; + desc = "AVR128DB64"; + signature = 0x1E 0x97 0x0B; +; + +#------------------------------------------------------------ +# jtag2updi programmer definitions +#------------------------------------------------------------ + + +programmer + id = "jtag2updi"; + desc = "JTAGv2 to UPDI bridge"; + type = "jtagmkii_pdi"; + connection_type = serial; + baudrate = 115200; +; diff --git a/software/tools/avrdude/readme.txt b/software/tools/avrdude/readme.txt new file mode 100644 index 0000000..aa0f63c --- /dev/null +++ b/software/tools/avrdude/readme.txt @@ -0,0 +1,3 @@ +Description: Modified avrdude config file to work with jtag2updi +Source: https://github.com/ElTangas/jtag2updi +License: MIT License diff --git a/software/tools/dfp/gcc/dev/attiny1604/avrxmega3/crtattiny1604.o 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HcmV?d00001 diff --git a/software/tools/dfp/gcc/dev/attiny1604/device-specs/specs-attiny1604 b/software/tools/dfp/gcc/dev/attiny1604/device-specs/specs-attiny1604 new file mode 100644 index 0000000..457cca3 --- /dev/null +++ b/software/tools/dfp/gcc/dev/attiny1604/device-specs/specs-attiny1604 @@ -0,0 +1,107 @@ +# +# Auto-generated specs for AVR device attiny1604 (core avrxmega3, 16-bit SP) +# +# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c +# Generated from : ./gcc/config/gcc.c +# ./gcc/config/avr/specs.h +# ./gcc/config/avr/avrlibc.h +# Used by : avr-gcc compiler driver +# Used for : building command options for sub-processes +# +# See +# for a documentation of spec files. + + +# If you intend to use an existing device specs file as a starting point +# for a new device spec file, make sure you are copying from a specs +# file for a device from the same core architecture and SP width. +# See for a description +# of how to use such own spec files. + +*avrlibc_startfile: + crtattiny1604.o%s + +*avrlibc_devicelib: + %{!nodevicelib:-lattiny1604} + +*cc1_n_flash: + %{!mn-flash=*:-mn-flash=1} + +*cc1_rmw: + %{mrmw} + +*cc1_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*cc1_absdata: + %{mabsdata} + +*asm_arch: + -mmcu=avrxmega3 + +*asm_relax: + %{mrelax:--mlink-relax} + +*asm_rmw: + %{mrmw} + +*asm_gccisr: + %{!mno-gas-isr-prologues: -mgcc-isr} + +*asm_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*link_pmem_wrap: + %{mpmem-wrap-around: --pmem-wrap-around=16k} + +*link_relax: + %{mrelax:--relax} + +*link_arch: + %{mmcu=*:-m%*} + +*link_data_start: + -Tdata 0x803C00 + +*link_text_start: + + +*self_spec: + % +# #elif ... +# +# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ +# as fallback to determine the name of the device header as +# +# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" +# +# If you provide your own specs file for a device not yet known to +# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ +# as needed so that +# +# #include +# +# will include the desired device header. For ATmega8A the supplement +# to *cpp would read +# +# -D__AVR_DEV_LIB_NAME__=m8a + + +*cpp: + -D__AVR_ATtiny1604__ -D__AVR_DEVICE_NAME__=attiny1604 -D__AVR_DEV_LIB_NAME__=tn1604 + +%rename link old_link + +*link: + %(old_link)--defsym=__RODATA_PM_OFFSET__=0x8000 + +# End of file diff --git a/software/tools/dfp/gcc/dev/attiny1614/avrxmega3/crtattiny1614.o b/software/tools/dfp/gcc/dev/attiny1614/avrxmega3/crtattiny1614.o new file mode 100644 index 0000000000000000000000000000000000000000..6f68d92fbe4e899076009cfda83faf23f4aec69f GIT binary patch literal 23084 zcmdVh2Y3{9{>SmzY!U*Ygr!LjRX~a9z=@DevLumBVRsY276J+7q!SRVq4(aaG^HpA zC?KK&A|O?;IB8h2AQ7RmfMNK!rjTid5*Mf=>m%3IP?0RVY!R zuL}KC=&!;ZD%`2UT`JtI!aXXKsxUx>G8G1@Fi3@R6)IF1tili#hN>`3h2N`iuL{Fe z7@@*Q6-KErT7@wxj8$Qr3Y991S7Cw*_o*;Zg-I&hufhW=JgCA$Dm<*hBPvumRGF;F z6iudTGEI}|n#|B-rY5sAnXSnjP3CGcPm}qYEYM`3CW|y#tjQ8hmTIz0ljWMM&}5}1 zt29}y$r?@8YO+p~^_pzZ8~o zG?}8wR86L7GF_7yn#|N>mL{_`nWM>EP3CDbUy}uzEYxI?CW|#$qRCQCmT9tFlNFk* z)MS+=t2J4p$y!a;X|i6E4VpZv$wo~!X|h?9Et+iAweXmo+(|$w^I4Y4VCDr!_gF$yrU#X>wkZ3!1#D$wf^rY4VyTuWMo~y#a5ZoA0Yf z2H$cwryVg);)rUI=A}k`j2uzUs^}^sO2`Zd-h-!s=a~YjCS)cgM#wBkbs-BNc$1z6 zUd|i{-qH_~g^-#;7C~wWSplgnWC^5>kd=@)Aq^pQg~UKyLJUYfAr1&_EC$}@2uK4V zPDn!`k&s40YC`Zp(7?;74rwf;2Be9QSV&VL(U4}A&;@wB;vmh%JW-GqLTW);ifh$} z#0zmjT8V3wKw1mQg|rcp0ck754QVGN6VhHt7UV`D*^mxGypWDU@*tgr+zz=(NN>o^ zLV7_uTf+BP5hOv(wL zvV@dDvV{zUc!Ugs^b#@#k|Sg+Bv;62NS=_1klTek2|?S_CoFwG6ieDTgX(%Jwm2IN`*{^3=mQUDHE~;GEm4;$RHuhAmu`qLn?%wp~Q9|ZIMhlq?86#vfWUP=a zka0q0x~hyyA(J8Fh0KCX5HbaFpOER0i9%*TCJC7axnD>X$s0a+Sj(KCH*YRT-0+_<3M}rbu#trphZugQm&3oS^BFB0)1GMSx~XG9s&t zS&||^vn4q|b0j%Ib0x)q=1Hm!nlC95v_MicXrZJi&>~6IK#L{CftEJR#wiMM_;=o?8} zLDwYh1br)MJLo$}yFuSedJ^;lQ+>mFp9S<+Ns~c8N}2-to203rpCnBK{VZt%=od+= zK)*^_4f;*eGSJ^8EeBnfGz(M}fm?!sZ_sSeWJyavQzR_{O_j75G)>Yx&~!=jK{F&R z0L_#XhbP}GNiNWANsT~rBsB!hl~fNjPf~r*d`UNe7D#FUS}3U*Xpy8Apv96JgO*5Y z0$M7mIcS-rrl93ayhq1?R>--cKr1ChgH}nZ23jpC7PLlEP0(6N4$wMD257yc+Mo@R zB0-Nza)LHWiU4hrR136Ol2H$@za%+8TO~z+9+Tt*JuWE{v`tbJXuG6n&<;t}KszPH zfS!<49rUE68lYX0VnMql)dW2ysTOFDq}rgplIno=Ns0qKEvYW(8A&eCeo6H}2PD-8 z9hB4n^sJ_QVq~KNwJ{wlB$C)NZJT` zRnjKVMM;}Mmn3Zgy(Y=P3*FZxIY34}&L6H25}LbkN3!!AB0dJrU-uqW>ezw*EIA z(_yn8ir|}XEv0P2*v`X;4IC7ooRFB1XpA2=va)Mwr8!PYM`Q(jUbm4~5TG#fi~CvN z54Z!x{{QY$w>K}-$STawcNb*yl4#*D{GVn1Z@I_F&df2_?dV z`VF7QZ}{E$MdnNaPkxcnH?JT!K>vFKM%MrM3eEeDHYPK84+b}x@4*spKF#3fJHT5U zNVKNy$~5fCqDl&0YL*UWyp!BU*hHp1VQwZaNJ-}9^$VZK$|^GaMY;I#8h)QA$G$-&-ozqbp5ZO=CY5-w zk>NWIZC0kFY$^LYW@QE}`ri%5I@d3SV8=`jV0j`vzF!By*ZKmWbA$Xd)G^T2$o0QzNr5JF8a? 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SC?=31UzGbhQ?yZ0fByscCIV&v literal 0 HcmV?d00001 diff --git a/software/tools/dfp/gcc/dev/attiny1614/device-specs/specs-attiny1614 b/software/tools/dfp/gcc/dev/attiny1614/device-specs/specs-attiny1614 new file mode 100644 index 0000000..c23a0d1 --- /dev/null +++ b/software/tools/dfp/gcc/dev/attiny1614/device-specs/specs-attiny1614 @@ -0,0 +1,107 @@ +# +# Auto-generated specs for AVR device attiny1614 (core avrxmega3, 16-bit SP) +# +# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c +# Generated from : ./gcc/config/gcc.c +# ./gcc/config/avr/specs.h +# ./gcc/config/avr/avrlibc.h +# Used by : avr-gcc compiler driver +# Used for : building command options for sub-processes +# +# See +# for a documentation of spec files. + + +# If you intend to use an existing device specs file as a starting point +# for a new device spec file, make sure you are copying from a specs +# file for a device from the same core architecture and SP width. +# See for a description +# of how to use such own spec files. + +*avrlibc_startfile: + crtattiny1614.o%s + +*avrlibc_devicelib: + %{!nodevicelib:-lattiny1614} + +*cc1_n_flash: + %{!mn-flash=*:-mn-flash=1} + +*cc1_rmw: + %{mrmw} + +*cc1_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*cc1_absdata: + %{mabsdata} + +*asm_arch: + -mmcu=avrxmega3 + +*asm_relax: + %{mrelax:--mlink-relax} + +*asm_rmw: + %{mrmw} + +*asm_gccisr: + %{!mno-gas-isr-prologues: -mgcc-isr} + +*asm_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*link_pmem_wrap: + %{mpmem-wrap-around: --pmem-wrap-around=16k} + +*link_relax: + %{mrelax:--relax} + +*link_arch: + %{mmcu=*:-m%*} + +*link_data_start: + -Tdata 0x803800 + +*link_text_start: + + +*self_spec: + % +# #elif ... +# +# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ +# as fallback to determine the name of the device header as +# +# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" +# +# If you provide your own specs file for a device not yet known to +# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ +# as needed so that +# +# #include +# +# will include the desired device header. For ATmega8A the supplement +# to *cpp would read +# +# -D__AVR_DEV_LIB_NAME__=m8a + + +*cpp: + -D__AVR_ATtiny1614__ -D__AVR_DEVICE_NAME__=attiny1614 -D__AVR_DEV_LIB_NAME__=tn1614 + +%rename link old_link + +*link: + %(old_link)--defsym=__RODATA_PM_OFFSET__=0x8000 + +# End of file diff --git a/software/tools/dfp/gcc/dev/attiny204/avrxmega3/short-calls/crtattiny204.o b/software/tools/dfp/gcc/dev/attiny204/avrxmega3/short-calls/crtattiny204.o new file mode 100644 index 0000000000000000000000000000000000000000..32b3c70a4f5b2e03d6298366fdb5c1e1a663cb47 GIT binary patch literal 18600 zcmd7ad3+Of{>SleI&CSGque)?OYYL7w1B9PrfI392T5AMs}@?Z3I$3z)K$uTcmg7d zq9|S{-WPZQo}7x}vAC$Hi>SCN;<29W`!o4WlF#?Mzu#|v|Lv^pyylt7%w#ed(n%gW z-yg_#xm?N_Tq>kuQ%Vi@D|HMv4z*|Kr`oC3O6_p9boFVTmaJ4lZ)G)4O+71BDJzzV zL!qaqj!Z3VJ*sI!6Qz=LNY(p_vZNb!eeOnhq^>Xr)7I9op#7 zR)=;vwAZ174jpyqq(f&Ny6DhVhi*D_*CAbp9y;{Yp_dN5b?BqRX*%@Pp`Q-@br_(- zKph6@Fj$8S9fs(Tse@Ywj}BQn4Ami9ha4S-=`dV}5jvc%!$=*@(BVuS&eCC&4x@GO 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of how to use such own spec files. + +*avrlibc_startfile: + crtattiny204.o%s + +*avrlibc_devicelib: + %{!nodevicelib:-lattiny204} + +*cc1_n_flash: + %{!mn-flash=*:-mn-flash=1} + +*cc1_rmw: + %{mrmw} + +*cc1_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*cc1_absdata: + %{mabsdata} + +*asm_arch: + -mmcu=avrxmega3 + +*asm_relax: + %{mrelax:--mlink-relax} + +*asm_rmw: + %{mrmw} + +*asm_gccisr: + %{!mno-gas-isr-prologues: -mgcc-isr} + +*asm_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*link_pmem_wrap: + + +*link_relax: + %{mrelax:--relax} + +*link_arch: + %{mmcu=*:-m%*} + +*link_data_start: + -Tdata 0x803F80 + +*link_text_start: + + +*self_spec: + % +# #elif ... +# +# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ +# as fallback to determine the name of the device header as +# +# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" +# +# If you provide your own specs file for a device not yet known to +# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ +# as needed so that +# +# #include +# +# will include the desired device header. For ATmega8A the supplement +# to *cpp would read +# +# -D__AVR_DEV_LIB_NAME__=m8a + + +*cpp: + -D__AVR_ATtiny204__ -D__AVR_DEVICE_NAME__=attiny204 -D__AVR_DEV_LIB_NAME__=tn204 + +%rename link old_link + +*link: + %(old_link)--defsym=__RODATA_PM_OFFSET__=0x8000 + +# End of file diff --git a/software/tools/dfp/gcc/dev/attiny214/avrxmega3/short-calls/crtattiny214.o b/software/tools/dfp/gcc/dev/attiny214/avrxmega3/short-calls/crtattiny214.o new file mode 100644 index 0000000000000000000000000000000000000000..065067e4abc121e43ad0f3457093fd60ec6b11a5 GIT binary patch literal 20312 zcmd7ad0-Rey2tT1owgLpQuZCnrlL@rw6x#?q-iLXbTLT_h*}F&tU|$35M0A5i^z@w zvdQX#3+i!K5O-1WDDDfcxE&R@qau2L&*YgT&-?1V=l*x*n9g@TnaoTklS!L|bB#YR z%;j<^XK<;Iiccx^`3R+s;L2QkhLcn~)mo{&u9mJo%`;M!O6skw=IQB!)0MK~nVbtf zE&cTL;?_f&CN)tiMTb-!8tIUxLt`D9=#Z{MQyrS=&|HTWI%Me3QioPLwAP`G4sCU4 zr$c)kI_S_*hfX?l)}f0IU3KWDLw6lAb?Bi(PaS&c&|8N-I-H=xi8`F5Lthu{D1BXkJpP@+Sr4rMx&>u|OXK^;OmgmtLUp;CvDI*ig` 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If you intend to use an existing device specs file as a starting point +# for a new device spec file, make sure you are copying from a specs +# file for a device from the same core architecture and SP width. +# See for a description +# of how to use such own spec files. + +*avrlibc_startfile: + crtattiny214.o%s + +*avrlibc_devicelib: + %{!nodevicelib:-lattiny214} + +*cc1_n_flash: + %{!mn-flash=*:-mn-flash=1} + +*cc1_rmw: + %{mrmw} + +*cc1_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*cc1_absdata: + %{mabsdata} + +*asm_arch: + -mmcu=avrxmega3 + +*asm_relax: + %{mrelax:--mlink-relax} + +*asm_rmw: + %{mrmw} + +*asm_gccisr: + %{!mno-gas-isr-prologues: -mgcc-isr} + +*asm_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*link_pmem_wrap: + + +*link_relax: + %{mrelax:--relax} + +*link_arch: + %{mmcu=*:-m%*} + +*link_data_start: + -Tdata 0x803F80 + +*link_text_start: + + +*self_spec: + % +# #elif ... +# +# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ +# as fallback to determine the name of the device header as +# +# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" +# +# If you provide your own specs file for a device not yet known to +# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ +# as needed so that +# +# #include +# +# will include the desired device header. For ATmega8A the supplement +# to *cpp would read +# +# -D__AVR_DEV_LIB_NAME__=m8a + + +*cpp: + -D__AVR_ATtiny214__ -D__AVR_DEVICE_NAME__=attiny214 -D__AVR_DEV_LIB_NAME__=tn214 + +%rename link old_link + +*link: + %(old_link)--defsym=__RODATA_PM_OFFSET__=0x8000 + +# End of file diff --git a/software/tools/dfp/gcc/dev/attiny404/avrxmega3/short-calls/crtattiny404.o b/software/tools/dfp/gcc/dev/attiny404/avrxmega3/short-calls/crtattiny404.o new file mode 100644 index 0000000000000000000000000000000000000000..d2ca724f4da5bb8dcab40017e9032d52ae4ca123 GIT binary patch literal 18600 zcmd7ad3+Of{>SleI&CSGque*N9CDW?JpfT5P190I50aF_s}`tOg#x7<>MG?vJOL3! zQ4}u}?+d&DPfkVgSX@-pMO0iB@mNpx{h53w$>;ms-|x4-|8~}PUh|yE%w#ed(jCjS#RywrSp^Xl0 zb!ewUdmTFH&{2m@I&{{diw<3N=%zz=9ny8k(4mJ8J$2}%LvI~U)1i+JeRb%kLw_9x z=rB-+K{{mWFj$8y9o#y2bja2rM~7S;@^l!Y!%!WD>2SIZ!*w`Ahck6JONS9UjMTxa zL%t3^9SU^t>rkjekq)DDDAwU@9Y*UA(4j@Z}fAuk#7 zvLUY+@~R=P8S=UzyA0WF$R0!X8nVxj{f4|@$eV^7Fyt*m-Ztc*A@3OSt|9Lk^1dN| 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short-calls) +# +# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c +# Generated from : ./gcc/config/gcc.c +# ./gcc/config/avr/specs.h +# ./gcc/config/avr/avrlibc.h +# Used by : avr-gcc compiler driver +# Used for : building command options for sub-processes +# +# See +# for a documentation of spec files. + + +# If you intend to use an existing device specs file as a starting point +# for a new device spec file, make sure you are copying from a specs +# file for a device from the same core architecture and SP width. +# See for a description +# of how to use such own spec files. + +*avrlibc_startfile: + crtattiny404.o%s + +*avrlibc_devicelib: + %{!nodevicelib:-lattiny404} + +*cc1_n_flash: + %{!mn-flash=*:-mn-flash=1} + +*cc1_rmw: + %{mrmw} + +*cc1_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*cc1_absdata: + %{mabsdata} + +*asm_arch: + -mmcu=avrxmega3 + +*asm_relax: + %{mrelax:--mlink-relax} + +*asm_rmw: + %{mrmw} + +*asm_gccisr: + %{!mno-gas-isr-prologues: -mgcc-isr} + +*asm_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*link_pmem_wrap: + + +*link_relax: + %{mrelax:--relax} + +*link_arch: + %{mmcu=*:-m%*} + +*link_data_start: + -Tdata 0x803F00 + +*link_text_start: + + +*self_spec: + % +# #elif ... +# +# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ +# as fallback to determine the name of the device header as +# +# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" +# +# If you provide your own specs file for a device not yet known to +# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ +# as needed so that +# +# #include +# +# will include the desired device header. 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short-calls) +# +# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c +# Generated from : ./gcc/config/gcc.c +# ./gcc/config/avr/specs.h +# ./gcc/config/avr/avrlibc.h +# Used by : avr-gcc compiler driver +# Used for : building command options for sub-processes +# +# See +# for a documentation of spec files. + + +# If you intend to use an existing device specs file as a starting point +# for a new device spec file, make sure you are copying from a specs +# file for a device from the same core architecture and SP width. +# See for a description +# of how to use such own spec files. + +*avrlibc_startfile: + crtattiny414.o%s + +*avrlibc_devicelib: + %{!nodevicelib:-lattiny414} + +*cc1_n_flash: + %{!mn-flash=*:-mn-flash=1} + +*cc1_rmw: + %{mrmw} + +*cc1_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*cc1_absdata: + %{mabsdata} + +*asm_arch: + -mmcu=avrxmega3 + +*asm_relax: + %{mrelax:--mlink-relax} + +*asm_rmw: + %{mrmw} + +*asm_gccisr: + %{!mno-gas-isr-prologues: -mgcc-isr} + +*asm_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*link_pmem_wrap: + + +*link_relax: + %{mrelax:--relax} + +*link_arch: + %{mmcu=*:-m%*} + +*link_data_start: + -Tdata 0x803F00 + +*link_text_start: + + +*self_spec: + % +# #elif ... +# +# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ +# as fallback to determine the name of the device header as +# +# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" +# +# If you provide your own specs file for a device not yet known to +# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ +# as needed so that +# +# #include +# +# will include the desired device header. For ATmega8A the supplement +# to *cpp would read +# +# -D__AVR_DEV_LIB_NAME__=m8a + + +*cpp: + -D__AVR_ATtiny414__ -D__AVR_DEVICE_NAME__=attiny414 -D__AVR_DEV_LIB_NAME__=tn414 + +%rename link old_link + +*link: + %(old_link)--defsym=__RODATA_PM_OFFSET__=0x8000 + +# End of file diff --git a/software/tools/dfp/gcc/dev/attiny804/avrxmega3/short-calls/crtattiny804.o b/software/tools/dfp/gcc/dev/attiny804/avrxmega3/short-calls/crtattiny804.o new file mode 100644 index 0000000000000000000000000000000000000000..a4f6c21d94c046d7e7bd705e7c2735cb63c2885d GIT binary patch literal 19980 zcmeI(cX$-_zQ^(3W>SDqLN8K6$3o0*3Lpw3n@w2R6m~bkN(>M+0s%un(4#IORT1eO zK~${R#d4&mSW&U-5iEFA>|z%S=kuNY&hCDHzjNX6D)p3{V|ZTc!56TD$tT%t%!#sgJT+rl$`}SIUZK zaxV0=^r7kgw!@nzHB%}@hg2QXbZDYOQyrS=kgh{>9a`wnQioPLWa!XZhc-I2)uEjZ z?RDs&Lq{Dt>Cjn+E;^i`LsuQT>Cjz=9y(;|&{KzAI`r0|j}Cox=%+(}9R}!dq7EnN zaIy}k=rB-+EFDhOAzKHx4jvtHbjZ~qPltRR2I(+Zhaozgro&JjPS@cK9fs*JT!#@l z6zEW>gI9+l9eg?z>rkS@NFDq-oTQJUbxegUNjMgEjLr90P4wX7o=`coz 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+*asm_relax: + %{mrelax:--mlink-relax} + +*asm_rmw: + %{mrmw} + +*asm_gccisr: + %{!mno-gas-isr-prologues: -mgcc-isr} + +*asm_errata_skip: + %{!mskip-bug: -mno-skip-bug} + +*link_pmem_wrap: + %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} + +*link_relax: + %{mrelax:--relax} + +*link_arch: + %{mmcu=*:-m%*} + +*link_data_start: + -Tdata 0x803E00 + +*link_text_start: + + +*self_spec: + % +# #elif ... +# +# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ +# as fallback to determine the name of the device header as +# +# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" +# +# If you provide your own specs file for a device not yet known to +# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ +# as needed so that +# +# #include +# +# will include the desired device header. For ATmega8A the supplement +# to *cpp would read +# +# -D__AVR_DEV_LIB_NAME__=m8a + + +*cpp: + -D__AVR_ATtiny804__ -D__AVR_DEVICE_NAME__=attiny804 -D__AVR_DEV_LIB_NAME__=tn804 + +%rename link old_link + +*link: + %(old_link)--defsym=__RODATA_PM_OFFSET__=0x8000 + +# End of file diff --git a/software/tools/dfp/gcc/dev/attiny814/avrxmega3/short-calls/crtattiny814.o b/software/tools/dfp/gcc/dev/attiny814/avrxmega3/short-calls/crtattiny814.o new file mode 100644 index 0000000000000000000000000000000000000000..d980ce8106f3faf2b8e40b088f9b674fa0b9aaeb GIT binary patch literal 20312 zcmd7acVHCdy2tT%Gf4=95_*TwR1{)%6B4iho6Qm;o8s;!fGq|H5QP9CG;63*L^=vc z6BI1iJ%Sa)E-D_yUa%l49u?bB5xu`>_L<#%-dFEE_rEj8&3xxGvon*~*-5gyoNN7o zAug9oIfF}uRBTGAFNP^~6f?8!1x{0KR7<7yx|+LsHBC!aDxs&cnx>`>OjXK?Wnwn; ztkknp3tJ9qoX|+ABps4jdf_ELsK1^>5!&Fa~)df&{Bt1I<(fI zjSg*fXs1Ja9XjaHQHM@Cbk?DZ4qbIf*P)vZ-F4`pLr)!g>2Qh;r|NK;4!w0aU57Jt z=%Yhl9Wrz{Q-@3)+&Xx4$kHKOhkiQb=#Z;Je;o$saFz~d>u`<^=jt#}he0|F*1@Yo zo(?`8@^$d*Fhqv}9fs;qsKa?W4AUW?Ly-=}I+W;8s>As@1a%1M5Z0kghjJZ;>o7ux zkvd$U!-YCrq{GEJT%tpT4wvdsslzB8M(Z#}hbkS$>M%}+@j6uNaG4I5>o7rwi8|Ei zFiD5WI!w`_R)?uN)afuyhv_=Z&|#(yvvjyZhbwisN{6d;xJHL-b*OjgGTV?jhRii& zo+0xMSzyR@hAcE>ks*r>Sz^fbhAcJY21Aw^vfPjrhO9JXl_9GQS!2jrLvA$WCPUU4 zvfhvlhTLq(Mng6kve}R=hHN$D7DKifvfYqd4Y|#b9fs^Qc zk0JLOa-Sjh8}fi54;u22A^$MsVMBHsvd54|40+U$#|(MgkS7dz(vZD|>@(ykL-rf; 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For ATmega8A the supplement +# to *cpp would read +# +# -D__AVR_DEV_LIB_NAME__=m8a + + +*cpp: + -D__AVR_ATtiny814__ -D__AVR_DEVICE_NAME__=attiny814 -D__AVR_DEV_LIB_NAME__=tn814 + +%rename link old_link + +*link: + %(old_link)--defsym=__RODATA_PM_OFFSET__=0x8000 + +# End of file diff --git a/software/tools/dfp/include/avr/iotn1604.h b/software/tools/dfp/include/avr/iotn1604.h new file mode 100644 index 0000000..4e24070 --- /dev/null +++ b/software/tools/dfp/include/avr/iotn1604.h @@ -0,0 +1,4667 @@ +/* + * Copyright (C) 2021, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. Publication is not required when + * this file is used in an embedded application. + * + * 3. Microchip's name may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn1604.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY1604_H_INCLUDED +#define _AVR_ATTINY1604_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t reserved_2[7]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[2]; +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + +/* CCL.TRUTH0 bit masks and bit positions */ +#define CCL_TRUTH_gm 0xFF /* Truth Table group mask. */ +#define CCL_TRUTH_gp 0 /* Truth Table group position. */ +#define CCL_TRUTH0_bm (1<<0) /* Truth Table bit 0 mask. */ +#define CCL_TRUTH0_bp 0 /* Truth Table bit 0 position. */ +#define CCL_TRUTH1_bm (1<<1) /* Truth Table bit 1 mask. */ +#define CCL_TRUTH1_bp 1 /* Truth Table bit 1 position. */ +#define CCL_TRUTH2_bm (1<<2) /* Truth Table bit 2 mask. */ +#define CCL_TRUTH2_bp 2 /* Truth Table bit 2 position. */ +#define CCL_TRUTH3_bm (1<<3) /* Truth Table bit 3 mask. */ +#define CCL_TRUTH3_bp 3 /* Truth Table bit 3 position. */ +#define CCL_TRUTH4_bm (1<<4) /* Truth Table bit 4 mask. */ +#define CCL_TRUTH4_bp 4 /* Truth Table bit 4 position. */ +#define CCL_TRUTH5_bm (1<<5) /* Truth Table bit 5 mask. */ +#define CCL_TRUTH5_bp 5 /* Truth Table bit 5 position. */ +#define CCL_TRUTH6_bm (1<<6) /* Truth Table bit 6 mask. */ +#define CCL_TRUTH6_bp 6 /* Truth Table bit 6 position. */ +#define CCL_TRUTH7_bm (1<<7) /* Truth Table bit 7 mask. */ +#define CCL_TRUTH7_bp 7 /* Truth Table bit 7 position. */ + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + +/* CCL.TRUTH1 bit masks and bit positions */ +/* CCL_TRUTH is already defined. */ + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +/* USART_CMODE is already defined. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (49152) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (49152U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3C00) +# define INTERNAL_SRAM_SIZE (1024) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3C00U) +# define INTERNAL_SRAM_SIZE (1024U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x25 + + +#endif /* #ifdef _AVR_ATTINY1604_H_INCLUDED */ + diff --git a/software/tools/dfp/include/avr/iotn1614.h b/software/tools/dfp/include/avr/iotn1614.h new file mode 100644 index 0000000..f822cb3 --- /dev/null +++ b/software/tools/dfp/include/avr/iotn1614.h @@ -0,0 +1,5536 @@ +/* + * Copyright (C) 2021, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. Publication is not required when + * this file is used in an embedded application. + * + * 3. Microchip's name may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn1614.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY1614_H_INCLUDED +#define _AVR_ATTINY1614_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_PTC_gc = (0x1B<<0), /* PTC/DAC2 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0/DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ + CCL_INSEL0_AC1_gc = (0x0C<<0), /* AC1 OUT input source */ + CCL_INSEL0_TCB1_gc = (0x0D<<0), /* TCB1 WO input source */ + CCL_INSEL0_AC2_gc = (0x0E<<0), /* AC2 OUT input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_AC1_gc = (0x0C<<4), /* AC1 OUT input source */ + CCL_INSEL1_TCB1_gc = (0x0D<<4), /* TCB1WO input source */ + CCL_INSEL1_AC2_gc = (0x0E<<4), /* AC2 OUT input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ + CCL_INSEL2_AC1_gc = (0x0C<<0), /* AC1 OUT input source */ + CCL_INSEL2_TCB1_gc = (0x0D<<0), /* TCB1 WO input source */ + CCL_INSEL2_AC2_gc = (0x0E<<0), /* AC2 OUT input source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ + EVSYS_ASYNCCH2_AC1_OUT_gc = (0x10<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH2_AC2_OUT_gc = (0x11<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ + EVSYS_ASYNCCH3_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH3_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER11_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER11_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER12_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER12_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ + EVSYS_SYNCCH1_TCB1_gc = (0x10<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB0 select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TCB1 select */ +typedef enum PORTMUX_TCB1_enum +{ + PORTMUX_TCB1_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCB1_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCB1_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* ADC1 reference select select */ +typedef enum VREF_ADC1REFSEL_enum +{ + VREF_ADC1REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC1REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC1REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC1REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC1REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC1REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* DAC1/AC1 reference select select */ +typedef enum VREF_DAC1REFSEL_enum +{ + VREF_DAC1REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC1REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC1REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC1REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC1REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC1REFSEL_t; + +/* DAC2/AC2 reference select select */ +typedef enum VREF_DAC2REFSEL_enum +{ + VREF_DAC2REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC2REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC2REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC2REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC2REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC2REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define ADC1 (*(ADC_t *) 0x0640) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define AC1 (*(AC_t *) 0x0688) /* Analog Comparator */ +#define AC2 (*(AC_t *) 0x0690) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x06A0) /* Digital to Analog Converter */ +#define DAC1 (*(DAC_t *) 0x06A8) /* Digital to Analog Converter */ +#define DAC2 (*(DAC_t *) 0x06B0) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A50) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) +#define VREF_CTRLC _SFR_MEM8(0x00A2) +#define VREF_CTRLD _SFR_MEM8(0x00A3) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* ADC (ADC1) - Analog to Digital Converter */ +#define ADC1_CTRLA _SFR_MEM8(0x0640) +#define ADC1_CTRLB _SFR_MEM8(0x0641) +#define ADC1_CTRLC _SFR_MEM8(0x0642) +#define ADC1_CTRLD _SFR_MEM8(0x0643) +#define ADC1_CTRLE _SFR_MEM8(0x0644) +#define ADC1_SAMPCTRL _SFR_MEM8(0x0645) +#define ADC1_MUXPOS _SFR_MEM8(0x0646) +#define ADC1_COMMAND _SFR_MEM8(0x0648) +#define ADC1_EVCTRL _SFR_MEM8(0x0649) +#define ADC1_INTCTRL _SFR_MEM8(0x064A) +#define ADC1_INTFLAGS _SFR_MEM8(0x064B) +#define ADC1_DBGCTRL _SFR_MEM8(0x064C) +#define ADC1_TEMP _SFR_MEM8(0x064D) +#define ADC1_RES _SFR_MEM16(0x0650) +#define ADC1_RESL _SFR_MEM8(0x0650) +#define ADC1_RESH _SFR_MEM8(0x0651) +#define ADC1_WINLT _SFR_MEM16(0x0652) +#define ADC1_WINLTL _SFR_MEM8(0x0652) +#define ADC1_WINLTH _SFR_MEM8(0x0653) +#define ADC1_WINHT _SFR_MEM16(0x0654) +#define ADC1_WINHTL _SFR_MEM8(0x0654) +#define ADC1_WINHTH _SFR_MEM8(0x0655) +#define ADC1_CALIB _SFR_MEM8(0x0656) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* AC (AC1) - Analog Comparator */ +#define AC1_CTRLA _SFR_MEM8(0x0688) +#define AC1_MUXCTRLA _SFR_MEM8(0x068A) +#define AC1_INTCTRL _SFR_MEM8(0x068E) +#define AC1_STATUS _SFR_MEM8(0x068F) + + +/* AC (AC2) - Analog Comparator */ +#define AC2_CTRLA _SFR_MEM8(0x0690) +#define AC2_MUXCTRLA _SFR_MEM8(0x0692) +#define AC2_INTCTRL _SFR_MEM8(0x0696) +#define AC2_STATUS _SFR_MEM8(0x0697) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x06A0) +#define DAC0_DATA _SFR_MEM8(0x06A1) + + +/* DAC (DAC1) - Digital to Analog Converter */ +#define DAC1_CTRLA _SFR_MEM8(0x06A8) +#define DAC1_DATA _SFR_MEM8(0x06A9) + + +/* DAC (DAC2) - Digital to Analog Converter */ +#define DAC2_CTRLA _SFR_MEM8(0x06B0) +#define DAC2_DATA _SFR_MEM8(0x06B1) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A50) +#define TCB1_CTRLB _SFR_MEM8(0x0A51) +#define TCB1_EVCTRL _SFR_MEM8(0x0A54) +#define TCB1_INTCTRL _SFR_MEM8(0x0A55) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A56) +#define TCB1_STATUS _SFR_MEM8(0x0A57) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A58) +#define TCB1_TEMP _SFR_MEM8(0x0A59) +#define TCB1_CNT _SFR_MEM16(0x0A5A) +#define TCB1_CNTL _SFR_MEM8(0x0A5A) +#define TCB1_CNTH _SFR_MEM8(0x0A5B) +#define TCB1_CCMP _SFR_MEM16(0x0A5C) +#define TCB1_CCMPL _SFR_MEM8(0x0A5C) +#define TCB1_CCMPH _SFR_MEM8(0x0A5D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +/* USART_CMODE is already defined. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ +#define VREF_DAC1REFEN_bm 0x08 /* DAC1/AC1 reference enable bit mask. */ +#define VREF_DAC1REFEN_bp 3 /* DAC1/AC1 reference enable bit position. */ +#define VREF_ADC1REFEN_bm 0x10 /* ADC1 reference enable bit mask. */ +#define VREF_ADC1REFEN_bp 4 /* ADC1 reference enable bit position. */ +#define VREF_DAC2REFEN_bm 0x20 /* DAC2/AC2 reference enable bit mask. */ +#define VREF_DAC2REFEN_bp 5 /* DAC2/AC2 reference enable bit position. */ + +/* VREF.CTRLC bit masks and bit positions */ +#define VREF_DAC1REFSEL_gm 0x07 /* DAC1/AC1 reference select group mask. */ +#define VREF_DAC1REFSEL_gp 0 /* DAC1/AC1 reference select group position. */ +#define VREF_DAC1REFSEL0_bm (1<<0) /* DAC1/AC1 reference select bit 0 mask. */ +#define VREF_DAC1REFSEL0_bp 0 /* DAC1/AC1 reference select bit 0 position. */ +#define VREF_DAC1REFSEL1_bm (1<<1) /* DAC1/AC1 reference select bit 1 mask. */ +#define VREF_DAC1REFSEL1_bp 1 /* DAC1/AC1 reference select bit 1 position. */ +#define VREF_DAC1REFSEL2_bm (1<<2) /* DAC1/AC1 reference select bit 2 mask. */ +#define VREF_DAC1REFSEL2_bp 2 /* DAC1/AC1 reference select bit 2 position. */ +#define VREF_ADC1REFSEL_gm 0x70 /* ADC1 reference select group mask. */ +#define VREF_ADC1REFSEL_gp 4 /* ADC1 reference select group position. */ +#define VREF_ADC1REFSEL0_bm (1<<4) /* ADC1 reference select bit 0 mask. */ +#define VREF_ADC1REFSEL0_bp 4 /* ADC1 reference select bit 0 position. */ +#define VREF_ADC1REFSEL1_bm (1<<5) /* ADC1 reference select bit 1 mask. */ +#define VREF_ADC1REFSEL1_bp 5 /* ADC1 reference select bit 1 position. */ +#define VREF_ADC1REFSEL2_bm (1<<6) /* ADC1 reference select bit 2 mask. */ +#define VREF_ADC1REFSEL2_bp 6 /* ADC1 reference select bit 2 position. */ + +/* VREF.CTRLD bit masks and bit positions */ +#define VREF_DAC2REFSEL_gm 0x07 /* DAC2/AC2 reference select group mask. */ +#define VREF_DAC2REFSEL_gp 0 /* DAC2/AC2 reference select group position. */ +#define VREF_DAC2REFSEL0_bm (1<<0) /* DAC2/AC2 reference select bit 0 mask. */ +#define VREF_DAC2REFSEL0_bp 0 /* DAC2/AC2 reference select bit 0 position. */ +#define VREF_DAC2REFSEL1_bm (1<<1) /* DAC2/AC2 reference select bit 1 mask. */ +#define VREF_DAC2REFSEL1_bp 1 /* DAC2/AC2 reference select bit 1 position. */ +#define VREF_DAC2REFSEL2_bm (1<<2) /* DAC2/AC2 reference select bit 2 mask. */ +#define VREF_DAC2REFSEL2_bp 2 /* DAC2/AC2 reference select bit 2 position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 14 +#define TCB1_INT_vect _VECTOR(14) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 15 +#define TCD0_OVF_vect _VECTOR(15) /* */ +#define TCD0_TRIG_vect_num 16 +#define TCD0_TRIG_vect _VECTOR(16) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* AC1 interrupt vectors */ +#define AC1_AC_vect_num 18 +#define AC1_AC_vect _VECTOR(18) /* */ + +/* AC2 interrupt vectors */ +#define AC2_AC_vect_num 19 +#define AC2_AC_vect _VECTOR(19) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* ADC1 interrupt vectors */ +#define ADC1_RESRDY_vect_num 22 +#define ADC1_RESRDY_vect _VECTOR(22) /* */ +#define ADC1_WCOMP_vect_num 23 +#define ADC1_WCOMP_vect _VECTOR(23) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (49152) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (49152U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3800) +# define INTERNAL_SRAM_SIZE (2048) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3800U) +# define INTERNAL_SRAM_SIZE (2048U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x22 + + +#endif /* #ifdef _AVR_ATTINY1614_H_INCLUDED */ + diff --git a/software/tools/dfp/include/avr/iotn204.h b/software/tools/dfp/include/avr/iotn204.h new file mode 100644 index 0000000..73be05d --- /dev/null +++ b/software/tools/dfp/include/avr/iotn204.h @@ -0,0 +1,4658 @@ +/* + * Copyright (C) 2021, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. Publication is not required when + * this file is used in an embedded application. + * + * 3. Microchip's name may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn204.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY204_H_INCLUDED +#define _AVR_ATTINY204_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t reserved_2[7]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + +/* CCL.TRUTH0 bit masks and bit positions */ +#define CCL_TRUTH_gm 0xFF /* Truth Table group mask. */ +#define CCL_TRUTH_gp 0 /* Truth Table group position. */ +#define CCL_TRUTH0_bm (1<<0) /* Truth Table bit 0 mask. */ +#define CCL_TRUTH0_bp 0 /* Truth Table bit 0 position. */ +#define CCL_TRUTH1_bm (1<<1) /* Truth Table bit 1 mask. */ +#define CCL_TRUTH1_bp 1 /* Truth Table bit 1 position. */ +#define CCL_TRUTH2_bm (1<<2) /* Truth Table bit 2 mask. */ +#define CCL_TRUTH2_bp 2 /* Truth Table bit 2 position. */ +#define CCL_TRUTH3_bm (1<<3) /* Truth Table bit 3 mask. */ +#define CCL_TRUTH3_bp 3 /* Truth Table bit 3 position. */ +#define CCL_TRUTH4_bm (1<<4) /* Truth Table bit 4 mask. */ +#define CCL_TRUTH4_bp 4 /* Truth Table bit 4 position. */ +#define CCL_TRUTH5_bm (1<<5) /* Truth Table bit 5 mask. */ +#define CCL_TRUTH5_bp 5 /* Truth Table bit 5 position. */ +#define CCL_TRUTH6_bm (1<<6) /* Truth Table bit 6 mask. */ +#define CCL_TRUTH6_bp 6 /* Truth Table bit 6 position. */ +#define CCL_TRUTH7_bm (1<<7) /* Truth Table bit 7 mask. */ +#define CCL_TRUTH7_bp 7 /* Truth Table bit 7 position. */ + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + +/* CCL.TRUTH1 bit masks and bit positions */ +/* CCL_TRUTH is already defined. */ + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +/* USART_CMODE is already defined. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (34816) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (34816U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (64) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (64U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F80) +# define INTERNAL_SRAM_SIZE (128) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F80U) +# define INTERNAL_SRAM_SIZE (128U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (2048) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (2048U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (2048) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (2048U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x22 + + +#endif /* #ifdef _AVR_ATTINY204_H_INCLUDED */ + diff --git a/software/tools/dfp/include/avr/iotn214.h b/software/tools/dfp/include/avr/iotn214.h new file mode 100644 index 0000000..053f8dd --- /dev/null +++ b/software/tools/dfp/include/avr/iotn214.h @@ -0,0 +1,5296 @@ +/* + * Copyright (C) 2021, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. Publication is not required when + * this file is used in an embedded application. + * + * 3. Microchip's name may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn214.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY214_H_INCLUDED +#define _AVR_ATTINY214_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x0680) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x0680) +#define DAC0_DATA _SFR_MEM8(0x0681) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + +/* CCL.TRUTH0 bit masks and bit positions */ +#define CCL_TRUTH_gm 0xFF /* Truth Table group mask. */ +#define CCL_TRUTH_gp 0 /* Truth Table group position. */ +#define CCL_TRUTH0_bm (1<<0) /* Truth Table bit 0 mask. */ +#define CCL_TRUTH0_bp 0 /* Truth Table bit 0 position. */ +#define CCL_TRUTH1_bm (1<<1) /* Truth Table bit 1 mask. */ +#define CCL_TRUTH1_bp 1 /* Truth Table bit 1 position. */ +#define CCL_TRUTH2_bm (1<<2) /* Truth Table bit 2 mask. */ +#define CCL_TRUTH2_bp 2 /* Truth Table bit 2 position. */ +#define CCL_TRUTH3_bm (1<<3) /* Truth Table bit 3 mask. */ +#define CCL_TRUTH3_bp 3 /* Truth Table bit 3 position. */ +#define CCL_TRUTH4_bm (1<<4) /* Truth Table bit 4 mask. */ +#define CCL_TRUTH4_bp 4 /* Truth Table bit 4 position. */ +#define CCL_TRUTH5_bm (1<<5) /* Truth Table bit 5 mask. */ +#define CCL_TRUTH5_bp 5 /* Truth Table bit 5 position. */ +#define CCL_TRUTH6_bm (1<<6) /* Truth Table bit 6 mask. */ +#define CCL_TRUTH6_bp 6 /* Truth Table bit 6 position. */ +#define CCL_TRUTH7_bm (1<<7) /* Truth Table bit 7 mask. */ +#define CCL_TRUTH7_bp 7 /* Truth Table bit 7 position. */ + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + +/* CCL.TRUTH1 bit masks and bit positions */ +/* CCL_TRUTH is already defined. */ + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +/* USART_CMODE is already defined. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (34816) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (34816U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (64) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (64U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F80) +# define INTERNAL_SRAM_SIZE (128) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F80U) +# define INTERNAL_SRAM_SIZE (128U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (2048) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (2048U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (2048) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (2048U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x20 + + +#endif /* #ifdef _AVR_ATTINY214_H_INCLUDED */ + diff --git a/software/tools/dfp/include/avr/iotn404.h b/software/tools/dfp/include/avr/iotn404.h new file mode 100644 index 0000000..121d78c --- /dev/null +++ b/software/tools/dfp/include/avr/iotn404.h @@ -0,0 +1,4658 @@ +/* + * Copyright (C) 2021, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. Publication is not required when + * this file is used in an embedded application. + * + * 3. Microchip's name may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn404.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY404_H_INCLUDED +#define _AVR_ATTINY404_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t reserved_2[7]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + +/* CCL.TRUTH0 bit masks and bit positions */ +#define CCL_TRUTH_gm 0xFF /* Truth Table group mask. */ +#define CCL_TRUTH_gp 0 /* Truth Table group position. */ +#define CCL_TRUTH0_bm (1<<0) /* Truth Table bit 0 mask. */ +#define CCL_TRUTH0_bp 0 /* Truth Table bit 0 position. */ +#define CCL_TRUTH1_bm (1<<1) /* Truth Table bit 1 mask. */ +#define CCL_TRUTH1_bp 1 /* Truth Table bit 1 position. */ +#define CCL_TRUTH2_bm (1<<2) /* Truth Table bit 2 mask. */ +#define CCL_TRUTH2_bp 2 /* Truth Table bit 2 position. */ +#define CCL_TRUTH3_bm (1<<3) /* Truth Table bit 3 mask. */ +#define CCL_TRUTH3_bp 3 /* Truth Table bit 3 position. */ +#define CCL_TRUTH4_bm (1<<4) /* Truth Table bit 4 mask. */ +#define CCL_TRUTH4_bp 4 /* Truth Table bit 4 position. */ +#define CCL_TRUTH5_bm (1<<5) /* Truth Table bit 5 mask. */ +#define CCL_TRUTH5_bp 5 /* Truth Table bit 5 position. */ +#define CCL_TRUTH6_bm (1<<6) /* Truth Table bit 6 mask. */ +#define CCL_TRUTH6_bp 6 /* Truth Table bit 6 position. */ +#define CCL_TRUTH7_bm (1<<7) /* Truth Table bit 7 mask. */ +#define CCL_TRUTH7_bp 7 /* Truth Table bit 7 position. */ + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + +/* CCL.TRUTH1 bit masks and bit positions */ +/* CCL_TRUTH is already defined. */ + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +/* USART_CMODE is already defined. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (36864) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (36864U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F00) +# define INTERNAL_SRAM_SIZE (256) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F00U) +# define INTERNAL_SRAM_SIZE (256U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (4096) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (4096U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (4096) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (4096U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x26 + + +#endif /* #ifdef _AVR_ATTINY404_H_INCLUDED */ + diff --git a/software/tools/dfp/include/avr/iotn414.h b/software/tools/dfp/include/avr/iotn414.h new file mode 100644 index 0000000..f54a3a0 --- /dev/null +++ b/software/tools/dfp/include/avr/iotn414.h @@ -0,0 +1,5296 @@ +/* + * Copyright (C) 2021, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. Publication is not required when + * this file is used in an embedded application. + * + * 3. Microchip's name may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn414.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY414_H_INCLUDED +#define _AVR_ATTINY414_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x0680) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x0680) +#define DAC0_DATA _SFR_MEM8(0x0681) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + +/* CCL.TRUTH0 bit masks and bit positions */ +#define CCL_TRUTH_gm 0xFF /* Truth Table group mask. */ +#define CCL_TRUTH_gp 0 /* Truth Table group position. */ +#define CCL_TRUTH0_bm (1<<0) /* Truth Table bit 0 mask. */ +#define CCL_TRUTH0_bp 0 /* Truth Table bit 0 position. */ +#define CCL_TRUTH1_bm (1<<1) /* Truth Table bit 1 mask. */ +#define CCL_TRUTH1_bp 1 /* Truth Table bit 1 position. */ +#define CCL_TRUTH2_bm (1<<2) /* Truth Table bit 2 mask. */ +#define CCL_TRUTH2_bp 2 /* Truth Table bit 2 position. */ +#define CCL_TRUTH3_bm (1<<3) /* Truth Table bit 3 mask. */ +#define CCL_TRUTH3_bp 3 /* Truth Table bit 3 position. */ +#define CCL_TRUTH4_bm (1<<4) /* Truth Table bit 4 mask. */ +#define CCL_TRUTH4_bp 4 /* Truth Table bit 4 position. */ +#define CCL_TRUTH5_bm (1<<5) /* Truth Table bit 5 mask. */ +#define CCL_TRUTH5_bp 5 /* Truth Table bit 5 position. */ +#define CCL_TRUTH6_bm (1<<6) /* Truth Table bit 6 mask. */ +#define CCL_TRUTH6_bp 6 /* Truth Table bit 6 position. */ +#define CCL_TRUTH7_bm (1<<7) /* Truth Table bit 7 mask. */ +#define CCL_TRUTH7_bp 7 /* Truth Table bit 7 position. */ + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + +/* CCL.TRUTH1 bit masks and bit positions */ +/* CCL_TRUTH is already defined. */ + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +/* USART_CMODE is already defined. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (36864) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (36864U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F00) +# define INTERNAL_SRAM_SIZE (256) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F00U) +# define INTERNAL_SRAM_SIZE (256U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (4096) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (4096U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (4096) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (4096U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x22 + + +#endif /* #ifdef _AVR_ATTINY414_H_INCLUDED */ + diff --git a/software/tools/dfp/include/avr/iotn804.h b/software/tools/dfp/include/avr/iotn804.h new file mode 100644 index 0000000..e831c47 --- /dev/null +++ b/software/tools/dfp/include/avr/iotn804.h @@ -0,0 +1,4667 @@ +/* + * Copyright (C) 2021, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. Publication is not required when + * this file is used in an embedded application. + * + * 3. Microchip's name may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn804.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY804_H_INCLUDED +#define _AVR_ATTINY804_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t reserved_2[7]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[2]; +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + +/* CCL.TRUTH0 bit masks and bit positions */ +#define CCL_TRUTH_gm 0xFF /* Truth Table group mask. */ +#define CCL_TRUTH_gp 0 /* Truth Table group position. */ +#define CCL_TRUTH0_bm (1<<0) /* Truth Table bit 0 mask. */ +#define CCL_TRUTH0_bp 0 /* Truth Table bit 0 position. */ +#define CCL_TRUTH1_bm (1<<1) /* Truth Table bit 1 mask. */ +#define CCL_TRUTH1_bp 1 /* Truth Table bit 1 position. */ +#define CCL_TRUTH2_bm (1<<2) /* Truth Table bit 2 mask. */ +#define CCL_TRUTH2_bp 2 /* Truth Table bit 2 position. */ +#define CCL_TRUTH3_bm (1<<3) /* Truth Table bit 3 mask. */ +#define CCL_TRUTH3_bp 3 /* Truth Table bit 3 position. */ +#define CCL_TRUTH4_bm (1<<4) /* Truth Table bit 4 mask. */ +#define CCL_TRUTH4_bp 4 /* Truth Table bit 4 position. */ +#define CCL_TRUTH5_bm (1<<5) /* Truth Table bit 5 mask. */ +#define CCL_TRUTH5_bp 5 /* Truth Table bit 5 position. */ +#define CCL_TRUTH6_bm (1<<6) /* Truth Table bit 6 mask. */ +#define CCL_TRUTH6_bp 6 /* Truth Table bit 6 position. */ +#define CCL_TRUTH7_bm (1<<7) /* Truth Table bit 7 mask. */ +#define CCL_TRUTH7_bp 7 /* Truth Table bit 7 position. */ + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + +/* CCL.TRUTH1 bit masks and bit positions */ +/* CCL_TRUTH is already defined. */ + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +/* USART_CMODE is already defined. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (40960) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (40960U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3E00) +# define INTERNAL_SRAM_SIZE (512) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3E00U) +# define INTERNAL_SRAM_SIZE (512U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (8192) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (8192U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (8192) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (8192U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x25 + + +#endif /* #ifdef _AVR_ATTINY804_H_INCLUDED */ + diff --git a/software/tools/dfp/include/avr/iotn814.h b/software/tools/dfp/include/avr/iotn814.h new file mode 100644 index 0000000..163287b --- /dev/null +++ b/software/tools/dfp/include/avr/iotn814.h @@ -0,0 +1,5278 @@ +/* + * Copyright (C) 2021, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. Publication is not required when + * this file is used in an embedded application. + * + * 3. Microchip's name may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn814.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY814_H_INCLUDED +#define _AVR_ATTINY814_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.1 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.9 V */ + BOD_LVL_BODLEVEL4_gc = (0x04<<0), /* 3.3 V */ + BOD_LVL_BODLEVEL5_gc = (0x05<<0), /* 3.7 V */ + BOD_LVL_BODLEVEL6_gc = (0x06<<0), /* 4.0 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x0680) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x0680) +#define DAC0_DATA _SFR_MEM8(0x0681) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_bm 0x08 /* Positive Input MUX Selection bit mask. */ +#define AC_MUXPOS_bp 3 /* Positive Input MUX Selection bit position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +/* USART_CMODE is already defined. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (40960) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (40960U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3E00) +# define INTERNAL_SRAM_SIZE (512) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3E00U) +# define INTERNAL_SRAM_SIZE (512U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (8192) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (8192U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (8192) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (8192U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x22 + + +#endif /* #ifdef _AVR_ATTINY814_H_INCLUDED */ + diff --git a/software/tools/dfp/include/component-version.h b/software/tools/dfp/include/component-version.h new file mode 100644 index 0000000..f87123d --- /dev/null +++ b/software/tools/dfp/include/component-version.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2021 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 2 +#define COMPONENT_VERSION_MINOR 7 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 20007 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 128 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "2.7" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2021-07-13 10:42:36" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/software/tools/dfp/readme.txt b/software/tools/dfp/readme.txt new file mode 100644 index 0000000..cb4fc98 --- /dev/null +++ b/software/tools/dfp/readme.txt @@ -0,0 +1,17 @@ +Description: Atmel ATtiny Series Device Support (1.10.348) + +Source: http://packs.download.atmel.com/ + +Copyright (c) 2020 Microchip Technology Inc. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the Licence at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/software/tools/pymcuprog/libs/appdirs.py b/software/tools/pymcuprog/libs/appdirs.py new file mode 100644 index 0000000..2acd1de --- /dev/null +++ b/software/tools/pymcuprog/libs/appdirs.py @@ -0,0 +1,608 @@ +#!/usr/bin/env python +# -*- coding: utf-8 -*- +# Copyright (c) 2005-2010 ActiveState Software Inc. +# Copyright (c) 2013 Eddy Petrișor + +"""Utilities for determining application-specific dirs. + +See for details and usage. +""" +# Dev Notes: +# - MSDN on where to store app data files: +# http://support.microsoft.com/default.aspx?scid=kb;en-us;310294#XSLTH3194121123120121120120 +# - Mac OS X: http://developer.apple.com/documentation/MacOSX/Conceptual/BPFileSystem/index.html +# - XDG spec for Un*x: http://standards.freedesktop.org/basedir-spec/basedir-spec-latest.html + +__version__ = "1.4.4" +__version_info__ = tuple(int(segment) for segment in __version__.split(".")) + + +import sys +import os + +PY3 = sys.version_info[0] == 3 + +if PY3: + unicode = str + +if sys.platform.startswith('java'): + import platform + os_name = platform.java_ver()[3][0] + if os_name.startswith('Windows'): # "Windows XP", "Windows 7", etc. + system = 'win32' + elif os_name.startswith('Mac'): # "Mac OS X", etc. + system = 'darwin' + else: # "Linux", "SunOS", "FreeBSD", etc. + # Setting this to "linux2" is not ideal, but only Windows or Mac + # are actually checked for and the rest of the module expects + # *sys.platform* style strings. + system = 'linux2' +else: + system = sys.platform + + + +def user_data_dir(appname=None, appauthor=None, version=None, roaming=False): + r"""Return full path to the user-specific data dir for this application. + + "appname" is the name of application. + If None, just the system directory is returned. + "appauthor" (only used on Windows) is the name of the + appauthor or distributing body for this application. Typically + it is the owning company name. This falls back to appname. You may + pass False to disable it. + "version" is an optional version path element to append to the + path. You might want to use this if you want multiple versions + of your app to be able to run independently. If used, this + would typically be ".". + Only applied when appname is present. + "roaming" (boolean, default False) can be set True to use the Windows + roaming appdata directory. That means that for users on a Windows + network setup for roaming profiles, this user data will be + sync'd on login. See + + for a discussion of issues. + + Typical user data directories are: + Mac OS X: ~/Library/Application Support/ + Unix: ~/.local/share/ # or in $XDG_DATA_HOME, if defined + Win XP (not roaming): C:\Documents and Settings\\Application Data\\ + Win XP (roaming): C:\Documents and Settings\\Local Settings\Application Data\\ + Win 7 (not roaming): C:\Users\\AppData\Local\\ + Win 7 (roaming): C:\Users\\AppData\Roaming\\ + + For Unix, we follow the XDG spec and support $XDG_DATA_HOME. + That means, by default "~/.local/share/". + """ + if system == "win32": + if appauthor is None: + appauthor = appname + const = roaming and "CSIDL_APPDATA" or "CSIDL_LOCAL_APPDATA" + path = os.path.normpath(_get_win_folder(const)) + if appname: + if appauthor is not False: + path = os.path.join(path, appauthor, appname) + else: + path = os.path.join(path, appname) + elif system == 'darwin': + path = os.path.expanduser('~/Library/Application Support/') + if appname: + path = os.path.join(path, appname) + else: + path = os.getenv('XDG_DATA_HOME', os.path.expanduser("~/.local/share")) + if appname: + path = os.path.join(path, appname) + if appname and version: + path = os.path.join(path, version) + return path + + +def site_data_dir(appname=None, appauthor=None, version=None, multipath=False): + r"""Return full path to the user-shared data dir for this application. + + "appname" is the name of application. + If None, just the system directory is returned. + "appauthor" (only used on Windows) is the name of the + appauthor or distributing body for this application. Typically + it is the owning company name. This falls back to appname. You may + pass False to disable it. + "version" is an optional version path element to append to the + path. You might want to use this if you want multiple versions + of your app to be able to run independently. If used, this + would typically be ".". + Only applied when appname is present. + "multipath" is an optional parameter only applicable to *nix + which indicates that the entire list of data dirs should be + returned. By default, the first item from XDG_DATA_DIRS is + returned, or '/usr/local/share/', + if XDG_DATA_DIRS is not set + + Typical site data directories are: + Mac OS X: /Library/Application Support/ + Unix: /usr/local/share/ or /usr/share/ + Win XP: C:\Documents and Settings\All Users\Application Data\\ + Vista: (Fail! "C:\ProgramData" is a hidden *system* directory on Vista.) + Win 7: C:\ProgramData\\ # Hidden, but writeable on Win 7. + + For Unix, this is using the $XDG_DATA_DIRS[0] default. + + WARNING: Do not use this on Windows. See the Vista-Fail note above for why. + """ + if system == "win32": + if appauthor is None: + appauthor = appname + path = os.path.normpath(_get_win_folder("CSIDL_COMMON_APPDATA")) + if appname: + if appauthor is not False: + path = os.path.join(path, appauthor, appname) + else: + path = os.path.join(path, appname) + elif system == 'darwin': + path = os.path.expanduser('/Library/Application Support') + if appname: + path = os.path.join(path, appname) + else: + # XDG default for $XDG_DATA_DIRS + # only first, if multipath is False + path = os.getenv('XDG_DATA_DIRS', + os.pathsep.join(['/usr/local/share', '/usr/share'])) + pathlist = [os.path.expanduser(x.rstrip(os.sep)) for x in path.split(os.pathsep)] + if appname: + if version: + appname = os.path.join(appname, version) + pathlist = [os.sep.join([x, appname]) for x in pathlist] + + if multipath: + path = os.pathsep.join(pathlist) + else: + path = pathlist[0] + return path + + if appname and version: + path = os.path.join(path, version) + return path + + +def user_config_dir(appname=None, appauthor=None, version=None, roaming=False): + r"""Return full path to the user-specific config dir for this application. + + "appname" is the name of application. + If None, just the system directory is returned. + "appauthor" (only used on Windows) is the name of the + appauthor or distributing body for this application. Typically + it is the owning company name. This falls back to appname. You may + pass False to disable it. + "version" is an optional version path element to append to the + path. You might want to use this if you want multiple versions + of your app to be able to run independently. If used, this + would typically be ".". + Only applied when appname is present. + "roaming" (boolean, default False) can be set True to use the Windows + roaming appdata directory. That means that for users on a Windows + network setup for roaming profiles, this user data will be + sync'd on login. See + + for a discussion of issues. + + Typical user config directories are: + Mac OS X: same as user_data_dir + Unix: ~/.config/ # or in $XDG_CONFIG_HOME, if defined + Win *: same as user_data_dir + + For Unix, we follow the XDG spec and support $XDG_CONFIG_HOME. + That means, by default "~/.config/". + """ + if system in ["win32", "darwin"]: + path = user_data_dir(appname, appauthor, None, roaming) + else: + path = os.getenv('XDG_CONFIG_HOME', os.path.expanduser("~/.config")) + if appname: + path = os.path.join(path, appname) + if appname and version: + path = os.path.join(path, version) + return path + + +def site_config_dir(appname=None, appauthor=None, version=None, multipath=False): + r"""Return full path to the user-shared data dir for this application. + + "appname" is the name of application. + If None, just the system directory is returned. + "appauthor" (only used on Windows) is the name of the + appauthor or distributing body for this application. Typically + it is the owning company name. This falls back to appname. You may + pass False to disable it. + "version" is an optional version path element to append to the + path. You might want to use this if you want multiple versions + of your app to be able to run independently. If used, this + would typically be ".". + Only applied when appname is present. + "multipath" is an optional parameter only applicable to *nix + which indicates that the entire list of config dirs should be + returned. By default, the first item from XDG_CONFIG_DIRS is + returned, or '/etc/xdg/', if XDG_CONFIG_DIRS is not set + + Typical site config directories are: + Mac OS X: same as site_data_dir + Unix: /etc/xdg/ or $XDG_CONFIG_DIRS[i]/ for each value in + $XDG_CONFIG_DIRS + Win *: same as site_data_dir + Vista: (Fail! "C:\ProgramData" is a hidden *system* directory on Vista.) + + For Unix, this is using the $XDG_CONFIG_DIRS[0] default, if multipath=False + + WARNING: Do not use this on Windows. See the Vista-Fail note above for why. + """ + if system in ["win32", "darwin"]: + path = site_data_dir(appname, appauthor) + if appname and version: + path = os.path.join(path, version) + else: + # XDG default for $XDG_CONFIG_DIRS + # only first, if multipath is False + path = os.getenv('XDG_CONFIG_DIRS', '/etc/xdg') + pathlist = [os.path.expanduser(x.rstrip(os.sep)) for x in path.split(os.pathsep)] + if appname: + if version: + appname = os.path.join(appname, version) + pathlist = [os.sep.join([x, appname]) for x in pathlist] + + if multipath: + path = os.pathsep.join(pathlist) + else: + path = pathlist[0] + return path + + +def user_cache_dir(appname=None, appauthor=None, version=None, opinion=True): + r"""Return full path to the user-specific cache dir for this application. + + "appname" is the name of application. + If None, just the system directory is returned. + "appauthor" (only used on Windows) is the name of the + appauthor or distributing body for this application. Typically + it is the owning company name. This falls back to appname. You may + pass False to disable it. + "version" is an optional version path element to append to the + path. You might want to use this if you want multiple versions + of your app to be able to run independently. If used, this + would typically be ".". + Only applied when appname is present. + "opinion" (boolean) can be False to disable the appending of + "Cache" to the base app data dir for Windows. See + discussion below. + + Typical user cache directories are: + Mac OS X: ~/Library/Caches/ + Unix: ~/.cache/ (XDG default) + Win XP: C:\Documents and Settings\\Local Settings\Application Data\\\Cache + Vista: C:\Users\\AppData\Local\\\Cache + + On Windows the only suggestion in the MSDN docs is that local settings go in + the `CSIDL_LOCAL_APPDATA` directory. This is identical to the non-roaming + app data dir (the default returned by `user_data_dir` above). Apps typically + put cache data somewhere *under* the given dir here. Some examples: + ...\Mozilla\Firefox\Profiles\\Cache + ...\Acme\SuperApp\Cache\1.0 + OPINION: This function appends "Cache" to the `CSIDL_LOCAL_APPDATA` value. + This can be disabled with the `opinion=False` option. + """ + if system == "win32": + if appauthor is None: + appauthor = appname + path = os.path.normpath(_get_win_folder("CSIDL_LOCAL_APPDATA")) + if appname: + if appauthor is not False: + path = os.path.join(path, appauthor, appname) + else: + path = os.path.join(path, appname) + if opinion: + path = os.path.join(path, "Cache") + elif system == 'darwin': + path = os.path.expanduser('~/Library/Caches') + if appname: + path = os.path.join(path, appname) + else: + path = os.getenv('XDG_CACHE_HOME', os.path.expanduser('~/.cache')) + if appname: + path = os.path.join(path, appname) + if appname and version: + path = os.path.join(path, version) + return path + + +def user_state_dir(appname=None, appauthor=None, version=None, roaming=False): + r"""Return full path to the user-specific state dir for this application. + + "appname" is the name of application. + If None, just the system directory is returned. + "appauthor" (only used on Windows) is the name of the + appauthor or distributing body for this application. Typically + it is the owning company name. This falls back to appname. You may + pass False to disable it. + "version" is an optional version path element to append to the + path. You might want to use this if you want multiple versions + of your app to be able to run independently. If used, this + would typically be ".". + Only applied when appname is present. + "roaming" (boolean, default False) can be set True to use the Windows + roaming appdata directory. That means that for users on a Windows + network setup for roaming profiles, this user data will be + sync'd on login. See + + for a discussion of issues. + + Typical user state directories are: + Mac OS X: same as user_data_dir + Unix: ~/.local/state/ # or in $XDG_STATE_HOME, if defined + Win *: same as user_data_dir + + For Unix, we follow this Debian proposal + to extend the XDG spec and support $XDG_STATE_HOME. + + That means, by default "~/.local/state/". + """ + if system in ["win32", "darwin"]: + path = user_data_dir(appname, appauthor, None, roaming) + else: + path = os.getenv('XDG_STATE_HOME', os.path.expanduser("~/.local/state")) + if appname: + path = os.path.join(path, appname) + if appname and version: + path = os.path.join(path, version) + return path + + +def user_log_dir(appname=None, appauthor=None, version=None, opinion=True): + r"""Return full path to the user-specific log dir for this application. + + "appname" is the name of application. + If None, just the system directory is returned. + "appauthor" (only used on Windows) is the name of the + appauthor or distributing body for this application. Typically + it is the owning company name. This falls back to appname. You may + pass False to disable it. + "version" is an optional version path element to append to the + path. You might want to use this if you want multiple versions + of your app to be able to run independently. If used, this + would typically be ".". + Only applied when appname is present. + "opinion" (boolean) can be False to disable the appending of + "Logs" to the base app data dir for Windows, and "log" to the + base cache dir for Unix. See discussion below. + + Typical user log directories are: + Mac OS X: ~/Library/Logs/ + Unix: ~/.cache//log # or under $XDG_CACHE_HOME if defined + Win XP: C:\Documents and Settings\\Local Settings\Application Data\\\Logs + Vista: C:\Users\\AppData\Local\\\Logs + + On Windows the only suggestion in the MSDN docs is that local settings + go in the `CSIDL_LOCAL_APPDATA` directory. (Note: I'm interested in + examples of what some windows apps use for a logs dir.) + + OPINION: This function appends "Logs" to the `CSIDL_LOCAL_APPDATA` + value for Windows and appends "log" to the user cache dir for Unix. + This can be disabled with the `opinion=False` option. + """ + if system == "darwin": + path = os.path.join( + os.path.expanduser('~/Library/Logs'), + appname) + elif system == "win32": + path = user_data_dir(appname, appauthor, version) + version = False + if opinion: + path = os.path.join(path, "Logs") + else: + path = user_cache_dir(appname, appauthor, version) + version = False + if opinion: + path = os.path.join(path, "log") + if appname and version: + path = os.path.join(path, version) + return path + + +class AppDirs(object): + """Convenience wrapper for getting application dirs.""" + def __init__(self, appname=None, appauthor=None, version=None, + roaming=False, multipath=False): + self.appname = appname + self.appauthor = appauthor + self.version = version + self.roaming = roaming + self.multipath = multipath + + @property + def user_data_dir(self): + return user_data_dir(self.appname, self.appauthor, + version=self.version, roaming=self.roaming) + + @property + def site_data_dir(self): + return site_data_dir(self.appname, self.appauthor, + version=self.version, multipath=self.multipath) + + @property + def user_config_dir(self): + return user_config_dir(self.appname, self.appauthor, + version=self.version, roaming=self.roaming) + + @property + def site_config_dir(self): + return site_config_dir(self.appname, self.appauthor, + version=self.version, multipath=self.multipath) + + @property + def user_cache_dir(self): + return user_cache_dir(self.appname, self.appauthor, + version=self.version) + + @property + def user_state_dir(self): + return user_state_dir(self.appname, self.appauthor, + version=self.version) + + @property + def user_log_dir(self): + return user_log_dir(self.appname, self.appauthor, + version=self.version) + + +#---- internal support stuff + +def _get_win_folder_from_registry(csidl_name): + """This is a fallback technique at best. I'm not sure if using the + registry for this guarantees us the correct answer for all CSIDL_* + names. + """ + if PY3: + import winreg as _winreg + else: + import _winreg + + shell_folder_name = { + "CSIDL_APPDATA": "AppData", + "CSIDL_COMMON_APPDATA": "Common AppData", + "CSIDL_LOCAL_APPDATA": "Local AppData", + }[csidl_name] + + key = _winreg.OpenKey( + _winreg.HKEY_CURRENT_USER, + r"Software\Microsoft\Windows\CurrentVersion\Explorer\Shell Folders" + ) + dir, type = _winreg.QueryValueEx(key, shell_folder_name) + return dir + + +def _get_win_folder_with_pywin32(csidl_name): + from win32com.shell import shellcon, shell + dir = shell.SHGetFolderPath(0, getattr(shellcon, csidl_name), 0, 0) + # Try to make this a unicode path because SHGetFolderPath does + # not return unicode strings when there is unicode data in the + # path. + try: + dir = unicode(dir) + + # Downgrade to short path name if have highbit chars. See + # . + has_high_char = False + for c in dir: + if ord(c) > 255: + has_high_char = True + break + if has_high_char: + try: + import win32api + dir = win32api.GetShortPathName(dir) + except ImportError: + pass + except UnicodeError: + pass + return dir + + +def _get_win_folder_with_ctypes(csidl_name): + import ctypes + + csidl_const = { + "CSIDL_APPDATA": 26, + "CSIDL_COMMON_APPDATA": 35, + "CSIDL_LOCAL_APPDATA": 28, + }[csidl_name] + + buf = ctypes.create_unicode_buffer(1024) + ctypes.windll.shell32.SHGetFolderPathW(None, csidl_const, None, 0, buf) + + # Downgrade to short path name if have highbit chars. See + # . + has_high_char = False + for c in buf: + if ord(c) > 255: + has_high_char = True + break + if has_high_char: + buf2 = ctypes.create_unicode_buffer(1024) + if ctypes.windll.kernel32.GetShortPathNameW(buf.value, buf2, 1024): + buf = buf2 + + return buf.value + +def _get_win_folder_with_jna(csidl_name): + import array + from com.sun import jna + from com.sun.jna.platform import win32 + + buf_size = win32.WinDef.MAX_PATH * 2 + buf = array.zeros('c', buf_size) + shell = win32.Shell32.INSTANCE + shell.SHGetFolderPath(None, getattr(win32.ShlObj, csidl_name), None, win32.ShlObj.SHGFP_TYPE_CURRENT, buf) + dir = jna.Native.toString(buf.tostring()).rstrip("\0") + + # Downgrade to short path name if have highbit chars. See + # . + has_high_char = False + for c in dir: + if ord(c) > 255: + has_high_char = True + break + if has_high_char: + buf = array.zeros('c', buf_size) + kernel = win32.Kernel32.INSTANCE + if kernel.GetShortPathName(dir, buf, buf_size): + dir = jna.Native.toString(buf.tostring()).rstrip("\0") + + return dir + +if system == "win32": + try: + import win32com.shell + _get_win_folder = _get_win_folder_with_pywin32 + except ImportError: + try: + from ctypes import windll + _get_win_folder = _get_win_folder_with_ctypes + except ImportError: + try: + import com.sun.jna + _get_win_folder = _get_win_folder_with_jna + except ImportError: + _get_win_folder = _get_win_folder_from_registry + + +#---- self test code + +if __name__ == "__main__": + appname = "MyApp" + appauthor = "MyCompany" + + props = ("user_data_dir", + "user_config_dir", + "user_cache_dir", + "user_state_dir", + "user_log_dir", + "site_data_dir", + "site_config_dir") + + print("-- app dirs %s --" % __version__) + + print("-- app dirs (with optional 'version')") + dirs = AppDirs(appname, appauthor, version="1.0") + for prop in props: + print("%s: %s" % (prop, getattr(dirs, prop))) + + print("\n-- app dirs (without optional 'version')") + dirs = AppDirs(appname, appauthor) + for prop in props: + print("%s: %s" % (prop, getattr(dirs, prop))) + + print("\n-- app dirs (without optional 'appauthor')") + dirs = AppDirs(appname) + for prop in props: + print("%s: %s" % (prop, getattr(dirs, prop))) + + print("\n-- app dirs (with disabled 'appauthor')") + dirs = AppDirs(appname, appauthor=False) + for prop in props: + print("%s: %s" % (prop, getattr(dirs, prop))) diff --git a/software/tools/pymcuprog/libs/intelhex/__init__.py b/software/tools/pymcuprog/libs/intelhex/__init__.py new file mode 100644 index 0000000..c6423a6 --- /dev/null +++ b/software/tools/pymcuprog/libs/intelhex/__init__.py @@ -0,0 +1,1372 @@ +# Copyright (c) 2005-2018, Alexander Belchenko +# All rights reserved. +# +# Redistribution and use in source and binary forms, +# with or without modification, are permitted provided +# that the following conditions are met: +# +# * Redistributions of source code must retain +# the above copyright notice, this list of conditions +# and the following disclaimer. +# * Redistributions in binary form must reproduce +# the above copyright notice, this list of conditions +# and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# * Neither the name of the author nor the names +# of its contributors may be used to endorse +# or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +# BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +# AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +'''Intel HEX format manipulation library.''' + +__docformat__ = "javadoc" + +from array import array +from binascii import hexlify, unhexlify +from bisect import bisect_right +import os +import sys + +from intelhex.compat import ( + IntTypes, + StrType, + StringIO, + array_tobytes, + asbytes, + asstr, + dict_items_g, + dict_keys, + dict_keys_g, + range_g, + range_l, + ) + +from intelhex.getsizeof import total_size + + +class _DeprecatedParam(object): + pass + +_DEPRECATED = _DeprecatedParam() + + +class IntelHex(object): + ''' Intel HEX file reader. ''' + + def __init__(self, source=None): + ''' Constructor. If source specified, object will be initialized + with the contents of source. Otherwise the object will be empty. + + @param source source for initialization + (file name of HEX file, file object, addr dict or + other IntelHex object) + ''' + # public members + self.padding = 0x0FF + # Start Address + self.start_addr = None + + # private members + self._buf = {} + self._offset = 0 + + if source is not None: + if isinstance(source, StrType) or getattr(source, "read", None): + # load hex file + self.loadhex(source) + elif isinstance(source, dict): + self.fromdict(source) + elif isinstance(source, IntelHex): + self.padding = source.padding + if source.start_addr: + self.start_addr = source.start_addr.copy() + self._buf = source._buf.copy() + else: + raise ValueError("source: bad initializer type") + + def _decode_record(self, s, line=0): + '''Decode one record of HEX file. + + @param s line with HEX record. + @param line line number (for error messages). + + @raise EndOfFile if EOF record encountered. + ''' + s = s.rstrip('\r\n') + if not s: + return # empty line + + if s[0] == ':': + try: + bin = array('B', unhexlify(asbytes(s[1:]))) + except (TypeError, ValueError): + # this might be raised by unhexlify when odd hexascii digits + raise HexRecordError(line=line) + length = len(bin) + if length < 5: + raise HexRecordError(line=line) + else: + raise HexRecordError(line=line) + + record_length = bin[0] + if length != (5 + record_length): + raise RecordLengthError(line=line) + + addr = bin[1]*256 + bin[2] + + record_type = bin[3] + if not (0 <= record_type <= 5): + raise RecordTypeError(line=line) + + crc = sum(bin) + crc &= 0x0FF + if crc != 0: + raise RecordChecksumError(line=line) + + if record_type == 0: + # data record + addr += self._offset + for i in range_g(4, 4+record_length): + if not self._buf.get(addr, None) is None: + raise AddressOverlapError(address=addr, line=line) + self._buf[addr] = bin[i] + addr += 1 # FIXME: addr should be wrapped + # BUT after 02 record (at 64K boundary) + # and after 04 record (at 4G boundary) + + elif record_type == 1: + # end of file record + if record_length != 0: + raise EOFRecordError(line=line) + raise _EndOfFile + + elif record_type == 2: + # Extended 8086 Segment Record + if record_length != 2 or addr != 0: + raise ExtendedSegmentAddressRecordError(line=line) + self._offset = (bin[4]*256 + bin[5]) * 16 + + elif record_type == 4: + # Extended Linear Address Record + if record_length != 2 or addr != 0: + raise ExtendedLinearAddressRecordError(line=line) + self._offset = (bin[4]*256 + bin[5]) * 65536 + + elif record_type == 3: + # Start Segment Address Record + if record_length != 4 or addr != 0: + raise StartSegmentAddressRecordError(line=line) + if self.start_addr: + raise DuplicateStartAddressRecordError(line=line) + self.start_addr = {'CS': bin[4]*256 + bin[5], + 'IP': bin[6]*256 + bin[7], + } + + elif record_type == 5: + # Start Linear Address Record + if record_length != 4 or addr != 0: + raise StartLinearAddressRecordError(line=line) + if self.start_addr: + raise DuplicateStartAddressRecordError(line=line) + self.start_addr = {'EIP': (bin[4]*16777216 + + bin[5]*65536 + + bin[6]*256 + + bin[7]), + } + + def loadhex(self, fobj): + """Load hex file into internal buffer. This is not necessary + if object was initialized with source set. This will overwrite + addresses if object was already initialized. + + @param fobj file name or file-like object + """ + if getattr(fobj, "read", None) is None: + fobj = open(fobj, "r") + fclose = fobj.close + else: + fclose = None + + self._offset = 0 + line = 0 + + try: + decode = self._decode_record + try: + for s in fobj: + line += 1 + decode(s, line) + except _EndOfFile: + pass + finally: + if fclose: + fclose() + + def loadbin(self, fobj, offset=0): + """Load bin file into internal buffer. Not needed if source set in + constructor. This will overwrite addresses without warning + if object was already initialized. + + @param fobj file name or file-like object + @param offset starting address offset + """ + fread = getattr(fobj, "read", None) + if fread is None: + f = open(fobj, "rb") + fread = f.read + fclose = f.close + else: + fclose = None + + try: + self.frombytes(array('B', asbytes(fread())), offset=offset) + finally: + if fclose: + fclose() + + def loadfile(self, fobj, format): + """Load data file into internal buffer. Preferred wrapper over + loadbin or loadhex. + + @param fobj file name or file-like object + @param format file format ("hex" or "bin") + """ + if format == "hex": + self.loadhex(fobj) + elif format == "bin": + self.loadbin(fobj) + else: + raise ValueError('format should be either "hex" or "bin";' + ' got %r instead' % format) + + # alias (to be consistent with method tofile) + fromfile = loadfile + + def fromdict(self, dikt): + """Load data from dictionary. Dictionary should contain int keys + representing addresses. Values should be the data to be stored in + those addresses in unsigned char form (i.e. not strings). + The dictionary may contain the key, ``start_addr`` + to indicate the starting address of the data as described in README. + + The contents of the dict will be merged with this object and will + overwrite any conflicts. This function is not necessary if the + object was initialized with source specified. + """ + s = dikt.copy() + start_addr = s.get('start_addr') + if start_addr is not None: + del s['start_addr'] + for k in dict_keys_g(s): + if type(k) not in IntTypes or k < 0: + raise ValueError('Source dictionary should have only int keys') + self._buf.update(s) + if start_addr is not None: + self.start_addr = start_addr + + def frombytes(self, bytes, offset=0): + """Load data from array or list of bytes. + Similar to loadbin() method but works directly with iterable bytes. + """ + for b in bytes: + self._buf[offset] = b + offset += 1 + + def _get_start_end(self, start=None, end=None, size=None): + """Return default values for start and end if they are None. + If this IntelHex object is empty then it's error to + invoke this method with both start and end as None. + """ + if (start,end) == (None,None) and self._buf == {}: + raise EmptyIntelHexError + if size is not None: + if None not in (start, end): + raise ValueError("tobinarray: you can't use start,end and size" + " arguments in the same time") + if (start, end) == (None, None): + start = self.minaddr() + if start is not None: + end = start + size - 1 + else: + start = end - size + 1 + if start < 0: + raise ValueError("tobinarray: invalid size (%d) " + "for given end address (%d)" % (size,end)) + else: + if start is None: + start = self.minaddr() + if end is None: + end = self.maxaddr() + if start > end: + start, end = end, start + return start, end + + def tobinarray(self, start=None, end=None, pad=_DEPRECATED, size=None): + ''' Convert this object to binary form as array. If start and end + unspecified, they will be inferred from the data. + @param start start address of output bytes. + @param end end address of output bytes (inclusive). + @param pad [DEPRECATED PARAMETER, please use self.padding instead] + fill empty spaces with this value + (if pad is None then this method uses self.padding). + @param size size of the block, used with start or end parameter. + @return array of unsigned char data. + ''' + if not isinstance(pad, _DeprecatedParam): + print ("IntelHex.tobinarray: 'pad' parameter is deprecated.") + if pad is not None: + print ("Please, use IntelHex.padding attribute instead.") + else: + print ("Please, don't pass it explicitly.") + print ("Use syntax like this: ih.tobinarray(start=xxx, end=yyy, size=zzz)") + else: + pad = None + return self._tobinarray_really(start, end, pad, size) + + def _tobinarray_really(self, start, end, pad, size): + """Return binary array.""" + if pad is None: + pad = self.padding + bin = array('B') + if self._buf == {} and None in (start, end): + return bin + if size is not None and size <= 0: + raise ValueError("tobinarray: wrong value for size") + start, end = self._get_start_end(start, end, size) + for i in range_g(start, end+1): + bin.append(self._buf.get(i, pad)) + return bin + + def tobinstr(self, start=None, end=None, pad=_DEPRECATED, size=None): + ''' Convert to binary form and return as binary string. + @param start start address of output bytes. + @param end end address of output bytes (inclusive). + @param pad [DEPRECATED PARAMETER, please use self.padding instead] + fill empty spaces with this value + (if pad is None then this method uses self.padding). + @param size size of the block, used with start or end parameter. + @return bytes string of binary data. + ''' + if not isinstance(pad, _DeprecatedParam): + print ("IntelHex.tobinstr: 'pad' parameter is deprecated.") + if pad is not None: + print ("Please, use IntelHex.padding attribute instead.") + else: + print ("Please, don't pass it explicitly.") + print ("Use syntax like this: ih.tobinstr(start=xxx, end=yyy, size=zzz)") + else: + pad = None + return self._tobinstr_really(start, end, pad, size) + + def _tobinstr_really(self, start, end, pad, size): + return array_tobytes(self._tobinarray_really(start, end, pad, size)) + + def tobinfile(self, fobj, start=None, end=None, pad=_DEPRECATED, size=None): + '''Convert to binary and write to file. + + @param fobj file name or file object for writing output bytes. + @param start start address of output bytes. + @param end end address of output bytes (inclusive). + @param pad [DEPRECATED PARAMETER, please use self.padding instead] + fill empty spaces with this value + (if pad is None then this method uses self.padding). + @param size size of the block, used with start or end parameter. + ''' + if not isinstance(pad, _DeprecatedParam): + print ("IntelHex.tobinfile: 'pad' parameter is deprecated.") + if pad is not None: + print ("Please, use IntelHex.padding attribute instead.") + else: + print ("Please, don't pass it explicitly.") + print ("Use syntax like this: ih.tobinfile(start=xxx, end=yyy, size=zzz)") + else: + pad = None + if getattr(fobj, "write", None) is None: + fobj = open(fobj, "wb") + close_fd = True + else: + close_fd = False + + fobj.write(self._tobinstr_really(start, end, pad, size)) + + if close_fd: + fobj.close() + + def todict(self): + '''Convert to python dictionary. + + @return dict suitable for initializing another IntelHex object. + ''' + r = {} + r.update(self._buf) + if self.start_addr: + r['start_addr'] = self.start_addr + return r + + def addresses(self): + '''Returns all used addresses in sorted order. + @return list of occupied data addresses in sorted order. + ''' + aa = dict_keys(self._buf) + aa.sort() + return aa + + def minaddr(self): + '''Get minimal address of HEX content. + @return minimal address or None if no data + ''' + aa = dict_keys(self._buf) + if aa == []: + return None + else: + return min(aa) + + def maxaddr(self): + '''Get maximal address of HEX content. + @return maximal address or None if no data + ''' + aa = dict_keys(self._buf) + if aa == []: + return None + else: + return max(aa) + + def __getitem__(self, addr): + ''' Get requested byte from address. + @param addr address of byte. + @return byte if address exists in HEX file, or self.padding + if no data found. + ''' + t = type(addr) + if t in IntTypes: + if addr < 0: + raise TypeError('Address should be >= 0.') + return self._buf.get(addr, self.padding) + elif t == slice: + addresses = dict_keys(self._buf) + ih = IntelHex() + if addresses: + addresses.sort() + start = addr.start or addresses[0] + stop = addr.stop or (addresses[-1]+1) + step = addr.step or 1 + for i in range_g(start, stop, step): + x = self._buf.get(i) + if x is not None: + ih[i] = x + return ih + else: + raise TypeError('Address has unsupported type: %s' % t) + + def __setitem__(self, addr, byte): + """Set byte at address.""" + t = type(addr) + if t in IntTypes: + if addr < 0: + raise TypeError('Address should be >= 0.') + self._buf[addr] = byte + elif t == slice: + if not isinstance(byte, (list, tuple)): + raise ValueError('Slice operation expects sequence of bytes') + start = addr.start + stop = addr.stop + step = addr.step or 1 + if None not in (start, stop): + ra = range_l(start, stop, step) + if len(ra) != len(byte): + raise ValueError('Length of bytes sequence does not match ' + 'address range') + elif (start, stop) == (None, None): + raise TypeError('Unsupported address range') + elif start is None: + start = stop - len(byte) + elif stop is None: + stop = start + len(byte) + if start < 0: + raise TypeError('start address cannot be negative') + if stop < 0: + raise TypeError('stop address cannot be negative') + j = 0 + for i in range_g(start, stop, step): + self._buf[i] = byte[j] + j += 1 + else: + raise TypeError('Address has unsupported type: %s' % t) + + def __delitem__(self, addr): + """Delete byte at address.""" + t = type(addr) + if t in IntTypes: + if addr < 0: + raise TypeError('Address should be >= 0.') + del self._buf[addr] + elif t == slice: + addresses = dict_keys(self._buf) + if addresses: + addresses.sort() + start = addr.start or addresses[0] + stop = addr.stop or (addresses[-1]+1) + step = addr.step or 1 + for i in range_g(start, stop, step): + x = self._buf.get(i) + if x is not None: + del self._buf[i] + else: + raise TypeError('Address has unsupported type: %s' % t) + + def __len__(self): + """Return count of bytes with real values.""" + return len(dict_keys(self._buf)) + + def _get_eol_textfile(eolstyle, platform): + if eolstyle == 'native': + return '\n' + elif eolstyle == 'CRLF': + if platform != 'win32': + return '\r\n' + else: + return '\n' + else: + raise ValueError("wrong eolstyle %s" % repr(eolstyle)) + _get_eol_textfile = staticmethod(_get_eol_textfile) + + def write_hex_file(self, f, write_start_addr=True, eolstyle='native', byte_count=16): + """Write data to file f in HEX format. + + @param f filename or file-like object for writing + @param write_start_addr enable or disable writing start address + record to file (enabled by default). + If there is no start address in obj, nothing + will be written regardless of this setting. + @param eolstyle can be used to force CRLF line-endings + for output file on different platforms. + Supported eol styles: 'native', 'CRLF'. + @param byte_count number of bytes in the data field + """ + if byte_count > 255 or byte_count < 1: + raise ValueError("wrong byte_count value: %s" % byte_count) + fwrite = getattr(f, "write", None) + if fwrite: + fobj = f + fclose = None + else: + fobj = open(f, 'w') + fwrite = fobj.write + fclose = fobj.close + + eol = IntelHex._get_eol_textfile(eolstyle, sys.platform) + + # Translation table for uppercasing hex ascii string. + # timeit shows that using hexstr.translate(table) + # is faster than hexstr.upper(): + # 0.452ms vs. 0.652ms (translate vs. upper) + if sys.version_info[0] >= 3: + # Python 3 + table = bytes(range_l(256)).upper() + else: + # Python 2 + table = ''.join(chr(i).upper() for i in range_g(256)) + + # start address record if any + if self.start_addr and write_start_addr: + keys = dict_keys(self.start_addr) + keys.sort() + bin = array('B', asbytes('\0'*9)) + if keys == ['CS','IP']: + # Start Segment Address Record + bin[0] = 4 # reclen + bin[1] = 0 # offset msb + bin[2] = 0 # offset lsb + bin[3] = 3 # rectyp + cs = self.start_addr['CS'] + bin[4] = (cs >> 8) & 0x0FF + bin[5] = cs & 0x0FF + ip = self.start_addr['IP'] + bin[6] = (ip >> 8) & 0x0FF + bin[7] = ip & 0x0FF + bin[8] = (-sum(bin)) & 0x0FF # chksum + fwrite(':' + + asstr(hexlify(array_tobytes(bin)).translate(table)) + + eol) + elif keys == ['EIP']: + # Start Linear Address Record + bin[0] = 4 # reclen + bin[1] = 0 # offset msb + bin[2] = 0 # offset lsb + bin[3] = 5 # rectyp + eip = self.start_addr['EIP'] + bin[4] = (eip >> 24) & 0x0FF + bin[5] = (eip >> 16) & 0x0FF + bin[6] = (eip >> 8) & 0x0FF + bin[7] = eip & 0x0FF + bin[8] = (-sum(bin)) & 0x0FF # chksum + fwrite(':' + + asstr(hexlify(array_tobytes(bin)).translate(table)) + + eol) + else: + if fclose: + fclose() + raise InvalidStartAddressValueError(start_addr=self.start_addr) + + # data + addresses = dict_keys(self._buf) + addresses.sort() + addr_len = len(addresses) + if addr_len: + minaddr = addresses[0] + maxaddr = addresses[-1] + + if maxaddr > 65535: + need_offset_record = True + else: + need_offset_record = False + high_ofs = 0 + + cur_addr = minaddr + cur_ix = 0 + + while cur_addr <= maxaddr: + if need_offset_record: + bin = array('B', asbytes('\0'*7)) + bin[0] = 2 # reclen + bin[1] = 0 # offset msb + bin[2] = 0 # offset lsb + bin[3] = 4 # rectyp + high_ofs = int(cur_addr>>16) + b = divmod(high_ofs, 256) + bin[4] = b[0] # msb of high_ofs + bin[5] = b[1] # lsb of high_ofs + bin[6] = (-sum(bin)) & 0x0FF # chksum + fwrite(':' + + asstr(hexlify(array_tobytes(bin)).translate(table)) + + eol) + + while True: + # produce one record + low_addr = cur_addr & 0x0FFFF + # chain_len off by 1 + chain_len = min(byte_count-1, 65535-low_addr, maxaddr-cur_addr) + + # search continuous chain + stop_addr = cur_addr + chain_len + if chain_len: + ix = bisect_right(addresses, stop_addr, + cur_ix, + min(cur_ix+chain_len+1, addr_len)) + chain_len = ix - cur_ix # real chain_len + # there could be small holes in the chain + # but we will catch them by try-except later + # so for big continuous files we will work + # at maximum possible speed + else: + chain_len = 1 # real chain_len + + bin = array('B', asbytes('\0'*(5+chain_len))) + b = divmod(low_addr, 256) + bin[1] = b[0] # msb of low_addr + bin[2] = b[1] # lsb of low_addr + bin[3] = 0 # rectype + try: # if there is small holes we'll catch them + for i in range_g(chain_len): + bin[4+i] = self._buf[cur_addr+i] + except KeyError: + # we catch a hole so we should shrink the chain + chain_len = i + bin = bin[:5+i] + bin[0] = chain_len + bin[4+chain_len] = (-sum(bin)) & 0x0FF # chksum + fwrite(':' + + asstr(hexlify(array_tobytes(bin)).translate(table)) + + eol) + + # adjust cur_addr/cur_ix + cur_ix += chain_len + if cur_ix < addr_len: + cur_addr = addresses[cur_ix] + else: + cur_addr = maxaddr + 1 + break + high_addr = int(cur_addr>>16) + if high_addr > high_ofs: + break + + # end-of-file record + fwrite(":00000001FF"+eol) + if fclose: + fclose() + + def tofile(self, fobj, format, byte_count=16): + """Write data to hex or bin file. Preferred method over tobin or tohex. + + @param fobj file name or file-like object + @param format file format ("hex" or "bin") + @param byte_count bytes per line + """ + if format == 'hex': + self.write_hex_file(fobj, byte_count=byte_count) + elif format == 'bin': + self.tobinfile(fobj) + else: + raise ValueError('format should be either "hex" or "bin";' + ' got %r instead' % format) + + def gets(self, addr, length): + """Get string of bytes from given address. If any entries are blank + from addr through addr+length, a NotEnoughDataError exception will + be raised. Padding is not used. + """ + a = array('B', asbytes('\0'*length)) + try: + for i in range_g(length): + a[i] = self._buf[addr+i] + except KeyError: + raise NotEnoughDataError(address=addr, length=length) + return array_tobytes(a) + + def puts(self, addr, s): + """Put string of bytes at given address. Will overwrite any previous + entries. + """ + a = array('B', asbytes(s)) + for i in range_g(len(a)): + self._buf[addr+i] = a[i] + + def getsz(self, addr): + """Get zero-terminated bytes string from given address. Will raise + NotEnoughDataError exception if a hole is encountered before a 0. + """ + i = 0 + try: + while True: + if self._buf[addr+i] == 0: + break + i += 1 + except KeyError: + raise NotEnoughDataError(msg=('Bad access at 0x%X: ' + 'not enough data to read zero-terminated string') % addr) + return self.gets(addr, i) + + def putsz(self, addr, s): + """Put bytes string in object at addr and append terminating zero at end.""" + self.puts(addr, s) + self._buf[addr+len(s)] = 0 + + def find(self, sub, start=None, end=None): + """Return the lowest index in self[start:end] where subsection sub is found. + Optional arguments start and end are interpreted as in slice notation. + + @param sub bytes-like subsection to find + @param start start of section to search within (optional) + @param end end of section to search within (optional) + """ + sub = bytes(sub) + for start, end in self[slice(start,end)].segments(): + b = self.gets(start, end-start) + i = b.find(sub) + if i != -1: + return start+i + return -1 + + def dump(self, tofile=None, width=16, withpadding=False): + """Dump object content to specified file object or to stdout if None. + Format is a hexdump with some header information at the beginning, + addresses on the left, and data on right. + + @param tofile file-like object to dump to + @param width number of bytes per line (i.e. columns) + @param withpadding print padding character instead of '--' + @raise ValueError if width is not a positive integer + """ + + if not isinstance(width,int) or width < 1: + raise ValueError('width must be a positive integer.') + # The integer can be of float type - does not work with bit operations + width = int(width) + if tofile is None: + tofile = sys.stdout + + # start addr possibly + if self.start_addr is not None: + cs = self.start_addr.get('CS') + ip = self.start_addr.get('IP') + eip = self.start_addr.get('EIP') + if eip is not None and cs is None and ip is None: + tofile.write('EIP = 0x%08X\n' % eip) + elif eip is None and cs is not None and ip is not None: + tofile.write('CS = 0x%04X, IP = 0x%04X\n' % (cs, ip)) + else: + tofile.write('start_addr = %r\n' % start_addr) + # actual data + addresses = dict_keys(self._buf) + if addresses: + addresses.sort() + minaddr = addresses[0] + maxaddr = addresses[-1] + startaddr = (minaddr // width) * width + endaddr = ((maxaddr // width) + 1) * width + maxdigits = max(len(hex(endaddr)) - 2, 4) # Less 2 to exclude '0x' + templa = '%%0%dX' % maxdigits + rangewidth = range_l(width) + if withpadding: + pad = self.padding + else: + pad = None + for i in range_g(startaddr, endaddr, width): + tofile.write(templa % i) + tofile.write(' ') + s = [] + for j in rangewidth: + x = self._buf.get(i+j, pad) + if x is not None: + tofile.write(' %02X' % x) + if 32 <= x < 127: # GNU less does not like 0x7F (128 decimal) so we'd better show it as dot + s.append(chr(x)) + else: + s.append('.') + else: + tofile.write(' --') + s.append(' ') + tofile.write(' |' + ''.join(s) + '|\n') + + def merge(self, other, overlap='error'): + """Merge content of other IntelHex object into current object (self). + @param other other IntelHex object. + @param overlap action on overlap of data or starting addr: + - error: raising OverlapError; + - ignore: ignore other data and keep current data + in overlapping region; + - replace: replace data with other data + in overlapping region. + + @raise TypeError if other is not instance of IntelHex + @raise ValueError if other is the same object as self + (it can't merge itself) + @raise ValueError if overlap argument has incorrect value + @raise AddressOverlapError on overlapped data + """ + # check args + if not isinstance(other, IntelHex): + raise TypeError('other should be IntelHex object') + if other is self: + raise ValueError("Can't merge itself") + if overlap not in ('error', 'ignore', 'replace'): + raise ValueError("overlap argument should be either " + "'error', 'ignore' or 'replace'") + # merge data + this_buf = self._buf + other_buf = other._buf + for i in other_buf: + if i in this_buf: + if overlap == 'error': + raise AddressOverlapError( + 'Data overlapped at address 0x%X' % i) + elif overlap == 'ignore': + continue + this_buf[i] = other_buf[i] + # merge start_addr + if self.start_addr != other.start_addr: + if self.start_addr is None: # set start addr from other + self.start_addr = other.start_addr + elif other.start_addr is None: # keep existing start addr + pass + else: # conflict + if overlap == 'error': + raise AddressOverlapError( + 'Starting addresses are different') + elif overlap == 'replace': + self.start_addr = other.start_addr + + def segments(self, min_gap=1): + """Return a list of ordered tuple objects, representing contiguous occupied data addresses. + Each tuple has a length of two and follows the semantics of the range and xrange objects. + The second entry of the tuple is always an integer greater than the first entry. + @param min_gap the minimum gap size between data in order to separate the segments + """ + addresses = self.addresses() + if not addresses: + return [] + elif len(addresses) == 1: + return([(addresses[0], addresses[0]+1)]) + adjacent_differences = [(b - a) for (a, b) in zip(addresses[:-1], addresses[1:])] + breaks = [i for (i, x) in enumerate(adjacent_differences) if x > min_gap] + endings = [addresses[b] for b in breaks] + endings.append(addresses[-1]) + beginnings = [addresses[b+1] for b in breaks] + beginnings.insert(0, addresses[0]) + return [(a, b+1) for (a, b) in zip(beginnings, endings)] + + def get_memory_size(self): + """Returns the approximate memory footprint for data.""" + n = sys.getsizeof(self) + n += sys.getsizeof(self.padding) + n += total_size(self.start_addr) + n += total_size(self._buf) + n += sys.getsizeof(self._offset) + return n + +#/IntelHex + + +class IntelHex16bit(IntelHex): + """Access to data as 16-bit words. Intended to use with Microchip HEX files.""" + + def __init__(self, source=None): + """Construct class from HEX file + or from instance of ordinary IntelHex class. If IntelHex object + is passed as source, the original IntelHex object should not be used + again because this class will alter it. This class leaves padding + alone unless it was precisely 0xFF. In that instance it is sign + extended to 0xFFFF. + + @param source file name of HEX file or file object + or instance of ordinary IntelHex class. + Will also accept dictionary from todict method. + """ + if isinstance(source, IntelHex): + # from ihex8 + self.padding = source.padding + self.start_addr = source.start_addr + # private members + self._buf = source._buf + self._offset = source._offset + elif isinstance(source, dict): + raise IntelHexError("IntelHex16bit does not support initialization from dictionary yet.\n" + "Patches are welcome.") + else: + IntelHex.__init__(self, source) + + if self.padding == 0x0FF: + self.padding = 0x0FFFF + + def __getitem__(self, addr16): + """Get 16-bit word from address. + Raise error if only one byte from the pair is set. + We assume a Little Endian interpretation of the hex file. + + @param addr16 address of word (addr8 = 2 * addr16). + @return word if bytes exists in HEX file, or self.padding + if no data found. + """ + addr1 = addr16 * 2 + addr2 = addr1 + 1 + byte1 = self._buf.get(addr1, None) + byte2 = self._buf.get(addr2, None) + + if byte1 != None and byte2 != None: + return byte1 | (byte2 << 8) # low endian + + if byte1 == None and byte2 == None: + return self.padding + + raise BadAccess16bit(address=addr16) + + def __setitem__(self, addr16, word): + """Sets the address at addr16 to word assuming Little Endian mode. + """ + addr_byte = addr16 * 2 + b = divmod(word, 256) + self._buf[addr_byte] = b[1] + self._buf[addr_byte+1] = b[0] + + def minaddr(self): + '''Get minimal address of HEX content in 16-bit mode. + + @return minimal address used in this object + ''' + aa = dict_keys(self._buf) + if aa == []: + return 0 + else: + return min(aa)>>1 + + def maxaddr(self): + '''Get maximal address of HEX content in 16-bit mode. + + @return maximal address used in this object + ''' + aa = dict_keys(self._buf) + if aa == []: + return 0 + else: + return max(aa)>>1 + + def tobinarray(self, start=None, end=None, size=None): + '''Convert this object to binary form as array (of 2-bytes word data). + If start and end unspecified, they will be inferred from the data. + @param start start address of output data. + @param end end address of output data (inclusive). + @param size size of the block (number of words), + used with start or end parameter. + @return array of unsigned short (uint16_t) data. + ''' + bin = array('H') + + if self._buf == {} and None in (start, end): + return bin + + if size is not None and size <= 0: + raise ValueError("tobinarray: wrong value for size") + + start, end = self._get_start_end(start, end, size) + + for addr in range_g(start, end+1): + bin.append(self[addr]) + + return bin + + +#/class IntelHex16bit + + +def hex2bin(fin, fout, start=None, end=None, size=None, pad=None): + """Hex-to-Bin convertor engine. + @return 0 if all OK + + @param fin input hex file (filename or file-like object) + @param fout output bin file (filename or file-like object) + @param start start of address range (optional) + @param end end of address range (inclusive; optional) + @param size size of resulting file (in bytes) (optional) + @param pad padding byte (optional) + """ + try: + h = IntelHex(fin) + except HexReaderError: + e = sys.exc_info()[1] # current exception + txt = "ERROR: bad HEX file: %s" % str(e) + print(txt) + return 1 + + # start, end, size + if size != None and size != 0: + if end == None: + if start == None: + start = h.minaddr() + end = start + size - 1 + else: + if (end+1) >= size: + start = end + 1 - size + else: + start = 0 + + try: + if pad is not None: + # using .padding attribute rather than pad argument to function call + h.padding = pad + h.tobinfile(fout, start, end) + except IOError: + e = sys.exc_info()[1] # current exception + txt = "ERROR: Could not write to file: %s: %s" % (fout, str(e)) + print(txt) + return 1 + + return 0 +#/def hex2bin + + +def bin2hex(fin, fout, offset=0): + """Simple bin-to-hex convertor. + @return 0 if all OK + + @param fin input bin file (filename or file-like object) + @param fout output hex file (filename or file-like object) + @param offset starting address offset for loading bin + """ + h = IntelHex() + try: + h.loadbin(fin, offset) + except IOError: + e = sys.exc_info()[1] # current exception + txt = 'ERROR: unable to load bin file:', str(e) + print(txt) + return 1 + + try: + h.tofile(fout, format='hex') + except IOError: + e = sys.exc_info()[1] # current exception + txt = "ERROR: Could not write to file: %s: %s" % (fout, str(e)) + print(txt) + return 1 + + return 0 +#/def bin2hex + + +def diff_dumps(ih1, ih2, tofile=None, name1="a", name2="b", n_context=3): + """Diff 2 IntelHex objects and produce unified diff output for their + hex dumps. + + @param ih1 first IntelHex object to compare + @param ih2 second IntelHex object to compare + @param tofile file-like object to write output + @param name1 name of the first hex file to show in the diff header + @param name2 name of the first hex file to show in the diff header + @param n_context number of context lines in the unidiff output + """ + def prepare_lines(ih): + sio = StringIO() + ih.dump(sio) + dump = sio.getvalue() + lines = dump.splitlines() + return lines + a = prepare_lines(ih1) + b = prepare_lines(ih2) + import difflib + result = list(difflib.unified_diff(a, b, fromfile=name1, tofile=name2, n=n_context, lineterm='')) + if tofile is None: + tofile = sys.stdout + output = '\n'.join(result)+'\n' + tofile.write(output) + + +class Record(object): + """Helper methods to build valid ihex records.""" + + def _from_bytes(bytes): + """Takes a list of bytes, computes the checksum, and outputs the entire + record as a string. bytes should be the hex record without the colon + or final checksum. + + @param bytes list of byte values so far to pack into record. + @return String representation of one HEX record + """ + assert len(bytes) >= 4 + # calculate checksum + s = (-sum(bytes)) & 0x0FF + bin = array('B', bytes + [s]) + return ':' + asstr(hexlify(array_tobytes(bin))).upper() + _from_bytes = staticmethod(_from_bytes) + + def data(offset, bytes): + """Return Data record. This constructs the full record, including + the length information, the record type (0x00), the + checksum, and the offset. + + @param offset load offset of first byte. + @param bytes list of byte values to pack into record. + + @return String representation of one HEX record + """ + assert 0 <= offset < 65536 + assert 0 < len(bytes) < 256 + b = [len(bytes), (offset>>8)&0x0FF, offset&0x0FF, 0x00] + bytes + return Record._from_bytes(b) + data = staticmethod(data) + + def eof(): + """Return End of File record as a string. + @return String representation of Intel Hex EOF record + """ + return ':00000001FF' + eof = staticmethod(eof) + + def extended_segment_address(usba): + """Return Extended Segment Address Record. + @param usba Upper Segment Base Address. + + @return String representation of Intel Hex USBA record. + """ + b = [2, 0, 0, 0x02, (usba>>8)&0x0FF, usba&0x0FF] + return Record._from_bytes(b) + extended_segment_address = staticmethod(extended_segment_address) + + def start_segment_address(cs, ip): + """Return Start Segment Address Record. + @param cs 16-bit value for CS register. + @param ip 16-bit value for IP register. + + @return String representation of Intel Hex SSA record. + """ + b = [4, 0, 0, 0x03, (cs>>8)&0x0FF, cs&0x0FF, + (ip>>8)&0x0FF, ip&0x0FF] + return Record._from_bytes(b) + start_segment_address = staticmethod(start_segment_address) + + def extended_linear_address(ulba): + """Return Extended Linear Address Record. + @param ulba Upper Linear Base Address. + + @return String representation of Intel Hex ELA record. + """ + b = [2, 0, 0, 0x04, (ulba>>8)&0x0FF, ulba&0x0FF] + return Record._from_bytes(b) + extended_linear_address = staticmethod(extended_linear_address) + + def start_linear_address(eip): + """Return Start Linear Address Record. + @param eip 32-bit linear address for the EIP register. + + @return String representation of Intel Hex SLA record. + """ + b = [4, 0, 0, 0x05, (eip>>24)&0x0FF, (eip>>16)&0x0FF, + (eip>>8)&0x0FF, eip&0x0FF] + return Record._from_bytes(b) + start_linear_address = staticmethod(start_linear_address) + + +class _BadFileNotation(Exception): + """Special error class to use with _get_file_and_addr_range.""" + pass + +def _get_file_and_addr_range(s, _support_drive_letter=None): + """Special method for hexmerge.py script to split file notation + into 3 parts: (filename, start, end) + + @raise _BadFileNotation when string cannot be safely split. + """ + if _support_drive_letter is None: + _support_drive_letter = (os.name == 'nt') + drive = '' + if _support_drive_letter: + if s[1:2] == ':' and s[0].upper() in ''.join([chr(i) for i in range_g(ord('A'), ord('Z')+1)]): + drive = s[:2] + s = s[2:] + parts = s.split(':') + n = len(parts) + if n == 1: + fname = parts[0] + fstart = None + fend = None + elif n != 3: + raise _BadFileNotation + else: + fname = parts[0] + def ascii_hex_to_int(ascii): + if ascii is not None: + try: + return int(ascii, 16) + except ValueError: + raise _BadFileNotation + return ascii + fstart = ascii_hex_to_int(parts[1] or None) + fend = ascii_hex_to_int(parts[2] or None) + return drive+fname, fstart, fend + + +## +# IntelHex Errors Hierarchy: +# +# IntelHexError - basic error +# HexReaderError - general hex reader error +# AddressOverlapError - data for the same address overlap +# HexRecordError - hex record decoder base error +# RecordLengthError - record has invalid length +# RecordTypeError - record has invalid type (RECTYP) +# RecordChecksumError - record checksum mismatch +# EOFRecordError - invalid EOF record (type 01) +# ExtendedAddressRecordError - extended address record base error +# ExtendedSegmentAddressRecordError - invalid extended segment address record (type 02) +# ExtendedLinearAddressRecordError - invalid extended linear address record (type 04) +# StartAddressRecordError - start address record base error +# StartSegmentAddressRecordError - invalid start segment address record (type 03) +# StartLinearAddressRecordError - invalid start linear address record (type 05) +# DuplicateStartAddressRecordError - start address record appears twice +# InvalidStartAddressValueError - invalid value of start addr record +# _EndOfFile - it's not real error, used internally by hex reader as signal that EOF record found +# BadAccess16bit - not enough data to read 16 bit value (deprecated, see NotEnoughDataError) +# NotEnoughDataError - not enough data to read N contiguous bytes +# EmptyIntelHexError - requested operation cannot be performed with empty object + +class IntelHexError(Exception): + '''Base Exception class for IntelHex module''' + + _fmt = 'IntelHex base error' #: format string + + def __init__(self, msg=None, **kw): + """Initialize the Exception with the given message. + """ + self.msg = msg + for key, value in dict_items_g(kw): + setattr(self, key, value) + + def __str__(self): + """Return the message in this Exception.""" + if self.msg: + return self.msg + try: + return self._fmt % self.__dict__ + except (NameError, ValueError, KeyError): + e = sys.exc_info()[1] # current exception + return 'Unprintable exception %s: %s' \ + % (repr(e), str(e)) + +class _EndOfFile(IntelHexError): + """Used for internal needs only.""" + _fmt = 'EOF record reached -- signal to stop read file' + +class HexReaderError(IntelHexError): + _fmt = 'Hex reader base error' + +class AddressOverlapError(HexReaderError): + _fmt = 'Hex file has data overlap at address 0x%(address)X on line %(line)d' + +# class NotAHexFileError was removed in trunk.revno.54 because it's not used + + +class HexRecordError(HexReaderError): + _fmt = 'Hex file contains invalid record at line %(line)d' + + +class RecordLengthError(HexRecordError): + _fmt = 'Record at line %(line)d has invalid length' + +class RecordTypeError(HexRecordError): + _fmt = 'Record at line %(line)d has invalid record type' + +class RecordChecksumError(HexRecordError): + _fmt = 'Record at line %(line)d has invalid checksum' + +class EOFRecordError(HexRecordError): + _fmt = 'File has invalid End-of-File record' + + +class ExtendedAddressRecordError(HexRecordError): + _fmt = 'Base class for extended address exceptions' + +class ExtendedSegmentAddressRecordError(ExtendedAddressRecordError): + _fmt = 'Invalid Extended Segment Address Record at line %(line)d' + +class ExtendedLinearAddressRecordError(ExtendedAddressRecordError): + _fmt = 'Invalid Extended Linear Address Record at line %(line)d' + + +class StartAddressRecordError(HexRecordError): + _fmt = 'Base class for start address exceptions' + +class StartSegmentAddressRecordError(StartAddressRecordError): + _fmt = 'Invalid Start Segment Address Record at line %(line)d' + +class StartLinearAddressRecordError(StartAddressRecordError): + _fmt = 'Invalid Start Linear Address Record at line %(line)d' + +class DuplicateStartAddressRecordError(StartAddressRecordError): + _fmt = 'Start Address Record appears twice at line %(line)d' + +class InvalidStartAddressValueError(StartAddressRecordError): + _fmt = 'Invalid start address value: %(start_addr)s' + + +class NotEnoughDataError(IntelHexError): + _fmt = ('Bad access at 0x%(address)X: ' + 'not enough data to read %(length)d contiguous bytes') + +class BadAccess16bit(NotEnoughDataError): + _fmt = 'Bad access at 0x%(address)X: not enough data to read 16 bit value' + +class EmptyIntelHexError(IntelHexError): + _fmt = "Requested operation cannot be executed with empty object" diff --git a/software/tools/pymcuprog/libs/intelhex/compat.py b/software/tools/pymcuprog/libs/intelhex/compat.py new file mode 100644 index 0000000..2a6bee6 --- /dev/null +++ b/software/tools/pymcuprog/libs/intelhex/compat.py @@ -0,0 +1,160 @@ +# Copyright (c) 2011, Bernhard Leiner +# Copyright (c) 2013-2018 Alexander Belchenko +# All rights reserved. +# +# Redistribution and use in source and binary forms, +# with or without modification, are permitted provided +# that the following conditions are met: +# +# * Redistributions of source code must retain +# the above copyright notice, this list of conditions +# and the following disclaimer. +# * Redistributions in binary form must reproduce +# the above copyright notice, this list of conditions +# and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# * Neither the name of the author nor the names +# of its contributors may be used to endorse +# or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +# BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +# AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +'''Compatibility functions for python 2 and 3. + +@author Bernhard Leiner (bleiner AT gmail com) +@author Alexander Belchenko (alexander belchenko AT gmail com) +''' + +__docformat__ = "javadoc" + + +import sys, array + + +if sys.version_info[0] >= 3: + # Python 3 + Python = 3 + + def asbytes(s): + if isinstance(s, bytes): + return s + return s.encode('latin1') + def asstr(s): + if isinstance(s, str): + return s + return s.decode('latin1') + + # for python >= 3.2 use 'tobytes', otherwise 'tostring' + array_tobytes = array.array.tobytes if sys.version_info[1] >= 2 else array.array.tostring + + IntTypes = (int,) + StrType = str + UnicodeType = str + + range_g = range # range generator + def range_l(*args): # range list + return list(range(*args)) + + def dict_keys(dikt): # dict keys list + return list(dikt.keys()) + def dict_keys_g(dikt): # dict keys generator + return dikt.keys() + def dict_items_g(dikt): # dict items generator + return dikt.items() + + from io import StringIO, BytesIO + + def get_binary_stdout(): + return sys.stdout.buffer + + def get_binary_stdin(): + return sys.stdin.buffer + +else: + # Python 2 + Python = 2 + + asbytes = str + asstr = str + + array_tobytes = array.array.tostring + + IntTypes = (int, long) + StrType = basestring + UnicodeType = unicode + + #range_g = xrange # range generator + def range_g(*args): + # we want to use xrange here but on python 2 it does not work with long ints + try: + return xrange(*args) + except OverflowError: + start = 0 + stop = 0 + step = 1 + n = len(args) + if n == 1: + stop = args[0] + elif n == 2: + start, stop = args + elif n == 3: + start, stop, step = args + else: + raise TypeError('wrong number of arguments in range_g call!') + if step == 0: + raise ValueError('step cannot be zero') + if step > 0: + def up(start, stop, step): + while start < stop: + yield start + start += step + return up(start, stop, step) + else: + def down(start, stop, step): + while start > stop: + yield start + start += step + return down(start, stop, step) + + range_l = range # range list + + def dict_keys(dikt): # dict keys list + return dikt.keys() + def dict_keys_g(dikt): # dict keys generator + return dikt.keys() + def dict_items_g(dikt): # dict items generator + return dikt.items() + + from cStringIO import StringIO + BytesIO = StringIO + + import os + def _force_stream_binary(stream): + """Force binary mode for stream on Windows.""" + if os.name == 'nt': + f_fileno = getattr(stream, 'fileno', None) + if f_fileno: + fileno = f_fileno() + if fileno >= 0: + import msvcrt + msvcrt.setmode(fileno, os.O_BINARY) + return stream + + def get_binary_stdout(): + return _force_stream_binary(sys.stdout) + + def get_binary_stdin(): + return _force_stream_binary(sys.stdin) diff --git a/software/tools/pymcuprog/libs/intelhex/getsizeof.py b/software/tools/pymcuprog/libs/intelhex/getsizeof.py new file mode 100644 index 0000000..b91d7eb --- /dev/null +++ b/software/tools/pymcuprog/libs/intelhex/getsizeof.py @@ -0,0 +1,64 @@ +# Recursive version sys.getsizeof(). Extendable with custom handlers. +# Code from http://code.activestate.com/recipes/577504/ +# Created by Raymond Hettinger on Fri, 17 Dec 2010 (MIT) + +import sys +from itertools import chain +from collections import deque +try: + from reprlib import repr +except ImportError: + pass + +def total_size(o, handlers={}, verbose=False): + """ Returns the approximate memory footprint an object and all of its contents. + + Automatically finds the contents of the following builtin containers and + their subclasses: tuple, list, deque, dict, set and frozenset. + To search other containers, add handlers to iterate over their contents: + + handlers = {SomeContainerClass: iter, + OtherContainerClass: OtherContainerClass.get_elements} + + """ + dict_handler = lambda d: chain.from_iterable(d.items()) + all_handlers = {tuple: iter, + list: iter, + deque: iter, + dict: dict_handler, + set: iter, + frozenset: iter, + } + all_handlers.update(handlers) # user handlers take precedence + seen = set() # track which object id's have already been seen + default_size = sys.getsizeof(0) # estimate sizeof object without __sizeof__ + + def sizeof(o): + if id(o) in seen: # do not double count the same object + return 0 + seen.add(id(o)) + s = sys.getsizeof(o, default_size) + + if verbose: + print(s, type(o), repr(o))#, file=stderr) + + for typ, handler in all_handlers.items(): + if isinstance(o, typ): + s += sum(map(sizeof, handler(o))) + break + return s + + return sizeof(o) + + +##### Example call ##### + +if __name__ == '__main__': + #d = dict(a=1, b=2, c=3, d=[4,5,6,7], e='a string of chars') + print("dict 3 elements") + d = {0:0xFF, 1:0xEE, 2:0xCC} + print(total_size(d, verbose=True)) + + #print("array 3 elements") + #import array + #print(total_size(array.array('B', b'\x01\x02\x03'))) diff --git a/software/tools/pymcuprog/libs/pyedbglib/__init__.py b/software/tools/pymcuprog/libs/pyedbglib/__init__.py new file mode 100644 index 0000000..78f7bdb --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/__init__.py @@ -0,0 +1,46 @@ +""" +Python EDBG protocol communication library +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +pyedbglib is a low-level protocol library for communicating with +Microchip CMSIS-DAP based debuggers. + +pyedbglib uses HIDAPI package with a USB-level driver such as libusb. + +The protocol library has no application usage on its own, but provides +USB-protocol-level tool drivers to applications such as pymcuprog. +In general a two-stage stack implementation is required for using pyedbglib: + + 1. Create transport HID layer + 2. Create protocol implementation using this transport layer + +All protocols implemented in the library generally take the transport layer +as a parameter to their constructors. + +To use pyedbglib as a library for applications, the following usage patterns +can be used: + +Import and instantiate transport object: + + >>> from pyedbglib.hidtransport.hidtransportfactory import hid_transport + >>> transport = hid_transport() + +Connect to any nEDBG tool. Serial number and product are optional, but must +be provided if more than one matching unit is connected: + + >>> status = transport.connect(serial_number="", product="nedbg") + +Example of application using housekeeping protocol to read out the target voltage: + + >>> from pyedbglib.protocols.housekeepingprotocol import Jtagice3HousekeepingProtocol + >>> housekeeper = Jtagice3HousekeepingProtocol(transport) + >>> housekeeper.start_session() + >>> voltage = housekeeper.get_le16(Jtagice3HousekeepingProtocol.HOUSEKEEPING_CONTEXT_ANALOG, + Jtagice3HousekeepingProtocol.HOUSEKEEPING_ANALOG_VTREF) + >>> voltage = voltage / 1000.0 + >>> housekeeper.end_session() + >>> print ("Target is running at {0:.02f}V".format(voltage)) + +""" +import logging +logging.getLogger(__name__).addHandler(logging.NullHandler()) diff --git a/software/tools/pymcuprog/libs/pyedbglib/hidtransport/__init__.py b/software/tools/pymcuprog/libs/pyedbglib/hidtransport/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/software/tools/pymcuprog/libs/pyedbglib/hidtransport/hidtransportbase.py b/software/tools/pymcuprog/libs/pyedbglib/hidtransport/hidtransportbase.py new file mode 100644 index 0000000..4228cb5 --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/hidtransport/hidtransportbase.py @@ -0,0 +1,165 @@ +"""Base class for all HID transport mechanisms.""" + +from logging import getLogger +from . import toolinfo + + +class HidTool(object): + """ + Holds transport and DAP properties of a CMSIS-DAP debugger. + + Used to select the debugger to use if multiple debuggers are connected. + """ + + # pylint: disable=too-many-instance-attributes, too-many-arguments + # These are primary keys used to identify the debugger. + + def __init__(self, vendor_id, product_id, serial_number, product_string="", manufacturer_string=""): + self.logger = getLogger(__name__) + self.interface_number = -1 + self.vendor_id = vendor_id + self.product_id = product_id + self.serial_number = serial_number + self.product_string = product_string + self.manufacturer_string = manufacturer_string + self.firmware_version = "" + self.device_vendor_id = "" + self.device_name = "" + self.packet_size = 64 + + def set_packet_size(self, packet_size): + """ + Sets the packet size + + :param packet_size: bytes per packet + """ + self.packet_size = packet_size + + def set_product_string(self, product_string): + """ + Sets the product string + + :param product_string: product name string + """ + self.product_string = product_string + + +class HidTransportBase(object): + """Base class for HID transports""" + + def __init__(self): + self.logger = getLogger(__name__) + self.devices = [] + self.device = None + self.detect_devices() + self.connected = False + + def __del__(self): + # Make sure we always disconnect the HID connection + self.disconnect() + + def detect_devices(self): + """Raise error as this method needs to be overridden.""" + raise NotImplementedError("method needs to be defined by sub-class") + + def get_matching_tools(self, serial_number_substring='', product=None): + """ + Returns a list of tools matching the given serial_number_substring and product. + + :param serial_number_substring: can be an empty string or a subset of a serial number. Not case sensitive + This function will do matching of the last part of the devices serial numbers to + the serial_number_substring. Examples: + '123' will match "MCHP3252000000043123" but not "MCP32520001230000000" + '' will match any serial number + :param product: product type to connect to. If None any tool matching the serial_number_substring + will be returned + :return: List of matching tools + """ + # Support systems which use None as the standard for a unspecified USB serial + if serial_number_substring is None: + serial_number_substring = "" + + # Making serial_number_substring case insensitive + serial_number_substring = serial_number_substring.lower() + + # Support tool shortnames + toolname_in_product_string = toolinfo.tool_shortname_to_product_string_name(product) + if toolname_in_product_string is not None: + # Making product name case insensitive + toolname_in_product_string = toolname_in_product_string.lower() + + matching_devices = [] + for device in self.devices: + if toolname_in_product_string is None or device.product_string.lower().startswith( + toolname_in_product_string): + if device.serial_number.lower().endswith(serial_number_substring): + matching_devices.append(device) + + return matching_devices + + def connect(self, serial_number=None, product=None): + """ + Makes a HID connection to a debugger + + :param serial_number: instance serial number to connect to + :param product: product type to connect to + :return: True if successfully connected to a tool, False if not + """ + if self.connected: + return True + + device_count = len(self.devices) + self.logger.debug("{:d} devices available".format(device_count)) + if device_count == 0: + self.logger.error("No CMSIS-DAP devices found.") + return False + + matching_devices = self.get_matching_tools(serial_number_substring=serial_number, product=product) + number_of_matching_devices = len(matching_devices) + + # Did we find exactly 1 tool? + if number_of_matching_devices != 1: + log_str = "Found {:d} daps matching the filter serial = \"{}\" and product = \"{}\"" + self.logger.debug(log_str.format(number_of_matching_devices, serial_number, product)) + if number_of_matching_devices > 1: + self.logger.error("Too many products found. Please specify one of:") + for device in self.devices: + self.logger.error(" > {:s} {:s}".format(device.product_string, + device.serial_number)) + return False + + # Everything is peachy, connect to the tool + self.device = matching_devices[0] + self.hid_connect(self.device) + self.logger.debug("Connected OK") + self.connected = True + packet_size = toolinfo.get_default_report_size(self.device.product_id) + self.device.set_packet_size(packet_size) + self.hid_info() + return True + + def disconnect(self): + """Release the HID connection""" + if self.connected: + self.hid_disconnect() + self.connected = False + + def hid_connect(self, device): + """Raise error as this method needs to be overridden.""" + raise NotImplementedError("method needs to be defined by sub-class") + + def hid_info(self): + """Raise error as this method needs to be overridden.""" + raise NotImplementedError("method needs to be defined by sub-class") + + def hid_disconnect(self): + """Raise error as this method needs to be overridden.""" + raise NotImplementedError("method needs to be defined by sub-class") + + def get_report_size(self): + """ + Get the packet size in bytes + + :return: bytes per packet/report + """ + return self.device.packet_size diff --git a/software/tools/pymcuprog/libs/pyedbglib/hidtransport/hidtransportfactory.py b/software/tools/pymcuprog/libs/pyedbglib/hidtransport/hidtransportfactory.py new file mode 100644 index 0000000..1ec9009 --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/hidtransport/hidtransportfactory.py @@ -0,0 +1,56 @@ +""" +Factory for HID transport connections. + +Currently supports only Cython/HIDAPI +""" + +import platform +from logging import getLogger +from ..pyedbglib_errors import PyedbglibNotSupportedError + + +def hid_transport(library="hidapi"): + """ + Dispatch a transport layer for the OS in question + + The transport layer is typically used to connect to a tool and then it is passed in as a parameter when creating + protocol objects. An example where the transport layer is used to create an instance of the housekeepingprotocol + for communication with the nEDBG debugger:: + + from pyedbglib.hidtransport.hidtransportfactory import hid_transport + transport = hid_transport() + connect_status = False + try: + connect_status = transport.connect(serial_number='', product='nedbg') + except IOError as error: + print("Unable to connect to USB device ({})".format(error)) + + if not connect_status: + print("Unable to connect to USB device") + + housekeeper = housekeepingprotocol.Jtagice3HousekeepingProtocol(transport) + + :param library: Transport library to use, currently only 'hidapi' is supported which will use the libusb hidapi + :type library: string + :returns: Instance of transport layer object + :rtype: class:cyhidapi:CyHidApiTransport + """ + logger = getLogger(__name__) + operating_system = platform.system().lower() + logger.debug("HID transport using library '{:s}' on OS '{:s}'".format(library, operating_system)) + + # HID API is the primary transport + if library == 'hidapi': + hid_api_supported_os = ['windows', 'darwin', 'linux', 'linux2'] + if operating_system in hid_api_supported_os: + from .cyhidapi import CyHidApiTransport + return CyHidApiTransport() + + msg = "System '{0:s}' not implemented for library '{1:s}'".format(operating_system, library) + logger.error(msg) + raise PyedbglibNotSupportedError(msg) + + # Other transports may include cmsis-dap DLL, atusbhid (dll or so) etc + msg = "Transport library '{0}' not implemented.".format(library) + logger.error(msg) + raise PyedbglibNotSupportedError(msg) diff --git a/software/tools/pymcuprog/libs/pyedbglib/hidtransport/toolinfo.py b/software/tools/pymcuprog/libs/pyedbglib/hidtransport/toolinfo.py new file mode 100644 index 0000000..73c8dbc --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/hidtransport/toolinfo.py @@ -0,0 +1,94 @@ +"""Gathering of all known Microchip CMSIS-DAP debuggers and default EP sizes""" + +from logging import getLogger + +# List of known useful HID/CMSIS-DAP tools +# 3G tools: +USB_TOOL_DEVICE_PRODUCT_ID_JTAGICE3 = 0x2140 +USB_TOOL_DEVICE_PRODUCT_ID_ATMELICE = 0x2141 +USB_TOOL_DEVICE_PRODUCT_ID_POWERDEBUGGER = 0x2144 +USB_TOOL_DEVICE_PRODUCT_ID_EDBG_A = 0x2111 +USB_TOOL_DEVICE_PRODUCT_ID_ZERO = 0x2157 +USB_TOOL_DEVICE_PRODUCT_ID_MASS_STORAGE = 0x2169 +USB_TOOL_DEVICE_PRODUCT_ID_PUBLIC_EDBG_C = 0x216A +USB_TOOL_DEVICE_PRODUCT_ID_KRAKEN = 0x2170 + +# 4G tools: +USB_TOOL_DEVICE_PRODUCT_ID_MEDBG = 0x2145 + +# 5G tools: +USB_TOOL_DEVICE_PRODUCT_ID_NEDBG_HID_MSD_DGI_CDC = 0x2175 +USB_TOOL_DEVICE_PRODUCT_ID_PICKIT4_HID_CDC = 0x2177 +USB_TOOL_DEVICE_PRODUCT_ID_SNAP_HID_CDC = 0x2180 + +# The Product String Names are used to identify the tool based on the USB +# device product strings (i.e. these names are usually just a subset of the +# actual product strings) +TOOL_SHORTNAME_TO_USB_PRODUCT_STRING = { + 'atmelice': "Atmel-ICE", + 'powerdebugger': "Power Debugger", + 'pickit4': "MPLAB PICkit 4", + 'snap': "MPLAB Snap", + 'nedbg': "nEDBG", + 'jtagice3': "JTAGICE3", + 'medbg': "mEDBG", + 'edbg': "EDBG", +} + +def get_default_report_size(pid): + """ + Retrieve default EP report size based on known PIDs + + :param pid: product ID + :return: packet size + """ + logger = getLogger(__name__) + hid_tools = [ + # 3G + {'pid': USB_TOOL_DEVICE_PRODUCT_ID_JTAGICE3, 'default_report_size': 512}, + {'pid': USB_TOOL_DEVICE_PRODUCT_ID_ATMELICE, 'default_report_size': 512}, + {'pid': USB_TOOL_DEVICE_PRODUCT_ID_POWERDEBUGGER, 'default_report_size': 512}, + {'pid': USB_TOOL_DEVICE_PRODUCT_ID_EDBG_A, 'default_report_size': 512}, + # 4G + {'pid': USB_TOOL_DEVICE_PRODUCT_ID_MEDBG, 'default_report_size': 64}, + # 5G + {'pid': USB_TOOL_DEVICE_PRODUCT_ID_NEDBG_HID_MSD_DGI_CDC, 'default_report_size': 64}, + {'pid': USB_TOOL_DEVICE_PRODUCT_ID_PICKIT4_HID_CDC, 'default_report_size': 64}, + {'pid': USB_TOOL_DEVICE_PRODUCT_ID_SNAP_HID_CDC, 'default_report_size': 64}] + + logger.debug("Looking up report size for pid 0x{:04X}".format(pid)) + for tool in hid_tools: + if tool['pid'] == pid: + logger.debug("Default report size is {:d}".format(tool['default_report_size'])) + return tool['default_report_size'] + logger.debug("PID not found! Reverting to 64b.") + return 64 + +def tool_shortname_to_product_string_name(shortname): + """ + Mapping for common short names of tools to product string name + + The intention is that this function is always run on the tool name and that the conversion + only happens if the name is a known shortname. If the shortname is not known of if the name + provided is already a valid Product string name then the provided shortname parameter will + just be returned unchanged. So if the name already is a correct Product string name it is + still safe to run this conversion funtion on it. + + :param shortname: shortname typically used by atbackend (powerdebugger, atmelice etc.) + :return: String to look for in USB product strings to identify the tool + """ + logger = getLogger(__name__) + + if shortname is None: + logger.debug("Tool shortname is None") + # This is also valid as the user might have provided no tool name, but the conversion function + # should still be valid + return shortname + + shortname_lower = shortname.lower() + if shortname_lower not in TOOL_SHORTNAME_TO_USB_PRODUCT_STRING: + logger.debug("%s is not a known tool shortname", shortname) + # ...but it could be a valid Product string name already so no reason to report an error + return shortname + + return TOOL_SHORTNAME_TO_USB_PRODUCT_STRING[shortname_lower] diff --git a/software/tools/pymcuprog/libs/pyedbglib/protocols/__init__.py b/software/tools/pymcuprog/libs/pyedbglib/protocols/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/software/tools/pymcuprog/libs/pyedbglib/protocols/avrcmsisdap.py b/software/tools/pymcuprog/libs/pyedbglib/protocols/avrcmsisdap.py new file mode 100644 index 0000000..964a70a --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/protocols/avrcmsisdap.py @@ -0,0 +1,144 @@ +""" +CMSIS-DAP wrapper for custom commands (using vendor extensions) +This mechanism is used to pass JTAGICE3-style commands for AVR devices +over the CMSIS-DAP interface +""" +import time +from logging import getLogger +from ..util.binary import unpack_be16 +from ..util import print_helpers +from .cmsisdap import CmsisDapUnit + + +class AvrCommandError(Exception): + """ + Exception type for AVR command-response wrapping + """ + pass + + +class AvrCommand(CmsisDapUnit): + """ + Wraps AVR command and responses + """ + + # Vendor Commands used to transport AVR over CMSIS-DAP + AVR_COMMAND = 0x80 + AVR_RESPONSE = 0x81 + AVR_EVENT = 0x82 + AVR_MORE_FRAGMENTS = 0x00 + AVR_FINAL_FRAGMENT = 0x01 + + # Retry delay on AVR receive frame + AVR_RETRY_DELAY_MS = 50 + + def __init__(self, transport, no_timeouts=False): + self.no_timeouts = no_timeouts + self.timeout = 1000 + CmsisDapUnit.__init__(self, transport) + self.ep_size = transport.get_report_size() + self.logger = getLogger(__name__) + self.logger.debug("Created AVR command on DAP wrapper") + + def poll_events(self): + """ + Polling for events from AVRs + + :return: response from events + """ + self.logger.debug("Polling AVR events") + resp = self.dap_command_response(bytearray([self.AVR_EVENT])) + return resp + + def _avr_response_receive_frame(self): + retries = int(self.timeout / self.AVR_RETRY_DELAY_MS) + # Get the delay in seconds + delay = self.AVR_RETRY_DELAY_MS / 1000 + while retries or self.no_timeouts: + resp = self.dap_command_response(bytearray([self.AVR_RESPONSE])) + if resp[0] != self.AVR_RESPONSE: + # Response received is not valid. Abort. + raise AvrCommandError("AVR response DAP command failed; invalid token: 0x{:02X}".format(resp[0])) + if resp[1] != 0x00: + return resp + self.logger.debug("Resp: %s", print_helpers.bytelist_to_hex_string(resp)) + + # Delay in seconds + time.sleep(delay) + retries -= 1 + raise AvrCommandError("AVR response timeout") + + # Chops command up into fragments + def _fragment_command_packet(self, command_packet): + packets_total = int((len(command_packet) / (self.ep_size - 4)) + 1) + self.logger.debug("Fragmenting AVR command into {:d} chunks".format(packets_total)) + fragments = [] + for i in range(0, packets_total): + command_fragment = bytearray([self.AVR_COMMAND, ((i + 1) << 4) + packets_total]) + if (len(command_packet) - (i * (self.ep_size - 4))) > (self.ep_size - 4): + length = self.ep_size - 4 + else: + length = len(command_packet) - (i * (self.ep_size - 4)) + + command_fragment.append(int(length >> 8)) + command_fragment.append(int(length & 0xFF)) + + for j in range(0, self.ep_size - 4): + if j < length: + command_fragment.append(command_packet[i * (self.ep_size - 4) + j]) + else: + command_fragment.append(0x00) + + fragments.append(command_fragment) + return fragments + + # Sends an AVR command and waits for response + def avr_command_response(self, command): + """ + Sends an AVR command and receives a response + + :param command: Command bytes to send + :return: Response bytes received + """ + fragments = self._fragment_command_packet(command) + self.logger.debug("Sending AVR command") + for fragment in fragments: + self.logger.debug("Sending AVR command 0x{:02X}".format(fragment[0])) + resp = self.dap_command_response(fragment) + if resp[0] != self.AVR_COMMAND: + raise AvrCommandError("AVR command DAP command failed; invalid token: 0x{:02X}".format(resp[0])) + if fragment == fragments[-1]: + if resp[1] != self.AVR_FINAL_FRAGMENT: + raise AvrCommandError( + "AVR command DAP command failed; invalid final fragment ack: 0x{:02X}".format(resp[1])) + else: + if resp[1] != self.AVR_MORE_FRAGMENTS: + raise AvrCommandError( + "AVR command DAP command failed; invalid non-final fragment ack: 0x{:02X}".format(resp[1])) + + # Receive response + fragment_info, _, response = self._avr_response_receive_fragment() + packets_remaining = (fragment_info & 0xF) - 1 + for _ in range(0, packets_remaining): + fragment_info, _, data = self._avr_response_receive_fragment() + response.extend(data) + return response + + def _avr_response_receive_fragment(self): + fragment = [] + # Receive a frame + response = self._avr_response_receive_frame() + + # Get the payload size from the header information + size = unpack_be16(response[2:4]) + + # The message header is 4 bytes, where the last two hold the size of the payload + if len(response) < (4 + size): + raise AvrCommandError("Response size does not match the header information.") + + # Extract data + for i in range(0, size): + fragment.append(response[4 + i]) + + fragment_info = response[1] + return fragment_info, size, fragment diff --git a/software/tools/pymcuprog/libs/pyedbglib/protocols/cmsisdap.py b/software/tools/pymcuprog/libs/pyedbglib/protocols/cmsisdap.py new file mode 100644 index 0000000..616d004 --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/protocols/cmsisdap.py @@ -0,0 +1,543 @@ +""" +CMSIS DAP access protocol + +Interfaces with CMSIS-DAP standard debuggers over HID +""" + +import time +from logging import getLogger + +from .dapwrapper import DapWrapper +from ..util import binary +from ..pyedbglib_errors import PyedbglibError + + +class CmsisDapUnit(DapWrapper): + """Communicates with a DAP via standard CMSIS-DAP firmware stack over HID transport""" + + # DAP command constants + ID_DAP_Info = 0x00 + ID_DAP_HostStatus = 0x01 + ID_DAP_Connect = 0x02 + ID_DAP_Disconnect = 0x03 + ID_DAP_TransferConfigure = 0x04 + ID_DAP_Transfer = 0x05 + ID_DAP_TransferBlock = 0x06 + ID_DAP_TransferAbort = 0x07 + ID_DAP_WriteABORT = 0x08 + ID_DAP_Delay = 0x09 + ID_DAP_ResetTarget = 0x0A + ID_DAP_SWJ_Pins = 0x10 + ID_DAP_SWJ_Clock = 0x11 + ID_DAP_SWJ_Sequence = 0x12 + ID_DAP_SWD_Configure = 0x13 + ID_DAP_JTAG_Sequence = 0x14 + ID_DAP_JTAG_Configure = 0x15 + ID_DAP_JTAG_IDCODE = 0x16 + + # DAP responses + DAP_OK = 0x00 + DAP_ERROR = 0xff + + # DAP info fields + DAP_ID_VENDOR = 0x01 + DAP_ID_PRODUCT = 0x02 + DAP_ID_SER_NUM = 0x03 + DAP_ID_FW_VER = 0x04 + DAP_ID_DEVICE_VENDOR = 0x05 + DAP_ID_DEVICE_NAME = 0x06 + DAP_ID_CAPABILITIES = 0xF0 + DAP_ID_PACKET_COUNT = 0xFE + DAP_ID_PACKET_SIZE = 0xFF + + # DAP ports + DAP_PORT_AUTODETECT = 0 + DAP_PORT_DISABLED = 0 + DAP_PORT_SWD = 1 + DAP_PORT_JTAG = 2 + + def __init__(self, transport): + self.logger = getLogger(__name__) + DapWrapper.__init__(self, transport) + + def _check_response(self, cmd, rsp): + """ + Checks that the response echoes the command + + :param cmd: command going in + :param rsp: response coming out + """ + self.logger.debug("Checking response: cmd=0x%02X rsp=0x%02X", cmd[0], rsp[0]) + if cmd[0] != rsp[0]: + raise PyedbglibError("Invalid response header") + + def dap_info(self): + """Collects the dap info""" + info = { + 'vendor': self._dap_info_field(self.DAP_ID_VENDOR), + 'product': self._dap_info_field(self.DAP_ID_PRODUCT), + 'serial': self._dap_info_field(self.DAP_ID_SER_NUM), + 'fw': self._dap_info_field(self.DAP_ID_FW_VER), + 'device_vendor': self._dap_info_field(self.DAP_ID_DEVICE_VENDOR), + 'device_name': self._dap_info_field(self.DAP_ID_DEVICE_NAME), + 'capabilities': self._dap_info_field(self.DAP_ID_CAPABILITIES) + } + return info + + def _dap_info_field(self, field): + """ + Queries one field from the dap info + + :param field: which field to query + """ + self.logger.debug("dap_info (%d)", field) + cmd = bytearray(2) + cmd[0] = self.ID_DAP_Info + cmd[1] = field + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + return (rsp[2:rsp[1] + 2].decode()).strip('\0') + + def dap_led(self, index, state): + """ + Operates the LED + + :param index: which led + :param state: what to do with it + :return: + """ + self.logger.debug("dap_led (%d, %d)", index, state) + cmd = bytearray(3) + cmd[0] = self.ID_DAP_HostStatus + cmd[1] = index + cmd[2] = state + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + + def dap_connect(self): + """Connects to the DAP""" + self.logger.debug("dap_connect (SWD)") + cmd = bytearray(2) + cmd[0] = self.ID_DAP_Connect + cmd[1] = self.DAP_PORT_SWD + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + if rsp[1] != self.DAP_PORT_SWD: + raise PyedbglibError("Connect failed (0x{0:02X})".format(rsp[1])) + + def dap_disconnect(self): + """Disconnects from the DAP""" + self.logger.debug("dap_disconnect") + cmd = bytearray(1) + cmd[0] = self.ID_DAP_Disconnect + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + + +class CmsisDapDebugger(CmsisDapUnit): + """ARM-specific cmsis-dap implementation""" + + # SWJ pin IDs + DAP_SWJ_SWCLK_TCK = (1 << 0) + DAP_SWJ_SWDIO_TMS = (1 << 1) + DAP_SWJ_TDI = (1 << 2) + DAP_SWJ_TDO = (1 << 3) + DAP_SWJ_nTRST = (1 << 5) + DAP_SWJ_nRESET = (1 << 7) + + # DAP transfer types + DAP_TRANSFER_APnDP = (1 << 0) + DAP_TRANSFER_RnW = (1 << 1) + DAP_TRANSFER_A2 = (1 << 2) + DAP_TRANSFER_A3 = (1 << 3) + DAP_TRANSFER_MATCH_VALUE = (1 << 4) + DAP_TRANSFER_MATCH_MASK = (1 << 5) + + # DAP transfer responses + DAP_TRANSFER_INVALID = 0 + DAP_TRANSFER_OK = (1 << 0) + DAP_TRANSFER_WAIT = (1 << 1) + DAP_TRANSFER_FAULT = (1 << 2) + DAP_TRANSFER_ERROR = (1 << 3) + DAP_TRANSFER_MISMATCH = (1 << 4) + + # DP definitions + DP_IDCODE = 0x00 + DP_ABORT = 0x00 + DP_CTRL_STAT = 0x04 + DP_WCR = 0x04 + DP_SELECT = 0x08 + DP_RESEND = 0x08 + DP_RDBUFF = 0x0C + + # JTAG-specific codes + JTAG_ABORT = 0x08 + JTAG_DPACC = 0x0A + JTAG_APACC = 0x0B + JTAG_IDCODE = 0x0E + JTAG_BYPASS = 0x0F + + # SWD-specific codes + SWD_AP_CSW = 0x00 + SWD_AP_TAR = 0x04 + SWD_AP_DRW = 0x0C + + # TAR size + TAR_MAX = 0x400 + + # DAP CTRL_STAT bits + # Source: Coresight Techref + CSYSPWRUPACK = (1 << 31) + CSYSPWRUPREQ = (1 << 30) + CDBGPWRUPACK = (1 << 29) + CDBGPWRUPREQ = (1 << 28) + CDBGRSTACK = (1 << 27) + CDBGRSTREQ = (1 << 26) + WDATAERR = (1 << 7) + READOK = (1 << 6) + STICKYERR = (1 << 5) + STICKYCMP = (1 << 4) + TRNMODE = (1 << 2) + STICKYORUN = (1 << 1) + ORUNDETECT = (1 << 0) + + # Useful CSW settings + CSW_32BIT = 0x02 + CSW_16BIT = 0x01 + CSW_8BIT = 0x00 + CSW_ADDRINC_OFF = 0x00 + CSW_ADDRINC_ON = (1 << 4) + + # Supported DAP IDs. + CM0P_DAPID = 0x0BC11477 + + def __init__(self, transport): + self.logger = getLogger(__name__) + CmsisDapUnit.__init__(self, transport) + + def dap_swj_clock(self, clock): + """ + Sets up the SWD clock timing + + :param clock: clock value in Hz + """ + self.logger.debug("dap_swj_clk (%d)", clock) + cmd = bytearray(1) + cmd[0] = self.ID_DAP_SWJ_Clock + cmd.extend(binary.pack_le32(clock)) + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + if rsp[1] != self.DAP_OK: + raise PyedbglibError("SWJ clock setting failed (0x{0:02X})".format(rsp[1])) + + def dap_transfer_configure(self, idle, count, retry): + """ + Configures SWD transfers + + :param idle: idle cycles + :param count: retry count + :param retry: match retry value + :return: + """ + self.logger.debug("dap_transfer_configure (%d, %d, %d)", idle, count, retry) + cmd = bytearray(2) + cmd[0] = self.ID_DAP_TransferConfigure + cmd[1] = idle + cmd.extend(binary.pack_le16(count)) + cmd.extend(binary.pack_le16(retry)) + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + if rsp[1] != self.DAP_OK: + raise PyedbglibError("Transfer configure failed (0x{0:02X})".format(rsp[1])) + + def dap_swd_configure(self, cfg): + """ + Configures the SWD interface + + :param cfg: turnaround and data phase config parameters + """ + self.logger.debug("dap_swd_configure (%d)", cfg) + cmd = bytearray(2) + cmd[0] = self.ID_DAP_SWD_Configure + cmd[1] = cfg + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + if rsp[1] != self.DAP_OK: + raise PyedbglibError("SWD configure failed (0x{0:02X})".format(rsp[1])) + + def dap_reset_target(self): + """Reset the target using the DAP""" + self.logger.debug("dap_reset_target") + cmd = bytearray(1) + cmd[0] = self.ID_DAP_ResetTarget + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + if rsp[1] != self.DAP_OK: + raise PyedbglibError("Reset target failed (0x{0:02X})".format(rsp[1])) + + def dap_read_reg(self, reg): + """ + Reads a DAP AP/DP register + + :param reg: register to read + """ + self.logger.debug("dap_read_reg (0x%02X)", reg) + cmd = bytearray(8) + cmd[0] = self.ID_DAP_Transfer + cmd[1] = 0x00 # dap + cmd[2] = 0x01 # 1 word + cmd[3] = reg | self.DAP_TRANSFER_RnW + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + if rsp[1] != 1 or rsp[2] != self.DAP_TRANSFER_OK: + raise PyedbglibError("Read reg failed (0x{0:02X}, {1:02X})".format(rsp[1], rsp[2])) + value = binary.unpack_le32(rsp[3:7]) + return value + + def dap_write_reg(self, reg, value): + """ + Writes a DAP AP/DP register + + :param reg: register to write + :param value: value to write + """ + self.logger.debug("dap_write_reg (0x%02X) = 0x%08X", reg, value) + cmd = bytearray(4) + cmd[0] = self.ID_DAP_Transfer + cmd[1] = 0x00 # dap + cmd[2] = 0x01 # 1 word + cmd[3] = reg + cmd.extend(binary.pack_le32(value)) + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + if rsp[1] != 1 or rsp[2] != self.DAP_TRANSFER_OK: + raise PyedbglibError("Write reg failed (0x{0:02X}, {1:02X})".format(rsp[1], rsp[2])) + + def read_word(self, address): + """ + Reads a word from the device memory bus + + :param address: address to read + """ + self.logger.debug("read word at 0x%08X", address) + self.dap_write_reg(self.SWD_AP_TAR | self.DAP_TRANSFER_APnDP, address) + return self.dap_read_reg(self.SWD_AP_DRW | self.DAP_TRANSFER_APnDP) + + def write_word(self, address, data): + """ + Writes a word to the device memory bus + + :param address: address to write + :param data: data to write + """ + self.logger.debug("write word at 0x%08X = 0x%08X", address, data) + self.dap_write_reg(self.SWD_AP_TAR | self.DAP_TRANSFER_APnDP, address) + self.dap_write_reg(self.SWD_AP_DRW | self.DAP_TRANSFER_APnDP, data) + + @staticmethod + def multiple_of_four(x): + """ 4 byte boundary """ + return x & ~0x03 + + def read_block(self, address, numbytes): + """ + Reads a block from the device memory bus + + :param address: byte address + :param numbytes: number of bytes + """ + self.logger.debug("Block read of %d bytes at address 0x%08X", numbytes, address) + # Collect results here + result = bytearray() + # In chunks of (len-header) + max_payload_size_bytes = self.multiple_of_four(self.transport.get_report_size() - 5) + self.logger.debug("Max payload size of %d bytes", max_payload_size_bytes) + while numbytes: + # Calculate read size + read_size_bytes = max_payload_size_bytes + + # Last chunk? + if read_size_bytes > numbytes: + read_size_bytes = numbytes + + # Too large for TAR? + tar_max_chunk = self.TAR_MAX - (address - (address & (1-self.TAR_MAX))) + if read_size_bytes > tar_max_chunk: + read_size_bytes = tar_max_chunk + + # Log + self.logger.debug("Read %d bytes from TAR address 0x%08X", read_size_bytes, address) + + # Set TAR + self.dap_write_reg(self.SWD_AP_TAR | self.DAP_TRANSFER_APnDP, address) + + # Read chunk + cmd = bytearray(2) + cmd[0] = self.ID_DAP_TransferBlock + cmd[1] = 0x00 + cmd.extend(binary.pack_le16(read_size_bytes // 4)) + cmd.extend([self.SWD_AP_DRW | self.DAP_TRANSFER_RnW | self.DAP_TRANSFER_APnDP]) + + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + + # Check outcome + if rsp[3] != self.DAP_TRANSFER_OK: + raise PyedbglibError("Transfer failed (0x{0:02X}) address 0x{1:08X}".format(rsp[3], address)) + + # Extract payload + num_words_read = binary.unpack_le16(rsp[1:3]) + + # Check + if num_words_read * 4 != read_size_bytes: + raise PyedbglibError( + "Unexpected number of bytes returned from block read ({0:d} != {1:d})".format(num_words_read * 4, + read_size_bytes)) + + # Extend results + result.extend(rsp[4:4 + read_size_bytes]) + numbytes -= read_size_bytes + address += read_size_bytes + + return result + + def write_block(self, address, data): + """ + Writes a block to the device memory bus + + :param address: byte address + :param data: data + """ + self.logger.debug("Block write of %d bytes at address 0x%08X", len(data), address) + + # In chunks of (len-header) + max_payload_size_bytes = self.multiple_of_four(self.transport.get_report_size() - 5) + while data: + # Calculate write size + write_size_bytes = max_payload_size_bytes + if write_size_bytes > len(data): + write_size_bytes = len(data) + + # Too large for TAR? + tar_max_chunk = self.TAR_MAX - (address - (address & (1 - self.TAR_MAX))) + if write_size_bytes > tar_max_chunk: + write_size_bytes = tar_max_chunk + + # Set TAR + self.dap_write_reg(self.SWD_AP_TAR | self.DAP_TRANSFER_APnDP, address) + + cmd = bytearray(2) + cmd[0] = self.ID_DAP_TransferBlock + cmd[1] = 0x00 + cmd.extend(binary.pack_le16(write_size_bytes // 4)) + cmd.extend([self.SWD_AP_DRW | self.DAP_TRANSFER_APnDP]) + cmd.extend(data[0:write_size_bytes]) + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + + # Shrink data buffer + data = data[write_size_bytes:] + address += write_size_bytes + + def _send_flush_tms(self): + cmd = bytearray(2) + cmd[0] = self.ID_DAP_SWJ_Sequence + cmd[1] = 7 * 8 + for _ in range(7): + cmd.extend([0xff]) + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + if rsp[1] != self.DAP_OK: + raise PyedbglibError("SWJ sequence failed (0x{0:02X})".format(rsp[1])) + + def init_swj(self): + """Magic sequence to execute on pins to enable SWD in case of JTAG-default parts""" + self.logger.debug("SWJ init sequence") + # According to ARM manuals: + # Send at least 50 cycles with TMS=1 + self._send_flush_tms() + + # Send 16-bit switching code + cmd = bytearray(2) + cmd[0] = self.ID_DAP_SWJ_Sequence + cmd[1] = 16 + cmd.extend(binary.pack_le16(0xE79E)) + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + if rsp[1] != self.DAP_OK: + raise PyedbglibError("SWJ sequence failed (0x{0:02X})".format(rsp[1])) + + # Flush TMS again + self._send_flush_tms() + + # Set data low again + cmd = bytearray(3) + cmd[0] = self.ID_DAP_SWJ_Sequence + cmd[1] = 1 + cmd[2] = 0x00 + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + if rsp[1] != self.DAP_OK: + raise PyedbglibError("SWJ sequence failed (0x{0:02X})".format(rsp[1])) + + # Now read the ID to check that it has switched + dap_id = self.dap_read_idcode() + if dap_id != self.CM0P_DAPID: + raise PyedbglibError("Invalid SWD DAP ID code! Only M0+ is currently supported.") + + def dap_read_idcode(self): + """Reads the IDCODE from the SWD DP""" + self.logger.debug("reading swd idcode") + return self.dap_read_reg(self.DP_IDCODE) + + def dap_target_init(self): + """Configures the DAP for use""" + self.logger.debug("dap_target_init") + # Clear all stickies + self.dap_write_reg(self.DP_ABORT, self.STICKYERR | self.STICKYCMP | self.STICKYORUN) + # Select to 0 + self.dap_write_reg(self.DP_SELECT, 0) + # Request debug power + self.dap_write_reg(self.DP_CTRL_STAT, self.CDBGPWRUPREQ | self.CSYSPWRUPREQ) + # Most useful default of 32-bit word access with auto-increment enabled + self.dap_write_reg(self.SWD_AP_CSW | self.DAP_TRANSFER_APnDP, self.CSW_ADDRINC_ON | self.CSW_32BIT) + + +class CmsisDapSamDebugger(CmsisDapDebugger): + """SAM specific CMSIS-DAP debugger""" + + def dap_reset_ext(self, extend=False): + """ + Reset the target using the hardware + + Some SAM devices (for example SAMDx and SAMLx) have an additional 'reset extension' capability which is not part + of the CMSIS-DAP standard. It is used to prevent the device from running after reset and then overriding its + SWD IO. The procedure is simply to hold SW_CLK low while releasing /RESET. This is done here using SWJ pins + function IF the extend argument is set. + + :param extend: boolean flag to extend reset + """ + self.logger.debug("dap_reset_ext") + cmd = bytearray(7) + cmd[0] = self.ID_DAP_SWJ_Pins + cmd[1] = 0 # Reset LOW, TCK LOW + cmd[2] = self.DAP_SWJ_nRESET + if extend: + cmd[2] |= self.DAP_SWJ_SWCLK_TCK + cmd[3] = 0 + cmd[4] = 0 + cmd[5] = 0 + cmd[6] = 0 + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + + cmd[1] = self.DAP_SWJ_nRESET # Reset high, TCK still low + cmd[2] = self.DAP_SWJ_nRESET + if extend: + cmd[2] |= self.DAP_SWJ_SWCLK_TCK + + rsp = self.dap_command_response(cmd) + self._check_response(cmd, rsp) + + # Allow Reset to be pulled high + time.sleep(0.1) diff --git a/software/tools/pymcuprog/libs/pyedbglib/protocols/dapwrapper.py b/software/tools/pymcuprog/libs/pyedbglib/protocols/dapwrapper.py new file mode 100644 index 0000000..178a561 --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/protocols/dapwrapper.py @@ -0,0 +1,38 @@ +"""Wrapper for any protocol over CMSIS-DAP""" + +from logging import getLogger + + +class DapWrapper(object): + """Base class for any CMSIS-DAP protocol wrapper""" + + def __init__(self, transport): + self.logger = getLogger(__name__) + self.transport = transport + self.logger.debug("Created DapWrapper") + + def dap_command_response(self, packet): + """ + Send a command, receive a response + + :param packet: bytes to send + :return: response received + """ + return self.transport.hid_transfer(packet) + + def dap_command_write(self, packet): + """ + Send a packet + + :param packet: packed data to sent + :return: bytes sent + """ + return self.transport.hid_write(packet) + + def dap_command_read(self): + """ + Receive data + + :return: data received + """ + return self.transport.hid_read() diff --git a/software/tools/pymcuprog/libs/pyedbglib/protocols/edbgprotocol.py b/software/tools/pymcuprog/libs/pyedbglib/protocols/edbgprotocol.py new file mode 100644 index 0000000..6e78cd4 --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/protocols/edbgprotocol.py @@ -0,0 +1,210 @@ +"""Implements EDBG Protocol, a sub-protocol in the JTAGICE3 family of protocols.""" + +from logging import getLogger +from ..util.binary import unpack_be16 +from .jtagice3protocol import Jtagice3Protocol + + +class EdbgProtocol(Jtagice3Protocol): + """Implements EDBG protocol functionality on the JTAGICE3 protocol family""" + + CMD_EDBG_QUERY = 0x00 # Capability discovery + CMD_EDBG_SET = 0x01 # Set parameters + CMD_EDBG_GET = 0x02 # Get parameters + + CMD_EDBG_PROGRAM_ID_CHIP = 0x50 # Programs an ID chip + CMD_EDBG_REFRESH_ID_CHIP = 0x51 # Triggers ID chip refresh + CMD_EDBG_READ_ID_CHIP = 0x7E # Retrieve ID chip info + + AVR_GET_CONFIG = 0x83 # CMSIS vendor 3 get config command + + RSP_EDBG_OK = 0x80 # All OK + RSP_EDBG_LIST = 0x81 # List of items returned + RSP_EDBG_DATA = 0x84 # Data returned + RSP_EDBG_FAILED = 0xA0 # Command failed to execute + + EDBG_QUERY_COMMANDS = 0x00 + + EDBG_CTXT_CONTROL = 0x00 # Control + EDBG_CONTROL_LED_USAGE = 0x00 + EDBG_CONTROL_EXT_PROG = 0x01 + EDBG_CONTROL_TARGET_POWER = 0x10 + + EDBG_CONFIG_KIT_DATA = 0x20 # Read the kit info flash page + + """Mapping EDBG error codes to more human friendly strings""" + EDBG_ERRORS = {0: 'SUCCESS'} + + """Mapping SHA204 response codes to more human friendly strings""" + RESPONSE_CODE = {0x00: 'SHA204_SUCCESS', + 0xD2: 'SHA204_PARSE_ERROR', + 0xD3: 'SHA204_CMD_FAIL', + 0xD4: 'SHA204_STATUS_CRC', + 0xE0: 'SHA204_FUNC_FAIL', + 0xE2: 'SHA204_BAD_PARAM', + 0xE4: 'SHA204_INVALID_SIZE', + 0xE5: 'SHA204_BAD_CRC', + 0xE6: 'SHA204_RX_FAIL', + 0xE7: 'SHA204_RX_NO_RESPONSE', + 0xE8: 'SHA204_RESYNC_WITH_WAKEUP', + 0xF0: 'SHA204_COMM_FAIL', + 0xF1: 'SHA204_TIMEOUT', + 0xFA: 'ID_DATA_LOCKED', + 0xFB: 'ID_CONFIG_LOCKED', + 0xFC: 'ID_INVALID_SLOT', + 0xFD: 'ID_DATA_PARSING_ERROR', + 0xFE: 'ID_DATA_NOT_EQUAL'} + + def __init__(self, transport): + self.logger = getLogger(__name__) + super(EdbgProtocol, self).__init__( + transport, Jtagice3Protocol.HANDLER_EDBG) + + def check_command_exists(self, command): + """ + Check if command is supported + + Runs a query to the tool to get a list of supported commands, then looks for + the input command in the list. If not supported, it raises NotImplementedError. + + :param command: The command to test. + :return: None + """ + commands_supported = self.query(self.EDBG_QUERY_COMMANDS) + if command not in commands_supported: + raise NotImplementedError("Invalid command: 0x{:02X}".format(command)) + + def error_as_string(self, code): + """ + Get the response error as a string (error code translated to descriptive string) + + :param code: error code + :return: error code as descriptive string + """ + try: + return self.EDBG_ERRORS[code] + except KeyError: + return "Unknown error!" + + def response_as_string(self, code): + """ + Get the response code as a string (response code translated to descriptive string) + + :param code: response code + :return: error code as descriptive string + """ + try: + return self.RESPONSE_CODE[code] + except KeyError: + return "Unknown response!" + + def program_id_chip(self, id_number, data): + """ + Program the connected ID device located at the id_number with data. + + :param id_number: Extension header ID number (Range 1 - 16) + :param data: A 64-byte data array to be programmed + :return: Response status from the programming + """ + self.logger.info("Programming ID chip...") + try: + self.check_command_exists(self.CMD_EDBG_PROGRAM_ID_CHIP) + except NotImplementedError as err: + self.logger.warning("Non-compliant command: %s", err) + + # Old EDBG implementations contained a non-compliant version of this command + # Version 0 command + packet = bytearray([self.CMD_EDBG_PROGRAM_ID_CHIP, self.CMD_VERSION0, id_number - 1] + data) + resp = self.jtagice3_command_response_raw(packet) + self.logger.debug("Program ID response: %s", self.response_as_string(resp[3])) + return resp[3] + else: + # Version 1 command + packet = bytearray([self.CMD_EDBG_PROGRAM_ID_CHIP, self.CMD_VERSION1, id_number] + data) + status = self.check_response(self.jtagice3_command_response(packet)) + self.logger.debug("Program ID response: %s", self.response_as_string(status[0])) + return status[0] + + def refresh_id_chip(self): + """ + Forces a refresh of the list of connected ID devices. + + :return: None + """ + self.logger.info("Refreshing ID chip...") + try: + self.check_command_exists(self.CMD_EDBG_REFRESH_ID_CHIP) + except NotImplementedError as err: + self.logger.warning("Non-compliant command: %s", err) + + # Old EDBG implementations contained a non-compliant version of this command + # Version 0 command + packet = bytearray([self.CMD_EDBG_REFRESH_ID_CHIP, self.CMD_VERSION0]) + resp = self.jtagice3_command_response_raw(packet) + if not resp[3] == self.RSP_EDBG_OK: + raise IOError("Invalid response from CMD_EDBG_REFRESH_ID_CHIP") + else: + # Version 1 command + packet = bytearray([self.CMD_EDBG_REFRESH_ID_CHIP, self.CMD_VERSION1]) + self.check_response(self.jtagice3_command_response(packet)) + + def read_id_chip(self, id_number): + """ + Reads the ID information from the ID chip connected at id_number + + :param id_number: Extension header ID number (Range 1 - 16) + :return: A 64-byte data array + """ + self.logger.info("Reading ID chip...") + try: + self.check_command_exists(self.CMD_EDBG_READ_ID_CHIP) + except NotImplementedError as err: + self.logger.warning("Non-compliant command: %s", err) + + # Old EDBG implementations contained a non-compliant version of this command + # Version 0 command + packet = bytearray([self.CMD_EDBG_READ_ID_CHIP, self.CMD_VERSION0, id_number - 1]) + resp = self.jtagice3_command_response_raw(packet) + if resp[4] == self.RSP_EDBG_DATA: + return resp[6:] + return False + else: + # Version 1 command + packet = bytearray([self.CMD_EDBG_READ_ID_CHIP, self.CMD_VERSION1, id_number]) + data = self.check_response(self.jtagice3_command_response(packet)) + return data + + def read_edbg_extra_info(self): + """ + Reads the kit info flash page, containing board specific data + + :return: A data array containing the kit info + """ + self.logger.info("Reading kit info...") + + # The second parameter tells the debugger it is the only command + # The last parameter tells what to read. If zero a whole page is read, and + # if non-zero 32-bytes is fetched from offset 32 * parameter. The parameter + # cannot be greater than 8 + response = self.dap_command_response(bytearray([self.AVR_GET_CONFIG, 0x01, + self.EDBG_CONFIG_KIT_DATA, 0x0])) + + # Remove unused data + if len(response) >= 256 + 6: + self.logger.info("Response size is truncated") + response = response[:256 + 6] + + # Byte 0 will echo the current command + # Byte 1 show the command status + if response[0] == self.AVR_GET_CONFIG: + + # Check the status code + if response[1] == 0: + # Bytes [3..2] contain the received size + size = unpack_be16(response[2:4]) + return response[6:size] + + self.logger.warning("Command failed with error: %i", response[1]) + + self.logger.warning("Command was not echoed back") + return False diff --git a/software/tools/pymcuprog/libs/pyedbglib/protocols/housekeepingprotocol.py b/software/tools/pymcuprog/libs/pyedbglib/protocols/housekeepingprotocol.py new file mode 100644 index 0000000..b43256e --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/protocols/housekeepingprotocol.py @@ -0,0 +1,141 @@ +"""Implements Housekeeping Protocol, a sub-protocol in the JTAGICE3 family of protocols.""" + +from logging import getLogger + +from .jtagice3protocol import Jtagice3Protocol +from .jtagice3protocol import Jtagice3ResponseError +from ..util import binary + + +class Jtagice3HousekeepingProtocol(Jtagice3Protocol): + """Implements housekeeping functionality on the JTAGICE3 protocol family""" + + # Query contexts + HOUSEKEEPING_QUERY_COMMANDS = 0x00 # List supported commands + HOUSEKEEPING_QUERY_ANALOG_CHANNELS = 0x01 # List which analog channels are present + HOUSEKEEPING_QUERY_SPECIAL_ABILITIES = 0x02 # List special abilities + + # Protocol commands + CMD_HOUSEKEEPING_START_SESSION = 0x10 # Sign on + CMD_HOUSEKEEPING_END_SESSION = 0x11 # Sign off + CMD_HOUSEKEEPING_FW_UPGRADE = 0x50 # Enter upgrade mode + + # Get/Set contexts + HOUSEKEEPING_CONTEXT_CONFIG = 0x00 # Configuration parameters + HOUSEKEEPING_CONTEXT_ANALOG = 0x01 # Analog parameters + HOUSEKEEPING_CONTEXT_STATEMENT = 0x02 # Statement memory (deprecated) + HOUSEKEEPING_CONTEXT_USB = 0x03 # USB parameters + HOUSEKEEPING_CONTEXT_STATISTICS = 0x80 # Statistics + HOUSEKEEPING_CONTEXT_DIAGNOSTICS = 0x81 # Diagnostics + + # Config context + HOUSEKEEPING_CONFIG_HWREV = 0x00 # Hardware version + HOUSEKEEPING_CONFIG_FWREV_MAJ = 0x01 # Major firmware version + HOUSEKEEPING_CONFIG_FWREV_MIN = 0x02 # Minor firmware version + HOUSEKEEPING_CONFIG_BUILD = 0x03 # Build number (2 bytes) + HOUSEKEEPING_CONFIG_CHIP = 0x05 # Chipset ID + HOUSEKEEPING_CONFIG_BLDR_MAJ = 0x06 # Bootloader major version + HOUSEKEEPING_CONFIG_BLDR_MIN = 0x07 # Bootloader minor version + HOUSEKEEPING_CONFIG_DEBUG_BUILD = 0x08 # Debug build flag + HOUSEKEEPING_CONFIG_FIRMWARE_IMAGE = 0x09 # Firmware Image enumerator + + # USB context + HOUSEKEEPING_USB_MAX_READ = 0x00 # Maximum USB read block size + HOUSEKEEPING_USB_MAX_WRITE = 0x01 # Maximum USB write block size + HOUSEKEEPING_USB_EP_SIZE_HID = 0x10 # Current HID endpoint size + HOUSEKEEPING_USB_EP_SIZE_CDC = 0x11 # Current CDC endpoint size + + # Diagnostics + HOUSEKEEPING_DIAGNOSTICS_RESET_CAUSE = 0x00 # Last reset cause + HOUSEKEEPING_DIAGNOSTICS_BOD_CTRL = 0x01 # BOD register + HOUSEKEEPING_HOST_ID = 0x02 # Debugger host device identifier + HOUSEKEEPING_HOST_REV = 0x03 # Debugger host device revision + HOUSEKEEPING_MODULE_VER_JTAG = 0x04 # Debugger host JTAG master version + HOUSEKEEPING_MODULE_VER_AW = 0x05 # Debugger host aWire master version + HOUSEKEEPING_DIAGNOSTICS_CPU_CLK = 0x06 # Debugger host CPU clock speed + + # Analog + HOUSEKEEPING_ANALOG_VTREF = 0x00 # Target voltage reference value + HOUSEKEEPING_ANALOG_VTG_BUF = 0x01 # Bufferred target voltage reference + HOUSEKEEPING_ANALOG_VUSB = 0x02 # USB voltage + HOUSEKEEPING_TSUP_VOLTAGE = 0x20 # Target supply voltage setpoint + + # Special Abilities + HOUSEKEEPING_ABILITY_RESET_EXTENSION = 0x00 # This tool is capable of reset extension + HOUSEKEEPING_ABILITY_HV_UPDI_ENABLE = 0x10 # This tool is capable of UPDI high-voltage activation + + def __init__(self, transport): + super(Jtagice3HousekeepingProtocol, self).__init__(transport, Jtagice3Protocol.HANDLER_HOUSEKEEPING) + self.logger = getLogger(__name__) + self.logger.debug("Created AVR housekeeping protocol") + + def list_supported_commands(self): + """Uses the query interface to list all supported commands""" + self.logger.debug("Querying commands supported by this instance of housekeeping handler") + commands = self.query(self.HOUSEKEEPING_QUERY_COMMANDS) + return commands + + # Direct protocol commands + def start_session(self): + """Starts a session with the debugger (sign-on)""" + self.logger.debug("Housekeeping::start_session") + response = self.jtagice3_command_response(bytearray([self.CMD_HOUSEKEEPING_START_SESSION, self.CMD_VERSION0])) + self.check_response(response) + + def end_session(self, reset_tool=False): + """ + Ends a session with the debugger (sign-off) + + :param reset_tool: resets the hardware + :return: + """ + self.logger.debug("Housekeeping::end_session") + response = self.jtagice3_command_response( + bytearray([self.CMD_HOUSEKEEPING_END_SESSION, self.CMD_VERSION0, 1 if reset_tool else 0])) + self.check_response(response) + + def enter_upgrade_mode(self, key=0x31727C10): + """ + Puts the debugger into firmware upgrade mode + + :param key: upgrade key + :return: + """ + self.logger.debug("Housekeeping::enter_upgrade_mode") + try: + response = self.jtagice3_command_response( + bytearray([self.CMD_HOUSEKEEPING_FW_UPGRADE, self.CMD_VERSION0]) + binary.pack_be32(key)) + except IOError: + self.logger.debug("IOError on enter upgrade mode. Device rebooted before response was read.") + else: + self.check_response(response) + + def read_version_info(self): + """Reads version info from the debugger""" + self.logger.debug("Housekeeping::reading version info") + + # Results in dict form + versions = { + # HW version + 'hardware': self.get_byte(self.HOUSEKEEPING_CONTEXT_CONFIG, self.HOUSEKEEPING_CONFIG_HWREV), + # FW version + 'firmware_major': self.get_byte(self.HOUSEKEEPING_CONTEXT_CONFIG, self.HOUSEKEEPING_CONFIG_FWREV_MAJ), + 'firmware_minor': self.get_byte(self.HOUSEKEEPING_CONTEXT_CONFIG, self.HOUSEKEEPING_CONFIG_FWREV_MIN), + 'build': self.get_le16(self.HOUSEKEEPING_CONTEXT_CONFIG, self.HOUSEKEEPING_CONFIG_BUILD), + # BLDR + 'bootloader': self.get_le16(self.HOUSEKEEPING_CONTEXT_CONFIG, self.HOUSEKEEPING_CONFIG_BLDR_MAJ), + # Host info + 'chip': self.get_byte(self.HOUSEKEEPING_CONTEXT_CONFIG, self.HOUSEKEEPING_CONFIG_CHIP), + 'host_id': self.get_le32(self.HOUSEKEEPING_CONTEXT_DIAGNOSTICS, self.HOUSEKEEPING_HOST_ID), + 'host_rev': self.get_byte(self.HOUSEKEEPING_CONTEXT_DIAGNOSTICS, self.HOUSEKEEPING_HOST_REV), + # Misc + 'debug': self.get_byte(self.HOUSEKEEPING_CONTEXT_CONFIG, self.HOUSEKEEPING_CONFIG_DEBUG_BUILD) + } + + # Firmware Image Requirement Enumerator is only supported on some tools + try: + versions['fire'] = self.get_byte(self.HOUSEKEEPING_CONTEXT_CONFIG, self.HOUSEKEEPING_CONFIG_FIRMWARE_IMAGE) + except Jtagice3ResponseError: + versions['fire'] = None + + return versions diff --git a/software/tools/pymcuprog/libs/pyedbglib/protocols/jtagice3protocol.py b/software/tools/pymcuprog/libs/pyedbglib/protocols/jtagice3protocol.py new file mode 100644 index 0000000..8708fd2 --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/protocols/jtagice3protocol.py @@ -0,0 +1,337 @@ +"""JTAGICE3 protocol mappings""" + +from logging import getLogger + +from .avrcmsisdap import AvrCommand +from ..util import binary +from ..util import print_helpers +from ..pyedbglib_errors import PyedbglibError + + +class Jtagice3Command(AvrCommand): + """ + Sends a "JTAGICE3" command frame, and received a response + + JTAGICE3 protocol header is formatted: + JTAGICE3_TOKEN 0x0E + PROTOCOL_VERSION 0 + SEQUENCE_NUMBER_L + SEQUENCE_NUMBER_H + HANDLER_ID + PAYLOAD + + Response format is: + JTAGICE3_TOKEN 0x0E + SEQUENCE_NUMBER_L echo + SEQUENCE_NUMBER_H echo + HANDLER_ID + PAYLOAD + """ + + # JTAGICE3 protocol token + JTAGICE3_TOKEN = 0x0E + JTAGICE3_PROTOCOL_VERSION = 0x00 + + # Handlers within JTAGICE3 protocol + HANDLER_DISCOVERY = 0x00 + HANDLER_HOUSEKEEPING = 0x01 + HANDLER_SPI = 0x11 + HANDLER_AVR8_GENERIC = 0x12 + HANDLER_AVR32_GENERIC = 0x13 + HANDLER_TPI = 0x14 + HANDLER_EDBG = 0x20 + HANDLER_COPROCESSOR = 0x21 + HANDLER_POWER = 0x22 + HANDLER_SELFTEST = 0x81 + + def __init__(self, transport, handler): + super(Jtagice3Command, self).__init__(transport) + self.logger = getLogger(__name__) + self.logger.debug("Created JTAGICE3 command") + self.handler = handler + self.sequence_id = 0 + + def validate_response(self, response): + """ + Validates the response form the debugger + + :param response: raw response bytes + """ + self.logger.debug("Checking response (%s)", print_helpers.bytelist_to_hex_string(response)) + + # Check length first + if len(response) < 5: + raise PyedbglibError("Invalid response length ({:d}).".format(len(response))) + + # Check token + if response[0] != self.JTAGICE3_TOKEN: + raise PyedbglibError("Invalid token (0x{:02X}) in response.".format(response[0])) + + # Check sequence + sequence = response[1] + (response[2] << 8) + if self.sequence_id != sequence: + raise PyedbglibError( + "Invalid sequence in response (0x{:04X} vs 0x{:04X}).".format(self.sequence_id, sequence)) + + # Check handler + if response[3] != self.handler: + raise PyedbglibError("Invalid handler (0x{:02X}) in response.".format(response[3])) + + def jtagice3_command_response_raw(self, command): + """ + Sends a JTAGICE3 command and receives the corresponding response + + :param command: + :return: + """ + # Header + header = bytearray([self.JTAGICE3_TOKEN, self.JTAGICE3_PROTOCOL_VERSION, self.sequence_id & 0xFF, + (self.sequence_id >> 8) & 0xFF, self.handler]) + + # Send command, receive response + packet = header + bytearray(command) + response = self.avr_command_response(packet) + return response + + def jtagice3_command_response(self, command): + """ + Sends a JTAGICE3 command and receives the corresponding response, and validates it + + :param command: + :return: + """ + response = self.jtagice3_command_response_raw(command) + + # Increment sequence number + self.sequence_id += 1 + if self.sequence_id > 0xFFFE: + self.sequence_id = 1 + + # Peel and return + return response[4:] + + +class Jtagice3ResponseError(Exception): + """Exception type for JTAGICE3 responses""" + + def __init__(self, msg, code): + super(Jtagice3ResponseError, self).__init__(msg) + # self.message = msg + self.code = code + + +class Jtagice3Protocol(Jtagice3Command): + """ + Base class for all protocols in the JTAGICE3 family. + + All sub-protocols support query, get and set commands. + """ + + # Command versioning + CMD_VERSION0 = 0 + CMD_VERSION1 = 1 + + # All handler share these functions: + CMD_QUERY = 0x00 + CMD_SET = 0x01 + CMD_GET = 0x02 + + # And these base responses + PROTOCOL_OK = 0x80 + PROTOCOL_LIST = 0x81 + PROTOCOL_DATA = 0x84 + PROTOCOL_FAILED = 0xA0 + # PROTOCOL_FAILED_WITH_DATA = 0xA1 + + # Failure codes + FAILURE_OK = 0 + + # CMD_SET and CMD_GET failure codes + SETGET_FAILURE_OK = 0x00 + SETGET_FAILURE_NOT_IMPLEMENTED = 0x10 + SETGET_FAILURE_NOT_SUPPORTED = 0x11 + SETGET_FAILURE_INVALID_CLOCK_SPEED = 0x20 + SETGET_FAILURE_ILLEGAL_STATE = 0x21 + SETGET_FAILURE_JTAGM_INIT_ERROR = 0x22 + SETGET_FAILURE_INVALID_VALUE = 0x23 + SETGET_FAILURE_HANDLER_ERROR = 0x30 + + """Mapping JTAGICE3 error codes to more human friendly strings""" + JTAGICE3_ERRORS = {0: 'SUCCESS'} + + def __init__(self, transport, handler, supports_trailing_status=True): + super(Jtagice3Protocol, self).__init__(transport, handler) + self.logger = getLogger(__name__) + self.logger.debug("Created JTAGICE3 protocol") + self.supports_trailing_status = supports_trailing_status + + def check_response(self, response, expected=None): + """ + Checks the response for known errors + + :param response: response bytes + :param expected: expected response + :return: data from response + """ + status, data = self.peel_response(response, expected) + if not status: + error_message = self.error_as_string(data[0]) + msg = "JTAGICE3 error response code 0x{:02X}: '{:s}' ".format(data[0], error_message) + self.logger.error(msg) + raise Jtagice3ResponseError(error_message, data[0]) + + return data + + def error_as_string(self, code): + """ + Get the response error as a string (error code translated to descriptive string) + + :param code: error code + :return: error code as descriptive string + """ + try: + return self.JTAGICE3_ERRORS[code] + except KeyError: + return "Unknown error!" + + def peel_response(self, response, expected=None): + """ + Process the response, extracting error codes and data + + :param response: raw response bytes + :param expected: expected response + :return: status, data + """ + return_list = False, [0xFF] + # Special handling + if expected is not None and response[0] == expected: + return_list = True, response[2:] + else: + if response[0] == self.PROTOCOL_OK: + return_list = True, [] + elif response[0] == self.PROTOCOL_LIST: + return_list = True, response[2:] + elif response[0] == self.PROTOCOL_DATA: + # Trailing status is not included on some handlers + if self.supports_trailing_status and response[-1] == self.FAILURE_OK: + return_list = True, response[2:-1] + else: + return_list = False, [response[-1]] + elif response[0] == self.PROTOCOL_FAILED: + return_list = False, [response[2]] + + return return_list + + def query(self, context): + """ + Queries functionality using the QUERY API + + :param context: Query context + :return: List of supported entries + """ + self.logger.debug("Query to context 0x{:02X}".format(context)) + resp = self.jtagice3_command_response([self.CMD_QUERY, self.CMD_VERSION0, context]) + status, data = self.peel_response(resp) + if not status: + msg = "Unable to QUERY (failure code 0x{:02X})".format(data[0]) + raise PyedbglibError(msg) + return data + + def set_byte(self, context, offset, value): + """ + Sets a single byte parameter + + :param context: context (address) to set + :param offset: offset address to set + :param value: value to set + :return: + """ + self._set_protocol(context, offset, bytearray([value])) + + def set_le16(self, context, offset, value): + """ + Sets a little-endian 16-bit parameter + + :param context: context (address) to set + :param offset: offset address to set + :param value: value to set + """ + self._set_protocol(context, offset, binary.pack_le16(value)) + + def set_le32(self, context, offset, value): + """ + Sets a little-endian 32-bit parameter + + :param context: context (address) to set + :param offset: offset address to set + :param value: value to set + """ + self._set_protocol(context, offset, binary.pack_le32(value)) + + def _set_protocol(self, context, offset, data): + """ + Generic function for setting parameters + + :param context: context (address) to set + :param offset: offset address to set + :param data: values to set + """ + self.logger.debug("JTAGICE3::set {:d} byte(s) to context {:d} offset {:d}".format(len(data), + context, + offset)) + resp = self.jtagice3_command_response( + bytearray([self.CMD_SET, self.CMD_VERSION0, context, offset, len(data)]) + data) + resp_status, resp_data = self.peel_response(resp) + if not resp_status: + msg = "Unable to SET (failure code 0x{:02X})".format(resp_data[0]) + raise PyedbglibError(msg) + + def get_byte(self, context, offset): + """ + Get a single-byte parameter + + :param context: context (address) to set + :param offset: offset address to set + :return: value read + """ + data = self._get_protocol(context, offset, 1) + return data[0] + + def get_le16(self, context, offset): + """ + Get a little-endian 16-bit parameter + + :param context: context (address) to set + :param offset: offset address to set + :return: value read + """ + data = self._get_protocol(context, offset, 2) + return binary.unpack_le16(data) + + def get_le32(self, context, offset): + """ + Get a little-endian 32-bit parameter + + :param context: context (address) to set + :param offset: offset address to set + :return: value read + """ + data = self._get_protocol(context, offset, 4) + return binary.unpack_le32(data) + + def _get_protocol(self, context, offset, numbytes): + """ + Generic function to get a parameter + + :param context: context (address) to set + :param offset: offset address to set + :param numbytes: number of bytes to get + :return: value read + """ + self.logger.debug("JTAGICE3::get {:d} byte(s) from context {:d} offset {:d}".format(numbytes, context, offset)) + resp = self.jtagice3_command_response([self.CMD_GET, self.CMD_VERSION0, context, offset, numbytes]) + status, data = self.peel_response(resp) + if not status: + msg = "Unable to GET (failure code 0x{:02X})".format(data[0]) + raise Jtagice3ResponseError(msg, data) + return data diff --git a/software/tools/pymcuprog/libs/pyedbglib/pyedbglib_errors.py b/software/tools/pymcuprog/libs/pyedbglib/pyedbglib_errors.py new file mode 100644 index 0000000..7bda8b0 --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/pyedbglib_errors.py @@ -0,0 +1,21 @@ +""" +pyedbglib specific exceptions +""" + +class PyedbglibError(Exception): + """ + Base class for all pyedbglib specific exceptions + """ + + def __init__(self, msg=None, code=0): + super(PyedbglibError, self).__init__(msg) + self.code = code + +class PyedbglibNotSupportedError(PyedbglibError): + """ + Signals that an attempted operation is not supported + """ + + def __init__(self, msg=None, code=0): + super(PyedbglibNotSupportedError, self).__init__(msg) + self.code = code diff --git a/software/tools/pymcuprog/libs/pyedbglib/util/__init__.py b/software/tools/pymcuprog/libs/pyedbglib/util/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/software/tools/pymcuprog/libs/pyedbglib/util/binary.py b/software/tools/pymcuprog/libs/pyedbglib/util/binary.py new file mode 100644 index 0000000..6e8621b --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/util/binary.py @@ -0,0 +1,146 @@ +"""Packing and unpacking numbers into bytearrays of 8-bit values with various endian encodings""" + +from numbers import Integral + +def _check_input_value(value, bits): + """ + :param value: An integer + :param bits: Number of bits used to represent this integer + :return: Raises an OverflowError if the value is too large + """ + # Be sure to support both py2 and py3 + if not isinstance(value, Integral): + raise TypeError("The input {} is not an Integral type".format(value)) + + if value > (2 ** bits) - 1: + raise OverflowError("Value {} is larger than the maximum value {}".format(value, (2 ** bits) - 1)) + + +def pack_le32(value): + """ + :param value: input value + :return: 32-bit little endian bytearray representation of the input value + """ + _check_input_value(value, 32) + return bytearray([value & 0xFF, (value >> 8) & 0xFF, (value >> 16) & 0xFF, (value >> 24) & 0xFF]) + + +def pack_be32(value): + """ + :param value: input value + :return: 32-bit big endian bytearray representation of the input value + """ + _check_input_value(value, 32) + return bytearray( + [(value >> 24) & 0xFF, + (value >> 16) & 0xFF, + (value >> 8) & 0xFF, + value & 0xFF]) + + +def pack_le24(value): + """ + :param value: input value + :return: 24-bit little endian bytearray representation of the input value + """ + _check_input_value(value, 24) + return bytearray([value & 0xFF, (value >> 8) & 0xFF, (value >> 16) & 0xFF]) + + +def pack_be24(value): + """ + :param value: input value + :return: 24-bit big endian bytearray representation of the input value + """ + _check_input_value(value, 24) + return bytearray( + [(value >> 16) & 0xFF, + (value >> 8) & 0xFF, + value & 0xFF]) + + +def pack_le16(value): + """ + :param value: input value + :return: 16-bit little endian bytearray representation of the input value + """ + _check_input_value(value, 16) + return bytearray([value & 0xFF, (value >> 8) & 0xFF]) + + +def pack_be16(value): + """ + :param value: input value + :return: 16-bit big endian bytearray representation of the input value + """ + _check_input_value(value, 16) + return bytearray([(value >> 8) & 0xFF, value & 0xFF]) + + +def _check_input_array(data, length): + """ + Used to check if a bytearray or list of 8-bit values has the correct length to convert to an integer + + :param data: bytearray (or list) representing a value + :param length: Expected length of the list + :return: Raises a ValueError if len(data) is not the same as length + """ + if not isinstance(data, (list, bytearray)): + raise TypeError("The input {} is not a list of bytearray".format(data)) + + if len(data) != length: + raise ValueError("Input data {} does not have length {}".format(data, length)) + + +def unpack_le32(data): + """ + :param data: 32-bit little endian bytearray representation of an integer + :return: integer value + """ + _check_input_array(data, 4) + return data[0] + (data[1] << 8) + (data[2] << 16) + (data[3] << 24) + + +def unpack_be32(data): + """ + :param data: 32-bit big endian bytearray representation of an integer + :return: integer value + """ + _check_input_array(data, 4) + return data[3] + (data[2] << 8) + (data[1] << 16) + (data[0] << 24) + + +def unpack_le24(data): + """ + :param data: 24-bit little endian bytearray representation of an integer + :return: integer value + """ + _check_input_array(data, 3) + return data[0] + (data[1] << 8) + (data[2] << 16) + + +def unpack_be24(data): + """ + :param data: 24-bit big endian bytearray representation of an integer + :return: integer value + """ + _check_input_array(data, 3) + return data[2] + (data[1] << 8) + (data[0] << 16) + + +def unpack_le16(data): + """ + :param data: 16-bit little endian bytearray representation of an integer + :return: integer value + """ + _check_input_array(data, 2) + return data[0] + (data[1] << 8) + + +def unpack_be16(data): + """ + :param data: 16-bit big endian bytearray representation of an integer + :return: integer value + """ + _check_input_array(data, 2) + return data[1] + (data[0] << 8) diff --git a/software/tools/pymcuprog/libs/pyedbglib/util/print_helpers.py b/software/tools/pymcuprog/libs/pyedbglib/util/print_helpers.py new file mode 100644 index 0000000..0c8ac99 --- /dev/null +++ b/software/tools/pymcuprog/libs/pyedbglib/util/print_helpers.py @@ -0,0 +1,8 @@ +"""Generating string representations of variables for nice printouts""" + +def bytelist_to_hex_string(bytelist): + """ + :param bytelist: list of byte values + :return: String representation of the bytelist with each item as a byte value on the format 0xXX + """ + return '[' + ', '.join("0x%02X" % x for x in bytelist) + ']' diff --git a/software/tools/pymcuprog/libs/pymcuprog/__init__.py b/software/tools/pymcuprog/libs/pymcuprog/__init__.py new file mode 100644 index 0000000..400b6cd --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/__init__.py @@ -0,0 +1,81 @@ +""" +Python MCU programmer utility +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +pymcuprog is a utility for programming various Microchip MCU devices using Microchip CMSIS-DAP based debuggers + +pymcuprog can be used as a library using its "backend API". For example: + +Setup logging - pymcuprog uses the Python logging module + >>> import logging + >>> logging.basicConfig(format="%(levelname)s: %(message)s", level=logging.WARNING) + +Configure the session: + >>> from pymcuprog.backend import SessionConfig + >>> sessionconfig = SessionConfig("atmega4808") + +Instantiate USB transport (only 1 tool connected) + >>> from pymcuprog.toolconnection import ToolUsbHidConnection + >>> transport = ToolUsbHidConnection() + +Instantiate backend + >>> from pymcuprog.backend import Backend + >>> backend = Backend() + +Connect to tool using transport + >>> backend.connect_to_tool(transport) + +Start the session + >>> backend.start_session(sessionconfig) + +Read the target device_id + >>> device_id = backend.read_device_id() + >>> print ("Device ID is {0:06X}".format(int.from_bytes(d, byteorder="little"))) + +Print the pymcuprog package version: + >>> from pymcuprog.version import VERSION as pymcuprog_version + >>> print("pymcuprog version {}".format(pymcuprog_version)) + +In addition, the CLI-backend API is versioned for convenience: + >>> print("pymcuprog backend API version: {}".format(backend.get_api_version())) + +Logging +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +This package uses the Python logging module for publishing log messages to library users. +A basic configuration can be used (see example), but for best results a more thorough configuration is +recommended in order to control the verbosity of output from dependencies in the stack which also use logging. +See logging.yaml which is included in the package (although only used for CLI) + +Dependencies +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +pymcuprog depends on pyedbglib for its transport protocol. +pyedbglib requires a USB transport library like libusb. See pyedbglib package for more information. + +Supported devices and tools +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Note: pymcuprog is primarily intended for use with PKOB nano (nEDBG) debuggers which +are found on Curiosity Nano kits and other development boards. This means that it is +continuously tested with a selection of AVR devices with UPDI interface as well as a +selection of PIC devices. However since the protocol is compatible between all +EDBG-based debuggers (pyedbglib) it is possible to use pymcuprog with a wide range of +debuggers and devices, although not all device families/interfaces have been implemented. + +The following Atmel/Microchip debuggers are supported: + * JTAGICE3 (only firmware version 3.x) + * Atmel-ICE + * Power Debugger + * EDBG + * mEDBG + * PKOB nano (nEDBG) + * MPLAB PICkit 4 ICD (only when in 'AVR mode') + * MPLAB Snap ICD (only when in 'AVR mode') + +Not all functionality is provided on all boards. See device support below. + +The following device-types are supported: + * All UPDI devices, whether mounted on kits or standalone + * PIC devices mounted on Curiosity Nano kits, or similar board with PKOB nano (nEDBG) debugger + * Other devices (eg ATmega328P, ATsamd21e18a) may be partially supported for experimental purposes +""" +import logging +logging.getLogger(__name__).addHandler(logging.NullHandler()) diff --git a/software/tools/pymcuprog/libs/pymcuprog/backend.py b/software/tools/pymcuprog/libs/pymcuprog/backend.py new file mode 100644 index 0000000..ce2d591 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/backend.py @@ -0,0 +1,658 @@ +""" +Backend interface for the pymcuprog utility. + +This module is the boundary between the Command Line Interface (CLI) part and +the backend part that does the actual job. Any external utility or script that +needs access to the functionality provided by pymcuprog should connect to the +interface provided by this backend module +""" +# Python 3 compatibility for Python 2 +from __future__ import print_function + +import os +from logging import getLogger + +# pyedbglib dependencies +from pyedbglib.hidtransport.hidtransportfactory import hid_transport +from pyedbglib.hidtransport.hidtransportbase import HidTransportBase +from pyedbglib.protocols import housekeepingprotocol +from pyedbglib.protocols.jtagice3protocol import Jtagice3ResponseError + +from .pymcuprog_errors import PymcuprogToolConfigurationError, PymcuprogToolConnectionError +from .pymcuprog_errors import PymcuprogNotSupportedError, PymcuprogEraseError +from .pymcuprog_errors import PymcuprogSessionConfigError, PymcuprogSessionError +from .programmer import Programmer +from .deviceinfo import deviceinfo +from .deviceinfo.memorynames import MemoryNames +from .deviceinfo.memorynames import MemoryNameAliases +from .deviceinfo.eraseflags import ChiperaseEffect +from .deviceinfo.deviceinfokeys import DeviceInfoKeys, DeviceMemoryInfoKeys +from .toolconnection import ToolUsbHidConnection, ToolSerialConnection +from .utils import read_tool_info +from .utils import read_target_voltage, read_supply_voltage_setpoint, read_usb_voltage +from .utils import set_supply_voltage_setpoint +from .hexfileutils import read_memories_from_hex + +# Files in devices folder not representing devices +NON_DEVICEFILES = ["__init__.py"] +DEVICE_FOLDER = os.path.dirname(os.path.abspath(__file__)) + "//deviceinfo//devices" + +# This class is a collection of parameters so no need for any methods +#pylint: disable=too-few-public-methods +class SessionConfig(object): + """ + Collection of all parameters needed when configuring a programming session + + Used as input parameter for the start_session function + """ + device = None + interface = None + # For some interfaces this is baud in bits per second and for other interfaces this is clock frequency in Hz + interface_speed = None + # Path to python devicesupportscripts for PIC devices + packpath = None + + # Content and format of special_options will depend on the device stack implementation. + # Normally these options are not in use. + special_options = None + + def __init__(self, device): + """ + device name is mandatory + """ + self.device = device + +# To achieve a single entry point for users of the backend part of pymcuprog it is accepted to exceed the maximum +# number of methods. +#pylint: disable=too-many-public-methods +class Backend(object): + """ + Backend interface of the pymcuprog utility. + This class provides access to all the functionality provided by pymcuprog + """ + API_VERSION = '2.0' + + def __init__(self): + # Hook onto logger + self.logger = getLogger(__name__) + self.transport = None + self.connected_to_tool = False + self.session_active = False + self.programmer = None + self.device_memory_info = None + self.housekeeper = None + + def get_api_version(self): + """ + Returns the current pymcuprog API version + """ + return self.API_VERSION + + @staticmethod + def get_supported_devices(): + """ + Return a list of devices supported by pymcuprog. + + This will be the list of devices with a corresponding device file + :returns: List of device names + """ + devices = [] + for filename in os.listdir(DEVICE_FOLDER): + if filename not in NON_DEVICEFILES and filename.endswith('.py'): + devices.append(filename.split('.py')[0]) + + return devices + + @staticmethod + def get_available_hid_tools(serialnumber_substring='', tool_name=None): + """ + Return a list of Microchip USB HID tools (debuggers) connected to the host + + :param serialnumber_substring: can be an empty string or a subset of a serial number. Not case sensitive + This function will do matching of the last part of the devices serial numbers to + the serialnumber_substring. Examples: + '123' will match "MCHP3252000000043123" but not "MCP32520001230000000" + '' will match any serial number + :param tool_name: tool type to connect to. If None any tool matching the serialnumber_substring + will be returned + :returns: List of pyedbglib.hidtransport.hidtransportbase.HidTool objects + """ + # Just use a temporary transport as the request is only to report connected Microchip HID tools, + # not to connect to any of them + transport = hid_transport() + + return transport.get_matching_tools(serialnumber_substring, tool_name) + + def connect_to_tool(self, toolconnection): + """ + Connect to a tool + + The tool can either be a USB HID tool or a serial port. + :param ToolConnection: This is an instance of one of the ToolConnection sub-classes. This object wraps + parameters needed to identify which tool to connect to like tool name and USB serial or serial port + name (e.g. 'COM1'). + + For USB HID tools there are some special handling: + - If both tool name and usb_serial are None any tool will be picked. + - If usb_serial is None any tool matching the tool name will be picked + - If tool name is None any tool matching the usb_serial will be picked + - If more than one tool is connected that matches the tool name and usb_serial parameters a + PymcuprogToolConnectionError exception will be raised. + + :raises: PymcuprogToolConnectionError if more than one matching tool is found or if no matching tool is found + :raises: PymcuprogToolConfigurationError if the toolconnection configuration is incorrect + """ + if isinstance(toolconnection, ToolSerialConnection): + # For serial port connection no connection action is needed, just need to store the + # Serial port number to be used (e.g. 'COM1') + self.transport = toolconnection.serialport + elif isinstance(toolconnection, ToolUsbHidConnection): + self.transport = hid_transport() + connect_status = False + try: + connect_status = self.transport.connect(serial_number=toolconnection.serialnumber, + product=toolconnection.tool_name) + except IOError as error: + raise PymcuprogToolConnectionError("Unable to connect to USB device ({})".format(error)) + + if not connect_status: + raise PymcuprogToolConnectionError("Unable to connect to USB device") + + self.housekeeper = housekeepingprotocol.Jtagice3HousekeepingProtocol(self.transport) + self.housekeeper.start_session() + + else: + raise PymcuprogToolConfigurationError("Unknown toolconnection argument type: {})". + format(type(toolconnection))) + + self.connected_to_tool = True + + def disconnect_from_tool(self): + """ + Disconnect the connected tool + + If no tool is connected nothing is done (i.e. no exception raised when not connected) + """ + if self._is_connected_to_hid_tool(): + self.housekeeper.end_session() + self.transport.disconnect() + + self.connected_to_tool = False + + def read_tool_info(self): + """ + Interrogates tool (debugger) for useful info + + :returns: Dictionary with various info about the connected debugger + + :raises PymcuprogToolConnectionError if not connected to any USB HID tool (connect_to_tool not run) + """ + self._is_hid_tool_not_connected_raise() + + return read_tool_info(self.housekeeper) + + def read_kit_device(self): + """ + Read out the device name from kit configuration. + + If the connected tool does not have any kit configuration + (i.e. the tool is not an onboard debugger) None will be returned. + connect_to_tool must have been called before calling read_kit_device, but start_session is not necessary. + Typically read_kit_device is used to get the device name required to configure a session before calling + start_session. + :returns: Name of target device as given by the kit, None if the tool does not have any device configured. + + :raises PymcuprogToolConnectionError if not connected to any USB HID tool (connect_to_tool not run) + """ + self._is_hid_tool_not_connected_raise() + + dap_info = read_tool_info(self.housekeeper) + + device_name = dap_info['device_name'].lower() + + if device_name == '': + device_name = None + + return device_name + + def read_target_voltage(self): + """ + Read target voltage + + :returns: Measured target voltage + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogNotSupportedError if the tool does not have supply capabilities + """ + self._is_hid_tool_not_connected_raise() + + try: + voltage = read_target_voltage(self.housekeeper) + except Jtagice3ResponseError: + raise PymcuprogNotSupportedError("Connected debugger/board does not have target voltage read capability") + + return voltage + + def read_supply_voltage_setpoint(self): + """ + Read tool power supply voltage setpoint + + :returns: Tool power supply voltage setpoint + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogNotSupportedError if the tool does not have supply capabilities + """ + self._is_hid_tool_not_connected_raise() + + try: + voltage = read_supply_voltage_setpoint(self.housekeeper) + except Jtagice3ResponseError: + raise PymcuprogNotSupportedError("Connected debugger/board does not have supply voltage capability.") + + return voltage + + def read_usb_voltage(self): + """ + Read USB voltage + + :returns: Measured USB voltage + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogNotSupportedError if the tool can't measure USB voltage + """ + self._is_hid_tool_not_connected_raise() + + try: + voltage = read_usb_voltage(self.housekeeper) + except Jtagice3ResponseError: + raise PymcuprogNotSupportedError("Connected debugger/board does not have USB voltage read capability.") + + return voltage + + def set_supply_voltage_setpoint(self, setpoint): + """ + Set tool power supply voltage setpoint + + :param setpoint: Power supply setpoint + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogNotSupportedError if the tool does not have supply capabilities + :raises: ValueError if the setpoint is out of range + """ + self._is_hid_tool_not_connected_raise() + + set_supply_voltage_setpoint(self.housekeeper, setpoint) + + + def reboot_tool(self): + """ + Trigger a reboot of the tool (debugger) + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + """ + self._is_hid_tool_not_connected_raise() + + self.housekeeper.end_session(reset_tool=True) + + # A tool reboot will automatically disconnect the tool. Calling self.disconnect_from_tool + # would just fail as it would try to talk to a tool while it is rebooting + self.connected_to_tool = False + + @staticmethod + def get_device_info(device): + """ + Get info about a device + + :param device: Name of the device + :returns: dictionary with device info as defined in the device files in pymcuprog.deviceinfo.devices + + :raises: PymcuprogNotSupportedError if device is not supported + """ + try: + info = deviceinfo.getdeviceinfo(device) + except ModuleNotFoundError: + raise PymcuprogNotSupportedError("No device info for device: {}".format(device)) + + return info + + def start_session(self, sessionconfig, user_interaction_callback=None): + """ + Start a programming session. + + This function will build the device model stack and initialize the tool for a + programming session. If a session is already started calling start_session will do an end_session and start + a new session from scratch. + + Note connect_to_tool must have been called before start_session is called. If not an exception will be thrown. + + :param sessionconfig: SessionConfig object wrapping the parameters configuring the session + :param user_interaction_callback: Callback to be called when user interaction is required, + for example when doing UPDI high-voltage activation with user target power toggle. + This function could ask the user to toggle power and halt execution waiting for the user + to respond (this is default behavior if the callback is None), or if the user is another + script it could toggle power automatically and then return. + + :raises: PymcuprogSessionConfigError if starting the session failed due to incorrectly configured session + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogDeviceLockedError if unable to start the session due to the device being locked + :raises: PymcuprogNotSupportedError if configured device is not supported + """ + self._is_tool_not_connected_raise() + + # Check that all session configuration parameters required are in place + if sessionconfig.device is None or sessionconfig.device == '': + raise PymcuprogSessionConfigError("Device must be specified") + + if self.session_active: + # A session is already active so it must be ended before starting a new session + self.end_session() + + # Setup the programmer + self.programmer = Programmer(self.transport) + + if sessionconfig.special_options is not None: + self.programmer.set_options(sessionconfig.special_options) + + # Try to build the stack for this device + self.programmer.load_device(sessionconfig.device) + + self.programmer.setup_device( + sessionconfig.interface, + sessionconfig.packpath, + sessionconfig.interface_speed) + + # Make contact + self.programmer.start(user_interaction_callback=user_interaction_callback) + + # Get device memory info + self.device_memory_info = self.programmer.get_device_memory_info() + + self.session_active = True + + def end_session(self): + """ + End a programming session + + This will take down the device model stack and stop the programming session on the tool. However the tool will + not be disconnected and it will be possible to do another start_session without another connect_to_tool call. + If no session has been started this function will do nothing (i.e. it won't fail even if a session has + not been started) + """ + if self.session_active: + # Lower the flag first to ensure it is updated as the rest of this function might fail with an exception + # for example if UPDI were disabled during the session + self.session_active = False + self.programmer.stop() + + def read_device_id(self): + """ + Read out the device id + + :return Byte array with device ID as raw byte values. Number of bytes will depend upon target type + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogSessionError if a session has not been started (session_start not run) + """ + self._is_tool_not_connected_raise() + self._is_session_not_active_raise() + + return self.programmer.read_device_id() + + + def erase(self, memory_name=MemoryNameAliases.ALL, address=None): + """ + Erase target device memory + + If a single memory is specified it will only be erased if it won't affect other memories + :param memory: name of memory to erase. To unlock a device use the MemoryNameAliases.ALL + MemoryNameAliases.ALL run the widest erase: + - For PIC the widest bulk erase will be run. + - For AVR a chip erase will be run + - The following memories will not be erased: + - AVR fuses + - EEPROM if EESAVE fuse is set for AVR + - EEPROM if the target device does not support EEPROM erase + - EEPROM if Data Code Protection (CPD_n) is not enabled for PIC + - PIC ICD memory (special memory used for Debug Executives) + :param address: optional address for erase command. If address is None the complete memory + segment will be erased. Note that the address parameter will just propagate through the stack down to the + device dependent implementation (devicesupportscripts for PIC and firmware for AVR). Normal use is to + leave the address as None. + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogSessionError if a session has not been started (session_start not run) + :raises: ValueError if the specified memory is not defined for the target device + :raises: PymcuprogEraseError if the memory can't be erased or if the memory can't be erased without affecting + other memories + """ + self._is_tool_not_connected_raise() + self._is_session_not_active_raise() + + if memory_name is not None and memory_name != MemoryNameAliases.ALL: + if not self.is_isolated_erase_possible(memory_name): + message = "{} memory can't be erased or can't be erased without side effect".format(memory_name) + raise PymcuprogEraseError(message) + + self.programmer.erase(memory_name, address) + + def is_isolated_erase_possible(self, memory_name): + """ + Can the memory be erased without affecting other memories? + + :param memory_name: name of memory + :return: True only if the memory can be erased without side effects, False if memory can't be erased at all or + if erasing it will erase other memories too. + + :raises ValueError if memory is not defined for the configured device + """ + # The device model must have been loaded upfront + self._is_session_not_active_raise() + + meminfo = self.device_memory_info.memory_info_by_name(memory_name) + isolated_erase_key = DeviceMemoryInfoKeys.ISOLATED_ERASE + if isolated_erase_key in meminfo: + return meminfo[isolated_erase_key] is True + + self.logger.error('%s flag not found for %s memory', isolated_erase_key, memory_name) + return False + + def get_chiperase_effect(self, memory_name): + """ + Get the effect of a chip erase (widest bulk erase) on the given memory + + :param memory_name: name of memory + :return: One of the values defined by deviceinfo.eraseflags.ChiperaseEffect depending upon the settings in the + device model for the configured device. If the chiperase_effect flag is missing in the device model + ChiperaseEffect.NOT_ERASED will be returned. + + :raises ValueError if memory is not defined for the configured device + """ + # The device model must have been loaded upfront + self._is_session_not_active_raise() + + meminfo = self.device_memory_info.memory_info_by_name(memory_name) + chiperase_effect_key = DeviceMemoryInfoKeys.CHIPERASE_EFFECT + if chiperase_effect_key in meminfo: + return meminfo[chiperase_effect_key] + + self.logger.error('%s flag not found for %s memory', chiperase_effect_key, memory_name) + return ChiperaseEffect.NOT_ERASED + + def read_memory(self, memory_name=MemoryNameAliases.ALL, offset_byte=0, numbytes=0, max_chunk_size=None): + """ + Read target device memory + + :param memory_name: Name of memory as defined in memorynames.py. MemoryNameAliases.ALL reads all memories + defined in the device model (numbytes and offset_byte will be ignored). + :param offset_byte: Byte offset within memory to start reading at. + :param numbytes: Number of bytes to read. 0 means read all memory locations from offset_byte and until end + of memory + :return: list of namedtuples with two fields: data and memory_info. data contains a byte array of + raw data bytes and memory_info is a dictionary with memory information (as defined in + deviceinfo.deviceinfo.DeviceMemoryInfo). Normally the list will contain one item, but when + memory_name parameter is MemoryNameAliases.ALL there will be one namedtuple item per memory + type read. + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogSessionError if a session has not been started (session_start not run) + :raises: ValueError if trying to read outside the specified memory + :raises: ValueError if the specified memory is not defined for the target device + """ + self._is_tool_not_connected_raise() + self._is_session_not_active_raise() + + return self.programmer.read_memory(memory_name=memory_name, offset=offset_byte, numbytes=numbytes, max_chunk_size=max_chunk_size) + + def write_memory(self, data, memory_name=MemoryNames.FLASH, offset_byte=0, blocksize=0, pagewrite_delay=0): + """ + Write target device memory + + :param memory_name: Name of memory as defined in memorynames.py + :param offset_byte: Byte offset within memory to start writing to. + :param data: bytearray of raw data bytes to write + :param blocksize: max number of bytes to send at a time. Ignored if 0 or omitted, and not passed + to write_memory; only serialupdi supports this. + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogSessionError if a session has not been started (session_start not run) + :raises: ValueError if trying to write outside the specified memory + :raises: ValueError if the specified memory is not defined for the target device + """ + self._is_tool_not_connected_raise() + self._is_session_not_active_raise() + if blocksize == 0: + self.programmer.write_memory(data=data, memory_name=memory_name, offset=offset_byte, pagewrite_delay=pagewrite_delay) + else: + self.programmer.write_memory(data=data, memory_name=memory_name, offset=offset_byte, blocksize=blocksize, pagewrite_delay=pagewrite_delay) + + def verify_memory(self, data, memory_name=MemoryNames.FLASH, offset_byte=0, max_read_chunk=None): + """ + Verify target device memory + + :param memory_name: Name of memory as defined in DeviceMemoryInfo (deviceinfo.py) + :param offset_byte: Byte offset within memory to start verifying at. + :param data: bytearray of raw data bytes to verify against + :return: boolean compare status + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogSessionError if a session has not been started (session_start not run) + :raises: ValueError if trying to verify outside the specified memory + :raises: ValueError if the specified memory is not defined for the target device + """ + self._is_tool_not_connected_raise() + self._is_session_not_active_raise() + + return self.programmer.verify_memory(data=data, memory_name=memory_name, offset=offset_byte, max_read_chunk=max_read_chunk) + + def hold_in_reset(self): + """ + Hold target device in reset + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogSessionError if a session has not been started (session_start not run) + """ + self._is_tool_not_connected_raise() + self._is_session_not_active_raise() + + self.programmer.hold_in_reset() + + def release_from_reset(self): + """ + Release target device from reset + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogSessionError if a session has not been started (session_start not run) + """ + self._is_tool_not_connected_raise() + self._is_session_not_active_raise() + + self.programmer.release_from_reset() + + # Releasing the target from reset will take it out of programming mode. In other words the session + # is partly taken down. To keep housekeeping right and to take down the stack properly end_session + # must be called + self.end_session() + + def write_hex_to_target(self, hexfile): + """ + Write hexfile to target device + + Note no erase will be run (i.e. memory is assumed to already be erased) + + :param hexfile: name of file to write + """ + self._is_tool_not_connected_raise() + self._is_session_not_active_raise() + + hex_memories = read_memories_from_hex(os.path.abspath(hexfile), self.device_memory_info) + for segment in hex_memories: + memory_name = segment.memory_info[DeviceInfoKeys.NAME] + self.logger.debug("Writing %s...", memory_name) + self.write_memory(segment.data, memory_name, segment.offset) + + def verify_hex(self, hexfile): + """ + Verify target memory content against hexfile + + :param hexfile: name of file to verify against + :return: boolean compare status + + :raises: PymcuprogToolConnectionError if not connected to any tool (connect_to_tool not run) + :raises: PymcuprogSessionError if a session has not been started (session_start not run) + """ + self._is_tool_not_connected_raise() + self._is_session_not_active_raise() + + hex_memories = read_memories_from_hex(os.path.abspath(hexfile), self.device_memory_info) + verify_ok = True + for segment in hex_memories: + memory_name = segment.memory_info[DeviceInfoKeys.NAME] + self.logger.debug("Verifying %s...", memory_name) + segment_ok = self.verify_memory(segment.data, memory_name, segment.offset, max_read_chunk=max_read_chunk) + if segment_ok: + self.logger.debug("OK!") + else: + verify_ok = False + + return verify_ok + + def _is_tool_not_connected_raise(self): + """ + Check if any tool is connected and if not raise an exception + + :raises: PymcuprogToolConnectionError if not connected to any tool + """ + if not self._is_connected_to_hid_tool() and not self._is_connected_to_serialport(): + raise PymcuprogToolConnectionError("Not connected to any tool") + + def _is_hid_tool_not_connected_raise(self): + """ + Check if a USB HID tool is connected and if not raise an exception + + :raises: PymcuprogToolConnectionError if not connected to any tool + """ + if not self._is_connected_to_hid_tool(): + raise PymcuprogToolConnectionError("Not connected to any USB HID debugger") + + def _is_connected_to_hid_tool(self): + """ + Check if a connection to a USB HID tool is active + """ + return self.connected_to_tool and isinstance(self.transport, HidTransportBase) + + def _is_connected_to_serialport(self): + """ + Check if a connection to a Serial port is active + """ + # For Serial port communication transport is only set to a string with the name of the serial port + # to use (e.g. 'COM1'). + return self.connected_to_tool and isinstance(self.transport, str) + + def _is_session_not_active_raise(self): + """ + Check if a programming session is active and if not raise an exception + + :raises: PymcuprogSessionError if programming session not active + """ + if not self.session_active: + raise PymcuprogSessionError("No programming session active") diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/__init__.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/deviceinfo.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/deviceinfo.py new file mode 100644 index 0000000..f59864b --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/deviceinfo.py @@ -0,0 +1,290 @@ +""" +deviceinfo.py +A simple Device Information service + +Device information is stored in files named .py in the devices sub-folder +Each device file contains a dict of values +These device files are [ideally] generated from DFP information by [running generate_device_info.py | hand] +""" +# Python 3 compatibility for Python 2 +from __future__ import print_function + +import os +import importlib + +from logging import getLogger + +from pymcuprog.pymcuprog_errors import PymcuprogError +from .memorynames import MemoryNames +from .deviceinfokeys import DeviceMemoryInfoKeys, DeviceInfoKeys, DeviceInfoKeysPic + +def getdeviceinfo(devicename): + """ + Looks up device info for a given part + + :param devicename: device to look up + :return: device information dict + """ + logger = getLogger(__name__) + logger.info("Looking for device %s", devicename) + + devicename = devicename.lower() + + try: + device_module = importlib.import_module("deviceinfo.devices.{}".format(devicename)) + except ImportError: + try: + # When pymcuprog is used as a package in other scripts + # the deviceinfo module is part of the pymcuprog package + device_module = importlib.import_module("pymcuprog.deviceinfo.devices.{}".format(devicename)) + except ImportError: + device_module = importlib.import_module("{}".format(devicename)) + + device_info = getattr(device_module, "DEVICE_INFO") + + # For PIC devices there will be a default_bulk_erase_address outside any memory information + # This address needs to be converted to byte address + default_bulk_erase_address_byte = None + for param in device_info: + if param.startswith(DeviceInfoKeysPic.DEFAULT_BULK_ERASE_ADDRESS): + # Check if it's word or byte oriented data + mul = DeviceMemoryInfo.bytes_or_words(param) + if mul is not None: + default_bulk_erase_address_byte = int(device_info[param] * mul) + else: + default_bulk_erase_address_byte = device_info[param] + + if default_bulk_erase_address_byte is not None: + device_info[DeviceInfoKeysPic.DEFAULT_BULK_ERASE_ADDRESS] = default_bulk_erase_address_byte + + return device_info + +def get_supported_devices(): + """ + Return a list of all supported devices + + A device is supported if it has a device model file in the devices folder + """ + root_folder = os.path.dirname(os.path.abspath(__file__)) + dir_list = os.listdir(root_folder + "//devices") + ignore_list = ['__init__.py'] + device_list = [] + for devicefile in dir_list: + if devicefile.endswith(".py") and devicefile not in ignore_list: + devicename = devicefile.split('.')[0] + device_list.append(devicename) + + return device_list + +class DeviceMemoryInfo: + """ + API to fetch information about device memory segments + """ + def __init__(self, device_info): + self.device = device_info + self.memtypes = MemoryNames.get_all() + + # hexfile_address is the start address for the memory segment in hex files. + # PIC and ARM devices usually does not need the parameter as all locations are mapped in a single address space. + # AVR8 devices does not map all memory types in a single address space. + # Memory types have defined offsets in hex files as defined below + self.avr8_hex_file_offsets = { + MemoryNames.FLASH: 0x000000, + MemoryNames.EEPROM: 0x810000, + MemoryNames.FUSES: 0x820000, + MemoryNames.LOCKBITS: 0x830000, + MemoryNames.SIGNATURES: 0x840000, + MemoryNames.USER_ROW: 0x850000 + } + + # erase_address is the address for the erase of the memory. + # Note that for PIC devices other memories might be erased in the same operation depending on the target, + # see the programming spec for the target device. + + # erase_address, hexfile_address, hexfile_size and verify mask are optional in the device models. + # erase_address will be set to the memory address if it's missing. + # Hex file address will be set to the memory address if it's missing, unless it's an AVR device where + # the hex file offset is used instead. + # Hex file size will be set to the memory size if it's missing except for EEPROM on PIC16 devices where + # the hex file will contain phantom bytes so the hex file will contain twice as many EEPROM bytes as + # the actual EEPROM in the device + # verify_mask is set based on architecture + self.paramtypes = [DeviceMemoryInfoKeys.ADDRESS, + DeviceMemoryInfoKeys.SIZE, + DeviceMemoryInfoKeys.PAGE_SIZE, + DeviceMemoryInfoKeys.WRITE_SIZE, + DeviceMemoryInfoKeys.READ_SIZE, + DeviceMemoryInfoKeys.VERIFY_MASK, + DeviceMemoryInfoKeys.ERASE_ADDRESS, + DeviceMemoryInfoKeys.HEXFILE_ADDRESS, + DeviceMemoryInfoKeys.HEXFILE_SIZE, + DeviceMemoryInfoKeys.CHIPERASE_EFFECT, + DeviceMemoryInfoKeys.ISOLATED_ERASE] + + self.mem_by_name = {} + + # Find information about memory segments + for param in self.device: + for mtype in self.memtypes: + # Does this line describe a memory location? + if param.startswith(mtype): + self._configure_memory_param(mtype, param) + + # erase_address and hexfile_address are optional and should default to the value of the address parameter + optional_params = [DeviceMemoryInfoKeys.VERIFY_MASK, + DeviceMemoryInfoKeys.HEXFILE_ADDRESS, + DeviceMemoryInfoKeys.ERASE_ADDRESS, + DeviceMemoryInfoKeys.HEXFILE_SIZE] + for optional_param in optional_params: + for memtype in self.mem_by_name: + if optional_param not in self.mem_by_name[memtype]: + # Set the verify mask based on architecture + if optional_param == DeviceMemoryInfoKeys.VERIFY_MASK: + verify_mask = self._get_verify_mask(self.device[DeviceInfoKeys.ARCHITECTURE], memtype) + self.mem_by_name[memtype][optional_param] = verify_mask + # Set the hexfile_address + elif optional_param == DeviceMemoryInfoKeys.HEXFILE_ADDRESS: + self._add_hexfile_address(memtype, optional_param) + # Set the hexfile_size + elif optional_param == DeviceMemoryInfoKeys.HEXFILE_SIZE: + self._add_hexfile_size(memtype, optional_param) + # Set the erase_address + elif optional_param == DeviceMemoryInfoKeys.ERASE_ADDRESS: + # By default the erase_address is the same as the address of the memory + address = self.mem_by_name[memtype][DeviceMemoryInfoKeys.ADDRESS] + self.mem_by_name[memtype][optional_param] = address + + def _configure_memory_param(self, memorytype, param): + # Check if it's word or byte oriented data + mul = self.bytes_or_words(param) + # Create a dict for the memory type if it does not exist + if not self.mem_by_name.get(memorytype): + self.mem_by_name[memorytype] = {DeviceMemoryInfoKeys.NAME: memorytype} + # Parse and store parameter + for ptype in self.paramtypes: + if param.startswith("{}_{}".format(memorytype, ptype)): + if mul is not None: + self.mem_by_name[memorytype][ptype] = int(self.device[param] * mul) + else: + self.mem_by_name[memorytype][ptype] = self.device[param] + + def _add_hexfile_address(self, memorytype, paramname): + # Inject hex file addresses for AVR memory areas + if self.device[DeviceInfoKeys.ARCHITECTURE].startswith('avr8'): + if memorytype in self.avr8_hex_file_offsets: + self.mem_by_name[memorytype][paramname] = self.avr8_hex_file_offsets[memorytype] + else: + # The hexfile_address for memory types that doesn't make sense in a hex file like SRAM + # and regular I/O space is defined to an address the other memory types will not reach + self.mem_by_name[memorytype][paramname] = 0xFFFFFF + # All other memory types are mapped 1 to 1 in the hex file + else: + self.mem_by_name[memorytype][paramname] = self.mem_by_name[memorytype][DeviceMemoryInfoKeys.ADDRESS] + + def _add_hexfile_size(self, memorytype, paramname): + if self.device[DeviceInfoKeys.ARCHITECTURE].startswith('PIC16') and memorytype == MemoryNames.EEPROM: + # For PIC16 devices there will be one phantom byte in the hex file for each EEPROM byte, so + # the size of EEPROM in a hex file will be twice the size of the actual EEPROM memory + self.mem_by_name[memorytype][paramname] = self.mem_by_name[memorytype][DeviceMemoryInfoKeys.SIZE] * 2 + else: + self.mem_by_name[memorytype][paramname] = self.mem_by_name[memorytype][DeviceMemoryInfoKeys.SIZE] + + @staticmethod + def _get_verify_mask(architecture, memtype): + # byte oriented memory + mask = [0xFF] + + # PIC16 is word addressed and has 14-bit flash, except EEPROM which is byte oriented + if architecture == 'PIC16' and memtype not in [MemoryNames.EEPROM]: + mask = [0xFF, 0x3F] + + # PIC18 is word addressed and has 16-bit flash, except EEPROM which is byte oriented + elif architecture == 'PIC18' and memtype not in [MemoryNames.EEPROM]: + mask = [0xFF, 0xFF] + + # PIC24 is word addressed and has 24-bit flash, except EEPROM which is word oriented + elif architecture == 'PIC24': + if memtype in [MemoryNames.EEPROM]: + mask = [0xFF, 0xFF] + else: + mask = [0xFF, 0xFF, 0xFF, 0x00] + + return mask + + @staticmethod + def bytes_or_words(address_param): + """ + Return multiplier for address parameter + + The returned multiplier can be used to convert the address parameter to byte address + :param address_param: Address parameter (used as key in device info dict) + :return: Multiplier to convert the address to byte address + """ + if address_param.endswith("_byte") or address_param.endswith("_bytes"): + mul = 1 + elif address_param.endswith("_word") or address_param.endswith("_words"): + mul = 2 + else: + mul = None + return mul + + def memory_info_by_address_range(self, + start, + stop, + address_type=DeviceMemoryInfoKeys.ADDRESS, + size_type=DeviceMemoryInfoKeys.SIZE): + """ + Returns a list of all memories applicable for the address range(start, stop) + + :param start: Start address (byte) + :param stop: End address (byte) + :param address_type: Selects between normal addresses and addresses used in hex files + (address vs hexfile_address) + :param size_type: Selects between normal size and size used in hexfiles (size vs hexfile_size) + """ + # We do not support negative memory ranges + if start > stop: + raise PymcuprogError("Cannot parse reverse memory range {} to {}".format(start, stop)) + + memtypes = [] + + # Loop through all known memory types for this device + for memtype in self.mem_by_name: + address = self.mem_by_name[memtype][address_type] + size = self.mem_by_name[memtype][size_type] + + # Check if any of the addresses between start and stop is within the memory type range + if start < address+size and stop > address: + memtypes.append(self.mem_by_name[memtype]) + return memtypes + + def memory_info_by_address(self, + byte_address, + address_type=DeviceMemoryInfoKeys.ADDRESS, + size_type=DeviceMemoryInfoKeys.SIZE): + """ + Returns information about the memory type for a given byte address + + :param byte_address: Memory address to check + :param address_type: Selects between normal addresses and addresses used in hex files + (ADDRESS vs HEXFILE_ADDRESS) + :param size_type: Selects between normal size and size used in hexfiles (size vs hexfile_size) + """ + memtype = None + for memory in self.mem_by_name: + if self.mem_by_name[memory][address_type] <= byte_address < \ + self.mem_by_name[memory][address_type] + self.mem_by_name[memory][size_type]: + if memtype is not None: + raise PymcuprogError("Duplicate memory area found for byte address '{}'".format(byte_address)) + memtype = self.mem_by_name[memory] + return memtype + + def memory_info_by_name(self, name): + """ + Returns information about the requested memory + """ + memory = self.mem_by_name.get(name) + if not memory: + message = "Memory type '{}' not defined for device '{}'".format(name, self.device[DeviceInfoKeys.NAME]) + raise ValueError(message) + return memory diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/deviceinfokeys.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/deviceinfokeys.py new file mode 100644 index 0000000..f3fba49 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/deviceinfokeys.py @@ -0,0 +1,88 @@ +#pylint: disable=too-few-public-methods +""" +Definitions of keys for device info dictionaries +""" + +class DeviceInfoKeys(object): + """ + Base class with common device info keys + """ + + NAME = 'name' + ARCHITECTURE = 'architecture' + INTERFACE = 'interface' + DEVICE_ID = 'device_id' + + @classmethod + def get_all(cls): + """ + Get a list of all keys + + :return List of all valid keys (baseclass and any subclass keys if run on a subclass) + """ + all_keys = [] + for attribute in dir(cls): + if not attribute.startswith('__') and not callable(getattr(cls, attribute)): + all_keys.append(getattr(cls, attribute)) + + return all_keys + +class DeviceInfoKeysAvr(DeviceInfoKeys): + """ + Keys specific to AVR device info files + """ + + NVMCTRL_BASE = 'nvmctrl_base' + SYSCFG_BASE = 'syscfg_base' + OCD_BASE = 'ocd_base' + PROG_CLOCK_KHZ = 'prog_clock_khz' + ADDRESS_SIZE = 'address_size' + +class DeviceInfoKeysAvr32(DeviceInfoKeys): + """ + Keys specific to 32-bit AVR device info files + """ + + RESET_DOMAINS = 'reset_domains' + +class DeviceInfoKeysPic(DeviceInfoKeys): + """ + Keys specific to PIC device info files + """ + + # This key should have _byte or _word ending in device info files to specify byte or word address + # This ending will be removed by the getdeviceinfo function before returning the device info dictionary + DEFAULT_BULK_ERASE_ADDRESS = 'default_bulk_erase_address' + +class DeviceMemoryInfoKeys(object): + """ + Keys for device memory info dictionary + + These keys are found in the dictionaries returned by DeviceMemoryInfo for each memory type + """ + NAME = 'name' + ADDRESS = 'address' + SIZE = 'size' + PAGE_SIZE = 'page_size' + WRITE_SIZE = 'write_size' + READ_SIZE = 'read_size' + ERASE_ADDRESS = 'erase_address' + CHIPERASE_EFFECT = 'chiperase_effect' + ISOLATED_ERASE = 'isolated_erase' + HEXFILE_ADDRESS = 'hexfile_address' + HEXFILE_SIZE = 'hexfile_size' + VERIFY_MASK = 'verify_mask' + + @classmethod + def get_all(cls): + """ + Get a list of all keys + + :return List of all valid keys (baseclass and any subclass keys if run on a subclass) + """ + all_keys = [] + for attribute in dir(cls): + if not attribute.startswith('__') and not callable(getattr(cls, attribute)): + all_keys.append(getattr(cls, attribute)) + + return all_keys diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/__init__.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1604.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1604.py new file mode 100644 index 0000000..68a92c7 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1604.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny1604 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny1604', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3c00, + 'internal_sram_size_bytes': 0x0400, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x4000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9425, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1606.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1606.py new file mode 100644 index 0000000..b1c73cf --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1606.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny1606 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny1606', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3c00, + 'internal_sram_size_bytes': 0x0400, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x4000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9424, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1607.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1607.py new file mode 100644 index 0000000..c024baa --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1607.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny1607 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny1607', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3c00, + 'internal_sram_size_bytes': 0x0400, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x4000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9423, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1614.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1614.py new file mode 100644 index 0000000..dda3352 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1614.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny1614 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny1614', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3800, + 'internal_sram_size_bytes': 0x0800, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x4000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9422, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1616.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1616.py new file mode 100644 index 0000000..9314fc2 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1616.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny1616 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny1616', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3800, + 'internal_sram_size_bytes': 0x0800, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x4000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9421, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1617.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1617.py new file mode 100644 index 0000000..1d09560 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1617.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny1617 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny1617', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3800, + 'internal_sram_size_bytes': 0x0800, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x4000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9420, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1624.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1624.py new file mode 100644 index 0000000..fa86eee --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1624.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny1624 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny1624', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3800, + 'internal_sram_size_bytes': 0x0800, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x4000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E942A, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1626.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1626.py new file mode 100644 index 0000000..0dc64c9 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1626.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny1626 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny1626', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3800, + 'internal_sram_size_bytes': 0x0800, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x4000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9429, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1627.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1627.py new file mode 100644 index 0000000..8d4849e --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny1627.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny1627 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny1627', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3800, + 'internal_sram_size_bytes': 0x0800, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x4000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9428, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny202.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny202.py new file mode 100644 index 0000000..4705b65 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny202.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny202 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny202', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0040, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3f80, + 'internal_sram_size_bytes': 0x0080, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x0800, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9123, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny204.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny204.py new file mode 100644 index 0000000..13c2007 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny204.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny204 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny204', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0040, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3f80, + 'internal_sram_size_bytes': 0x0080, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x0800, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9122, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny212.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny212.py new file mode 100644 index 0000000..7bd0d69 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny212.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny212 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny212', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0040, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3f80, + 'internal_sram_size_bytes': 0x0080, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x0800, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9121, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny214.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny214.py new file mode 100644 index 0000000..2deb063 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny214.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny214 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny214', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0040, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3f80, + 'internal_sram_size_bytes': 0x0080, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x0800, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9120, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3216.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3216.py new file mode 100644 index 0000000..77b7cd2 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3216.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny3216 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny3216', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x40, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3800, + 'internal_sram_size_bytes': 0x0800, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x80, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x40, + 'user_row_page_size_bytes': 0x40, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x8000, + 'flash_page_size_bytes': 0x80, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x80, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9521, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3217.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3217.py new file mode 100644 index 0000000..3bc3395 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3217.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny3217 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny3217', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x40, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3800, + 'internal_sram_size_bytes': 0x0800, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x80, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x40, + 'user_row_page_size_bytes': 0x40, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x8000, + 'flash_page_size_bytes': 0x80, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x80, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9522, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3224.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3224.py new file mode 100644 index 0000000..76d67ac --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3224.py @@ -0,0 +1,85 @@ + +""" +Required device info for the attiny3224 devices +The following data would normally have been collected from device packs. +But since Microchip hasn't done this, it was deduced from device packs by Spence Konde. +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny3224', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x40, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3400, + 'internal_sram_size_bytes': 0x0C00, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x80, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x40, + 'user_row_page_size_bytes': 0x40, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x8000, + 'flash_page_size_bytes': 0x80, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x80, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9528, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3226.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3226.py new file mode 100644 index 0000000..0ba489d --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3226.py @@ -0,0 +1,85 @@ + +""" +Required device info for the attiny3226 devices +The following data would normally have been collected from device packs. +But since Microchip hasn't done this, it was deduced from device packs by Spence Konde. +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny3226', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x40, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3400, + 'internal_sram_size_bytes': 0x0C00, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x80, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x40, + 'user_row_page_size_bytes': 0x40, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x8000, + 'flash_page_size_bytes': 0x80, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x80, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9527, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3227.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3227.py new file mode 100644 index 0000000..77de9b9 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny3227.py @@ -0,0 +1,85 @@ + +""" +Required device info for the attiny3227 devices +The following data would normally have been collected from device packs. +But since Microchip hasn't done this, it was deduced from device packs by Spence Konde. +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny3227', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0100, + 'eeprom_page_size_bytes': 0x40, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3400, + 'internal_sram_size_bytes': 0x0C00, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x80, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x40, + 'user_row_page_size_bytes': 0x40, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x8000, + 'flash_page_size_bytes': 0x80, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x80, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9526, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny402.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny402.py new file mode 100644 index 0000000..9955161 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny402.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny402 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny402', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3f00, + 'internal_sram_size_bytes': 0x0100, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x1000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9227, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny404.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny404.py new file mode 100644 index 0000000..dd05741 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny404.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny404 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny404', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3f00, + 'internal_sram_size_bytes': 0x0100, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x1000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9226, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny406.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny406.py new file mode 100644 index 0000000..ede10b5 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny406.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny406 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny406', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3f00, + 'internal_sram_size_bytes': 0x0100, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x1000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9225, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny412.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny412.py new file mode 100644 index 0000000..c7631b7 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny412.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny412 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny412', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3f00, + 'internal_sram_size_bytes': 0x0100, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x1000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9223, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny414.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny414.py new file mode 100644 index 0000000..5626bcb --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny414.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny414 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny414', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3f00, + 'internal_sram_size_bytes': 0x0100, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x1000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9222, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny416.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny416.py new file mode 100644 index 0000000..becf143 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny416.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny416 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny416', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3f00, + 'internal_sram_size_bytes': 0x0100, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x1000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9221, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny417.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny417.py new file mode 100644 index 0000000..c4306f2 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny417.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny417 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny417', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3f00, + 'internal_sram_size_bytes': 0x0100, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x1000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9220, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny424.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny424.py new file mode 100644 index 0000000..b98513e --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny424.py @@ -0,0 +1,86 @@ + +""" +Required device info for the attiny424 devices +The following data would normally have been collected from device packs. +But since Microchip hasn't done this, and his users were complaining, +it was deduced from device packs by Spence Konde. +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny424', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3e00, + 'internal_sram_size_bytes': 0x0200, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x1000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E922C, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny426.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny426.py new file mode 100644 index 0000000..20cefa3 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny426.py @@ -0,0 +1,86 @@ + +""" +Required device info for the attiny426 devices +The following data would normally have been collected from device packs. +But since Microchip hasn't done this, and his users were complaining, +it was deduced from device packs by Spence Konde. +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny426', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3e00, + 'internal_sram_size_bytes': 0x0200, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x1000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E922B, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny427.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny427.py new file mode 100644 index 0000000..348830c --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny427.py @@ -0,0 +1,86 @@ + +""" +Required device info for the attiny427 devices +The following data would normally have been collected from device packs. +But since Microchip hasn't done this, and his users were complaining, +it was deduced from device packs by Spence Konde. +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny427', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3e00, + 'internal_sram_size_bytes': 0x0200, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x1000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E922A, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny804.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny804.py new file mode 100644 index 0000000..833a221 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny804.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny804 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny804', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3e00, + 'internal_sram_size_bytes': 0x0200, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x2000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9325, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny806.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny806.py new file mode 100644 index 0000000..07d22dd --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny806.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny806 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny806', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3e00, + 'internal_sram_size_bytes': 0x0200, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x2000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9324, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny807.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny807.py new file mode 100644 index 0000000..584da93 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny807.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny807 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny807', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3e00, + 'internal_sram_size_bytes': 0x0200, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x2000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9323, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny814.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny814.py new file mode 100644 index 0000000..e36a6c5 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny814.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny814 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny814', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3e00, + 'internal_sram_size_bytes': 0x0200, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x2000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9322, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny816.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny816.py new file mode 100644 index 0000000..8db56f4 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny816.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny816 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny816', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3e00, + 'internal_sram_size_bytes': 0x0200, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x2000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9321, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny817.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny817.py new file mode 100644 index 0000000..5c67ef5 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny817.py @@ -0,0 +1,84 @@ + +""" +Required device info for the attiny817 devices +The following data was collected from device pack Microchip.ATtiny_DFP 2.4.111 +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny817', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3e00, + 'internal_sram_size_bytes': 0x0200, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x2000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9320, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny824.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny824.py new file mode 100644 index 0000000..7aa50e4 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny824.py @@ -0,0 +1,86 @@ + +""" +Required device info for the attiny824 devices +The following data would normally have been collected from device packs. +But since Microchip hasn't done this, and his users were complaining, +it was deduced from device packs by Spence Konde. +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny824', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3c00, + 'internal_sram_size_bytes': 0x0400, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x2000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9329, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny826.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny826.py new file mode 100644 index 0000000..d8c0da8 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny826.py @@ -0,0 +1,86 @@ + +""" +Required device info for the attiny826 devices +The following data would normally have been collected from device packs. +But since Microchip hasn't done this, and his users were complaining, +it was deduced from device packs by Spence Konde. +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny826', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3c00, + 'internal_sram_size_bytes': 0x0400, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x2000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9328, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny827.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny827.py new file mode 100644 index 0000000..83a8264 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/devices/attiny827.py @@ -0,0 +1,86 @@ + +""" +Required device info for the attiny827 devices +The following data would normally have been collected from device packs. +But since Microchip hasn't done this, and his users were complaining, +it was deduced from device packs by Spence Konde. +""" + +from pymcuprog.deviceinfo.eraseflags import ChiperaseEffect + +DEVICE_INFO = { + 'name': 'attiny827', + 'architecture': 'avr8x', + + # eeprom + 'eeprom_address_byte': 0x00001400, + 'eeprom_size_bytes': 0x0080, + 'eeprom_page_size_bytes': 0x20, + 'eeprom_read_size_bytes': 1, + 'eeprom_write_size_bytes': 1, + 'eeprom_chiperase_effect': ChiperaseEffect.CONDITIONALLY_ERASED_AVR, + 'eeprom_isolated_erase': True, + + # fuses + 'fuses_address_byte': 0x00001280, + 'fuses_size_bytes': 0xA, + 'fuses_page_size_bytes': 1, + 'fuses_read_size_bytes': 1, + 'fuses_write_size_bytes': 1, + 'fuses_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'fuses_isolated_erase': False, + + # internal_sram + 'internal_sram_address_byte': 0x3c00, + 'internal_sram_size_bytes': 0x0400, + 'internal_sram_page_size_bytes': 1, + 'internal_sram_read_size_bytes': 1, + 'internal_sram_write_size_bytes': 1, + 'internal_sram_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'internal_sram_isolated_erase': False, + + # lockbits + 'lockbits_address_byte': 0x0000128A, + 'lockbits_size_bytes': 0x1, + 'lockbits_page_size_bytes': 1, + 'lockbits_read_size_bytes': 1, + 'lockbits_write_size_bytes': 1, + 'lockbits_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'lockbits_isolated_erase': False, + + # signatures + 'signatures_address_byte': 0x00001100, + 'signatures_size_bytes': 0x3, + 'signatures_page_size_bytes': 0x40, + 'signatures_read_size_bytes': 1, + 'signatures_write_size_bytes': 0, + 'signatures_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'signatures_isolated_erase': False, + + # user_row + 'user_row_address_byte': 0x00001300, + 'user_row_size_bytes': 0x20, + 'user_row_page_size_bytes': 0x20, + 'user_row_read_size_bytes': 1, + 'user_row_write_size_bytes': 1, + 'user_row_chiperase_effect': ChiperaseEffect.NOT_ERASED, + 'user_row_isolated_erase': True, + + # flash + 'flash_address_byte': 0x00008000, + 'flash_size_bytes': 0x2000, + 'flash_page_size_bytes': 0x40, + 'flash_read_size_bytes': 2, + 'flash_write_size_bytes': 0x40, + 'flash_chiperase_effect': ChiperaseEffect.ALWAYS_ERASED, + 'flash_isolated_erase': True, + + # Some extra AVR specific fields + 'nvmctrl_base': 0x00001000, + 'syscfg_base': 0x00000F00, + 'ocd_base': 0x00000F80, + 'prog_clock_khz': 900, + 'interface': 'UPDI', + 'address_size': '16-bit', + 'device_id': 0x1E9327, +} diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/eraseflags.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/eraseflags.py new file mode 100644 index 0000000..9e37e75 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/eraseflags.py @@ -0,0 +1,25 @@ +""" +Definitions of erase related flags for the device models +""" +import inspect + +from pymcuprog.utils import enum + +# Flag used to specify if a memory type will be erased by a chip erase (AVR) or the widest/default bulk erase (PIC) +ChiperaseEffect = enum( + ALWAYS_ERASED='always erased', + CONDITIONALLY_ERASED_AVR='conditionally erased (depending upon EESAVE fuse setting)', + CONDITIONALLY_ERASED_PIC='conditionally erased (depending upon Code Protect configuration bit(s) settings)', + NOT_ERASED='not erased') + +def get_list_of_chiperase_effects(): + """Return a list of all ChiperaseEffect values""" + chiperase_effect_attributes = inspect.getmembers(ChiperaseEffect, lambda a: not inspect.isroutine(a)) + chiperase_effect_values = [] + for attribute in chiperase_effect_attributes: + # Builtin routines always starts and ends with double underscore (__) + if not (attribute[0].startswith('__') and attribute[0].endswith('__')): + # Only the attribute values are returned + chiperase_effect_values.append(attribute[1]) + + return chiperase_effect_values diff --git a/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/memorynames.py b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/memorynames.py new file mode 100644 index 0000000..68e21ca --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/deviceinfo/memorynames.py @@ -0,0 +1,41 @@ +#pylint: disable=too-few-public-methods +""" +Memory name definitions +""" + +class MemoryNameAliases(object): + """ + Memory names that are actually not real memories but an alias for several memories + """ + ALL = 'all' + +class MemoryNames(object): + """ + Memory names corresponding to target device memories + """ + # Real memories + FLASH = 'flash' + CONFIG_WORD = 'config_words' + USER_ID = 'user_id' + USER_ROW = 'user_row' + EEPROM = 'eeprom' + FUSES = 'fuses' + CALIBRATION_ROW = 'calibration_row' + ICD = 'icd' + LOCKBITS = 'lockbits' + SIGNATURES = 'signatures' + INTERNAL_SRAM = 'internal_sram' + + @classmethod + def get_all(cls): + """ + Get a list of all memories representing actual device memories + + :return List of all memory names representing actual device memories + """ + all_memories = [] + for attribute in dir(cls): + if not attribute.startswith('__') and not callable(getattr(cls, attribute)): + all_memories.append(getattr(cls, attribute)) + + return all_memories diff --git a/software/tools/pymcuprog/libs/pymcuprog/hexfileutils.py b/software/tools/pymcuprog/libs/pymcuprog/hexfileutils.py new file mode 100644 index 0000000..82ade4e --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/hexfileutils.py @@ -0,0 +1,181 @@ +""" +Module providing read and write functionality towards hex files with data intended for target device memories +""" +import copy +import os +from array import array +from collections import namedtuple +from intelhex import IntelHex +try: + from pathlib import Path +except ImportError: + from pathlib2 import Path # python 2 backport + +from .deviceinfo.deviceinfokeys import DeviceMemoryInfoKeys, DeviceInfoKeys + +def write_memories_to_hex(filename, memory_segments): + """ + Write a collection of memory segments to a hex file + + Each segment will be written from relative offset 0 (i.e. start of each memory segment) + :param filename: Name/path of hex file to write to + :param memory_segments: list of namedtuples with two fields: data and memory_info. data contains a + byte array of raw data bytes and memory_info is a dictionary with memory information as defined + in deviceinfo.deviceinfo.DeviceMemoryInfo. + """ + hexfile = IntelHex() + + for memory_segment in memory_segments: + _add_data_to_hex(hexfile, memory_segment.data, memory_segment.memory_info) + + _write_hex_to_file(hexfile, filename) + +def write_memory_to_hex(filename, memory_segment, offset): + """ + Write one memory segment to a hex file with data starting at relative offset given by offset parameter. + + :param filename: Name/path of hex file to write to + :param memory_segment: namedtuple with two fields: data and memory_info. data contains a byte array + of raw data bytes and memory_info is a dictionary with memory information as defined in + deviceinfo.deviceinfo.DeviceMemoryInfo). + :param offset: Relative offset for the data within the memory segment + """ + hexfile = IntelHex() + + _add_data_to_hex(hexfile, memory_segment.data, memory_segment.memory_info, offset) + + _write_hex_to_file(hexfile, filename) + +def read_memories_from_hex(filename, device_memory_info): + """ + Read the content of a hexfile + + :param filename: Name/path of hex file to read from + :param device_memory_info: DeviceMemoryInfo instance for the device the hex file is intended for + :returns: list of namedtuples with three fields: data, offset and memory_info. data contains a byte array + of raw data bytes, offset is the start address within the memory the data starts at and memory_info + is a dictionary with the memory info as defined in pymcuprog.deviceinfo.deviceinfo + """ + hexfile = IntelHex() + hexfile.fromfile(filename, format='hex') + + memory_segments = [] + for segment in hexfile.segments(): + start = segment[0] + stop = segment[1] + + subsegment_start = start + subsegment_stop = start + while subsegment_stop < stop: + current_memory_info = device_memory_info.memory_info_by_address(subsegment_start, + DeviceMemoryInfoKeys.HEXFILE_ADDRESS, + DeviceMemoryInfoKeys.HEXFILE_SIZE) + + if current_memory_info is None: + raise IndexError( + "Hexfile contains data at hex address 0x{:X} which is outside any memory".format(subsegment_start)) + + current_hexfile_address = current_memory_info[DeviceMemoryInfoKeys.HEXFILE_ADDRESS] + current_hexfile_size = current_memory_info[DeviceMemoryInfoKeys.HEXFILE_SIZE] + subsegment_stop = current_hexfile_address + current_hexfile_size + if stop < subsegment_stop: + # Reached end of segment + subsegment_stop = stop + memory_tuple = namedtuple('MemorySegment', 'data offset memory_info') + + data = hexfile.tobinarray(start=subsegment_start, end=subsegment_stop - 1) + current_size = current_memory_info[DeviceMemoryInfoKeys.SIZE] + if current_hexfile_size == current_size*2: + # There are phantom bytes in the hexfile (PIC16 EEPROM), so every 2nd byte should be removed + data = remove_phantom_bytes(data) + + memory_tuple.data = data + memory_tuple.memory_info = current_memory_info + memory_tuple.offset = subsegment_start - current_hexfile_address + + memory_segments.append(copy.deepcopy(memory_tuple)) + + subsegment_start = subsegment_stop + + return memory_segments + + +def verify_flash_from_hex(hex_filename, backend, max_read_chunk=None): + """ + Verify the contents of flash against a hex-file + + :param filename: Name/path of hex-file to verify + :param device_memory_info: DeviceMemoryInfo instance for the device the hex file should be verified against + :param backend: Reference to the Backend class of pymcuprog + :returns: Boolean value indicating success or failure of the operation + """ + hexfile = IntelHex(hex_filename) + segments = hexfile.segments() + + for i in range(len(segments)): + segment_data = [] + for j in range(segments[i][1]-segments[i][0]): + segment_data.append(hexfile[segments[i][0]+j]) + + verify_status = backend.verify_memory(segment_data, 'flash', segments[i][0], max_read_chunk=max_read_chunk) + if verify_status is False: + return False + return True + + +def remove_phantom_bytes(data): + """ + Remove every 2nd byte from the data + """ + data_stripped = [] + for index in range(0, len(data), 2): + data_stripped.append(data[index]) + # Make a bin array out of the data list to be consistent with the data format of + # the data fetched directly from the hex file + data_stripped_binarray = array('B') + data_stripped_binarray.fromlist(data_stripped) + return data_stripped_binarray + +def _add_data_to_hex(intelhex, data, memory_info, offset=0): + """ + Add given data starting at relative index offset to IntelHex instance intelhex + + :param intelhex: IntelHex object + :param data: raw data bytes + :param memory_info: memory info as provided by pymcuprog.deviceinfo.deviceinfo + :param offset: relative offset within the memory + """ + hexfile_address_key = DeviceMemoryInfoKeys.HEXFILE_ADDRESS + hexfile_size_key = DeviceMemoryInfoKeys.HEXFILE_SIZE + size_key = DeviceMemoryInfoKeys.SIZE + name = memory_info[DeviceInfoKeys.NAME] + + if offset+len(data) > memory_info[hexfile_size_key]: + raise IndexError( + "Attempting to write outside boundary of {} memory ({} bytes starting at offset {})".format(name, + len(data), + offset)) + + hex_offset = memory_info[hexfile_address_key] + offset + if memory_info[hexfile_size_key] == memory_info[size_key]*2: + # Hex file should contain one phantom byte per data byte in the hex file (PIC16 EEPROM) + for i, dat in enumerate(data): + intelhex[i*2 + hex_offset] = data[i] + intelhex[i*2 + 1 + hex_offset] = 0 & 0xFF + else: + for i, dat in enumerate(data): + intelhex[i + hex_offset] = dat + +def _write_hex_to_file(intelhex, filename): + """ + Write intelhex object to file. + + Directories will be created if path does not exist + :param intelhex: IntelHex instance + :param filename: Name/path to write intelhex object to + """ + directory = os.path.dirname(filename) + if directory != '' and not os.path.exists(directory): + Path(directory).mkdir(exist_ok=True, parents=True) + + intelhex.write_hex_file(filename) diff --git a/software/tools/pymcuprog/libs/pymcuprog/logging.yaml b/software/tools/pymcuprog/libs/pymcuprog/logging.yaml new file mode 100644 index 0000000..5127ade --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/logging.yaml @@ -0,0 +1,57 @@ +version: 1 +disable_existing_loggers: False +formatters: + timestamped: + format: "%(asctime)s - %(name)s - %(levelname)s - %(message)s" + detailed: + format: "%(name)s - %(levelname)s - %(message)s" + simple: + format: "%(message)s" + +handlers: + # Logging to the console is default to WARNING with detailed output: + console: + class: logging.StreamHandler + level: WARNING + formatter: detailed + stream: ext://sys.stdout + + # Logging debug output to file + # Handler disabled by default - for reference only + debug_file_handler: + class: logging.FileHandler + level: DEBUG + formatter: timestamped + # File path will be user log directory for this application + filename: debug.log + encoding: utf8 + + # Logging errors to file + # Handler disabled by default - for reference only + error_file_handler: + class: logging.handlers.RotatingFileHandler + level: ERROR + formatter: timestamped + # File path will be user log directory for this application + filename: errors.log + maxBytes: 10485760 # 10MB + backupCount: 20 + encoding: utf8 + +loggers: + # pyedbglib library should be kept to critical errors to console only + pyedbglib: + level: ERROR + handlers: [console] + propagate: no + +root: + # Default level is warning + # this is increased with -v in CLI usage + level: WARNING + # Default handlers is console only + handlers: [console] + # Add debug_file_handler for debug output to file + # Add error_file_handler for error output to file + # See configuration in handlers section above + #handlers: [console, debug_file_handler, error_file_handler] diff --git a/software/tools/pymcuprog/libs/pymcuprog/nvm.py b/software/tools/pymcuprog/libs/pymcuprog/nvm.py new file mode 100644 index 0000000..75bbbba --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/nvm.py @@ -0,0 +1,130 @@ +""" +NVM layer protocols +""" +# Python 3 compatibility for Python 2 +from __future__ import print_function +from logging import getLogger + +from .deviceinfo.deviceinfokeys import DeviceInfoKeys + +def get_nvm_access_provider(transport, device_info, interface="", packpath=None, frequency=None, options=""): + """ + Returns an NVM provider with the requested properties + + :param transport: transport layer object + :param device_info: device info dict + :param interface: physical interface for NVM + :param packpath: path to pack + :param frequency: interface clock + :param options: special options + :return: NVM access object + """ + # Although it is considered best practice to have imports at top level, in this case it makes sense to have the + # imports on the function level as in most cases only one import will be used. Having all imports at the top + # level will then be a waste of resources. + #pylint: disable=import-outside-toplevel + # There will be cyclic imports since the modules imported below containing NVM Access providers will import + # from the current module since all NVM Access providers inherits from the NVM Access provider base classes + # defined in the current module, but this should be ok since the imports below are late. + #pylint: disable=cyclic-import + accessprovider = None + architecture = device_info[DeviceInfoKeys.ARCHITECTURE].lower() + if DeviceInfoKeys.INTERFACE in device_info: + interface = device_info[DeviceInfoKeys.INTERFACE].lower() + + if architecture in ['pic16', 'pic18', 'pic24']: + from .nvmpic import NvmAccessProviderCmsisDapPic + accessprovider = NvmAccessProviderCmsisDapPic(transport, device_info, packpath, options=options) + elif architecture == 'avr8x': + if isinstance(transport, str): + if interface == 'updi': + from .nvmserialupdi import NvmAccessProviderSerial + accessprovider = NvmAccessProviderSerial(transport, device_info, baud=frequency) + elif interface == 'updi': + from .nvmupdi import NvmAccessProviderCmsisDapUpdi + accessprovider = NvmAccessProviderCmsisDapUpdi(transport, device_info=device_info, + frequency=frequency, options=options) + elif architecture == 'avr8': + if interface == 'isp': + if interface == "debugwire": + from .nvmdebugwire import NvmAccessProviderCmsisDapDebugwire + accessprovider = NvmAccessProviderCmsisDapDebugwire(transport, device_info) + else: + from .nvmspi import NvmAccessProviderCmsisDapSpi + accessprovider = NvmAccessProviderCmsisDapSpi(transport, device_info) + elif architecture == 'cortex-m0plus': + from .nvmmzeroplus import NvmAccessProviderCmsisDapMZeroPlus + accessprovider = NvmAccessProviderCmsisDapMZeroPlus(transport, device_info, frequency) + elif architecture == 'avr32': + from .nvmavr32 import NvmAccessProviderCmsisDapAvr32 + accessprovider = NvmAccessProviderCmsisDapAvr32(transport, device_info) + + return accessprovider + +class NvmAccessProvider: + """ + Wrapper for device info + """ + + def __init__(self, device_info): + self.device_info = device_info + self.logger = getLogger(__name__) + + def _log_incomplete_stack(self, device_stack): + """ + Used to tell the user this device stack is not completed yet + + :param device_stack: User friendly name of target stack + """ + self.logger.warning("") + self.logger.warning("%s stack is in Alpha state", device_stack) + self.logger.warning("Expect some features to be missing") + self.logger.warning("") + + def start(self, user_interaction_callback=None): + """ + Start (activate) session + + :param user_interaction_callback: Callback to be called when user interaction is required, + for example when doing UPDI high-voltage activation with user target power toggle. + This function could ask the user to toggle power and halt execution waiting for the user + to respond (this is default behavior if the callback is None), or if the user is another + script it could toggle power automatically and then return. + """ + #pylint: disable=unused-argument + self.logger.info("No specific initializer for this provider") + + def stop(self): + """ + Stop (deactivate) session + """ + self.logger.info("No specific de-initializer for this provider") + + def hold_in_reset(self): + """ + Hold target in reset + """ + self.logger.info("hold_in_reset not implemented for this provider") + + def release_from_reset(self): + """ + Release target from reset + """ + self.logger.info("release_from_reset not implemented for this provider") + +class NvmAccessProviderCmsisDapTool(NvmAccessProvider): + """ + General CMSIS-DAP Tool + """ + + def __init__(self, device_info): + NvmAccessProvider.__init__(self, device_info) + + +class NvmAccessProviderCmsisDapAvr(NvmAccessProviderCmsisDapTool): + """ + AVR CMSIS DAP Tool + """ + + def __init__(self, device_info): + NvmAccessProviderCmsisDapTool.__init__(self, device_info) diff --git a/software/tools/pymcuprog/libs/pymcuprog/nvmserialupdi.py b/software/tools/pymcuprog/libs/pymcuprog/nvmserialupdi.py new file mode 100644 index 0000000..d4274d1 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/nvmserialupdi.py @@ -0,0 +1,248 @@ +""" +pyupdi-esque NVM implementation +""" +import binascii + +from pyedbglib.util import binary + +from . import utils +from .nvm import NvmAccessProvider +from .deviceinfo import deviceinfo +from .deviceinfo.deviceinfokeys import DeviceInfoKeysAvr, DeviceMemoryInfoKeys +from .deviceinfo.memorynames import MemoryNames +from .serialupdi.application import UpdiApplication + +import math + +from . import progress_bar + +# This is a data class so it should not need any methods but will have many instance variables +# pylint: disable=too-many-instance-attributes,too-few-public-methods +class Dut: + """ + Create a device object for UpdiApplication + """ + + def __init__(self, dev_info): + # Parse the device info for memory descriptions + device_memory_info = deviceinfo.DeviceMemoryInfo(dev_info) + + flash_info = device_memory_info.memory_info_by_name(MemoryNames.FLASH) + self.flash_start = flash_info[DeviceMemoryInfoKeys.ADDRESS] + self.flash_size = flash_info[DeviceMemoryInfoKeys.SIZE] + self.flash_pagesize = flash_info[DeviceMemoryInfoKeys.PAGE_SIZE] + self.syscfg_address = dev_info[DeviceInfoKeysAvr.SYSCFG_BASE] + self.nvmctrl_address = dev_info[DeviceInfoKeysAvr.NVMCTRL_BASE] + address_key = DeviceMemoryInfoKeys.ADDRESS + self.sigrow_address = device_memory_info.memory_info_by_name(MemoryNames.SIGNATURES)[address_key] + self.fuses_address = device_memory_info.memory_info_by_name(MemoryNames.FUSES)[address_key] + self.userrow_address = device_memory_info.memory_info_by_name(MemoryNames.USER_ROW)[address_key] + + +class NvmAccessProviderSerial(NvmAccessProvider): + """ + NVM Access the Python AVR way + """ + + def __init__(self, port, device_info, baud): + self.avr = None + NvmAccessProvider.__init__(self, device_info) + if not baud: + baud = 115200 + self.dut = Dut(device_info) + self.avr = UpdiApplication(port, baud, self.dut) + # Read the device info to set up the UPDI stack variant + + self.avr.read_device_info() + try: + self.avr.enter_progmode() + except IOError as inst: + self.logger.error("Device is locked.\nError:\n%s", inst) + + def read_device_id(self): + """ + Read and display (log) the device info + + :returns: Device ID raw bytes (Little endian) + """ + self.avr.read_device_info() + + signatures_base = self.dut.sigrow_address + + # Read 3 bytes + sig = self.avr.read_data(signatures_base, 3) + device_id_read = binary.unpack_be24(sig) + self.logger.info("Device ID: '%06X'", device_id_read) + if not self.device_info.get(DeviceInfoKeysAvr.DEVICE_ID) == device_id_read: + self.logger.warning("ID read ('%06X') does not match expected device id! ('%06X')", device_id_read, + self.device_info.get(DeviceInfoKeysAvr.DEVICE_ID)) + raise ValueError("Device ID does not match") + revision = self.avr.read_data(self.device_info.get(DeviceInfoKeysAvr.SYSCFG_BASE) + 1, 1) + self.logger.info("Device revision: '%s'", chr(revision[0] + ord('A'))) + serial = self.avr.read_data(signatures_base + 3, 10) + self.logger.info("Device serial number: '%s'", binascii.hexlify(serial)) + + # Return the raw signature bytes, but swap the endianness as target sends ID as Big endian + return bytearray([sig[2], sig[1], sig[0]]) + + def erase(self, memory_info=None, address=None): + """ + Do a chip erase of the device + """ + _dummy = memory_info + _dummy = address + try: + self.avr.nvm.chip_erase() + except IOError as inst: + self.logger.error("Device is locked. Performing unlock with chip erase.\nError: ('%s')", inst) + self.avr.unlock() + + def write(self, memory_info, offset, data, blocksize=0, pagewrite_delay=0): + """ + Write the memory with data + + :param memory_info: dictionary for the memory as provided by the DeviceMemoryInfo class + :param offset: relative offset within the memory type + :param data: the data to program + :return: None + """ + # Make sure the data is aligned to a memory page + data_aligned, offset_aligned = utils.pagealign(data, + offset, + memory_info[DeviceMemoryInfoKeys.PAGE_SIZE], + memory_info[DeviceMemoryInfoKeys.WRITE_SIZE]) + memtype_string = memory_info[DeviceMemoryInfoKeys.NAME] + + offset_aligned += memory_info[DeviceMemoryInfoKeys.ADDRESS] + + if memtype_string in (MemoryNames.FLASH, MemoryNames.EEPROM, MemoryNames.FUSES): + write_chunk_size = memory_info[DeviceMemoryInfoKeys.PAGE_SIZE] + else: + write_chunk_size = len(data_aligned) + + n_chunk = math.ceil(len(data_aligned)/write_chunk_size) + bar = progress_bar.ProgressBar(n_chunk, hide=n_chunk == 1) + while data_aligned: + if len(data_aligned) < write_chunk_size: + write_chunk_size = len(data_aligned) + chunk = data_aligned[0:write_chunk_size] + self.logger.debug("Writing %d bytes to address 0x%06X", write_chunk_size, offset_aligned) + if memtype_string == MemoryNames.FUSES: + self.avr.nvm.write_fuse(offset_aligned, chunk) + elif memtype_string == MemoryNames.EEPROM: + self.avr.nvm.write_eeprom(offset_aligned, chunk) + else: + # Spence Konde, 5/8/2021: + # As far as I can tell, this is the only point where, we're writing a hex file, we know both the page size + # AND are in the path of blocksize parameter. So - if its 0 or not given we should "do the old behavior", then + # blocksize=2. The special value -1 tells us to have it write blocks equal to chunk/page size. Any other number + # will be used as blocksize. Negative numbers beyond -1 were replaced with zero way at the beginning, as they would + # result in crazy behavior and make everything fall over. + # megaTinyCore and DxCore will always pass -1 as blocksize unless we find something where that doesn't work. + # + # Also, we are now finally in the section of the code specific to serialupdi. Up until we get here, 0 is the default + # and if that's what we got, we omit it when making other calls, because there are almost certainly calls elsewhere + # that. Now that we are here, the default value is 2 (ie, one word at a time) but that won'ty be something we see often. + # + # It strikes me that here is *ALSO* where we know whether we are on the first, a middle, or the last page. Say we + # kept count of how many pages had been written already - if it was 0 and nChunk > 1, we would pass an argument that says + # This is the first page we are writing, do all that stuff we need to do at the start of a bulk write. + # if it was nChunk - 1, we would send a different value for that argumennt, saying it was the last one of a bulk write + # so it should do the stuff to end the bulk write mode. And otherwise, it gets a third value that gets treated as + # a signal to omit all of those. for the streamlined write protocol, which could improve performance by another 22-45% + # If you agree, we should do that. + # What we currently do is grossly inefficient, because (due to the penalty for small packets) we spend half of our time + # for every page: Setting the address pointer (only need to do this at the beginning - when reading second and subsequent pages + # the previous writes left the pointer at exactly the location we then set it to.). Setting NVM cmd to FLWR - only needs to be done + # at the start of a bulk write, assuming we also stop setting NVM command to NOOP after every page. Setting RSD - if we + # do all I'm talking about here, we can set it at start of bulk write. And we can juyst check for for NVM errors before + # the first and after the last page, not before and after every page. My models suggest this should improve performance + # by 22% at 115200 baud, and 44% and 345600 baud (which is 1.5x 230400 baud - and happens to be about the fastest you can + # do a bulk write that is consistent with the datasheet flash write time spec. + # + # See also my comment below in read() - these two places are where we can achieve the last noticable performance leaps. + # -Spence + bulk = 1 + if n_chunk == 1: + #if omly one chunk, it is NOT a bulk write. + bulk = 0 + elif len(data_aligned) <= write_chunk_size: + # We are on the last page of a bulk write + bulk = 2 + if blocksize == 0: + self.avr.nvm.write_flash(offset_aligned, chunk, pagewrite_delay=pagewrite_delay) + else: + self.avr.nvm.write_flash(offset_aligned, chunk, blocksize=blocksize, bulkwrite = bulk, pagewrite_delay=pagewrite_delay) + offset_aligned += write_chunk_size + data_aligned = data_aligned[write_chunk_size:] + bar.step() + + def read(self, memory_info, offset, numbytes, max_read_chunk=None): + """ + Read the memory in chunks + + :param memory_info: dictionary for the memory as provided by the DeviceMemoryInfo class + :param offset: relative offset in the memory type + :param numbytes: number of bytes to read + :param max_read_chunk: <=256 + :return: array of bytes read + """ + offset += memory_info[DeviceMemoryInfoKeys.ADDRESS] + + # if reading from flash, we want to read words if it would reduce number of USB serial transactions. + # this function is called for everything though, so be careful not to use it for memories read one byte at a time, like fuses + data = [] + + if max_read_chunk is None: + read_chunk_size = 0x100 + else: + read_chunk_size = max_read_chunk + + use_word_access = False + memtype_string = memory_info[DeviceMemoryInfoKeys.NAME] + if memtype_string in (MemoryNames.FLASH): + if numbytes > 0x100 and max_read_chunk is None: + use_word_access = True + read_chunk_size = 0x200 + + # SACRIFICES SPEED FOR COMPATIBILITY - above line should happen whenever --limitreadsize=1 command line parameter is not passed, so we can only turn it on for specific tools -> programmer options that have this weird limitation. I couldn't propagate it through this mess! + n_chunk = math.ceil(numbytes/read_chunk_size) + bar = progress_bar.ProgressBar(n_chunk, hide=n_chunk == 1) + + while numbytes: + if numbytes < read_chunk_size: + read_chunk_size = numbytes + self.logger.debug("Reading %d bytes from address 0x%06X", read_chunk_size, offset) + if use_word_access: + data += self.avr.read_data_words(offset, read_chunk_size>> 1) + else: + data += self.avr.read_data(offset, read_chunk_size) + offset += read_chunk_size + numbytes -= read_chunk_size + bar.step() + + return data + + def hold_in_reset(self): + """ + Hold device in reset + """ + # For UPDI parts it is sufficient to enter programming mode to hold the target in reset + # Since the start function is a prerequisite to all functions in this file it can be + # assumed that programming mode already has been entered + return + + def release_from_reset(self): + """ + Release device from reset + """ + # Entering programming mode on UPDI parts will hold the device in reset. So to release + # the reset the programming mode must be left. + self.avr.leave_progmode() + + def stop(self): + """ + Stop the debugging session + """ + if self.avr is not None: + self.avr.leave_progmode() diff --git a/software/tools/pymcuprog/libs/pymcuprog/programmer.py b/software/tools/pymcuprog/libs/pymcuprog/programmer.py new file mode 100644 index 0000000..f0cc276 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/programmer.py @@ -0,0 +1,314 @@ +""" +Python MCU programmer +""" +import copy +from logging import getLogger +from collections import namedtuple + +# Device data +from .deviceinfo import deviceinfo + +from . import utils +from .pymcuprog_errors import PymcuprogNotSupportedError, PymcuprogSessionConfigError +from .pymcuprog_errors import PymcuprogError +from .nvm import get_nvm_access_provider +from .deviceinfo.memorynames import MemoryNameAliases +from .deviceinfo.deviceinfokeys import DeviceInfoKeysPic, DeviceMemoryInfoKeys + +DEFAULT_BULK_ERASE_ADDRESS_KEY = DeviceInfoKeysPic.DEFAULT_BULK_ERASE_ADDRESS + +class Programmer: + """ + Main programmer class. + """ + + def __init__(self, transport): + # Hook onto logger + self.logger = getLogger(__name__) + # Use transport passed in + self.transport = transport + # Clear device model and mem info objects + self.device_info = None + self.device_model = None + self.device_memory_info = None + self.options = {} + + def set_options(self, options): + """ + Stores options + + :param options: options to store + """ + self.options = options + + def load_device(self, device_name): + """ + Loads the device from the device folder + + :param device_name: + :raises: PymcuprogNotSupportedError if device is not supported + """ + # Try to instantiate device info. This will check if there is device support at all + try: + self.logger.info("Setting up programming session for '%s'", device_name) + self.device_info = deviceinfo.getdeviceinfo(device_name) + except ImportError as err: + raise PymcuprogNotSupportedError("Unable to find device info: {}".format(err)) + + # Now build a memory model for this device + self.device_memory_info = deviceinfo.DeviceMemoryInfo(self.device_info) + + def setup_device(self, interface=None, packpath=None, clk=None): + """ + Sets up a programming session with a given device + + :param device_name: device to program + :param interface: interface to use + :param packpath: path to packs to use (for PIC) + :param clk: clock frequency + + :raises SerialException if unable to connect to serial port (if using serial port instead of physical debugger) + """ + # Device must be loaded first + if self.device_info is None: + raise PymcuprogError("Device must be loaded before setup!") + + # Find a NVM provider that matches the device and transport + try: + self.device_model = get_nvm_access_provider(self.transport, + self.device_info, + interface=interface, + packpath=packpath, + frequency=clk, + options=self.options) + except ImportError: + raise PymcuprogSessionConfigError( + "Unable to setup stack using the given packpath: '{0:s}'".format( + packpath or "None")) + if self.device_model is None: + raise PymcuprogSessionConfigError("Unable to setup stack, check session config parameters") + + def start(self, user_interaction_callback=None): + """ + Starts the programming session with the device model + + :param user_interaction_callback: Callback to be called when user interaction is required, + for example when doing UPDI high-voltage activation with user target power toggle. + This function could ask the user to toggle power and halt execution waiting for the user + to respond (this is default behavior if the callback is None), or if the user is another + script it could toggle power automatically and then return. + """ + self.device_model.start(user_interaction_callback=user_interaction_callback) + + def stop(self): + """ + Stops the programming session with the device model + """ + return self.device_model.stop() + + def get_device_model(self): + """ + Exposes the device model in use to clients + """ + return self.device_model + + def get_device_memory_info(self): + """ + Exposes the device memory model to clients + """ + return self.device_memory_info + + # Device model API functions + + def read_device_id(self): + """ + Read the device ID + + :returns: Device ID raw bytes (Little endian) + """ + self.logger.info("Reading device ID...") + return self.device_model.read_device_id() + + def erase(self, memory_name, address): + """ + Erase the device + + :param memory_name: memory region to erase as defined in deviceinfo.memorynames + MemoryNameAliases.ALL will run the widest erase (e.g. chip erase on AVR or the widest bulk erase on PIC) + :param address: address to erase + """ + self.logger.info("Erase...") + if memory_name == MemoryNameAliases.ALL: + # Run default erase which is the widest erase + memory_info = None + if DEFAULT_BULK_ERASE_ADDRESS_KEY in self.device_info: + address = self.device_info[DEFAULT_BULK_ERASE_ADDRESS_KEY] + else: + address = None + else: + memory_info = self.device_memory_info.memory_info_by_name(memory_name) + self.device_model.erase(memory_info=memory_info, address=address) + + def write_memory(self, data, memory_name, offset=0, blocksize=0, pagewrite_delay=0): + """ + Write memory on the device + + :param data: data to write + :param memory_name: memory type to write + :param offset: offset/address within that region to write + :return: boolean status + + :raises: ValueError if trying to write outside the specified memory + :raises: ValueError if the specified memory is not defined for the target device + :raises: PymcuprogNotSupportedError if memory can't be written + """ + self.logger.info("Write...") + + # Just some sanity checking of inputs + if offset < 0: + raise ValueError("Write offset can't be negative, requested offset: {}".format(offset)) + + # Get information about the memory area + memory = self.device_memory_info.memory_info_by_name(memory_name) + size = memory[DeviceMemoryInfoKeys.SIZE] + + if memory[DeviceMemoryInfoKeys.WRITE_SIZE] == 0: + raise PymcuprogNotSupportedError("{} memory can't be written".format(memory_name)) + + if offset + len(data) > size: + msg = "{} bytes of data at offset {} is outside the boundaries of '{}' with size {}".format(len(data), + offset, + memory_name, + size) + raise ValueError(msg) + + # Write the data to NVM + self.logger.info("Writing %d bytes of data to %s...", len(data), memory[DeviceMemoryInfoKeys.NAME]) + if blocksize == 0: + self.device_model.write(memory, offset, data, pagewrite_delay=pagewrite_delay) + else: + self.device_model.write(memory, offset, data, blocksize=blocksize, pagewrite_delay=pagewrite_delay) + self.logger.info("Write complete.") + return True + + def verify_memory(self, data, memory_name, offset=0, max_read_chunk=None): + """ + Verify memory content + + :param data: data to verify against + :param memory_name: memory type + :param offset: offset/address within that memory region + :return: boolean compare status + """ + # Get information about the memory area + memory = self.device_memory_info.memory_info_by_name(memory_name) + verify_mask = memory[DeviceMemoryInfoKeys.VERIFY_MASK] + + # Read back and compare the data to verify + data_verify = self.read_memory(memory_name, offset, len(data), max_read_chunk=max_read_chunk)[0].data + + self.logger.info("Verifying...") + try: + # Use the compare util, which throws ValueError on mismatch + utils.compare(data, data_verify, offset, verify_mask) + except ValueError as error: + self.logger.error("Verify failed: %s", str(error)) + return False + return True + + def read_memory(self, memory_name, offset, numbytes=0, max_read_chunk=None): + """ + Read device memory + + :param memory_name: memory type to read as defined in deviceinfo.memorynames + MemoryNameAliases.ALL will read all memories defined in the device model for the configured + device (numbytes and offset will be ignored) + :param offset: offset/start address within the memory to start reading from + :param numbytes: number of bytes to read. 0 means read all memory locations for given memory + type (offset still applies) + :return: list of namedtuples with two fields: data and memory_info. data contains a byte array + of raw data bytes and memory_info is a dictionary with memory information as defined in + deviceinfo.deviceinfo.DeviceMemoryInfo. Normally the list will contain one item, + but when memory_name parameter is MemoryNameAliases.ALL there will be one namedtuple + item per memory type read. + :raises: ValueError if trying to read outside the specified memory + :raises: ValueError if the specified memory is not defined for the target device + """ + # Just some sanity checking of inputs + if offset < 0: + raise ValueError("Read offset can't be negative, requested offset: {}".format(offset)) + if numbytes < 0: + raise ValueError("Can't read negative number of bytes, requested numbytes: {}".format(numbytes)) + + memories_read = [] + + if memory_name == MemoryNameAliases.ALL: + memories = list(self.device_memory_info.mem_by_name.keys()) + + # When reading all memories offset is ignored + offset = 0 + # ...and the same with numbytes + numbytes = 0 + else: + memories = [memory_name] + + for memory in memories: + # Get information about the memory area + meminfo = self.device_memory_info.memory_info_by_name(memory) + + # For each memory type there will be one named tuple with raw data as a bytearray and a dictionary + # with information about the memory + memory_read_tuple = namedtuple("Memory", 'data memory_info') + memory_read_tuple.data = bytearray([]) + memory_read_tuple.memory_info = meminfo + + # Align the read to a page boundary + page_offset = offset % meminfo[DeviceMemoryInfoKeys.PAGE_SIZE] + + offset_adjusted = offset - page_offset + numbytes_adjusted = numbytes + # If number of bytes is not given, default to read the complete memory starting at the given offset + if numbytes == 0: + numbytes_adjusted = meminfo[DeviceMemoryInfoKeys.SIZE] - offset_adjusted + else: + numbytes_adjusted = numbytes_adjusted + page_offset + + # Read size correction + read_size_key = DeviceMemoryInfoKeys.READ_SIZE + if numbytes_adjusted % meminfo[read_size_key]: + extra = meminfo[read_size_key] - numbytes_adjusted % meminfo[read_size_key] + numbytes_adjusted += extra + else: + extra = 0 + + if offset_adjusted + numbytes_adjusted > meminfo[DeviceMemoryInfoKeys.SIZE]: + raise ValueError("{} bytes of data at offset {} is outside the boundaries of '{}' with size {}".format( + numbytes_adjusted, offset, meminfo[DeviceMemoryInfoKeys.NAME], meminfo[DeviceMemoryInfoKeys.SIZE])) + + # Read the data + self.logger.info("Reading %d bytes from %s...", numbytes_adjusted, meminfo[DeviceMemoryInfoKeys.NAME]) + data = self.device_model.read(meminfo, offset_adjusted, numbytes_adjusted, max_read_chunk=max_read_chunk) + + # Strip the extra data that was read + memory_read_tuple.data = data[page_offset:numbytes_adjusted - extra] + + # Append a copy of the memory namedtuple to avoid a reference being appended as the memory_read_tuple will + # change for each loop iteration. Note that when using a deepcopy the content of the memory_read_tuple will + # be copied too + memories_read.append(copy.deepcopy(memory_read_tuple)) + + return memories_read + + def hold_in_reset(self): + """ + Hold the device in reset + """ + self.logger.info("Hold in reset") + self.device_model.hold_in_reset() + + def release_from_reset(self): + """ + Release the device from reset (i.e. let the device run) + """ + self.logger.info("Release from reset") + self.device_model.release_from_reset() diff --git a/software/tools/pymcuprog/libs/pymcuprog/progress_bar.py b/software/tools/pymcuprog/libs/pymcuprog/progress_bar.py new file mode 100644 index 0000000..d3af192 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/progress_bar.py @@ -0,0 +1,58 @@ +import sys +import time + + +class ProgressBar: + def __init__(self, n_steps, width=50, hide=False): + self.width = width + self.n_steps = n_steps + self.count_step = 0 + self.count_char = 0 + self.hide = hide + self.print_start() + + def print_start(self): + if not self.hide: + sys.stdout.write("[%s]" % (" " * self.width)) + sys.stdout.flush() + + def print_end(self): + if not self.hide: + sys.stdout.write("\n") + sys.stdout.flush() + + def update(self): + n1 = self.count_char + n2 = self.width - self.count_char + if not self.hide: + sys.stdout.write("\r[" + "=" * n1 + " " * n2 + "] {}/{}".format(self.count_step, self.n_steps)) + sys.stdout.flush() + + def step(self): + self.count_step += 1 + count_char_new = self.width * self.count_step // self.n_steps + + if count_char_new > self.count_char: + self.count_char = count_char_new + self.update() + + if self.count_step == self.n_steps: + self.print_end() + + +def test(): + n_steps = 100 + + print("Starting...") + + b = ProgressBar(n_steps) + + for i in range(n_steps): + time.sleep(0.01) + b.step() + + print("done.") + + +if __name__ == "__main__": + test() diff --git a/software/tools/pymcuprog/libs/pymcuprog/pymcuprog.py b/software/tools/pymcuprog/libs/pymcuprog/pymcuprog.py new file mode 100644 index 0000000..353630e --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/pymcuprog.py @@ -0,0 +1,258 @@ +""" +Python MCU programmer Command Line Interface utility +""" +# Python 3 compatibility for Python 2 +from __future__ import print_function + +# args, logging +import sys +import argparse +import os +import logging +from logging.config import dictConfig +import textwrap +import yaml + +try: + from pathlib import Path +except ImportError: + from pathlib2 import Path # python 2 backport + +from appdirs import user_log_dir +from yaml.scanner import ScannerError + +# pymcuprog main function +from . import pymcuprog_main +from .pymcuprog_main import WRITE_TO_HEX_MEMORIES +from .deviceinfo.memorynames import MemoryNames, MemoryNameAliases + + +def setup_logging(user_requested_level=logging.WARNING, default_path='logging.yaml', + env_key='MICROCHIP_PYTHONTOOLS_CONFIG'): + """ + Setup logging configuration for pymcuprog CLI + """ + # Logging config YAML file can be specified via environment variable + value = os.getenv(env_key, None) + if value: + path = value + else: + # Otherwise use the one shipped with this application + path = os.path.join(os.path.dirname(__file__), default_path) + # Load the YAML if possible + if os.path.exists(path): + try: + with open(path, 'rt') as file: + # Load logging configfile from yaml + configfile = yaml.safe_load(file) + # File logging goes to user log directory under Microchip/modulename + logdir = user_log_dir(__name__, "Microchip") + # Look through all handlers, and prepend log directory to redirect all file loggers + num_file_handlers = 0 + for handler in configfile['handlers'].keys(): + # A filename key + if 'filename' in configfile['handlers'][handler].keys(): + configfile['handlers'][handler]['filename'] = os.path.join( + logdir, configfile['handlers'][handler]['filename']) + num_file_handlers += 1 + # If file logging is enabled, it needs a folder + if num_file_handlers > 0: + # Create it if it does not exist + Path(logdir).mkdir(exist_ok=True, parents=True) + # Console logging takes granularity argument from CLI user + configfile['handlers']['console']['level'] = user_requested_level + # Root logger must be the most verbose of the ALL YAML configurations and the CLI user argument + most_verbose_logging = min(user_requested_level, getattr(logging, configfile['root']['level'])) + for handler in configfile['handlers'].keys(): + # A filename key + if 'filename' in configfile['handlers'][handler].keys(): + level = getattr(logging, configfile['handlers'][handler]['level']) + most_verbose_logging = min(most_verbose_logging, level) + configfile['root']['level'] = most_verbose_logging + dictConfig(configfile) + return + except ScannerError: + # Error while parsing YAML + print("Error parsing logging config file '{}'".format(path)) + except KeyError as keyerror: + # Error looking for custom fields in YAML + print("Key {} not found in logging config file".format(keyerror)) + else: + # Config specified by environment variable not found + print("Unable to open logging config file '{}'".format(path)) + + # If all else fails, revert to basic logging at specified level for this application + print("Reverting to basic logging.") + logging.basicConfig(level=user_requested_level) + + +# Helper functions +def _parse_literal(literal): + """ + Literals can either be integers or float values. Default is Integer + """ + try: + return int(literal, 0) + except ValueError: + return float(literal) + + +def main(): + """ + Entrypoint for installable CLI + + Configures the CLI and parses the arguments + """ + parser = argparse.ArgumentParser( + formatter_class=argparse.RawDescriptionHelpFormatter, + description=textwrap.dedent('''\ + Generic programmer of selected AVR, PIC and SAM devices + + Basic actions: + - ping: reads the device ID or signature + - read: read NVM + - write: write NVM + - erase: erase NVM + '''), + epilog=textwrap.dedent('''\ + Usage examples: + + Ping a device on-board a kit: + - pymcuprog.py ping + + Ping a device using Atmel-ICE + - pymcuprog.py -t atmelice -d atmega4809 -i updi ping + + Read the some bytes of flash: + - pymcuprog.py read -m flash -o 0x80 -b 64 + + Erase an UPDI device: + - pymcuprog.py erase + + Erase a locked UPDI device: + - pymcuprog.py ping --chip-erase-locked-device + + Set target supply voltage on a kit: + - pymcuprog.py setsupplyvoltage -l 3.3 + ''')) + + parser.add_argument("action", + help="action to perform", + # This makes the action argument optional + # only if -V/--version or -R/release_info argument is given + nargs="?" if "-V" in sys.argv or "--version" in sys.argv \ + or "-R" in sys.argv or "--release-info" in sys.argv else None, + default="ping", + # nargs='?', # this makes ping the default, and -h the only way to get usage() + choices=['ping', 'erase', 'read', 'write', 'verify', 'getvoltage', 'getsupplyvoltage', + 'reboot-debugger', + 'setsupplyvoltage', 'getusbvoltage', 'reset']) + + # Device to program + parser.add_argument("-d", "--device", + type=str, + help="device to program") + + # Pack path + parser.add_argument("-p", "--packpath", + type=str, + help="path to pack") + + # Tool to use + parser.add_argument("-t", "--tool", + type=str, + help="tool to connect to") + + parser.add_argument("-s", "--serialnumber", + type=str, + help="USB serial number of the unit to use") + + # Memtype + memtype_helpstring = "memory area to access: {}".format(MemoryNameAliases.ALL) + for memtype in MemoryNames.get_all(): + memtype_helpstring += ", '{}'".format(memtype) + parser.add_argument("-m", "--memory", + type=str, + default=MemoryNameAliases.ALL, + help=memtype_helpstring) + + parser.add_argument("-o", "--offset", + type=lambda x: int(x, 0), + default="0", + help="memory byte offset to access") + + parser.add_argument("-b", "--bytes", + type=int, + default=0, + help="number of bytes to access") + + parser.add_argument("-l", "--literal", + type=_parse_literal, + nargs='+', + help="literal values to write") + + filename_helpstring_extra = "Note that when reading to hex file only " + filename_helpstring_extra += ", ".join(WRITE_TO_HEX_MEMORIES) + filename_helpstring_extra += " memories will be written to the hex file" + parser.add_argument("-f", "--filename", + type=str, + help="file to write / read. " + "{}".format(filename_helpstring_extra)) + + parser.add_argument("-c", "--clk", + type=str, + help="clock frequency in Hz (bps) for programming interface. " + "(eg: '-c 32768' or '-c 115k' or '-c 1M')") + + parser.add_argument("-u", "--uart", + type=str, + help="UART to use for UPDI") + + parser.add_argument("-i", "--interface", + type=str, + help="Interface to use") + + parser.add_argument("-v", "--verbose", + default="warning", choices=['debug', 'info', 'warning', 'error', 'critical'], + help="Logging verbosity level") + + parser.add_argument("-V", "--version", + help="Print pymcuprog version number and exit", + action="store_true") + + parser.add_argument("-R", "--release-info", action="store_true", + help="Print pymcuprog release details and exit") + + parser.add_argument("--verify", + help="verify after write from file", + action="store_true") + + parser.add_argument("-x", "--timing", + help="add timing output", + action="store_true") + + # Ex-options + parser.add_argument("-hv", "--high-voltage", + choices=['tool-toggle-power', 'user-toggle-power', 'simple-unsafe-pulse'], + help="UPDI high-voltage activation mode") + + parser.add_argument("-ul", "--user-row-locked-device", + help="Writes the User Row on a locked device (UPDI devices only)", + action="store_true") + + parser.add_argument("-cl", "--chip-erase-locked-device", + help="Execute a Chip Erase on a locked device (UPDI devices only)", + action="store_true") + + # Parse args + arguments = parser.parse_args() + + # Setup logging + setup_logging(user_requested_level=getattr(logging, arguments.verbose.upper())) + + # Call main with args + return pymcuprog_main.pymcuprog(arguments) + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/software/tools/pymcuprog/libs/pymcuprog/pymcuprog_errors.py b/software/tools/pymcuprog/libs/pymcuprog/pymcuprog_errors.py new file mode 100644 index 0000000..b83501d --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/pymcuprog_errors.py @@ -0,0 +1,79 @@ +""" +Pymcuprog specific exceptions +""" + +class PymcuprogError(Exception): + """ + Base class for all Pymcuprog specific exceptions + """ + + def __init__(self, msg=None, code=0): + super(PymcuprogError, self).__init__(msg) + self.code = code + +class PymcuprogToolConfigurationError(PymcuprogError): + """ + Signals that a tool was incorrectly configured + """ + + def __init__(self, msg=None, code=0): + super(PymcuprogToolConfigurationError, self).__init__(msg) + self.code = code + +class PymcuprogToolConnectionError(PymcuprogError): + """ + Signals that an attempted connect failed + """ + + def __init__(self, msg=None, code=0): + super(PymcuprogToolConnectionError, self).__init__(msg) + self.code = code + +class PymcuprogNotSupportedError(PymcuprogError): + """ + Signals that an attempted operation is not supported + """ + + def __init__(self, msg=None, code=0): + super(PymcuprogNotSupportedError, self).__init__(msg) + self.code = code + +class PymcuprogSessionError(PymcuprogError): + """ + Signals that a session is not active + """ + + def __init__(self, msg=None, code=0): + super(PymcuprogSessionError, self).__init__(msg) + self.code = code + +class PymcuprogSessionConfigError(PymcuprogError): + """ + Signals that a session is not configured correctly + """ + + def __init__(self, msg=None, code=0): + super(PymcuprogSessionConfigError, self).__init__(msg) + self.code = code + + +class PymcuprogDeviceLockedError(PymcuprogError): + """ + Signals that the device is locked and a chip erase is required to unlock it + """ + + def __init__(self, msg=None, code=0): + super(PymcuprogDeviceLockedError, self).__init__(msg) + self.code = code + +class PymcuprogEraseError(PymcuprogError): + """ + Signals that an erase can't be executed + + Either the erase is not possible or the erase can't be executed without side effects, + i.e. erasing more memories than requested + """ + + def __init__(self, msg=None, code=0): + super(PymcuprogEraseError, self).__init__(msg) + self.code = code diff --git a/software/tools/pymcuprog/libs/pymcuprog/pymcuprog_main.py b/software/tools/pymcuprog/libs/pymcuprog/pymcuprog_main.py new file mode 100644 index 0000000..cd984fe --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/pymcuprog_main.py @@ -0,0 +1,561 @@ +""" +Python MCU programmer, CLI main program +""" +# Python 3 compatibility for Python 2 +from __future__ import print_function + +# utils +import time +import os +from copy import copy + +from .backend import Backend, SessionConfig +from .toolconnection import ToolUsbHidConnection, ToolSerialConnection +from .deviceinfo.memorynames import MemoryNameAliases, MemoryNames +from .deviceinfo.eraseflags import ChiperaseEffect +from .deviceinfo.deviceinfo import get_supported_devices +from .deviceinfo.deviceinfokeys import DeviceMemoryInfoKeys + +from .utils import print_tool_info, showdata, verify_flash_from_bin, compare +from .hexfileutils import write_memories_to_hex, write_memory_to_hex, read_memories_from_hex, verify_flash_from_hex +from .pymcuprog_errors import PymcuprogNotSupportedError, PymcuprogSessionConfigError, \ + PymcuprogToolConnectionError, PymcuprogDeviceLockedError + +try: + from .version import VERSION, BUILD_DATE, COMMIT_ID +except ImportError: + VERSION = "0.0.0" + COMMIT_ID = "N/A" + BUILD_DATE = "N/A" + +STATUS_SUCCESS = 0 +STATUS_FAILURE = 1 +STATUS_FAILURE_LOCKED = 2 + +# Only include memories that can be written when writing memories to hex file +WRITE_TO_HEX_MEMORIES = [MemoryNames.EEPROM, MemoryNames.FLASH, MemoryNames.FUSES, MemoryNames.CONFIG_WORD] + + +def pymcuprog(args): + """ + Main program + """ + if args.version or args.release_info: + print("pymcuprog version {}".format(VERSION)) + if args.release_info: + print("Build date: {}".format(BUILD_DATE)) + print("Commit ID: {}".format(COMMIT_ID)) + return STATUS_SUCCESS + + backend = Backend() + + toolconnection = _setup_tool_connection(args) + + try: + backend.connect_to_tool(toolconnection) + except PymcuprogToolConnectionError as error: + print(error) + return STATUS_FAILURE + + status = None + if args.tool not in ['uart']: + # This section can initialise all features requiring non-UART transports + + # DAP info only available on native CMSIS-DAP + dap_info = backend.read_tool_info() + print_tool_info(dap_info) + + # Targetless actions, only available on HID tools + status = _debugger_actions(backend, args) + + if status is not None: + backend.disconnect_from_tool() + return status + + device_selected = _select_target_device(backend, args) + if device_selected is None: + backend.disconnect_from_tool() + return STATUS_FAILURE + + status = _start_session(backend, device_selected, args) + if status != STATUS_SUCCESS: + backend.disconnect_from_tool() + return status + + # -x timer argument + time_start = None + if args.timing: + print("Starting timer") + time_start = time.time() + + _programming_actions(backend, args) + + backend.end_session() + backend.disconnect_from_tool() + if args.timing: + time_stop = time.time() + print("Operation took {0:.03f}s".format(time_stop - time_start)) + + print("Done.") + + return status + + +def _action_getvoltage(backend): + voltage = backend.read_target_voltage() + print("Measured voltage: {0:0.2f}V".format(voltage)) + return STATUS_SUCCESS + + +def _action_getsupplyvoltage(backend): + voltage = backend.read_supply_voltage_setpoint() + print("Supply voltage set to {0:0.2f}V".format(voltage)) + return STATUS_SUCCESS + + +def _action_getusbvoltage(backend): + voltage = backend.read_usb_voltage() + print("USB voltage is {0:0.2f}V".format(voltage)) + return STATUS_SUCCESS + + +def _action_setsupplyvoltage(backend, literal): + voltage = backend.read_supply_voltage_setpoint() + print("Supply voltage is currently set to {0:0.2f}V".format(voltage)) + if literal is None: + print("Specify voltage in Volts using -l ") + else: + setvoltage = literal[0] + if setvoltage == voltage: + print("Voltage is already right where you want it.") + else: + print("Setting supply voltage to {0:0.2f}V".format(setvoltage)) + backend.set_supply_voltage_setpoint(setvoltage) + voltage = backend.read_supply_voltage_setpoint() + print("Supply voltage is now set to {0:0.2f}V".format(voltage)) + + # Static delay to let the target voltage settle before reading it out + # Alternatively a retry loop could be used, but it is difficult to know when to terminate + # the loop as sometimes the final voltage is not known, for example if setting the voltage + # to 5.5V the actual voltage will depend upon the USB voltage. If the USB voltage is only + # 4.9V the target voltage will never reach more than 4.9V + time.sleep(0.5) + voltage = backend.read_target_voltage() + print("Measured voltage: {0:0.2f}V".format(voltage)) + return STATUS_SUCCESS + + +def _action_reboot_debugger(backend): + print("Rebooting tool...") + backend.reboot_tool() + return STATUS_SUCCESS + + +def _action_ping(backend): + print("Pinging device...") + response = backend.read_device_id() + idstring = '' + for idbyte in response: + idstring = '{:02X}'.format(idbyte) + idstring + print("Ping response: {}".format(idstring)) + return STATUS_SUCCESS + + +def _action_erase(backend, args): + if args.memory is None or args.memory == MemoryNameAliases.ALL: + print("Chip/Bulk erase,") + for memname in MemoryNames.get_all(): + try: + effect = backend.get_chiperase_effect(memname) + except ValueError: + # This memory type does not exist for this device, just continue + continue + else: + if effect != ChiperaseEffect.NOT_ERASED: + print("Memory type {} is {}".format(memname, effect)) + print("...") + else: + if backend.is_isolated_erase_possible(args.memory): + print("Erasing {}...".format(args.memory)) + else: + print("ERROR: {} memory can't be erased or " + "can't be erased without affecting other memories".format(args.memory)) + chiperase_effect = backend.get_chiperase_effect(args.memory) + if chiperase_effect != ChiperaseEffect.NOT_ERASED: + print("{} memory is {} by a chip/bulk erase".format(args.memory, chiperase_effect)) + print("Use erase without -m option to erase this memory") + return STATUS_FAILURE + + backend.erase(args.memory, address=None) + print("Erased.") + return STATUS_SUCCESS + + +def _action_read(backend, args): + # Reading with bytes argument requires that memory type is specified + if args.bytes != 0 and args.memory == MemoryNameAliases.ALL: + print("Memory area must be specified when number of bytes is specified.") + return STATUS_FAILURE + + print("Reading...") + result = backend.read_memory(args.memory, args.offset, args.bytes, args.max_chunk_size) + + # If a filename is specified, write to it + hexfile = False + binary = False + filepath = None + if args.filename is not None: + filepath = os.path.normpath(args.filename) + prefix, postfix = _get_file_prefix_and_postfix(filepath) + # If it ends in hex, use intel hex format, else binary + if postfix == 'hex': + hexfile = True + else: + binary = True + + # Print the data or save it to a file + if hexfile: + if args.memory == MemoryNameAliases.ALL: + # Only memories that can be written should go into the hex file + result_to_write = _extract_writeable_memories(result) + write_memories_to_hex(filepath, result_to_write) + else: + write_memory_to_hex(filepath, result[0], args.offset) + print("Data written to hex file: '{0:s}'".format(filepath)) + elif binary: + for item in result: + memory_name = item.memory_info[DeviceMemoryInfoKeys.NAME] + data = item.data + filepath = "{}_{}.{}".format(prefix, memory_name, postfix) + # Binary files does not have addressing, and needs a split on memory type + with open(filepath, "wb") as binfile: + binfile.write(data) + print("Data written to binary file: '{0:s}'".format(filepath)) + else: + for item in result: + memory_info = item.memory_info + print("Memory type: {}".format(memory_info[DeviceMemoryInfoKeys.NAME])) + showdata(item.data, + args.offset + memory_info[DeviceMemoryInfoKeys.ADDRESS], + memory_info[DeviceMemoryInfoKeys.PAGE_SIZE]) + print("\n") + + return STATUS_SUCCESS + + +def _action_verify(backend, args): + hexfile = False + binary = False + literal = False + filepath = None + if args.filename is not None: + filepath = os.path.normpath(args.filename) + _, postfix = _get_file_prefix_and_postfix(filepath) + # If it ends in hex, use intel hex format, else binary + if postfix == 'hex': + hexfile = True + else: + binary = True + if args.literal is not None: + literal = True + if args.filename is not None: + print("Both file and literal value was specified. Literal verify will be ignored in favor of file verify") + literal = False + + if hexfile: + print("Verifying...") + verify_status = verify_flash_from_hex(args.filename, backend, max_read_chunk=args.max_read_chunk) + if verify_status is True: + print("Verify successful. Data in flash matches data in specified hex-file") + elif binary: + print("Verifying...") + verify_status = verify_flash_from_bin(args.filename, backend, args.offset, max_read_chunk=args.max_read_chunk) + if verify_status is True: + print("Verify successful. Data in flash matches data in specified bin-file") + elif literal: + print("Verifying...") + flash_data = backend.read_memory('flash', args.offset, len(args.literal), max_read_chunk=args.max_read_chunk)[0].data + compare(flash_data, args.literal, args.offset) + print("Verify successful. Data in flash matches literal data specified") + else: + raise Exception('No file or literal specified for verify') + + return STATUS_SUCCESS + + +def _get_file_prefix_and_postfix(filepath): + """ + Get file prefix and postfix from the filepath + + If the file name in the filepath has not file extension the file is supposed to be a binary file + :param filepath: File name and full path + :return: prefix, postfix + """ + prefix = filepath.split('.')[0] + postfix = filepath.split('.')[-1].lower() + # If no "." is found in the filepath + if postfix == prefix: + postfix = "bin" + + return prefix, postfix + + +def _extract_writeable_memories(memory_segments): + """ + Take a list of memory segments and return the segments that can be written + + :param memory_segments: List of namedtuples with two fields: data and memory_info. data contains a byte array of + raw data bytes and memory_info is a dictionary with memory information (as defined in + deviceinfo.deviceinfo.DeviceMemoryInfo). + :return: List of namedtuples (a subset of the memory_segments input parameter) only containing memory segments + that can be written + """ + writeable_segments = [] + for segment in memory_segments: + if segment.memory_info[DeviceMemoryInfoKeys.NAME] in WRITE_TO_HEX_MEMORIES: + writeable_segments.append(segment) + return writeable_segments + + +def _action_write(backend, args): + # If a filename is specified, read from it + if args.filename is not None: + filepath = os.path.normpath(args.filename) + _, postfix = _get_file_prefix_and_postfix(filepath) + # If it ends in hex, use intel hex format, else binary + if postfix == 'hex': + # Hexfiles contain addressing information that cannot be remapped, so offset/memory are not allowed here + if args.offset: + print("Offset cannot be specified when writing hex file") + return STATUS_FAILURE + + if args.memory != MemoryNameAliases.ALL: + print("Memory area cannot be specified when writing hex file") + return STATUS_FAILURE + + result = read_memories_from_hex(args.filename, backend.device_memory_info) + + print("Writing from hex file...") + + _write_memory_segments(backend, result, args.verify, blocksize=args.blocksize, pagewrite_delay=args.pagewrite_delay) + else: + with open(filepath, "rb") as binfile: + data_from_file = bytearray(binfile.read()) + + # Prepare and write data + print("Writing from binary file...") + # When writing data to target the data might be pagealigned so we make a copy to avoid verifying + # more than needed (in case verify option is enabled) + data_to_write = copy(data_from_file) + backend.write_memory(data_to_write, args.memory, args.offset) + if args.verify: + print("Verifying from binary file...") + # Verify content, an exception is thrown on mismatch + backend.verify_memory(data_from_file, args.memory, args.offset) + elif args.literal: + # Prepare and write data + print("Writing literal values...") + backend.write_memory(bytearray(args.literal), args.memory, args.offset) + if args.verify: + print("Verifying literal values...") + # Verify content, an exception is thrown on mismatch + backend.verify_memory(bytearray(args.literal), args.memory, args.offset) + else: + print("Error: for writing use either -f or -l ") + + return STATUS_SUCCESS + + +def _write_memory_segments(backend, memory_segments, verify, blocksize = 0, pagewrite_delay=0): + """ + Write content of list of memory segments + + :param backend: pymcuprog Backend instance + :param memory_segments: List of namedtuples with two fields: data and memory_info. data contains a byte array of + raw data bytes and memory_info is a dictionary with memory information (as defined in + deviceinfo.deviceinfo.DeviceMemoryInfo). + :param verify: If True verify the written data by reading it back and compare + :param blocksize: this is a signal to write_memory for updiserial when writing flash; if 0 or not supplied + do not use blocks (equivalent to blocksize == 2 bytes or 1 word). If -1, it will set tje blocksize to + the page size of the target chip, which can imcrease write speed more than 10:1. Any other number will + be used as supplied. Even numbers up to the page size are recommended. + Any other negative number is invalid, and is zero'ed out. + """ + for segment in memory_segments: + memory_name = segment.memory_info[DeviceMemoryInfoKeys.NAME] + print("Writing {}...".format(memory_name)) + backend.write_memory(segment.data, memory_name, segment.offset, blocksize=blocksize, pagewrite_delay=pagewrite_delay) + if verify: + print("Verifying {}...".format(memory_name)) + verify_ok = backend.verify_memory(segment.data, memory_name, segment.offset) + if verify_ok: + print("OK") + else: + print("Verification failed!") + + +def _action_reset(backend): + backend.hold_in_reset() + # Wait a bit to make sure the device has entered reset + # If needed this sleep could be made configurable by a CLI parameter, + # but for now a hardcoded value is assumed to be sufficient + time.sleep(0.1) + backend.release_from_reset() + return STATUS_SUCCESS + + +def _debugger_actions(backend, args): + """ + Debugger related actions + + Targetless actions only involving the debugger. Only available on HID tools + """ + status = None + if args.action == 'getvoltage': + status = _action_getvoltage(backend) + if args.action == 'getsupplyvoltage': + status = _action_getsupplyvoltage(backend) + if args.action == 'getusbvoltage': + status = _action_getusbvoltage(backend) + if args.action == 'setsupplyvoltage': + status = _action_setsupplyvoltage(backend, args.literal) + if args.action == 'reboot-debugger': + status = _action_reboot_debugger(backend) + + return status + + +def _programming_actions(backend, args): + status = None + # Ping: checks that the device is there by reading its ID, or equivalent + if args.action == "ping": + status = _action_ping(backend) + # Erase: perform a full chip erase, or memtype-only erase if specified + elif args.action == "erase": + status = _action_erase(backend, args) + # Reading data: + elif args.action == "read": + status = _action_read(backend, args) + elif args.action == "write": + status = _action_write(backend, args) + elif args.action == "reset": + status = _action_reset(backend) + elif args.action == "verify": + status = _action_verify(backend, args) + else: + print("Unknown command '{0:s}'".format(args.action)) + status = STATUS_FAILURE + + return status + + +def _setup_tool_connection(args): + toolconnection = None + + # Parse the requested tool from the CLI + if args.tool == "uart": + # Embedded GPIO/UART tool (eg: raspberry pi) => no USB connection + toolconnection = ToolSerialConnection(serialport=args.uart) + else: + usb_serial = args.serialnumber + product = args.tool + if usb_serial and product: + print("Connecting to {0:s} ({1:s})'".format(product, usb_serial)) + else: + if usb_serial: + print("Connecting to any tool with USB serial number '{0:s}'".format(usb_serial)) + elif product: + print("Connecting to any {0:s}".format(product)) + else: + print("Connecting to anything possible") + toolconnection = ToolUsbHidConnection(serialnumber=usb_serial, tool_name=product) + + return toolconnection + + +def _select_target_device(backend, args): + device_mounted = None + device_selected = None + if args.tool not in ['uart']: + # Find out from the board (kit) if a device is mounted + device_mounted = backend.read_kit_device() + if device_mounted is not None: + device_mounted = device_mounted.lower() + print("Device mounted: '{0:s}'".format(device_mounted)) + + # Parse device field. If unspecified, use the board's device + if args.device: + device_selected = args.device.lower() + else: + if device_mounted is None: + print("Unable to determine on-board target! Please specify device using -d ") + else: + print("No device specified. Using on-board target ({0:s})".format(device_mounted)) + device_selected = device_mounted + + # Mismatch. Allow user to proceed at own risk. + if device_mounted is not None and device_selected != device_mounted: + print("Warning: you are attempting to use a device which is not the one which was mounted on the kit!") + print("Cut all straps between the debugger and the on-board target when accessing an external device!") + + return device_selected + + +def _start_session(backend, device, args): + """ + Setup the session and try to build the stack for this device + """ + sessionconfig = SessionConfig(device) + + # -c clock argument + # allow Hz, or kHz ending in 'k' (eg: 100k) or MHz ending in 'M' eg (1M) + if args.clk: + if args.clk[-1] == 'k': + clk = int(args.clk.strip('k')) * 1000 + elif args.clk[-1] == 'M': + clk = int(args.clk.strip('M')) * 1000000 + else: + clk = int(args.clk) + + sessionconfig.interface_speed = clk + + # Translate args into "special_options" to pass down the stack + sessionconfig.special_options = {} + if args.high_voltage: + sessionconfig.special_options['high-voltage'] = args.high_voltage + if args.user_row_locked_device: + sessionconfig.special_options['user-row-locked-device'] = args.user_row_locked_device + if args.chip_erase_locked_device: + sessionconfig.special_options['chip-erase-locked-device'] = args.chip_erase_locked_device + + # Programming user row on locked parts and erasing to unlock are mutually exclusive + if args.chip_erase_locked_device and args.user_row_locked_device: + print("User row cannot be written on a locked device while erasing and unlocking.") + return STATUS_FAILURE + + if args.interface: + sessionconfig.interface = args.interface + + if args.packpath: + sessionconfig.packpath = args.packpath + + status = STATUS_SUCCESS + try: + backend.start_session(sessionconfig) + except PymcuprogDeviceLockedError: + print("The device is in a locked state and is not accessible; a chip erase is required.") + print("Locked AVR UPDI devices can:") + print(" - be unlocked using command: erase --chip-erase-locked-device") + print(" - write user row values using command: write --user-row-locked-device") + status = STATUS_FAILURE_LOCKED + except PymcuprogNotSupportedError: + print("Unable to setup stack for device {0:s}".format(sessionconfig.device)) + print("Currently supported devices (in 'devices' folder):") + device_list = get_supported_devices() + print(', '.join(map(str, device_list))) + status = STATUS_FAILURE + except PymcuprogSessionConfigError as error: + print("Unable to start session: {}".format(error)) + status = STATUS_FAILURE + + return status diff --git a/software/tools/pymcuprog/libs/pymcuprog/serialupdi/__init__.py b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/software/tools/pymcuprog/libs/pymcuprog/serialupdi/application.py b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/application.py new file mode 100644 index 0000000..02ca956 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/application.py @@ -0,0 +1,268 @@ +""" +Application layer for UPDI stack +""" +from logging import getLogger +from pymcuprog.pymcuprog_errors import PymcuprogError +from . import constants +from .link import UpdiDatalink16bit, UpdiDatalink24bit +from .nvm import NvmUpdi, NvmUpdiTinyMega, NvmUpdiAvrDx +from .readwrite import UpdiReadWrite +from .physical import UpdiPhysical +from .timeout import Timeout + + +def decode_sib(sib): + """ + Turns the SIB into something readable + :param sib: SIB data to decode + """ + sib_info = {} + logger = getLogger(__name__) + + sib = sib.replace(b"\x00", b"") + + try: + sib_string = sib.decode('ascii') + except UnicodeDecodeError: + return None + + if len(sib_string) < 19: + return None + + logger.info("SIB: '%s'", sib_string) + + # Parse fixed width fields according to spec + family = sib[0:7].strip().decode() + logger.info("Device family ID: '%s'", family) + sib_info['family'] = family + + nvm = sib[8:11].strip().decode() + logger.info("NVM interface: '%s'", nvm) + sib_info['NVM'] = nvm.split(':')[1] + + ocd = sib[11:14].strip().decode() + logger.info("Debug interface: '%s'", ocd) + sib_info['OCD'] = ocd.split(':')[1] + + osc = sib[15:19].strip().decode() + logger.info("PDI oscillator: '%s'", osc) + sib_info['OSC'] = osc + + extra = sib[19:].strip().decode() + logger.info("Extra info: '%s'", extra) + sib_info['extra'] = extra + + return sib_info + + +class UpdiApplication: + """ + Generic application layer for UPDI + """ + + def __init__(self, serialport, baud, device=None): + self.logger = getLogger(__name__) + self.device = device + # Build the UPDI stack: + # Create a physical + + baud_temp = min(baud, 115200) + self.phy = UpdiPhysical(serialport, baud_temp) + + # Create a DL - use 16-bit until otherwise known + datalink = UpdiDatalink16bit() + + # Set the physical for use in the datalink + datalink.set_physical(self.phy) + + # Init (active) the datalink + datalink.init_datalink() + + # set the actual baud + datalink.change_baud(baud) + + # Create a read write access layer using this data link + self.readwrite = UpdiReadWrite(datalink) + + # Create an NVM driver + self.nvm = NvmUpdi(self.readwrite, self.device) + + def read_device_info(self): + """ + Reads out device information from various sources + """ + sib = self.readwrite.read_sib() + sib_info = decode_sib(sib) + + if sib_info is None: + self.logger.warning("Cannot read SIB, hard reset...") + self.phy.send_double_break() + sib = self.readwrite.read_sib() + sib_info = decode_sib(sib) + if sib_info is None: + self.logger.error("Hard reset failed.") + raise RuntimeError("Failed to read device info.") + + if sib_info['NVM'] == '2': + # This is a Dx-family member, and needs new DL and NVM + self.logger.info("Using 24-bit UPDI") + # Create new DL + datalink = UpdiDatalink24bit() + # Use the existing PHY + datalink.set_physical(self.phy) + # And re-init + datalink.init_datalink() + # Create a read write access layer using this data link + self.readwrite = UpdiReadWrite(datalink) + # Create new NVM driver + self.nvm = NvmUpdiAvrDx(self.readwrite, self.device) + else: + self.logger.info("Using 16-bit UPDI") + # DL is correctly configured already + # Create new NVM driver + self.nvm = NvmUpdiTinyMega(self.readwrite, self.device) + + self.logger.info("PDI revision = 0x%02X", self.readwrite.read_cs(constants.UPDI_CS_STATUSA) >> 4) + if self.in_prog_mode(): + if self.device is not None: + devid = self.read_data(self.device.sigrow_address, 3) + devrev = self.read_data(self.device.syscfg_address + 1, 1) + self.logger.info("Device ID from pyupdi = '%02X%02X%02X' rev '%s'", devid[0], devid[1], devid[2], + chr(ord('A') + devrev[0])) + + def read_data(self, address, size): + """ + Reads a number of bytes of data from UPDI + :param address: address to write to + :param size: number of bytes to read + """ + return self.readwrite.read_data(address, size) + + def read_data_words(self, address, words): + """ + Reads a number of words of data from UPDI + :param address: address to write to + :param words: number of words to read + """ + return self.readwrite.read_data_words(address, words) + + def write_data_words(self, address, data): + """ + Writes a number of words to memory + :param address: address to write to + :param data: data to write + """ + return self.readwrite.write_data_words(address, data) + + def write_data(self, address, data): + """ + Writes a number of bytes to memory + :param address: address to write to + :param data: data to write + """ + return self.write_data(address, data) + + def in_prog_mode(self): + """ + Checks whether the NVM PROG flag is up + """ + if self.readwrite.read_cs(constants.UPDI_ASI_SYS_STATUS) & (1 << constants.UPDI_ASI_SYS_STATUS_NVMPROG): + return True + return False + + def wait_unlocked(self, timeout_ms): + """ + Waits for the device to be unlocked. + All devices boot up as locked until proven otherwise + :param timeout_ms: number of milliseconts to wait + """ + timeout = Timeout(timeout_ms) + + while not timeout.expired(): + if not self.readwrite.read_cs(constants.UPDI_ASI_SYS_STATUS) & ( + 1 << constants.UPDI_ASI_SYS_STATUS_LOCKSTATUS): + return True + + self.logger.error("Timeout waiting for device to unlock") + return False + + def unlock(self): + """ + Unlock by chip erase + """ + # Put in the key + self.readwrite.write_key(constants.UPDI_KEY_64, constants.UPDI_KEY_CHIPERASE) + + # Check key status + key_status = self.readwrite.read_cs(constants.UPDI_ASI_KEY_STATUS) + self.logger.debug("Key status = 0x%02X", key_status) + + if not key_status & (1 << constants.UPDI_ASI_KEY_STATUS_CHIPERASE): + raise PymcuprogError("Key not accepted") + + # Toggle reset + self.reset(apply_reset=True) + self.reset(apply_reset=False) + + # And wait for unlock + if not self.wait_unlocked(100): + raise PymcuprogError("Failed to chip erase using key") + + def enter_progmode(self): + """ + Enters into NVM programming mode + """ + # First check if NVM is already enabled + if self.in_prog_mode(): + self.logger.info("Already in NVM programming mode") + return True + + self.logger.info("Entering NVM programming mode") + + # Put in the key + self.readwrite.write_key(constants.UPDI_KEY_64, constants.UPDI_KEY_NVM) + + # Check key status + key_status = self.readwrite.read_cs(constants.UPDI_ASI_KEY_STATUS) + self.logger.debug("Key status = 0x%02X", key_status) + + if not key_status & (1 << constants.UPDI_ASI_KEY_STATUS_NVMPROG): + self.logger.error("Key status = 0x%02X", key_status) + raise IOError("Key not accepted") + + # Toggle reset + self.reset(apply_reset=True) + self.reset(apply_reset=False) + + # And wait for unlock + if not self.wait_unlocked(100): + raise IOError("Failed to enter NVM programming mode: device is locked") + + # Check for NVMPROG flag + if not self.in_prog_mode(): + raise IOError("Failed to enter NVM programming mode") + + self.logger.debug("Now in NVM programming mode") + return True + + def leave_progmode(self): + """ + Disables UPDI which releases any keys enabled + """ + self.logger.info("Leaving NVM programming mode") + self.reset(apply_reset=True) + self.reset(apply_reset=False) + self.readwrite.write_cs(constants.UPDI_CS_CTRLB, + (1 << constants.UPDI_CTRLB_UPDIDIS_BIT) | (1 << constants.UPDI_CTRLB_CCDETDIS_BIT)) + + def reset(self, apply_reset): + """ + Applies or releases an UPDI reset condition + :param apply_reset: True to apply, False to release + """ + if apply_reset: + self.logger.info("Apply reset") + self.readwrite.write_cs(constants.UPDI_ASI_RESET_REQ, constants.UPDI_RESET_REQ_VALUE) + else: + self.logger.info("Release reset") + self.readwrite.write_cs(constants.UPDI_ASI_RESET_REQ, 0x00) diff --git a/software/tools/pymcuprog/libs/pymcuprog/serialupdi/constants.py b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/constants.py new file mode 100644 index 0000000..4a834c0 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/constants.py @@ -0,0 +1,110 @@ +""" +UPDI protocol constants +""" +# UPDI commands and control definitions +UPDI_BREAK = 0x00 + +UPDI_LDS = 0x00 +UPDI_STS = 0x40 +UPDI_LD = 0x20 +UPDI_ST = 0x60 +UPDI_LDCS = 0x80 +UPDI_STCS = 0xC0 +UPDI_REPEAT = 0xA0 +UPDI_KEY = 0xE0 + +UPDI_PTR = 0x00 +UPDI_PTR_INC = 0x04 +UPDI_PTR_ADDRESS = 0x08 + +UPDI_ADDRESS_8 = 0x00 +UPDI_ADDRESS_16 = 0x04 +UPDI_ADDRESS_24 = 0x08 + +UPDI_DATA_8 = 0x00 +UPDI_DATA_16 = 0x01 +UPDI_DATA_24 = 0x02 + +UPDI_KEY_SIB = 0x04 +UPDI_KEY_KEY = 0x00 + +UPDI_KEY_64 = 0x00 +UPDI_KEY_128 = 0x01 +UPDI_KEY_256 = 0x02 + +UPDI_SIB_8BYTES = UPDI_KEY_64 +UPDI_SIB_16BYTES = UPDI_KEY_128 +UPDI_SIB_32BYTES = UPDI_KEY_256 + +UPDI_REPEAT_BYTE = 0x00 +UPDI_REPEAT_WORD = 0x01 + +UPDI_PHY_SYNC = 0x55 +UPDI_PHY_ACK = 0x40 + +UPDI_MAX_REPEAT_SIZE = (0xFF+1) # Repeat counter of 1-byte, with off-by-one counting + +# CS and ASI Register Address map +UPDI_CS_STATUSA = 0x00 +UPDI_CS_STATUSB = 0x01 +UPDI_CS_CTRLA = 0x02 +UPDI_CS_CTRLB = 0x03 +UPDI_ASI_KEY_STATUS = 0x07 +UPDI_ASI_RESET_REQ = 0x08 +UPDI_ASI_CTRLA = 0x09 +UPDI_ASI_SYS_CTRLA = 0x0A +UPDI_ASI_SYS_STATUS = 0x0B +UPDI_ASI_CRC_STATUS = 0x0C + +UPDI_CTRLA_IBDLY_BIT = 7 +UPDI_CTRLB_CCDETDIS_BIT = 3 +UPDI_CTRLB_UPDIDIS_BIT = 2 + +UPDI_KEY_NVM = b"NVMProg " +UPDI_KEY_CHIPERASE = b"NVMErase" + +UPDI_ASI_STATUSA_REVID = 4 +UPDI_ASI_STATUSB_PESIG = 0 + +UPDI_ASI_KEY_STATUS_CHIPERASE = 3 +UPDI_ASI_KEY_STATUS_NVMPROG = 4 +UPDI_ASI_KEY_STATUS_UROWWRITE = 5 + +UPDI_ASI_SYS_STATUS_RSTSYS = 5 +UPDI_ASI_SYS_STATUS_INSLEEP = 4 +UPDI_ASI_SYS_STATUS_NVMPROG = 3 +UPDI_ASI_SYS_STATUS_UROWPROG = 2 +UPDI_ASI_SYS_STATUS_LOCKSTATUS = 0 + +UPDI_RESET_REQ_VALUE = 0x59 + +# FLASH CONTROLLER +UPDI_NVMCTRL_CTRLA = 0x00 +UPDI_NVMCTRL_CTRLB = 0x01 +UPDI_NVMCTRL_STATUS = 0x02 +UPDI_NVMCTRL_INTCTRL = 0x03 +UPDI_NVMCTRL_INTFLAGS = 0x04 +UPDI_NVMCTRL_DATAL = 0x06 +UPDI_NVMCTRL_DATAH = 0x07 +UPDI_NVMCTRL_ADDRL = 0x08 +UPDI_NVMCTRL_ADDRH = 0x09 + +# NVMCTRL v0 CTRLA +UPDI_V0_NVMCTRL_CTRLA_NOP = 0x00 +UPDI_V0_NVMCTRL_CTRLA_WRITE_PAGE = 0x01 +UPDI_V0_NVMCTRL_CTRLA_ERASE_PAGE = 0x02 +UPDI_V0_NVMCTRL_CTRLA_ERASE_WRITE_PAGE = 0x03 +UPDI_V0_NVMCTRL_CTRLA_PAGE_BUFFER_CLR = 0x04 +UPDI_V0_NVMCTRL_CTRLA_CHIP_ERASE = 0x05 +UPDI_V0_NVMCTRL_CTRLA_ERASE_EEPROM = 0x06 +UPDI_V0_NVMCTRL_CTRLA_WRITE_FUSE = 0x07 + +# NVMCTRL v1 CTRLA +UPDI_V1_NVMCTRL_CTRLA_NOCMD = 0x00 +UPDI_V1_NVMCTRL_CTRLA_FLASH_WRITE = 0x02 +UPDI_V1_NVMCTRL_CTRLA_EEPROM_ERASE_WRITE = 0x13 +UPDI_V1_NVMCTRL_CTRLA_CHIP_ERASE = 0x20 + +UPDI_NVM_STATUS_WRITE_ERROR = 2 +UPDI_NVM_STATUS_EEPROM_BUSY = 1 +UPDI_NVM_STATUS_FLASH_BUSY = 0 diff --git a/software/tools/pymcuprog/libs/pymcuprog/serialupdi/link.py b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/link.py new file mode 100644 index 0000000..52b3273 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/link.py @@ -0,0 +1,431 @@ +""" +Link layer in UPDI protocol stack +""" +from logging import getLogger + +from pymcuprog.pymcuprog_errors import PymcuprogError +from . import constants + +class UpdiDatalink: + """ + UPDI data link class handles the UPDI data protocol within the device + """ + + LDCS_RESPONSE_BYTES = 1 + + def __init__(self): + self.logger = getLogger(__name__) + self.updi_phy = None + + def set_physical(self, physical): + """ + Inject a serial-port based physical layer for use by this DL + """ + self.updi_phy = physical + + def _init_session_parameters(self): + """ + Set the inter-byte delay bit and disable collision detection + """ + self.stcs(constants.UPDI_CS_CTRLB, 1 << constants.UPDI_CTRLB_CCDETDIS_BIT) + self.stcs(constants.UPDI_CS_CTRLA, 0x06) + + def init_datalink(self): + """ + Init DL layer + """ + self._init_session_parameters() + # Check + if not self._check_datalink(): + # Send double break if all is not well, and re-check + self.updi_phy.send_double_break() + self._init_session_parameters() + if not self._check_datalink(): + raise PymcuprogError("UPDI initialisation failed") + + def change_baud(self, baud): + if self.updi_phy is not None: + self.stcs(constants.UPDI_CS_CTRLA, 0x06) + if baud <= 115200: + self.stcs(constants.UPDI_ASI_CTRLA, 0x03) + elif baud > 230400: + self.stcs(constants.UPDI_ASI_CTRLA, 0x01) + else: + self.stcs(constants.UPDI_ASI_CTRLA, 0x02) + self.updi_phy.change_baud(baud) + + def _check_datalink(self): + """ + Check UPDI by loading CS STATUSA + """ + try: + if self.ldcs(constants.UPDI_CS_STATUSA) != 0: + self.logger.info("UPDI init OK") + return True + except PymcuprogError: + self.logger.warning("Check failed") + return False + self.logger.info("UPDI not OK - reinitialisation required") + return False + + def ldcs(self, address): + """ + Load data from Control/Status space + :param address: address to load + """ + self.logger.debug("LDCS from 0x%02X", address) + self.updi_phy.send([constants.UPDI_PHY_SYNC, constants.UPDI_LDCS | (address & 0x0F)]) + response = self.updi_phy.receive(self.LDCS_RESPONSE_BYTES) + numbytes_received = len(response) + if numbytes_received != self.LDCS_RESPONSE_BYTES: + raise PymcuprogError("Unexpected number of bytes in response: " + "{} byte(s) expected {} byte(s)".format(numbytes_received, self.LDCS_RESPONSE_BYTES)) + + return response[0] + + def stcs(self, address, value): + """ + Store a value to Control/Status space + :param address: address to store to + :param value: value to write + """ + self.logger.debug("STCS to 0x%02X", address) + self.updi_phy.send([constants.UPDI_PHY_SYNC, constants.UPDI_STCS | (address & 0x0F), value]) + + def ld_ptr_inc(self, size): + """ + Loads a number of bytes from the pointer location with pointer post-increment + :param size: number of bytes to load + :return: values read + """ + self.logger.debug("LD8 from ptr++") + self.updi_phy.send([constants.UPDI_PHY_SYNC, constants.UPDI_LD | constants.UPDI_PTR_INC | + constants.UPDI_DATA_8]) + return self.updi_phy.receive(size) + + def ld_ptr_inc16(self, words): + """ + Load a 16-bit word value from the pointer location with pointer post-increment. + For improved performance of serialupdi for Arduino, send the REP instruction in the same command as LD + :param words: number of words to load + :return: values read + """ + self.logger.debug("LD16 from ptr++") + # combine REP, words with ld *ptr++ + self.updi_phy.send([constants.UPDI_PHY_SYNC, constants.UPDI_REPEAT | constants.UPDI_REPEAT_BYTE, + (words - 1) & 0xFF, constants.UPDI_PHY_SYNC, constants.UPDI_LD | constants.UPDI_PTR_INC | + constants.UPDI_DATA_16]) + return self.updi_phy.receive(words << 1) + + def st_ptr_inc(self, data): + """ + Store data to the pointer location with pointer post-increment + :param data: data to store + """ + self.logger.debug("ST8 to *ptr++") + self.updi_phy.send([constants.UPDI_PHY_SYNC, constants.UPDI_ST | constants.UPDI_PTR_INC | constants.UPDI_DATA_8, + data[0]]) + response = self.updi_phy.receive(1) + + if len(response) != 1 or response[0] != constants.UPDI_PHY_ACK: + raise PymcuprogError("ACK error with st_ptr_inc") + + num = 1 + while num < len(data): + self.updi_phy.send([data[num]]) + response = self.updi_phy.receive(1) + + if len(response) != 1 or response[0] != constants.UPDI_PHY_ACK: + raise PymcuprogError("Error with st_ptr_inc") + num += 1 + + def st_ptr_inc16(self, data): + """ + Store a 16-bit word value to the pointer location with pointer post-increment + :param data: data to store + """ + self.logger.debug("ST16 to *ptr++") + self.updi_phy.send([constants.UPDI_PHY_SYNC, constants.UPDI_ST | constants.UPDI_PTR_INC | + constants.UPDI_DATA_16, data[0], data[1]]) + response = self.updi_phy.receive(1) + + if len(response) != 1 or response[0] != constants.UPDI_PHY_ACK: + raise PymcuprogError("ACK error with st_ptr_inc16") + + num = 2 + while num < len(data): + self.updi_phy.send([data[num], data[num + 1]]) + response = self.updi_phy.receive(1) + + if len(response) != 1 or response[0] != constants.UPDI_PHY_ACK: + raise PymcuprogError("Error with st_ptr_inc16") + num += 2 + + def st_ptr_inc16_RSD(self, data, blocksize): + """ + Store a 16-bit word value to the pointer location with pointer post-increment + :param data: data to store + :blocksize: max number of bytes being sent, None for all. + Warning: This does not strictly honor blocksize for values < 6 + We always glob together the STCS(RSD) and REP commands. + But this should pose no problems for compatibility, because your serial adapter can't deal with 6b chunks, + none of pymcuprog would work! + """ + self.logger.debug("ST16 to *ptr++ with RSD, data length: 0x%03X in blocks of: %d", len(data), blocksize) + + #for performance we glob everything together into one USB transfer.... + repnumber= ((len(data) >> 1) -1) + data = [*data, *[constants.UPDI_PHY_SYNC, constants.UPDI_STCS | constants.UPDI_CS_CTRLA, 0x06]] + + if blocksize is None: + # Send whole thing at once stcs + repeat + st + (data + stcs) + blocksize = 3 + 3 + 2 + len(data) + num = 0 + firstpacket = [] + if blocksize < 10 : + # very small block size - we send pair of 2-byte commands first. + firstpacket = [*[constants.UPDI_PHY_SYNC, constants.UPDI_STCS | constants.UPDI_CS_CTRLA, 0x0E], + *[constants.UPDI_PHY_SYNC, constants.UPDI_REPEAT | constants.UPDI_REPEAT_BYTE, (repnumber & 0xFF)]] + data = [*[constants.UPDI_PHY_SYNC, constants.UPDI_ST | constants.UPDI_PTR_INC |constants.UPDI_DATA_16], *data] + num = 0 + else: + firstpacket = [*[constants.UPDI_PHY_SYNC, constants.UPDI_STCS | constants.UPDI_CS_CTRLA , 0x0E], + *[constants.UPDI_PHY_SYNC, constants.UPDI_REPEAT | constants.UPDI_REPEAT_BYTE, (repnumber & 0xFF)], + *[constants.UPDI_PHY_SYNC, constants.UPDI_ST | constants.UPDI_PTR_INC | constants.UPDI_DATA_16], + *data[:blocksize - 8]] + num = blocksize - 8 + if len(firstpacket) == 64 and blocksize != 64: + firstpacket = firstpacket[:32] + num = 32-8 + # workaround bug in D11C as serial adapter compiled with the USB implementation used in the mattairtech core; + # this chokes on any block of exactly (!!) 64 bytes. Nobody seems to understand the reason for this bizzare issue. + # The D11C as serial adapter is important because the fablab at MIT uses them heavilly, and wishes to upload Arduino sketches to tinyAVR 0/1/2-series + # and AVR-Dx-series parts with them. It was desirable from their perspective to have an more accessible firmware (like that Arduino one) as opposed + # to a pure-C one. Hence, a workaround is implemented to avoid triggering it. Thankfully, 64-byte blocks being written are not as natural as one might + # expect for a power-of-two, since we combine the data with the commands on either side. + # This workaround will only be invoked under unusual conditions, specifically if one of these is true: + # A. The last page of the hex file has a length of 53 bytes exactly OR + # B. The last page of the hex file has a length modulo the write chunk size, of 53 bytes exactly OR + # C. A write chunk is specified which is exactly 53 bytes shorter than the page OR + # D. The write chunk is specified as 153 when writing to a part with a page size of 512 OR + # E. Situations like D in the event that a future product permits REPEAT with 2 bytes of data to support pages larger than 512b. + # Conditions C-E will invoke it on the last chunk of every page; For E, here are 6 cursed numbers for 1024b pages with 2 byte repeats, and 2 for 2048b pages + # (in addition to pagelength - 52), however, there is no specific reason to expect such a part will be made. In any event, for those conditions, the + # performance impact is on the order of 1-4ms per page, the same as the the penalty for each chunk that a write is divided into, hence the speed penalty of + # using that write chunk size will be (1-4ms * ceil(page size/chunk size) + 1 instead of 1-4ms * ceil(page size/chunk size), which is always smaller than the + # penalty already being accepted for the write chunking. + # Conditions A and B will happen at most once per upload; thus the performance penalty would be acceptable even if they happened frequently. However + # avr-gcc rarely, if ever, generates odd size hex files. I was not able to get it to by tweaking the sketch I was compiling, so they will occur on + # considerably less than 1/64th of the time, if it is even possible for avr-gcc to generate such a file, which is unclear. + # In summary, the performance impact is small but noticable in remote corner cases (where chunk size is chosen randomly, or intentionally in an effort to provoke + # this bug, and is negligible (at worst 4 ms for 1 out of 32 uploads, assuming upload size modulo page size are evenly distributed and even ) in unlikely cases + # (requiring an odd write chunk size such that B could be provoked from an even-length hex file) as well as -possibly- case A if there is indeed a programming + # construct that results in a non-even length hex file. It is (barely) worth noting that for a hypothetical part that used a 2 byte REPEAT argument, this could + # be provoked with an even sketch size, and so would impose a penalty of less than 4ms on 1 out of 32 uploads. + # In light of the fact write chunking is intended as a workaround for an ill-mannered serial adapter in the first place (ex: HT42 workaround in DxCore), this + # performance impact is not a concern. + # If a write chunk size of 64 is specified, we will not activate this workaround. + # -Spence 6/29/21 + self.updi_phy.send( firstpacket ) + # if finite block size, this is used. + while num < len(data): + data_slice = data[num:num+blocksize] + if len(data_slice) == 64 and blocksize != 64: + data_slice=data[num:num+32] # workaround as above. + self.updi_phy.send(data_slice) + num += len(data_slice) + + def repeat(self, repeats): + """ + Store a value to the repeat counter + :param repeats: number of repeats requested + """ + self.logger.debug("Repeat %d", repeats) + if (repeats - 1) > constants.UPDI_MAX_REPEAT_SIZE: + self.logger.error("Invalid repeat count of %d", repeats) + raise Exception("Invalid repeat count!") + repeats -= 1 + self.updi_phy.send([constants.UPDI_PHY_SYNC, constants.UPDI_REPEAT | constants.UPDI_REPEAT_BYTE, + repeats & 0xFF]) + + def read_sib(self): + """ + Read the SIB + """ + return self.updi_phy.sib() + + def key(self, size, key): + """ + Write a key + :param size: size of key (0=64B, 1=128B, 2=256B) + :param key: key value + """ + self.logger.debug("Writing key") + if len(key) != 8 << size: + raise PymcuprogError("Invalid KEY length!") + self.updi_phy.send([constants.UPDI_PHY_SYNC, constants.UPDI_KEY | constants.UPDI_KEY_KEY | size]) + self.updi_phy.send(list(reversed(list(key)))) + + def _st_data_phase(self, values): + """ + Performs data phase of transaction: + receive ACK + send data + :param values: bytearray of value(s) to send + """ + response = self.updi_phy.receive(1) + if len(response) != 1 or response[0] != constants.UPDI_PHY_ACK: + raise PymcuprogError("Error with st") + + self.updi_phy.send(values) + response = self.updi_phy.receive(1) + if len(response) != 1 or response[0] != constants.UPDI_PHY_ACK: + raise PymcuprogError("Error with st") + + +class UpdiDatalink16bit(UpdiDatalink): + """ + UPDI data link layer in 16-bit version + This means that all addresses and pointers contain 2 bytes + """ + + def __init__(self): + UpdiDatalink.__init__(self) + self.logger = getLogger(__name__) + + # pylint: disable=invalid-name + def ld(self, address): + """ + Load a single byte direct from a 16-bit address + :param address: address to load from + :return: value read + """ + self.logger.info("LD from 0x{0:06X}".format(address)) + self.updi_phy.send( + [constants.UPDI_PHY_SYNC, constants.UPDI_LDS | constants.UPDI_ADDRESS_16 | constants.UPDI_DATA_8, + address & 0xFF, (address >> 8) & 0xFF]) + return self.updi_phy.receive(1)[0] + + def ld16(self, address): + """ + Load a 16-bit word directly from a 16-bit address + :param address: address to load from + :return: values read + """ + self.logger.info("LD from 0x{0:06X}".format(address)) + self.updi_phy.send( + [constants.UPDI_PHY_SYNC, constants.UPDI_LDS | constants.UPDI_ADDRESS_16 | constants.UPDI_DATA_16, + address & 0xFF, (address >> 8) & 0xFF]) + return self.updi_phy.receive(2) + + # pylint: disable=invalid-name + def st(self, address, value): + """ + Store a single byte value directly to a 16-bit address + :param address: address to write to + :param value: value to write + """ + self.logger.info("ST to 0x{0:06X}".format(address)) + self.updi_phy.send( + [constants.UPDI_PHY_SYNC, constants.UPDI_STS | constants.UPDI_ADDRESS_16 | constants.UPDI_DATA_8, + address & 0xFF, (address >> 8) & 0xFF]) + return self._st_data_phase([value & 0xFF]) + + def st16(self, address, value): + """ + Store a 16-bit word value directly to a 16-bit address + :param address: address to write to + :param value: value to write + """ + self.logger.info("ST to 0x{0:06X}".format(address)) + self.updi_phy.send( + [constants.UPDI_PHY_SYNC, constants.UPDI_STS | constants.UPDI_ADDRESS_16 | constants.UPDI_DATA_16, + address & 0xFF, (address >> 8) & 0xFF]) + return self._st_data_phase([value & 0xFF, (value >> 8) & 0xFF]) + + def st_ptr(self, address): + """ + Set the pointer location + :param address: address to write + """ + self.logger.info("ST to ptr") + self.updi_phy.send( + [constants.UPDI_PHY_SYNC, constants.UPDI_ST | constants.UPDI_PTR_ADDRESS | constants.UPDI_DATA_16, + address & 0xFF, (address >> 8) & 0xFF]) + response = self.updi_phy.receive(1) + if len(response) != 1 or response[0] != constants.UPDI_PHY_ACK: + raise PymcuprogError("Error with st_ptr") + + +class UpdiDatalink24bit(UpdiDatalink): + """ + UPDI data link layer in 24-bit version + This means that all addresses and pointers contain 3 bytes + """ + + def __init__(self): + UpdiDatalink.__init__(self) + self.logger = getLogger(__name__) + + # pylint: disable=invalid-name + def ld(self, address): + """ + Load a single byte direct from a 24-bit address + :param address: address to load from + :return: value read + """ + self.logger.info("LD from 0x{0:06X}".format(address)) + self.updi_phy.send( + [constants.UPDI_PHY_SYNC, constants.UPDI_LDS | constants.UPDI_ADDRESS_24 | constants.UPDI_DATA_8, + address & 0xFF, (address >> 8) & 0xFF, (address >> 16) & 0xFF]) + return self.updi_phy.receive(1)[0] + + def ld16(self, address): + """ + Load a 16-bit word directly from a 24-bit address + :param address: address to load from + :return: values read + """ + self.logger.info("LD from 0x{0:06X}".format(address)) + self.updi_phy.send( + [constants.UPDI_PHY_SYNC, constants.UPDI_LDS | constants.UPDI_ADDRESS_24 | constants.UPDI_DATA_16, + address & 0xFF, (address >> 8) & 0xFF, (address >> 16) & 0xFF]) + return self.updi_phy.receive(2) + + # pylint: disable=invalid-name + def st(self, address, value): + """ + Store a single byte value directly to a 24-bit address + :param address: address to write to + :param value: value to write + """ + self.logger.info("ST to 0x{0:06X}".format(address)) + self.updi_phy.send( + [constants.UPDI_PHY_SYNC, constants.UPDI_STS | constants.UPDI_ADDRESS_24 | constants.UPDI_DATA_8, + address & 0xFF, (address >> 8) & 0xFF, (address >> 16) & 0xFF]) + return self._st_data_phase([value & 0xFF]) + + def st16(self, address, value): + """ + Store a 16-bit word value directly to a 24-bit address + :param address: address to write to + :param value: value to write + """ + self.logger.info("ST to 0x{0:06X}".format(address)) + self.updi_phy.send( + [constants.UPDI_PHY_SYNC, constants.UPDI_STS | constants.UPDI_ADDRESS_24 | constants.UPDI_DATA_16, + address & 0xFF, (address >> 8) & 0xFF, (address >> 16) & 0xFF]) + return self._st_data_phase([value & 0xFF, (value >> 8) & 0xFF]) + + def st_ptr(self, address): + """ + Set the pointer location + :param address: address to write + """ + self.logger.info("ST to ptr") + self.updi_phy.send( + [constants.UPDI_PHY_SYNC, constants.UPDI_ST | constants.UPDI_PTR_ADDRESS | constants.UPDI_DATA_24, + address & 0xFF, (address >> 8) & 0xFF, (address >> 16) & 0xFF]) + response = self.updi_phy.receive(1) + if len(response) != 1 or response[0] != constants.UPDI_PHY_ACK: + raise PymcuprogError("Error with st_ptr") diff --git a/software/tools/pymcuprog/libs/pymcuprog/serialupdi/nvm.py b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/nvm.py new file mode 100644 index 0000000..f96320a --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/nvm.py @@ -0,0 +1,322 @@ +""" +NVM implementations on various UPDI device families +""" +from logging import getLogger +from pymcuprog.pymcuprog_errors import PymcuprogError +from . import constants +from .timeout import Timeout +from time import sleep + +class NvmUpdi(object): + """ + Base class for NVM + """ + + def __init__(self, readwrite, device): + self.logger = getLogger(__name__) + self.readwrite = readwrite + self.device = device + + def chip_erase(self): + """ + Does a chip erase using the NVM controller + """ + raise NotImplementedError("NVM stack not ready") + + def write_flash(self, address, data): + """ + Writes data to flash + :param address: address to write to + :param data: data to write + """ + raise NotImplementedError("NVM stack not ready") + + def write_eeprom(self, address, data): + """ + Write data to EEPROM + :param address: address to write to + :param data: data to write + """ + raise NotImplementedError("NVM stack not ready") + + def write_fuse(self, address, data): + """ + Writes one fuse value + :param address: address to write to + :param data: data to write + """ + raise NotImplementedError("NVM stack not ready") + + def wait_flash_ready(self): + """ + Waits for the NVM controller to be ready + """ + timeout = Timeout(10000) # 10 sec timeout, just to be sure + + self.logger.debug("Wait flash ready") + while not timeout.expired(): + status = self.readwrite.read_byte(self.device.nvmctrl_address + constants.UPDI_NVMCTRL_STATUS) + if status & (1 << constants.UPDI_NVM_STATUS_WRITE_ERROR): + self.logger.error("NVM error") + return False + + if not status & ((1 << constants.UPDI_NVM_STATUS_EEPROM_BUSY) | + (1 << constants.UPDI_NVM_STATUS_FLASH_BUSY)): + return True + + self.logger.error("Wait flash ready timed out") + return False + + def execute_nvm_command(self, command): + """ + Executes an NVM COMMAND on the NVM CTRL + :param command: command to execute + """ + self.logger.debug("NVMCMD %d executing", command) + return self.readwrite.write_byte(self.device.nvmctrl_address + constants.UPDI_NVMCTRL_CTRLA, command) + + +class NvmUpdiTinyMega(NvmUpdi): + """ + AKA Version 0 UPDI NVM + Present on, for example, tiny817 -> mega4809 + """ + + def __init__(self, readwrite, device): + NvmUpdi.__init__(self, readwrite, device) + self.logger = getLogger(__name__) + + def chip_erase(self): + """ + Does a chip erase using the NVM controller + + Note that on locked devices this is not possible + and the ERASE KEY has to be used instead, see the unlock method + """ + self.logger.info("Chip erase using NVM CTRL") + + # Wait until NVM CTRL is ready to erase + if not self.wait_flash_ready(): + raise IOError("Timeout waiting for flash ready before erase ") + + # Erase + self.execute_nvm_command(constants.UPDI_V0_NVMCTRL_CTRLA_CHIP_ERASE) + + # And wait for it + if not self.wait_flash_ready(): + raise IOError("Timeout waiting for flash ready after erase") + + return True + + def write_flash(self, address, data, blocksize=2, bulkwrite=0, pagewrite_delay=0): + """ + Writes data to flash (v0) + :param address: address to write to + :param data: data to write + """ + return self.write_nvm(address, data, use_word_access=True, blocksize=blocksize, bulkwrite=bulkwrite, pagewrite_delay=pagewrite_delay) + + def write_eeprom(self, address, data): + """ + Write data to EEPROM (v0) + :param address: address to write to + :param data: data to write + """ + return self.write_nvm(address, data, use_word_access=False, + nvmcommand=constants.UPDI_V0_NVMCTRL_CTRLA_ERASE_WRITE_PAGE) + + def write_fuse(self, address, data): + """ + Writes one fuse value (v0) + :param address: address to write to + :param data: data to write + """ + + # Check that NVM controller is ready + if not self.wait_flash_ready(): + raise PymcuprogError("Timeout waiting for flash ready before page buffer clear ") + + # Write address to NVMCTRL ADDR + self.logger.debug("Load NVM address") + self.readwrite.write_byte(self.device.nvmctrl_address + constants.UPDI_NVMCTRL_ADDRL, address & 0xFF) + self.readwrite.write_byte(self.device.nvmctrl_address + constants.UPDI_NVMCTRL_ADDRH, (address >> 8) & 0xFF) + + # Write data + self.logger.debug("Load fuse data") + self.readwrite.write_byte(self.device.nvmctrl_address + constants.UPDI_NVMCTRL_DATAL, data[0] & 0xFF) + + # Execute + self.logger.debug("Execute fuse write") + self.execute_nvm_command(constants.UPDI_V0_NVMCTRL_CTRLA_WRITE_FUSE) + + if not self.wait_flash_ready(): + raise PymcuprogError("Timeout waiting for flash ready before page buffer clear ") + + def write_nvm(self, address, data, use_word_access, nvmcommand=constants.UPDI_V0_NVMCTRL_CTRLA_WRITE_PAGE, + blocksize=2, bulkwrite=0, pagewrite_delay=0): + """ + Writes a page of data to NVM (v0) + + By default the PAGE_WRITE command is used, which + requires that the page is already erased. + By default word access is used (flash) + :param address: address to write to + :param data: data to write + :param use_word_access: write whole words? + :param nvmcommand: command to use for commit + :param bulkwrite: Passed down from nvmserialupdi 0 = normal or single write. + 1 means it's part of writing the whole flash. + In that case we only st ptr if address = 0. + :param pagewrite_delay: (ms) delay before pagewrite + + """ + + # unless we are in a bulk (whole flash) write, in which case we skip almost everything. + if (bulkwrite == 0 ) or address == 0x8000 or address == 0x4000 or not use_word_access: + # Check that NVM controller is ready + # I will grudgingly check this at the very start. I am extremely skeptical about the usefulness of this test. + # If it's not ready, they'll get another error will they not? Every command like this costs about a half second + # on every upload when using serialupdi - at any bsaud rate, assuming 256 pages. It's all USB latency. + if not self.wait_flash_ready(): + raise PymcuprogError("Timeout waiting for flash ready before page buffer clear ") + # Clear the page buffer + self.logger.debug("Clear page buffer") + self.execute_nvm_command(constants.UPDI_V0_NVMCTRL_CTRLA_PAGE_BUFFER_CLR) + + # Wait for NVM controller to be ready + if not self.wait_flash_ready(): + raise PymcuprogError("Timeout waiting for flash ready after page buffer clear") + + # Load the page buffer by writing directly to location + if use_word_access: + self.readwrite.write_data_words(address, data, blocksize) + else: + self.readwrite.write_data(address, data) + + # Write the page to NVM, maybe erase first + self.logger.debug("Committing data") + + self.execute_nvm_command(nvmcommand) + + if pagewrite_delay > 0: + sleep(pagewrite_delay/1000.0) + # SACRIFICES SPEED FOR COMPATIBILITY - above line should execute only when --pagepause command line parameter is 1 or more (default 0), so we can adjust it externally + # it should sleep for that many milliseconds (the granularity of this is low enough enough that 0.001 vs 0.005 makes no difference in my testing) + # I couldn't propagate it through this mess, and I really tried, because it is a 2:1 performance hit on CH340 on some parts, which is brutal, but it breaks too many adapters to not have it + # this should only ever happen for tinyAVR/megaAVR, NEVER Dx-series parts. + if not bulkwrite == 1: + # do a final NVM status check only if not doing a bulk write, or after the last chunk (when bulkwrite = 2) + # not doing this every page made uploads about 15% faster + if not self.wait_flash_ready(): + raise PymcuprogError("Timeout waiting for flash ready after page write ") + + +class NvmUpdiAvrDx(NvmUpdi): + """ + AKA Version 1 UPDI NVM + Present on, for example, AVR-DA and newer + """ + + def __init__(self, readwrite, device): + NvmUpdi.__init__(self, readwrite, device) + self.logger = getLogger(__name__) + + def chip_erase(self): + """ + Does a chip erase using the NVM controller + Note that on locked devices this it not possible + and the ERASE KEY has to be used instead + """ + self.logger.info("Chip erase using NVM CTRL") + + # Wait until NVM CTRL is ready to erase + if not self.wait_flash_ready(): + raise Exception("Timeout waiting for flash ready before erase ") + + # Erase + self.execute_nvm_command(constants.UPDI_V1_NVMCTRL_CTRLA_CHIP_ERASE) + + # And wait for it + if not self.wait_flash_ready(): + raise Exception("Timeout waiting for flash ready after erase") + + return True + + def write_flash(self, address, data, blocksize=2, bulkwrite=0, pagewrite_delay=0): + """ + Writes data to flash (v1) + :param address: address to write to + :param data: data to write + :return: + """ + return self.write_nvm(address, data, use_word_access=True, blocksize=blocksize, bulkwrite=bulkwrite, pagewrite_delay=pagewrite_delay) + + def write_eeprom(self, address, data): + """ + Writes data to NVM (EEPROM) + :param address: address to write to + :param data: data to write + """ + nvm_command = constants.UPDI_V1_NVMCTRL_CTRLA_EEPROM_ERASE_WRITE + + # Check that NVM controller is ready + if not self.wait_flash_ready(): + raise Exception("Timeout waiting for NVM ready before command write") + + # Write the command to the NVM controller + self.logger.info("NVM EEPROM erase/write command") + self.execute_nvm_command(nvm_command) + + # Write the data + self.readwrite.write_data(address, data) + + # Wait for NVM controller to be ready again + if not self.wait_flash_ready(): + raise Exception("Timeout waiting for NVM ready after data write") + + # Remove command from NVM controller + self.logger.info("Clear NVM command") + self.execute_nvm_command(constants.UPDI_V1_NVMCTRL_CTRLA_NOCMD) + + def write_fuse(self, address, data): + """ + Writes one fuse value + V1 fuses are EEPROM-based + :param address: address to write to + :param data: data to write + """ + return self.write_eeprom(address, data) + + def write_nvm(self, address, data, use_word_access, blocksize=2, bulkwrite=0, pagewrite_delay=0): + """ + Writes data to NVM (version 1) + This version of the NVM block has no page buffer, so words are written directly. + :param address: address to write to + :param data: data to write + :param use_word_access: write in whole words? + """ + nvm_command = constants.UPDI_V1_NVMCTRL_CTRLA_FLASH_WRITE + + if bulkwrite == 0 or address == 0x800000: + # Check that NVM controller is ready + if not self.wait_flash_ready(): + raise Exception("Timeout waiting for flash ready before page buffer clear ") + + # Write the command to the NVM controller + self.logger.info("NVM write command") + self.execute_nvm_command(nvm_command) + + # Write the data + if use_word_access: + self.readwrite.write_data_words(address, data, blocksize) + else: + self.readwrite.write_data(address, data) + + # Wait for NVM controller to be ready again + if bulkwrite != 1: + if not self.wait_flash_ready(): + raise Exception("Timeout waiting for flash ready after data write") + + # Remove command from NVM controller + self.logger.info("Clear NVM command") + self.execute_nvm_command(constants.UPDI_V1_NVMCTRL_CTRLA_NOCMD) diff --git a/software/tools/pymcuprog/libs/pymcuprog/serialupdi/physical.py b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/physical.py new file mode 100644 index 0000000..6470748 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/physical.py @@ -0,0 +1,150 @@ +""" +Serial driver for UPDI stack +""" +import time +from logging import getLogger +import serial +from serial.serialutil import SerialException + +from . import constants + + +class UpdiPhysical: + """ + PDI physical driver using a given serial port at a given baud + """ + + def __init__(self, port, baud=115200): + """ + Initialise the serial port + """ + self.logger = getLogger(__name__) + + # Inter-byte delay + self.ibdly = 0.0001 + self.port = port + self.baud = baud + self.ser = None + + self.initialise_serial(self.port, self.baud) + + # send an initial break as handshake + self.send([constants.UPDI_BREAK]) + + def change_baud(self, newbaud): + self.ser.baudrate = newbaud + + def initialise_serial(self, port, baud): + """ + Standard serial port initialisation + :param port: serial port to use + :param baud: baud rate + """ + self.logger.info("Opening port '%s' at '%d' baud", port, baud) + try: + self.ser = serial.Serial(None, baud, parity=serial.PARITY_EVEN, timeout=1, stopbits=serial.STOPBITS_TWO) + self.ser.port = port + self.ser.dtr = False + self.ser.rts = False + self.ser.open() + except SerialException: + self.logger.error("Unable to open serial port '%s'", port) + raise + + def _loginfo(self, msg, data): + if data and isinstance(data[0], str): + i_data = [ord(x) for x in data] + else: + i_data = data + data_str = "[" + ", ".join([hex(x) for x in i_data]) + "]" + self.logger.debug("%s : %s", msg, data_str) + + def send_double_break(self): + """ + Sends a double break to reset the UPDI port + + BREAK is actually just a slower zero frame + A double break is guaranteed to push the UPDI state + machine into a known state, albeit rather brutally + """ + + self.logger.info("Sending double break") + + # Re-init at a lower baud + # At 300 bauds, the break character will pull the line low for 30ms + # Which is slightly above the recommended 24.6ms + self.ser.close() + temporary_serial = serial.Serial(None, 300, parity=serial.PARITY_EVEN, timeout=1, + stopbits=serial.STOPBITS_ONE) + temporary_serial.port = self.port + temporary_serial.dtr = False + temporary_serial.rts = False + temporary_serial.open() + + # Send two break characters, with 1 stop bit in between + temporary_serial.write([constants.UPDI_BREAK]) + + # Wait for the double break end + temporary_serial.read(1) + + time.sleep(0.1) + + # Send two break characters, with 1 stop bit in between + temporary_serial.write([constants.UPDI_BREAK]) + + # Wait for the double break end + temporary_serial.read(1) + + # Re-init at the real baud + temporary_serial.close() + self.initialise_serial(self.port, self.baud) + + def send(self, command): + """ + Sends a char array to UPDI with NO inter-byte delay + Note that the byte will echo back + """ + self.logger.info("send %d bytes", len(command)) + self._loginfo("data: ", command) + + self.ser.write(command) + # it will echo back. + echo = self.ser.read(len(command)) + + def receive(self, size): + """ + Receives a frame of a known number of chars from UPDI + :param size: bytes to receive + """ + response = bytearray() + timeout = 1 + + # For each byte + while size and timeout: + + # Read + character = self.ser.read() + + # Anything in? + if character: + response.append(ord(character)) + size -= 1 + else: + timeout -= 1 + + self._loginfo("receive", response) + return response + + def sib(self): + """ + System information block is just a string coming back from a SIB command + """ + self.send([ + constants.UPDI_PHY_SYNC, + constants.UPDI_KEY | constants.UPDI_KEY_SIB | constants.UPDI_SIB_32BYTES]) + return self.ser.readline() + + def __del__(self): + if self.ser: + self.logger.info("Closing port '%s'", self.port) + self.ser.close() diff --git a/software/tools/pymcuprog/libs/pymcuprog/serialupdi/readwrite.py b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/readwrite.py new file mode 100644 index 0000000..5265af8 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/readwrite.py @@ -0,0 +1,160 @@ +""" +Read/write access provider for UPDI +""" +from logging import getLogger +from pymcuprog.pymcuprog_errors import PymcuprogError +from . import constants + + +class UpdiReadWrite(object): + """ + Provides various forms of reads and writes for UPDI applications + Makes us of the datalink provided + """ + + def __init__(self, datalink): + self.logger = getLogger(__name__) + self.datalink = datalink + + def read_cs(self, address): + """ + Read from Control/Status space + :param address: address (index) to read + :return: value read + """ + return self.datalink.ldcs(address) + + def write_cs(self, address, value): + """ + Write to Control/Status space + :param address: address (index) to write + :param value: 8-bit value to write + """ + return self.datalink.stcs(address, value) + + def write_key(self, size, key): + """ + Write a KEY into UPDI + :param size: size of key to send + :param key: key value + """ + return self.datalink.key(size, key) + + def read_sib(self): + """ + Read the SIB from UPDI + :return: SIB string (bytearray) read + """ + return self.datalink.read_sib() + + def read_byte(self, address): + """ + Read a single byte from UPDI + :param address: address to read from + :return: value read + """ + return self.datalink.ld(address) + + def write_byte(self, address, value): + """ + Writes a single byte to UPDI + :param address: address to write to + :param value: value to write + """ + return self.datalink.st(address, value) + + def read_data(self, address, size): + """ + Reads a number of bytes of data from UPDI + :param address: address to write to + :param size: number of bytes to read + """ + self.logger.debug("Reading %d bytes from 0x%04X", size, address) + # Range check + if size > constants.UPDI_MAX_REPEAT_SIZE: + raise PymcuprogError("Cant read that many bytes in one go") + + + # Store the address + self.datalink.st_ptr(address) + + # Fire up the repeat + if size > 1: + self.datalink.repeat(size) + + # Do the read(s) + return self.datalink.ld_ptr_inc(size) + + def read_data_words(self, address, words): + """ + Reads a number of words of data from UPDI + :param address: address to write to + :param words: number of words to read + """ + self.logger.debug("Reading %d words from 0x%04X", words, address) + + # Range check + if words > constants.UPDI_MAX_REPEAT_SIZE: + raise PymcuprogError("Cant read that many words in one go") + + # special case for single word - so we can optimize ld_ptr_inc16 for >1 word to improve performance. + if words == 1: + return self.datalink.ld16(self,address) + + # Otherwise, store the address + self.datalink.st_ptr(address) + + # For performance, managing repeat count is done in ld_ptr_inc16() + return self.datalink.ld_ptr_inc16(words) + + def write_data_words(self, address, data, blocksize): + """ + Writes a number of words to memory + :param address: address to write to + :param data: data to write + :blocksize: max number of bytes being sent + """ + # Special-case of 1 word + if len(data) == 2: + value = data[0] + (data[1] << 8) + return self.datalink.st16(address, value) + + # Range check + if len(data) > constants.UPDI_MAX_REPEAT_SIZE << 1: + raise PymcuprogError("Invalid length") + + # Store the address + self.datalink.st_ptr(address) + + + # For performance, we want to do this with Response Signature Disable set, otherwise the USB Serial latency kills you + # Just setting RSD here then turning it off at the end - it helps a lot, but you run up against the USB latency. So + # now, EVERYTHING was moved into the st_ptr_inc16_RSD() function. Unless blocksize precludes it, the whole thing + # is sent to the serial adapter in a single transfer. + # the st_pty_inc16_RSD routine does the repeat and rsd enable/disable stu + return self.datalink.st_ptr_inc16_RSD(data, blocksize) + + def write_data(self, address, data): + """ + Writes a number of bytes to memory + :param address: address to write to + :param data: data to write + """ + # Special case of 1 byte + if len(data) == 1: + return self.datalink.st(address, data[0]) + # Special case of 2 byte + if len(data) == 2: + self.datalink.st(address, data[0]) + return self.datalink.st(address + 1, data[1]) + + # Range check + if len(data) > constants.UPDI_MAX_REPEAT_SIZE: + raise PymcuprogError("Invalid length") + + # Store the address + self.datalink.st_ptr(address) + + # Fire up the repeat + self.datalink.repeat(len(data)) + return self.datalink.st_ptr_inc(data) diff --git a/software/tools/pymcuprog/libs/pymcuprog/serialupdi/timeout.py b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/timeout.py new file mode 100644 index 0000000..9e99856 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/serialupdi/timeout.py @@ -0,0 +1,25 @@ +""" +Simple timer helper for UPDI stack +""" +import time + +#pylint: disable=too-few-public-methods +class Timeout: + """ + Simple timeout helper in milliseconds. + """ + + def __init__(self, timeout_ms): + """ + Start the expired counter instantly + :param timeout_ms: milliseconds to count + """ + + self.timeout_ms = timeout_ms + self.start_time = time.time() + + def expired(self): + """ + Check if the timeout has expired + """ + return time.time() - self.start_time > self.timeout_ms / 1000.0 diff --git a/software/tools/pymcuprog/libs/pymcuprog/toolconnection.py b/software/tools/pymcuprog/libs/pymcuprog/toolconnection.py new file mode 100644 index 0000000..9d548e2 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/toolconnection.py @@ -0,0 +1,36 @@ +""" +This module includes wrapper classes for Tool connection parameters +""" + +#pylint: disable=too-few-public-methods +class ToolConnection(object): + """ + Base class for ToolConnection classes used to wrap configuration parameters for tool connections + """ + +#pylint: disable=too-few-public-methods +class ToolUsbHidConnection(ToolConnection): + """ + Helper class wrapping configuration parameters for a connection to a USB HID tool + """ + serialnumber = None + tool_name = None + + def __init__(self, serialnumber=None, tool_name=None): + """ + :param tool_name: Tool name as given in USB Product string. Some shortnames are also supported + as defined in pyedbglib.hidtransport.toolinfo.py. Set to None if don't care + :param serialnumber: USB serial number string. Set to None if don't care + """ + self.serialnumber = serialnumber + self.tool_name = tool_name + +#pylint: disable=too-few-public-methods +class ToolSerialConnection(ToolConnection): + """ + Helper class wrapping configuration parameters for a connection to a serial port + """ + serialport = None + + def __init__(self, serialport="COM1"): + self.serialport = serialport diff --git a/software/tools/pymcuprog/libs/pymcuprog/utils.py b/software/tools/pymcuprog/libs/pymcuprog/utils.py new file mode 100644 index 0000000..6a16a11 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/utils.py @@ -0,0 +1,275 @@ +""" +Utility functions for pymcuprog +""" +# Python 3 compatibility for Python 2 +from __future__ import print_function + +from pyedbglib.protocols.housekeepingprotocol import Jtagice3HousekeepingProtocol +from pyedbglib.protocols.jtagice3protocol import Jtagice3ResponseError +from pyedbglib.protocols.jtagice3protocol import Jtagice3Protocol + +from .pymcuprog_errors import PymcuprogNotSupportedError + +def read_tool_info(housekeeper): + """ + Interrogates tool (debugger) for useful info + + :returns: Dictionary with various info about the connected debugger + """ + dap_info = housekeeper.dap_info() + + # Add alias for serialnumber(==serial) + dap_info['serialnumber'] = dap_info['serial'] + + # Read FW versions + dap_info['firmware_major'] = housekeeper.get_byte(Jtagice3HousekeepingProtocol.HOUSEKEEPING_CONTEXT_CONFIG, + Jtagice3HousekeepingProtocol.HOUSEKEEPING_CONFIG_FWREV_MAJ) + dap_info['firmware_minor'] = housekeeper.get_byte(Jtagice3HousekeepingProtocol.HOUSEKEEPING_CONTEXT_CONFIG, + Jtagice3HousekeepingProtocol.HOUSEKEEPING_CONFIG_FWREV_MIN) + dap_info['build'] = housekeeper.get_le16(Jtagice3HousekeepingProtocol.HOUSEKEEPING_CONTEXT_CONFIG, + Jtagice3HousekeepingProtocol.HOUSEKEEPING_CONFIG_BUILD) + + # Read HW revision + dap_info['hardware_rev'] = housekeeper.get_byte(Jtagice3HousekeepingProtocol.HOUSEKEEPING_CONTEXT_CONFIG, + Jtagice3HousekeepingProtocol.HOUSEKEEPING_CONFIG_HWREV) + + # Some EDBG versions do NOT have the dap_info 'device' tag populated for non-ARM parts. + # Sneak in and collect the data from the EDBG config instead + if dap_info['product'][:4] == 'EDBG' and dap_info['device_name'] == '': + try: + # Vendor command + cmd = bytearray([0x83]) + # Add cnt of '1' element: + cmd.append(1) + # Add tag of 'TARGET DEVICE NAME' + cmd.append(0x04) + # Add dummy 'param' + cmd.append(ord('?')) + # Add the offset + offset = 0 + cmd.extend([offset & 0xFF, offset >> 8]) + + # Add the chunk size + numbytes = 32 + cmd.extend([numbytes & 0xFF, numbytes >> 8]) + + # raw command routed via the HK interface + response = housekeeper.dap_command_response(cmd) + dap_info['device_name'] = response[6:6 + numbytes].split(b'\0')[0].decode() + except: #pylint: disable=bare-except + # resort to '' + pass + return dap_info + +def print_tool_info(info): + """ + Print out various tool information + + :param info: Dictionary with various tool info as returned from read_tool_info() + """ + print("Connected to {0:s} from {1:s} (serial number {2:s})".format(info['product'], info['vendor'], + info['serial'])) + + print("Debugger firmware version {0:d}.{1:d}.{2:d}".format(info['firmware_major'], + info['firmware_minor'], + info['build'])) + + print("Debugger hardware revision {0:d}".format(info['hardware_rev'])) + +def read_target_voltage(housekeeper): + """ + Read target voltage + + :param housekeeper: instance of pyedbglib.protocols.housekeepingprotocol.Jtagice3HousekeepingProtocol + """ + return read_voltage_parameter(housekeeper, Jtagice3HousekeepingProtocol.HOUSEKEEPING_ANALOG_VTREF) + +def read_supply_voltage_setpoint(housekeeper): + """ + Read supply setpoint + + :param housekeeper: instance of pyedbglib.protocols.housekeepingprotocol.Jtagice3HousekeepingProtocol + """ + return read_voltage_parameter(housekeeper, Jtagice3HousekeepingProtocol.HOUSEKEEPING_TSUP_VOLTAGE) + +def read_usb_voltage(housekeeper): + """ + Read USB voltage + + :param housekeeper: instance of pyedbglib.protocols.housekeepingprotocol.Jtagice3HousekeepingProtocol + """ + return read_voltage_parameter(housekeeper, Jtagice3HousekeepingProtocol.HOUSEKEEPING_ANALOG_VUSB) + +def read_voltage_parameter(housekeeper, offset): + """ + Generic read voltage from tool parameter + + :param housekeeper: Instance of pyedbglib.protocols.housekeepingprotocol.Jtagice3HousekeepingProtocol + :param offset: Tool parameter offset to read + """ + housekeeper.start_session() + voltage = housekeeper.get_le16(Jtagice3HousekeepingProtocol.HOUSEKEEPING_CONTEXT_ANALOG, offset) + voltage = voltage / 1000.0 + housekeeper.end_session() + return voltage + +def set_supply_voltage_setpoint(housekeeper, voltage): + """ + Set supply setpoint + + :param housekeeper: Instance of pyedbglib.protocols.housekeepingprotocol.Jtagice3HousekeepingProtocol + :param voltage: New setpoint for target supply + """ + try: + housekeeper.get_le16(Jtagice3HousekeepingProtocol.HOUSEKEEPING_CONTEXT_ANALOG, + Jtagice3HousekeepingProtocol.HOUSEKEEPING_TSUP_VOLTAGE) + except Jtagice3ResponseError: + raise PymcuprogNotSupportedError("Connected debugger/board does not have supply voltage capability.") + + setpoint_mv = int(voltage*1000) + + try: + housekeeper.set_le16(Jtagice3HousekeepingProtocol.HOUSEKEEPING_CONTEXT_ANALOG, + Jtagice3HousekeepingProtocol.HOUSEKEEPING_TSUP_VOLTAGE, setpoint_mv) + # Unfortunately pyedbglib only throws a generic Exception in this case so no specific Exceptions can be caught + # See DSG-1494 + #pylint: disable=broad-except + except Exception as error: + if "failure code 0x{:02x}".format(Jtagice3Protocol.SETGET_FAILURE_INVALID_VALUE) in str(error).lower(): + raise ValueError("Specified voltage out of range!") + # Voltage was within range but something else went wrong. Just forward the exception. + raise + +def compare(data0, data1, offset, verify_mask=None): + """ + Compares the two byte arrays + + :param data0: first array for compare + :param data1: second array for compare + :param offset: address offset in the memory area, for printing + :param verify_mask: compare mask (for varying instruction width) + :return: + """ + if verify_mask is None: + verify_mask = [0xFF] + + # Check first that lengths match + if len(data0) != len(data1): + raise ValueError("Length mismatch on verify, expect 0x{:04X} but got 0x{:04X}".format(len(data0),len(data1))) + + mask_len = len(verify_mask) + + for i in range(0, len(data0), mask_len): + for dat in range(0, mask_len): + if (data0[i+dat] & verify_mask[dat]) != (data1[i+dat] & verify_mask[dat]): + raise ValueError("Verify mismatch starting at location 0x{:06X}: 0x{:02X} vs 0x{:02X}". + format(i+dat+offset, data0[i+dat] & verify_mask[dat], data1[i+dat] & verify_mask[dat])) + + +def showdata(data, address=0, page_size=None, line_wrap=16): + """ + Show (print) the data + + :param data: an array/list of data to show + :param address: byte address to data + :param page_size: page size in bytes + :param line_wrap: how many bytes to print per line + """ + + # Cannot print more per line than the page size + if page_size is not None: + if line_wrap > page_size: + line_wrap = page_size + + print("-"*(line_wrap*3+9)) + + # Page alignment + rows = 0 + if page_size is not None: + page = address % page_size + rows = int(page / line_wrap) + for row in range(rows): + print("0x{0:06X}: ".format(address-page+row*line_wrap), end='') + print("xx "*line_wrap, end='') + print("") + + # Calculate offset from aligned data + div = address % line_wrap + + print("0x{0:06X}: ".format(address-div), end='') + # Add some empty bytes + print("xx "*div, end='') + + # keep track of page wraps + wrap = False + + for i, value in enumerate(data, div+1): + print("{0:02X} ".format(value), end='') + if page_size is not None: + if (i+(rows*line_wrap)) % page_size == 0 and i != len(data)+div: + print("") + wrap = True + if i % line_wrap == 0 and i != len(data)+div or wrap: + print("") + print("0x{0:06X}: ".format(address-div + i), end='') + wrap = False + + # Figure out how many extra empty data positions to print + extra = line_wrap - div - (len(data) % line_wrap) + if extra % line_wrap == 0: + extra = 0 + + print("xx "*extra, end='') + print("") + print("-"*(line_wrap*3+9)) + + +def pagealign(data, address, page_size, data_size=1): + """ + Aligns data to the start of a page + """ + # Pre-pad the data if it does not start at the start of a page + offset = address % page_size + for _ in range(offset): + data.insert(0, 0xFF) + # In case of other data sizes, post-pad the data + while len(data) % data_size: + data.append(0xFF) + + return data, address-offset + +def pad_to_size(memory_block, chunk_size, pad_value): + """ + Pads a chunk of memory + """ + while len(memory_block) % chunk_size > 0: + memory_block.append(pad_value) + + +def enum(**enums): + """ + Emulates an Enum type + + Needed for Python 2.7 compatibility as Python did not get built-in support for enums until version 3.4 + """ + return type('Enum', (), enums) + + +def verify_flash_from_bin(bin_filename, backend, offset=0, max_read_chunk=None): + """ + Verify the contents of flash against a bin-file + + :param filename: Name/path of bin-file to verify + :param backend: Reference the Backend class of pymcuprog + :param offset: Memory offset to start verify from + :returns: Boolean value indicating success or failure of the operation + """ + bin_file = open(bin_filename, 'rb') + bin_data = bytearray() + for line in bin_file.readlines(): + bin_data.extend(line) + + verify_status = backend.verify_memory(bin_data, 'flash', offset, max_read_chunk=max_read_chunk) + if verify_status is False: + return False + return True diff --git a/software/tools/pymcuprog/libs/pymcuprog/version.py b/software/tools/pymcuprog/libs/pymcuprog/version.py new file mode 100644 index 0000000..570d373 --- /dev/null +++ b/software/tools/pymcuprog/libs/pymcuprog/version.py @@ -0,0 +1,4 @@ +""" This file was generated when pymcuprog was built """ +VERSION = '3.6.4.86' +COMMIT_ID = '6224623cfc85c5e7cb6b1df8419b72c338c223f9' +BUILD_DATE = '2020-11-09 14:49:15 +0000' diff --git a/software/tools/pymcuprog/libs/serial/__init__.py b/software/tools/pymcuprog/libs/serial/__init__.py new file mode 100644 index 0000000..c24ced8 --- /dev/null +++ b/software/tools/pymcuprog/libs/serial/__init__.py @@ -0,0 +1,89 @@ +#!/usr/bin/env python +# +# This is a wrapper module for different platform implementations +# +# This file is part of pySerial. https://github.com/pyserial/pyserial +# (C) 2001-2017 Chris Liechti +# +# SPDX-License-Identifier: BSD-3-Clause + +import sys +import importlib + +from serial.serialutil import * +#~ SerialBase, SerialException, to_bytes, iterbytes + +__version__ = '3.4' + +VERSION = __version__ + +# pylint: disable=wrong-import-position +if sys.platform == 'cli': + from serial.serialcli import Serial +else: + import os + # chose an implementation, depending on os + if os.name == 'nt': # sys.platform == 'win32': + from serial.serialwin32 import Serial + elif os.name == 'posix': + from serial.serialposix import Serial, PosixPollSerial, VTIMESerial # noqa + elif os.name == 'java': + from serial.serialjava import Serial + else: + raise ImportError("Sorry: no implementation for your platform ('{}') available".format(os.name)) + + +protocol_handler_packages = [ + 'serial.urlhandler', +] + + +def serial_for_url(url, *args, **kwargs): + """\ + Get an instance of the Serial class, depending on port/url. The port is not + opened when the keyword parameter 'do_not_open' is true, by default it + is. All other parameters are directly passed to the __init__ method when + the port is instantiated. + + The list of package names that is searched for protocol handlers is kept in + ``protocol_handler_packages``. + + e.g. we want to support a URL ``foobar://``. A module + ``my_handlers.protocol_foobar`` is provided by the user. Then + ``protocol_handler_packages.append("my_handlers")`` would extend the search + path so that ``serial_for_url("foobar://"))`` would work. + """ + # check and remove extra parameter to not confuse the Serial class + do_open = not kwargs.pop('do_not_open', False) + # the default is to use the native implementation + klass = Serial + try: + url_lowercase = url.lower() + except AttributeError: + # it's not a string, use default + pass + else: + # if it is an URL, try to import the handler module from the list of possible packages + if '://' in url_lowercase: + protocol = url_lowercase.split('://', 1)[0] + module_name = '.protocol_{}'.format(protocol) + for package_name in protocol_handler_packages: + try: + importlib.import_module(package_name) + handler_module = importlib.import_module(module_name, package_name) + except ImportError: + continue + else: + if hasattr(handler_module, 'serial_class_for_url'): + url, klass = handler_module.serial_class_for_url(url) + else: + klass = handler_module.Serial + break + else: + raise ValueError('invalid URL, protocol {!r} not known'.format(protocol)) + # instantiate and open when desired + instance = klass(None, *args, **kwargs) + instance.port = url + if do_open: + instance.open() + return instance diff --git a/software/tools/pymcuprog/libs/serial/aio.py b/software/tools/pymcuprog/libs/serial/aio.py new file mode 100644 index 0000000..257c47c --- /dev/null +++ b/software/tools/pymcuprog/libs/serial/aio.py @@ -0,0 +1,115 @@ +#!/usr/bin/env python3 +# +# Python Serial Port Extension for Win32, Linux, BSD, Jython +# module for serial IO for POSIX compatible systems, like Linux +# see __init__.py +# +# (C) 2015 Chris Liechti +# +# SPDX-License-Identifier: BSD-3-Clause +"""\ +Support asyncio with serial ports. EXPERIMENTAL + +Posix platforms only, Python 3.4+ only. + +Windows event loops can not wait for serial ports with the current +implementation. It should be possible to get that working though. +""" +import asyncio +import serial +import logger + + +class SerialTransport(asyncio.Transport): + def __init__(self, loop, protocol, serial_instance): + self._loop = loop + self._protocol = protocol + self.serial = serial_instance + self._closing = False + self._paused = False + # XXX how to support url handlers too + self.serial.timeout = 0 + self.serial.nonblocking() + loop.call_soon(protocol.connection_made, self) + # only start reading when connection_made() has been called + loop.call_soon(loop.add_reader, self.serial.fd, self._read_ready) + + def __repr__(self): + return '{self.__class__.__name__}({self._loop}, {self._protocol}, {self.serial})'.format(self=self) + + def close(self): + if self._closing: + return + self._closing = True + self._loop.remove_reader(self.serial.fd) + self.serial.close() + self._loop.call_soon(self._protocol.connection_lost, None) + + def _read_ready(self): + data = self.serial.read(1024) + if data: + self._protocol.data_received(data) + + def write(self, data): + self.serial.write(data) + + def can_write_eof(self): + return False + + def pause_reading(self): + if self._closing: + raise RuntimeError('Cannot pause_reading() when closing') + if self._paused: + raise RuntimeError('Already paused') + self._paused = True + self._loop.remove_reader(self._sock_fd) + if self._loop.get_debug(): + logger.debug("%r pauses reading", self) + + def resume_reading(self): + if not self._paused: + raise RuntimeError('Not paused') + self._paused = False + if self._closing: + return + self._loop.add_reader(self._sock_fd, self._read_ready) + if self._loop.get_debug(): + logger.debug("%r resumes reading", self) + + #~ def set_write_buffer_limits(self, high=None, low=None): + #~ def get_write_buffer_size(self): + #~ def writelines(self, list_of_data): + #~ def write_eof(self): + #~ def abort(self): + + +@asyncio.coroutine +def create_serial_connection(loop, protocol_factory, *args, **kwargs): + ser = serial.Serial(*args, **kwargs) + protocol = protocol_factory() + transport = SerialTransport(loop, protocol, ser) + return (transport, protocol) + +# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +# test +if __name__ == '__main__': + class Output(asyncio.Protocol): + def connection_made(self, transport): + self.transport = transport + print('port opened', transport) + transport.serial.rts = False + transport.write(b'hello world\n') + + def data_received(self, data): + print('data received', repr(data)) + self.transport.close() + + def connection_lost(self, exc): + print('port closed') + asyncio.get_event_loop().stop() + + loop = asyncio.get_event_loop() + coro = create_serial_connection(loop, Output, '/dev/ttyUSB0', baudrate=115200) + loop.run_until_complete(coro) + loop.run_forever() + loop.close() diff --git a/software/tools/pymcuprog/libs/serial/rfc2217.py b/software/tools/pymcuprog/libs/serial/rfc2217.py new file mode 100644 index 0000000..419947d --- /dev/null +++ b/software/tools/pymcuprog/libs/serial/rfc2217.py @@ -0,0 +1,1346 @@ +#! python +# +# This module implements a RFC2217 compatible client. RF2217 descibes a +# protocol to access serial ports over TCP/IP and allows setting the baud rate, +# modem control lines etc. +# +# This file is part of pySerial. https://github.com/pyserial/pyserial +# (C) 2001-2015 Chris Liechti +# +# SPDX-License-Identifier: BSD-3-Clause + +# TODO: +# - setting control line -> answer is not checked (had problems with one of the +# severs). consider implementing a compatibility mode flag to make check +# conditional +# - write timeout not implemented at all + +# ########################################################################### +# observations and issues with servers +# =========================================================================== +# sredird V2.2.1 +# - http://www.ibiblio.org/pub/Linux/system/serial/ sredird-2.2.2.tar.gz +# - does not acknowledge SET_CONTROL (RTS/DTR) correctly, always responding +# [105 1] instead of the actual value. +# - SET_BAUDRATE answer contains 4 extra null bytes -> probably for larger +# numbers than 2**32? +# - To get the signature [COM_PORT_OPTION 0] has to be sent. +# - run a server: while true; do nc -l -p 7000 -c "sredird debug /dev/ttyUSB0 /var/lock/sredir"; done +# =========================================================================== +# telnetcpcd (untested) +# - http://ftp.wayne.edu/kermit/sredird/telnetcpcd-1.09.tar.gz +# - To get the signature [COM_PORT_OPTION] w/o data has to be sent. +# =========================================================================== +# ser2net +# - does not negotiate BINARY or COM_PORT_OPTION for his side but at least +# acknowledges that the client activates these options +# - The configuration may be that the server prints a banner. As this client +# implementation does a flushInput on connect, this banner is hidden from +# the user application. +# - NOTIFY_MODEMSTATE: the poll interval of the server seems to be one +# second. +# - To get the signature [COM_PORT_OPTION 0] has to be sent. +# - run a server: run ser2net daemon, in /etc/ser2net.conf: +# 2000:telnet:0:/dev/ttyS0:9600 remctl banner +# ########################################################################### + +# How to identify ports? pySerial might want to support other protocols in the +# future, so lets use an URL scheme. +# for RFC2217 compliant servers we will use this: +# rfc2217://:[?option[&option...]] +# +# options: +# - "logging" set log level print diagnostic messages (e.g. "logging=debug") +# - "ign_set_control": do not look at the answers to SET_CONTROL +# - "poll_modem": issue NOTIFY_MODEMSTATE requests when CTS/DTR/RI/CD is read. +# Without this option it expects that the server sends notifications +# automatically on change (which most servers do and is according to the +# RFC). +# the order of the options is not relevant + +import logging +import socket +import struct +import threading +import time +try: + import urlparse +except ImportError: + import urllib.parse as urlparse +try: + import Queue +except ImportError: + import queue as Queue + +import serial +from serial.serialutil import SerialBase, SerialException, to_bytes, \ + iterbytes, portNotOpenError, Timeout + +# port string is expected to be something like this: +# rfc2217://host:port +# host may be an IP or including domain, whatever. +# port is 0...65535 + +# map log level names to constants. used in from_url() +LOGGER_LEVELS = { + 'debug': logging.DEBUG, + 'info': logging.INFO, + 'warning': logging.WARNING, + 'error': logging.ERROR, +} + + +# telnet protocol characters +SE = b'\xf0' # Subnegotiation End +NOP = b'\xf1' # No Operation +DM = b'\xf2' # Data Mark +BRK = b'\xf3' # Break +IP = b'\xf4' # Interrupt process +AO = b'\xf5' # Abort output +AYT = b'\xf6' # Are You There +EC = b'\xf7' # Erase Character +EL = b'\xf8' # Erase Line +GA = b'\xf9' # Go Ahead +SB = b'\xfa' # Subnegotiation Begin +WILL = b'\xfb' +WONT = b'\xfc' +DO = b'\xfd' +DONT = b'\xfe' +IAC = b'\xff' # Interpret As Command +IAC_DOUBLED = b'\xff\xff' + +# selected telnet options +BINARY = b'\x00' # 8-bit data path +ECHO = b'\x01' # echo +SGA = b'\x03' # suppress go ahead + +# RFC2217 +COM_PORT_OPTION = b'\x2c' + +# Client to Access Server +SET_BAUDRATE = b'\x01' +SET_DATASIZE = b'\x02' +SET_PARITY = b'\x03' +SET_STOPSIZE = b'\x04' +SET_CONTROL = b'\x05' +NOTIFY_LINESTATE = b'\x06' +NOTIFY_MODEMSTATE = b'\x07' +FLOWCONTROL_SUSPEND = b'\x08' +FLOWCONTROL_RESUME = b'\x09' +SET_LINESTATE_MASK = b'\x0a' +SET_MODEMSTATE_MASK = b'\x0b' +PURGE_DATA = b'\x0c' + +SERVER_SET_BAUDRATE = b'\x65' +SERVER_SET_DATASIZE = b'\x66' +SERVER_SET_PARITY = b'\x67' +SERVER_SET_STOPSIZE = b'\x68' +SERVER_SET_CONTROL = b'\x69' +SERVER_NOTIFY_LINESTATE = b'\x6a' +SERVER_NOTIFY_MODEMSTATE = b'\x6b' +SERVER_FLOWCONTROL_SUSPEND = b'\x6c' +SERVER_FLOWCONTROL_RESUME = b'\x6d' +SERVER_SET_LINESTATE_MASK = b'\x6e' +SERVER_SET_MODEMSTATE_MASK = b'\x6f' +SERVER_PURGE_DATA = b'\x70' + +RFC2217_ANSWER_MAP = { + SET_BAUDRATE: SERVER_SET_BAUDRATE, + SET_DATASIZE: SERVER_SET_DATASIZE, + SET_PARITY: SERVER_SET_PARITY, + SET_STOPSIZE: SERVER_SET_STOPSIZE, + SET_CONTROL: SERVER_SET_CONTROL, + NOTIFY_LINESTATE: SERVER_NOTIFY_LINESTATE, + NOTIFY_MODEMSTATE: SERVER_NOTIFY_MODEMSTATE, + FLOWCONTROL_SUSPEND: SERVER_FLOWCONTROL_SUSPEND, + FLOWCONTROL_RESUME: SERVER_FLOWCONTROL_RESUME, + SET_LINESTATE_MASK: SERVER_SET_LINESTATE_MASK, + SET_MODEMSTATE_MASK: SERVER_SET_MODEMSTATE_MASK, + PURGE_DATA: SERVER_PURGE_DATA, +} + +SET_CONTROL_REQ_FLOW_SETTING = b'\x00' # Request Com Port Flow Control Setting (outbound/both) +SET_CONTROL_USE_NO_FLOW_CONTROL = b'\x01' # Use No Flow Control (outbound/both) +SET_CONTROL_USE_SW_FLOW_CONTROL = b'\x02' # Use XON/XOFF Flow Control (outbound/both) +SET_CONTROL_USE_HW_FLOW_CONTROL = b'\x03' # Use HARDWARE Flow Control (outbound/both) +SET_CONTROL_REQ_BREAK_STATE = b'\x04' # Request BREAK State +SET_CONTROL_BREAK_ON = b'\x05' # Set BREAK State ON +SET_CONTROL_BREAK_OFF = b'\x06' # Set BREAK State OFF +SET_CONTROL_REQ_DTR = b'\x07' # Request DTR Signal State +SET_CONTROL_DTR_ON = b'\x08' # Set DTR Signal State ON +SET_CONTROL_DTR_OFF = b'\x09' # Set DTR Signal State OFF +SET_CONTROL_REQ_RTS = b'\x0a' # Request RTS Signal State +SET_CONTROL_RTS_ON = b'\x0b' # Set RTS Signal State ON +SET_CONTROL_RTS_OFF = b'\x0c' # Set RTS Signal State OFF +SET_CONTROL_REQ_FLOW_SETTING_IN = b'\x0d' # Request Com Port Flow Control Setting (inbound) +SET_CONTROL_USE_NO_FLOW_CONTROL_IN = b'\x0e' # Use No Flow Control (inbound) +SET_CONTROL_USE_SW_FLOW_CONTOL_IN = b'\x0f' # Use XON/XOFF Flow Control (inbound) +SET_CONTROL_USE_HW_FLOW_CONTOL_IN = b'\x10' # Use HARDWARE Flow Control (inbound) +SET_CONTROL_USE_DCD_FLOW_CONTROL = b'\x11' # Use DCD Flow Control (outbound/both) +SET_CONTROL_USE_DTR_FLOW_CONTROL = b'\x12' # Use DTR Flow Control (inbound) +SET_CONTROL_USE_DSR_FLOW_CONTROL = b'\x13' # Use DSR Flow Control (outbound/both) + +LINESTATE_MASK_TIMEOUT = 128 # Time-out Error +LINESTATE_MASK_SHIFTREG_EMPTY = 64 # Transfer Shift Register Empty +LINESTATE_MASK_TRANSREG_EMPTY = 32 # Transfer Holding Register Empty +LINESTATE_MASK_BREAK_DETECT = 16 # Break-detect Error +LINESTATE_MASK_FRAMING_ERROR = 8 # Framing Error +LINESTATE_MASK_PARTIY_ERROR = 4 # Parity Error +LINESTATE_MASK_OVERRUN_ERROR = 2 # Overrun Error +LINESTATE_MASK_DATA_READY = 1 # Data Ready + +MODEMSTATE_MASK_CD = 128 # Receive Line Signal Detect (also known as Carrier Detect) +MODEMSTATE_MASK_RI = 64 # Ring Indicator +MODEMSTATE_MASK_DSR = 32 # Data-Set-Ready Signal State +MODEMSTATE_MASK_CTS = 16 # Clear-To-Send Signal State +MODEMSTATE_MASK_CD_CHANGE = 8 # Delta Receive Line Signal Detect +MODEMSTATE_MASK_RI_CHANGE = 4 # Trailing-edge Ring Detector +MODEMSTATE_MASK_DSR_CHANGE = 2 # Delta Data-Set-Ready +MODEMSTATE_MASK_CTS_CHANGE = 1 # Delta Clear-To-Send + +PURGE_RECEIVE_BUFFER = b'\x01' # Purge access server receive data buffer +PURGE_TRANSMIT_BUFFER = b'\x02' # Purge access server transmit data buffer +PURGE_BOTH_BUFFERS = b'\x03' # Purge both the access server receive data + # buffer and the access server transmit data buffer + + +RFC2217_PARITY_MAP = { + serial.PARITY_NONE: 1, + serial.PARITY_ODD: 2, + serial.PARITY_EVEN: 3, + serial.PARITY_MARK: 4, + serial.PARITY_SPACE: 5, +} +RFC2217_REVERSE_PARITY_MAP = dict((v, k) for k, v in RFC2217_PARITY_MAP.items()) + +RFC2217_STOPBIT_MAP = { + serial.STOPBITS_ONE: 1, + serial.STOPBITS_ONE_POINT_FIVE: 3, + serial.STOPBITS_TWO: 2, +} +RFC2217_REVERSE_STOPBIT_MAP = dict((v, k) for k, v in RFC2217_STOPBIT_MAP.items()) + +# Telnet filter states +M_NORMAL = 0 +M_IAC_SEEN = 1 +M_NEGOTIATE = 2 + +# TelnetOption and TelnetSubnegotiation states +REQUESTED = 'REQUESTED' +ACTIVE = 'ACTIVE' +INACTIVE = 'INACTIVE' +REALLY_INACTIVE = 'REALLY_INACTIVE' + + +class TelnetOption(object): + """Manage a single telnet option, keeps track of DO/DONT WILL/WONT.""" + + def __init__(self, connection, name, option, send_yes, send_no, ack_yes, + ack_no, initial_state, activation_callback=None): + """\ + Initialize option. + :param connection: connection used to transmit answers + :param name: a readable name for debug outputs + :param send_yes: what to send when option is to be enabled. + :param send_no: what to send when option is to be disabled. + :param ack_yes: what to expect when remote agrees on option. + :param ack_no: what to expect when remote disagrees on option. + :param initial_state: options initialized with REQUESTED are tried to + be enabled on startup. use INACTIVE for all others. + """ + self.connection = connection + self.name = name + self.option = option + self.send_yes = send_yes + self.send_no = send_no + self.ack_yes = ack_yes + self.ack_no = ack_no + self.state = initial_state + self.active = False + self.activation_callback = activation_callback + + def __repr__(self): + """String for debug outputs""" + return "{o.name}:{o.active}({o.state})".format(o=self) + + def process_incoming(self, command): + """\ + A DO/DONT/WILL/WONT was received for this option, update state and + answer when needed. + """ + if command == self.ack_yes: + if self.state is REQUESTED: + self.state = ACTIVE + self.active = True + if self.activation_callback is not None: + self.activation_callback() + elif self.state is ACTIVE: + pass + elif self.state is INACTIVE: + self.state = ACTIVE + self.connection.telnet_send_option(self.send_yes, self.option) + self.active = True + if self.activation_callback is not None: + self.activation_callback() + elif self.state is REALLY_INACTIVE: + self.connection.telnet_send_option(self.send_no, self.option) + else: + raise ValueError('option in illegal state {!r}'.format(self)) + elif command == self.ack_no: + if self.state is REQUESTED: + self.state = INACTIVE + self.active = False + elif self.state is ACTIVE: + self.state = INACTIVE + self.connection.telnet_send_option(self.send_no, self.option) + self.active = False + elif self.state is INACTIVE: + pass + elif self.state is REALLY_INACTIVE: + pass + else: + raise ValueError('option in illegal state {!r}'.format(self)) + + +class TelnetSubnegotiation(object): + """\ + A object to handle subnegotiation of options. In this case actually + sub-sub options for RFC 2217. It is used to track com port options. + """ + + def __init__(self, connection, name, option, ack_option=None): + if ack_option is None: + ack_option = option + self.connection = connection + self.name = name + self.option = option + self.value = None + self.ack_option = ack_option + self.state = INACTIVE + + def __repr__(self): + """String for debug outputs.""" + return "{sn.name}:{sn.state}".format(sn=self) + + def set(self, value): + """\ + Request a change of the value. a request is sent to the server. if + the client needs to know if the change is performed he has to check the + state of this object. + """ + self.value = value + self.state = REQUESTED + self.connection.rfc2217_send_subnegotiation(self.option, self.value) + if self.connection.logger: + self.connection.logger.debug("SB Requesting {} -> {!r}".format(self.name, self.value)) + + def is_ready(self): + """\ + Check if answer from server has been received. when server rejects + the change, raise a ValueError. + """ + if self.state == REALLY_INACTIVE: + raise ValueError("remote rejected value for option {!r}".format(self.name)) + return self.state == ACTIVE + # add property to have a similar interface as TelnetOption + active = property(is_ready) + + def wait(self, timeout=3): + """\ + Wait until the subnegotiation has been acknowledged or timeout. It + can also throw a value error when the answer from the server does not + match the value sent. + """ + timeout_timer = Timeout(timeout) + while not timeout_timer.expired(): + time.sleep(0.05) # prevent 100% CPU load + if self.is_ready(): + break + else: + raise SerialException("timeout while waiting for option {!r}".format(self.name)) + + def check_answer(self, suboption): + """\ + Check an incoming subnegotiation block. The parameter already has + cut off the header like sub option number and com port option value. + """ + if self.value == suboption[:len(self.value)]: + self.state = ACTIVE + else: + # error propagation done in is_ready + self.state = REALLY_INACTIVE + if self.connection.logger: + self.connection.logger.debug("SB Answer {} -> {!r} -> {}".format(self.name, suboption, self.state)) + + +class Serial(SerialBase): + """Serial port implementation for RFC 2217 remote serial ports.""" + + BAUDRATES = (50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, 4800, + 9600, 19200, 38400, 57600, 115200) + + def __init__(self, *args, **kwargs): + self._thread = None + self._socket = None + self._linestate = 0 + self._modemstate = None + self._modemstate_timeout = Timeout(-1) + self._remote_suspend_flow = False + self._write_lock = None + self.logger = None + self._ignore_set_control_answer = False + self._poll_modem_state = False + self._network_timeout = 3 + self._telnet_options = None + self._rfc2217_port_settings = None + self._rfc2217_options = None + self._read_buffer = None + super(Serial, self).__init__(*args, **kwargs) # must be last call in case of auto-open + + def open(self): + """\ + Open port with current settings. This may throw a SerialException + if the port cannot be opened. + """ + self.logger = None + self._ignore_set_control_answer = False + self._poll_modem_state = False + self._network_timeout = 3 + if self._port is None: + raise SerialException("Port must be configured before it can be used.") + if self.is_open: + raise SerialException("Port is already open.") + try: + self._socket = socket.create_connection(self.from_url(self.portstr), timeout=5) # XXX good value? + self._socket.setsockopt(socket.IPPROTO_TCP, socket.TCP_NODELAY, 1) + except Exception as msg: + self._socket = None + raise SerialException("Could not open port {}: {}".format(self.portstr, msg)) + + # use a thread save queue as buffer. it also simplifies implementing + # the read timeout + self._read_buffer = Queue.Queue() + # to ensure that user writes does not interfere with internal + # telnet/rfc2217 options establish a lock + self._write_lock = threading.Lock() + # name the following separately so that, below, a check can be easily done + mandadory_options = [ + TelnetOption(self, 'we-BINARY', BINARY, WILL, WONT, DO, DONT, INACTIVE), + TelnetOption(self, 'we-RFC2217', COM_PORT_OPTION, WILL, WONT, DO, DONT, REQUESTED), + ] + # all supported telnet options + self._telnet_options = [ + TelnetOption(self, 'ECHO', ECHO, DO, DONT, WILL, WONT, REQUESTED), + TelnetOption(self, 'we-SGA', SGA, WILL, WONT, DO, DONT, REQUESTED), + TelnetOption(self, 'they-SGA', SGA, DO, DONT, WILL, WONT, REQUESTED), + TelnetOption(self, 'they-BINARY', BINARY, DO, DONT, WILL, WONT, INACTIVE), + TelnetOption(self, 'they-RFC2217', COM_PORT_OPTION, DO, DONT, WILL, WONT, REQUESTED), + ] + mandadory_options + # RFC 2217 specific states + # COM port settings + self._rfc2217_port_settings = { + 'baudrate': TelnetSubnegotiation(self, 'baudrate', SET_BAUDRATE, SERVER_SET_BAUDRATE), + 'datasize': TelnetSubnegotiation(self, 'datasize', SET_DATASIZE, SERVER_SET_DATASIZE), + 'parity': TelnetSubnegotiation(self, 'parity', SET_PARITY, SERVER_SET_PARITY), + 'stopsize': TelnetSubnegotiation(self, 'stopsize', SET_STOPSIZE, SERVER_SET_STOPSIZE), + } + # There are more subnegotiation objects, combine all in one dictionary + # for easy access + self._rfc2217_options = { + 'purge': TelnetSubnegotiation(self, 'purge', PURGE_DATA, SERVER_PURGE_DATA), + 'control': TelnetSubnegotiation(self, 'control', SET_CONTROL, SERVER_SET_CONTROL), + } + self._rfc2217_options.update(self._rfc2217_port_settings) + # cache for line and modem states that the server sends to us + self._linestate = 0 + self._modemstate = None + self._modemstate_timeout = Timeout(-1) + # RFC 2217 flow control between server and client + self._remote_suspend_flow = False + + self.is_open = True + self._thread = threading.Thread(target=self._telnet_read_loop) + self._thread.setDaemon(True) + self._thread.setName('pySerial RFC 2217 reader thread for {}'.format(self._port)) + self._thread.start() + + try: # must clean-up if open fails + # negotiate Telnet/RFC 2217 -> send initial requests + for option in self._telnet_options: + if option.state is REQUESTED: + self.telnet_send_option(option.send_yes, option.option) + # now wait until important options are negotiated + timeout = Timeout(self._network_timeout) + while not timeout.expired(): + time.sleep(0.05) # prevent 100% CPU load + if sum(o.active for o in mandadory_options) == sum(o.state != INACTIVE for o in mandadory_options): + break + else: + raise SerialException( + "Remote does not seem to support RFC2217 or BINARY mode {!r}".format(mandadory_options)) + if self.logger: + self.logger.info("Negotiated options: {}".format(self._telnet_options)) + + # fine, go on, set RFC 2271 specific things + self._reconfigure_port() + # all things set up get, now a clean start + if not self._dsrdtr: + self._update_dtr_state() + if not self._rtscts: + self._update_rts_state() + self.reset_input_buffer() + self.reset_output_buffer() + except: + self.close() + raise + + def _reconfigure_port(self): + """Set communication parameters on opened port.""" + if self._socket is None: + raise SerialException("Can only operate on open ports") + + # if self._timeout != 0 and self._interCharTimeout is not None: + # XXX + + if self._write_timeout is not None: + raise NotImplementedError('write_timeout is currently not supported') + # XXX + + # Setup the connection + # to get good performance, all parameter changes are sent first... + if not 0 < self._baudrate < 2 ** 32: + raise ValueError("invalid baudrate: {!r}".format(self._baudrate)) + self._rfc2217_port_settings['baudrate'].set(struct.pack(b'!I', self._baudrate)) + self._rfc2217_port_settings['datasize'].set(struct.pack(b'!B', self._bytesize)) + self._rfc2217_port_settings['parity'].set(struct.pack(b'!B', RFC2217_PARITY_MAP[self._parity])) + self._rfc2217_port_settings['stopsize'].set(struct.pack(b'!B', RFC2217_STOPBIT_MAP[self._stopbits])) + + # and now wait until parameters are active + items = self._rfc2217_port_settings.values() + if self.logger: + self.logger.debug("Negotiating settings: {}".format(items)) + timeout = Timeout(self._network_timeout) + while not timeout.expired(): + time.sleep(0.05) # prevent 100% CPU load + if sum(o.active for o in items) == len(items): + break + else: + raise SerialException("Remote does not accept parameter change (RFC2217): {!r}".format(items)) + if self.logger: + self.logger.info("Negotiated settings: {}".format(items)) + + if self._rtscts and self._xonxoff: + raise ValueError('xonxoff and rtscts together are not supported') + elif self._rtscts: + self.rfc2217_set_control(SET_CONTROL_USE_HW_FLOW_CONTROL) + elif self._xonxoff: + self.rfc2217_set_control(SET_CONTROL_USE_SW_FLOW_CONTROL) + else: + self.rfc2217_set_control(SET_CONTROL_USE_NO_FLOW_CONTROL) + + def close(self): + """Close port""" + self.is_open = False + if self._socket: + try: + self._socket.shutdown(socket.SHUT_RDWR) + self._socket.close() + except: + # ignore errors. + pass + if self._thread: + self._thread.join(7) # XXX more than socket timeout + self._thread = None + # in case of quick reconnects, give the server some time + time.sleep(0.3) + self._socket = None + + def from_url(self, url): + """\ + extract host and port from an URL string, other settings are extracted + an stored in instance + """ + parts = urlparse.urlsplit(url) + if parts.scheme != "rfc2217": + raise SerialException( + 'expected a string in the form ' + '"rfc2217://:[?option[&option...]]": ' + 'not starting with rfc2217:// ({!r})'.format(parts.scheme)) + try: + # process options now, directly altering self + for option, values in urlparse.parse_qs(parts.query, True).items(): + if option == 'logging': + logging.basicConfig() # XXX is that good to call it here? + self.logger = logging.getLogger('pySerial.rfc2217') + self.logger.setLevel(LOGGER_LEVELS[values[0]]) + self.logger.debug('enabled logging') + elif option == 'ign_set_control': + self._ignore_set_control_answer = True + elif option == 'poll_modem': + self._poll_modem_state = True + elif option == 'timeout': + self._network_timeout = float(values[0]) + else: + raise ValueError('unknown option: {!r}'.format(option)) + if not 0 <= parts.port < 65536: + raise ValueError("port not in range 0...65535") + except ValueError as e: + raise SerialException( + 'expected a string in the form ' + '"rfc2217://:[?option[&option...]]": {}'.format(e)) + return (parts.hostname, parts.port) + + # - - - - - - - - - - - - - - - - - - - - - - - - + + @property + def in_waiting(self): + """Return the number of bytes currently in the input buffer.""" + if not self.is_open: + raise portNotOpenError + return self._read_buffer.qsize() + + def read(self, size=1): + """\ + Read size bytes from the serial port. If a timeout is set it may + return less characters as requested. With no timeout it will block + until the requested number of bytes is read. + """ + if not self.is_open: + raise portNotOpenError + data = bytearray() + try: + timeout = Timeout(self._timeout) + while len(data) < size: + if self._thread is None: + raise SerialException('connection failed (reader thread died)') + data += self._read_buffer.get(True, timeout.time_left()) + if timeout.expired(): + break + except Queue.Empty: # -> timeout + pass + return bytes(data) + + def write(self, data): + """\ + Output the given byte string over the serial port. Can block if the + connection is blocked. May raise SerialException if the connection is + closed. + """ + if not self.is_open: + raise portNotOpenError + # XXX use protocol_socket's write + with self._write_lock: + try: + self._socket.sendall(to_bytes(data).replace(IAC, IAC_DOUBLED)) + except socket.error as e: + raise SerialException("connection failed (socket error): {}".format(e)) + return len(data) + + def reset_input_buffer(self): + """Clear input buffer, discarding all that is in the buffer.""" + if not self.is_open: + raise portNotOpenError + self.rfc2217_send_purge(PURGE_RECEIVE_BUFFER) + # empty read buffer + while self._read_buffer.qsize(): + self._read_buffer.get(False) + + def reset_output_buffer(self): + """\ + Clear output buffer, aborting the current output and + discarding all that is in the buffer. + """ + if not self.is_open: + raise portNotOpenError + self.rfc2217_send_purge(PURGE_TRANSMIT_BUFFER) + + def _update_break_state(self): + """\ + Set break: Controls TXD. When active, to transmitting is + possible. + """ + if not self.is_open: + raise portNotOpenError + if self.logger: + self.logger.info('set BREAK to {}'.format('active' if self._break_state else 'inactive')) + if self._break_state: + self.rfc2217_set_control(SET_CONTROL_BREAK_ON) + else: + self.rfc2217_set_control(SET_CONTROL_BREAK_OFF) + + def _update_rts_state(self): + """Set terminal status line: Request To Send.""" + if not self.is_open: + raise portNotOpenError + if self.logger: + self.logger.info('set RTS to {}'.format('active' if self._rts_state else 'inactive')) + if self._rts_state: + self.rfc2217_set_control(SET_CONTROL_RTS_ON) + else: + self.rfc2217_set_control(SET_CONTROL_RTS_OFF) + + def _update_dtr_state(self): + """Set terminal status line: Data Terminal Ready.""" + if not self.is_open: + raise portNotOpenError + if self.logger: + self.logger.info('set DTR to {}'.format('active' if self._dtr_state else 'inactive')) + if self._dtr_state: + self.rfc2217_set_control(SET_CONTROL_DTR_ON) + else: + self.rfc2217_set_control(SET_CONTROL_DTR_OFF) + + @property + def cts(self): + """Read terminal status line: Clear To Send.""" + if not self.is_open: + raise portNotOpenError + return bool(self.get_modem_state() & MODEMSTATE_MASK_CTS) + + @property + def dsr(self): + """Read terminal status line: Data Set Ready.""" + if not self.is_open: + raise portNotOpenError + return bool(self.get_modem_state() & MODEMSTATE_MASK_DSR) + + @property + def ri(self): + """Read terminal status line: Ring Indicator.""" + if not self.is_open: + raise portNotOpenError + return bool(self.get_modem_state() & MODEMSTATE_MASK_RI) + + @property + def cd(self): + """Read terminal status line: Carrier Detect.""" + if not self.is_open: + raise portNotOpenError + return bool(self.get_modem_state() & MODEMSTATE_MASK_CD) + + # - - - platform specific - - - + # None so far + + # - - - RFC2217 specific - - - + + def _telnet_read_loop(self): + """Read loop for the socket.""" + mode = M_NORMAL + suboption = None + try: + while self.is_open: + try: + data = self._socket.recv(1024) + except socket.timeout: + # just need to get out of recv form time to time to check if + # still alive + continue + except socket.error as e: + # connection fails -> terminate loop + if self.logger: + self.logger.debug("socket error in reader thread: {}".format(e)) + break + if not data: + break # lost connection + for byte in iterbytes(data): + if mode == M_NORMAL: + # interpret as command or as data + if byte == IAC: + mode = M_IAC_SEEN + else: + # store data in read buffer or sub option buffer + # depending on state + if suboption is not None: + suboption += byte + else: + self._read_buffer.put(byte) + elif mode == M_IAC_SEEN: + if byte == IAC: + # interpret as command doubled -> insert character + # itself + if suboption is not None: + suboption += IAC + else: + self._read_buffer.put(IAC) + mode = M_NORMAL + elif byte == SB: + # sub option start + suboption = bytearray() + mode = M_NORMAL + elif byte == SE: + # sub option end -> process it now + self._telnet_process_subnegotiation(bytes(suboption)) + suboption = None + mode = M_NORMAL + elif byte in (DO, DONT, WILL, WONT): + # negotiation + telnet_command = byte + mode = M_NEGOTIATE + else: + # other telnet commands + self._telnet_process_command(byte) + mode = M_NORMAL + elif mode == M_NEGOTIATE: # DO, DONT, WILL, WONT was received, option now following + self._telnet_negotiate_option(telnet_command, byte) + mode = M_NORMAL + finally: + self._thread = None + if self.logger: + self.logger.debug("read thread terminated") + + # - incoming telnet commands and options + + def _telnet_process_command(self, command): + """Process commands other than DO, DONT, WILL, WONT.""" + # Currently none. RFC2217 only uses negotiation and subnegotiation. + if self.logger: + self.logger.warning("ignoring Telnet command: {!r}".format(command)) + + def _telnet_negotiate_option(self, command, option): + """Process incoming DO, DONT, WILL, WONT.""" + # check our registered telnet options and forward command to them + # they know themselves if they have to answer or not + known = False + for item in self._telnet_options: + # can have more than one match! as some options are duplicated for + # 'us' and 'them' + if item.option == option: + item.process_incoming(command) + known = True + if not known: + # handle unknown options + # only answer to positive requests and deny them + if command == WILL or command == DO: + self.telnet_send_option((DONT if command == WILL else WONT), option) + if self.logger: + self.logger.warning("rejected Telnet option: {!r}".format(option)) + + def _telnet_process_subnegotiation(self, suboption): + """Process subnegotiation, the data between IAC SB and IAC SE.""" + if suboption[0:1] == COM_PORT_OPTION: + if suboption[1:2] == SERVER_NOTIFY_LINESTATE and len(suboption) >= 3: + self._linestate = ord(suboption[2:3]) # ensure it is a number + if self.logger: + self.logger.info("NOTIFY_LINESTATE: {}".format(self._linestate)) + elif suboption[1:2] == SERVER_NOTIFY_MODEMSTATE and len(suboption) >= 3: + self._modemstate = ord(suboption[2:3]) # ensure it is a number + if self.logger: + self.logger.info("NOTIFY_MODEMSTATE: {}".format(self._modemstate)) + # update time when we think that a poll would make sense + self._modemstate_timeout.restart(0.3) + elif suboption[1:2] == FLOWCONTROL_SUSPEND: + self._remote_suspend_flow = True + elif suboption[1:2] == FLOWCONTROL_RESUME: + self._remote_suspend_flow = False + else: + for item in self._rfc2217_options.values(): + if item.ack_option == suboption[1:2]: + #~ print "processing COM_PORT_OPTION: %r" % list(suboption[1:]) + item.check_answer(bytes(suboption[2:])) + break + else: + if self.logger: + self.logger.warning("ignoring COM_PORT_OPTION: {!r}".format(suboption)) + else: + if self.logger: + self.logger.warning("ignoring subnegotiation: {!r}".format(suboption)) + + # - outgoing telnet commands and options + + def _internal_raw_write(self, data): + """internal socket write with no data escaping. used to send telnet stuff.""" + with self._write_lock: + self._socket.sendall(data) + + def telnet_send_option(self, action, option): + """Send DO, DONT, WILL, WONT.""" + self._internal_raw_write(IAC + action + option) + + def rfc2217_send_subnegotiation(self, option, value=b''): + """Subnegotiation of RFC2217 parameters.""" + value = value.replace(IAC, IAC_DOUBLED) + self._internal_raw_write(IAC + SB + COM_PORT_OPTION + option + value + IAC + SE) + + def rfc2217_send_purge(self, value): + """\ + Send purge request to the remote. + (PURGE_RECEIVE_BUFFER / PURGE_TRANSMIT_BUFFER / PURGE_BOTH_BUFFERS) + """ + item = self._rfc2217_options['purge'] + item.set(value) # transmit desired purge type + item.wait(self._network_timeout) # wait for acknowledge from the server + + def rfc2217_set_control(self, value): + """transmit change of control line to remote""" + item = self._rfc2217_options['control'] + item.set(value) # transmit desired control type + if self._ignore_set_control_answer: + # answers are ignored when option is set. compatibility mode for + # servers that answer, but not the expected one... (or no answer + # at all) i.e. sredird + time.sleep(0.1) # this helps getting the unit tests passed + else: + item.wait(self._network_timeout) # wait for acknowledge from the server + + def rfc2217_flow_server_ready(self): + """\ + check if server is ready to receive data. block for some time when + not. + """ + #~ if self._remote_suspend_flow: + #~ wait--- + + def get_modem_state(self): + """\ + get last modem state (cached value. If value is "old", request a new + one. This cache helps that we don't issue to many requests when e.g. all + status lines, one after the other is queried by the user (CTS, DSR + etc.) + """ + # active modem state polling enabled? is the value fresh enough? + if self._poll_modem_state and self._modemstate_timeout.expired(): + if self.logger: + self.logger.debug('polling modem state') + # when it is older, request an update + self.rfc2217_send_subnegotiation(NOTIFY_MODEMSTATE) + timeout = Timeout(self._network_timeout) + while not timeout.expired(): + time.sleep(0.05) # prevent 100% CPU load + # when expiration time is updated, it means that there is a new + # value + if not self._modemstate_timeout.expired(): + break + else: + if self.logger: + self.logger.warning('poll for modem state failed') + # even when there is a timeout, do not generate an error just + # return the last known value. this way we can support buggy + # servers that do not respond to polls, but send automatic + # updates. + if self._modemstate is not None: + if self.logger: + self.logger.debug('using cached modem state') + return self._modemstate + else: + # never received a notification from the server + raise SerialException("remote sends no NOTIFY_MODEMSTATE") + + +############################################################################# +# The following is code that helps implementing an RFC 2217 server. + +class PortManager(object): + """\ + This class manages the state of Telnet and RFC 2217. It needs a serial + instance and a connection to work with. Connection is expected to implement + a (thread safe) write function, that writes the string to the network. + """ + + def __init__(self, serial_port, connection, logger=None): + self.serial = serial_port + self.connection = connection + self.logger = logger + self._client_is_rfc2217 = False + + # filter state machine + self.mode = M_NORMAL + self.suboption = None + self.telnet_command = None + + # states for modem/line control events + self.modemstate_mask = 255 + self.last_modemstate = None + self.linstate_mask = 0 + + # all supported telnet options + self._telnet_options = [ + TelnetOption(self, 'ECHO', ECHO, WILL, WONT, DO, DONT, REQUESTED), + TelnetOption(self, 'we-SGA', SGA, WILL, WONT, DO, DONT, REQUESTED), + TelnetOption(self, 'they-SGA', SGA, DO, DONT, WILL, WONT, INACTIVE), + TelnetOption(self, 'we-BINARY', BINARY, WILL, WONT, DO, DONT, INACTIVE), + TelnetOption(self, 'they-BINARY', BINARY, DO, DONT, WILL, WONT, REQUESTED), + TelnetOption(self, 'we-RFC2217', COM_PORT_OPTION, WILL, WONT, DO, DONT, REQUESTED, self._client_ok), + TelnetOption(self, 'they-RFC2217', COM_PORT_OPTION, DO, DONT, WILL, WONT, INACTIVE, self._client_ok), + ] + + # negotiate Telnet/RFC2217 -> send initial requests + if self.logger: + self.logger.debug("requesting initial Telnet/RFC 2217 options") + for option in self._telnet_options: + if option.state is REQUESTED: + self.telnet_send_option(option.send_yes, option.option) + # issue 1st modem state notification + + def _client_ok(self): + """\ + callback of telnet option. It gets called when option is activated. + This one here is used to detect when the client agrees on RFC 2217. A + flag is set so that other functions like check_modem_lines know if the + client is OK. + """ + # The callback is used for we and they so if one party agrees, we're + # already happy. it seems not all servers do the negotiation correctly + # and i guess there are incorrect clients too.. so be happy if client + # answers one or the other positively. + self._client_is_rfc2217 = True + if self.logger: + self.logger.info("client accepts RFC 2217") + # this is to ensure that the client gets a notification, even if there + # was no change + self.check_modem_lines(force_notification=True) + + # - outgoing telnet commands and options + + def telnet_send_option(self, action, option): + """Send DO, DONT, WILL, WONT.""" + self.connection.write(IAC + action + option) + + def rfc2217_send_subnegotiation(self, option, value=b''): + """Subnegotiation of RFC 2217 parameters.""" + value = value.replace(IAC, IAC_DOUBLED) + self.connection.write(IAC + SB + COM_PORT_OPTION + option + value + IAC + SE) + + # - check modem lines, needs to be called periodically from user to + # establish polling + + def check_modem_lines(self, force_notification=False): + """\ + read control lines from serial port and compare the last value sent to remote. + send updates on changes. + """ + modemstate = ( + (self.serial.cts and MODEMSTATE_MASK_CTS) | + (self.serial.dsr and MODEMSTATE_MASK_DSR) | + (self.serial.ri and MODEMSTATE_MASK_RI) | + (self.serial.cd and MODEMSTATE_MASK_CD)) + # check what has changed + deltas = modemstate ^ (self.last_modemstate or 0) # when last is None -> 0 + if deltas & MODEMSTATE_MASK_CTS: + modemstate |= MODEMSTATE_MASK_CTS_CHANGE + if deltas & MODEMSTATE_MASK_DSR: + modemstate |= MODEMSTATE_MASK_DSR_CHANGE + if deltas & MODEMSTATE_MASK_RI: + modemstate |= MODEMSTATE_MASK_RI_CHANGE + if deltas & MODEMSTATE_MASK_CD: + modemstate |= MODEMSTATE_MASK_CD_CHANGE + # if new state is different and the mask allows this change, send + # notification. suppress notifications when client is not rfc2217 + if modemstate != self.last_modemstate or force_notification: + if (self._client_is_rfc2217 and (modemstate & self.modemstate_mask)) or force_notification: + self.rfc2217_send_subnegotiation( + SERVER_NOTIFY_MODEMSTATE, + to_bytes([modemstate & self.modemstate_mask])) + if self.logger: + self.logger.info("NOTIFY_MODEMSTATE: {}".format(modemstate)) + # save last state, but forget about deltas. + # otherwise it would also notify about changing deltas which is + # probably not very useful + self.last_modemstate = modemstate & 0xf0 + + # - outgoing data escaping + + def escape(self, data): + """\ + This generator function is for the user. All outgoing data has to be + properly escaped, so that no IAC character in the data stream messes up + the Telnet state machine in the server. + + socket.sendall(escape(data)) + """ + for byte in iterbytes(data): + if byte == IAC: + yield IAC + yield IAC + else: + yield byte + + # - incoming data filter + + def filter(self, data): + """\ + Handle a bunch of incoming bytes. This is a generator. It will yield + all characters not of interest for Telnet/RFC 2217. + + The idea is that the reader thread pushes data from the socket through + this filter: + + for byte in filter(socket.recv(1024)): + # do things like CR/LF conversion/whatever + # and write data to the serial port + serial.write(byte) + + (socket error handling code left as exercise for the reader) + """ + for byte in iterbytes(data): + if self.mode == M_NORMAL: + # interpret as command or as data + if byte == IAC: + self.mode = M_IAC_SEEN + else: + # store data in sub option buffer or pass it to our + # consumer depending on state + if self.suboption is not None: + self.suboption += byte + else: + yield byte + elif self.mode == M_IAC_SEEN: + if byte == IAC: + # interpret as command doubled -> insert character + # itself + if self.suboption is not None: + self.suboption += byte + else: + yield byte + self.mode = M_NORMAL + elif byte == SB: + # sub option start + self.suboption = bytearray() + self.mode = M_NORMAL + elif byte == SE: + # sub option end -> process it now + self._telnet_process_subnegotiation(bytes(self.suboption)) + self.suboption = None + self.mode = M_NORMAL + elif byte in (DO, DONT, WILL, WONT): + # negotiation + self.telnet_command = byte + self.mode = M_NEGOTIATE + else: + # other telnet commands + self._telnet_process_command(byte) + self.mode = M_NORMAL + elif self.mode == M_NEGOTIATE: # DO, DONT, WILL, WONT was received, option now following + self._telnet_negotiate_option(self.telnet_command, byte) + self.mode = M_NORMAL + + # - incoming telnet commands and options + + def _telnet_process_command(self, command): + """Process commands other than DO, DONT, WILL, WONT.""" + # Currently none. RFC2217 only uses negotiation and subnegotiation. + if self.logger: + self.logger.warning("ignoring Telnet command: {!r}".format(command)) + + def _telnet_negotiate_option(self, command, option): + """Process incoming DO, DONT, WILL, WONT.""" + # check our registered telnet options and forward command to them + # they know themselves if they have to answer or not + known = False + for item in self._telnet_options: + # can have more than one match! as some options are duplicated for + # 'us' and 'them' + if item.option == option: + item.process_incoming(command) + known = True + if not known: + # handle unknown options + # only answer to positive requests and deny them + if command == WILL or command == DO: + self.telnet_send_option((DONT if command == WILL else WONT), option) + if self.logger: + self.logger.warning("rejected Telnet option: {!r}".format(option)) + + def _telnet_process_subnegotiation(self, suboption): + """Process subnegotiation, the data between IAC SB and IAC SE.""" + if suboption[0:1] == COM_PORT_OPTION: + if self.logger: + self.logger.debug('received COM_PORT_OPTION: {!r}'.format(suboption)) + if suboption[1:2] == SET_BAUDRATE: + backup = self.serial.baudrate + try: + (baudrate,) = struct.unpack(b"!I", suboption[2:6]) + if baudrate != 0: + self.serial.baudrate = baudrate + except ValueError as e: + if self.logger: + self.logger.error("failed to set baud rate: {}".format(e)) + self.serial.baudrate = backup + else: + if self.logger: + self.logger.info("{} baud rate: {}".format('set' if baudrate else 'get', self.serial.baudrate)) + self.rfc2217_send_subnegotiation(SERVER_SET_BAUDRATE, struct.pack(b"!I", self.serial.baudrate)) + elif suboption[1:2] == SET_DATASIZE: + backup = self.serial.bytesize + try: + (datasize,) = struct.unpack(b"!B", suboption[2:3]) + if datasize != 0: + self.serial.bytesize = datasize + except ValueError as e: + if self.logger: + self.logger.error("failed to set data size: {}".format(e)) + self.serial.bytesize = backup + else: + if self.logger: + self.logger.info("{} data size: {}".format('set' if datasize else 'get', self.serial.bytesize)) + self.rfc2217_send_subnegotiation(SERVER_SET_DATASIZE, struct.pack(b"!B", self.serial.bytesize)) + elif suboption[1:2] == SET_PARITY: + backup = self.serial.parity + try: + parity = struct.unpack(b"!B", suboption[2:3])[0] + if parity != 0: + self.serial.parity = RFC2217_REVERSE_PARITY_MAP[parity] + except ValueError as e: + if self.logger: + self.logger.error("failed to set parity: {}".format(e)) + self.serial.parity = backup + else: + if self.logger: + self.logger.info("{} parity: {}".format('set' if parity else 'get', self.serial.parity)) + self.rfc2217_send_subnegotiation( + SERVER_SET_PARITY, + struct.pack(b"!B", RFC2217_PARITY_MAP[self.serial.parity])) + elif suboption[1:2] == SET_STOPSIZE: + backup = self.serial.stopbits + try: + stopbits = struct.unpack(b"!B", suboption[2:3])[0] + if stopbits != 0: + self.serial.stopbits = RFC2217_REVERSE_STOPBIT_MAP[stopbits] + except ValueError as e: + if self.logger: + self.logger.error("failed to set stop bits: {}".format(e)) + self.serial.stopbits = backup + else: + if self.logger: + self.logger.info("{} stop bits: {}".format('set' if stopbits else 'get', self.serial.stopbits)) + self.rfc2217_send_subnegotiation( + SERVER_SET_STOPSIZE, + struct.pack(b"!B", RFC2217_STOPBIT_MAP[self.serial.stopbits])) + elif suboption[1:2] == SET_CONTROL: + if suboption[2:3] == SET_CONTROL_REQ_FLOW_SETTING: + if self.serial.xonxoff: + self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_USE_SW_FLOW_CONTROL) + elif self.serial.rtscts: + self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_USE_HW_FLOW_CONTROL) + else: + self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_USE_NO_FLOW_CONTROL) + elif suboption[2:3] == SET_CONTROL_USE_NO_FLOW_CONTROL: + self.serial.xonxoff = False + self.serial.rtscts = False + if self.logger: + self.logger.info("changed flow control to None") + self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_USE_NO_FLOW_CONTROL) + elif suboption[2:3] == SET_CONTROL_USE_SW_FLOW_CONTROL: + self.serial.xonxoff = True + if self.logger: + self.logger.info("changed flow control to XON/XOFF") + self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_USE_SW_FLOW_CONTROL) + elif suboption[2:3] == SET_CONTROL_USE_HW_FLOW_CONTROL: + self.serial.rtscts = True + if self.logger: + self.logger.info("changed flow control to RTS/CTS") + self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_USE_HW_FLOW_CONTROL) + elif suboption[2:3] == SET_CONTROL_REQ_BREAK_STATE: + if self.logger: + self.logger.warning("requested break state - not implemented") + pass # XXX needs cached value + elif suboption[2:3] == SET_CONTROL_BREAK_ON: + self.serial.break_condition = True + if self.logger: + self.logger.info("changed BREAK to active") + self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_BREAK_ON) + elif suboption[2:3] == SET_CONTROL_BREAK_OFF: + self.serial.break_condition = False + if self.logger: + self.logger.info("changed BREAK to inactive") + self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_BREAK_OFF) + elif suboption[2:3] == SET_CONTROL_REQ_DTR: + if self.logger: + self.logger.warning("requested DTR state - not implemented") + pass # XXX needs cached value + elif suboption[2:3] == SET_CONTROL_DTR_ON: + self.serial.dtr = True + if self.logger: + self.logger.info("changed DTR to active") + self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_DTR_ON) + elif suboption[2:3] == SET_CONTROL_DTR_OFF: + self.serial.dtr = False + if self.logger: + self.logger.info("changed DTR to inactive") + self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_DTR_OFF) + elif suboption[2:3] == SET_CONTROL_REQ_RTS: + if self.logger: + self.logger.warning("requested RTS state - not implemented") + pass # XXX needs cached value + #~ self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_RTS_ON) + elif suboption[2:3] == SET_CONTROL_RTS_ON: + self.serial.rts = True + if self.logger: + self.logger.info("changed RTS to active") + self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_RTS_ON) + elif suboption[2:3] == SET_CONTROL_RTS_OFF: + self.serial.rts = False + if self.logger: + self.logger.info("changed RTS to inactive") + self.rfc2217_send_subnegotiation(SERVER_SET_CONTROL, SET_CONTROL_RTS_OFF) + #~ elif suboption[2:3] == SET_CONTROL_REQ_FLOW_SETTING_IN: + #~ elif suboption[2:3] == SET_CONTROL_USE_NO_FLOW_CONTROL_IN: + #~ elif suboption[2:3] == SET_CONTROL_USE_SW_FLOW_CONTOL_IN: + #~ elif suboption[2:3] == SET_CONTROL_USE_HW_FLOW_CONTOL_IN: + #~ elif suboption[2:3] == SET_CONTROL_USE_DCD_FLOW_CONTROL: + #~ elif suboption[2:3] == SET_CONTROL_USE_DTR_FLOW_CONTROL: + #~ elif suboption[2:3] == SET_CONTROL_USE_DSR_FLOW_CONTROL: + elif suboption[1:2] == NOTIFY_LINESTATE: + # client polls for current state + self.rfc2217_send_subnegotiation( + SERVER_NOTIFY_LINESTATE, + to_bytes([0])) # sorry, nothing like that implemented + elif suboption[1:2] == NOTIFY_MODEMSTATE: + if self.logger: + self.logger.info("request for modem state") + # client polls for current state + self.check_modem_lines(force_notification=True) + elif suboption[1:2] == FLOWCONTROL_SUSPEND: + if self.logger: + self.logger.info("suspend") + self._remote_suspend_flow = True + elif suboption[1:2] == FLOWCONTROL_RESUME: + if self.logger: + self.logger.info("resume") + self._remote_suspend_flow = False + elif suboption[1:2] == SET_LINESTATE_MASK: + self.linstate_mask = ord(suboption[2:3]) # ensure it is a number + if self.logger: + self.logger.info("line state mask: 0x{:02x}".format(self.linstate_mask)) + elif suboption[1:2] == SET_MODEMSTATE_MASK: + self.modemstate_mask = ord(suboption[2:3]) # ensure it is a number + if self.logger: + self.logger.info("modem state mask: 0x{:02x}".format(self.modemstate_mask)) + elif suboption[1:2] == PURGE_DATA: + if suboption[2:3] == PURGE_RECEIVE_BUFFER: + self.serial.reset_input_buffer() + if self.logger: + self.logger.info("purge in") + self.rfc2217_send_subnegotiation(SERVER_PURGE_DATA, PURGE_RECEIVE_BUFFER) + elif suboption[2:3] == PURGE_TRANSMIT_BUFFER: + self.serial.reset_output_buffer() + if self.logger: + self.logger.info("purge out") + self.rfc2217_send_subnegotiation(SERVER_PURGE_DATA, PURGE_TRANSMIT_BUFFER) + elif suboption[2:3] == PURGE_BOTH_BUFFERS: + self.serial.reset_input_buffer() + self.serial.reset_output_buffer() + if self.logger: + self.logger.info("purge both") + self.rfc2217_send_subnegotiation(SERVER_PURGE_DATA, PURGE_BOTH_BUFFERS) + else: + if self.logger: + self.logger.error("undefined PURGE_DATA: {!r}".format(list(suboption[2:]))) + else: + if self.logger: + self.logger.error("undefined COM_PORT_OPTION: {!r}".format(list(suboption[1:]))) + else: + if self.logger: + self.logger.warning("unknown subnegotiation: {!r}".format(suboption)) + + +# simple client test +if __name__ == '__main__': + import sys + s = Serial('rfc2217://localhost:7000', 115200) + sys.stdout.write('{}\n'.format(s)) + + sys.stdout.write("write...\n") + s.write(b"hello\n") + s.flush() + sys.stdout.write("read: {}\n".format(s.read(5))) + s.close() diff --git a/software/tools/pymcuprog/libs/serial/rs485.py b/software/tools/pymcuprog/libs/serial/rs485.py new file mode 100644 index 0000000..2939350 --- /dev/null +++ b/software/tools/pymcuprog/libs/serial/rs485.py @@ -0,0 +1,92 @@ +#!/usr/bin/env python + +# RS485 support +# +# This file is part of pySerial. https://github.com/pyserial/pyserial +# (C) 2015 Chris Liechti +# +# SPDX-License-Identifier: BSD-3-Clause + +"""\ +The settings for RS485 are stored in a dedicated object that can be applied to +serial ports (where supported). +NOTE: Some implementations may only support a subset of the settings. +""" + +import time +import serial + + +class RS485Settings(object): + def __init__( + self, + rts_level_for_tx=True, + rts_level_for_rx=False, + loopback=False, + delay_before_tx=None, + delay_before_rx=None): + self.rts_level_for_tx = rts_level_for_tx + self.rts_level_for_rx = rts_level_for_rx + self.loopback = loopback + self.delay_before_tx = delay_before_tx + self.delay_before_rx = delay_before_rx + + +class RS485(serial.Serial): + """\ + A subclass that replaces the write method with one that toggles RTS + according to the RS485 settings. + + NOTE: This may work unreliably on some serial ports (control signals not + synchronized or delayed compared to data). Using delays may be + unreliable (varying times, larger than expected) as the OS may not + support very fine grained delays (no smaller than in the order of + tens of milliseconds). + + NOTE: Some implementations support this natively. Better performance + can be expected when the native version is used. + + NOTE: The loopback property is ignored by this implementation. The actual + behavior depends on the used hardware. + + Usage: + + ser = RS485(...) + ser.rs485_mode = RS485Settings(...) + ser.write(b'hello') + """ + + def __init__(self, *args, **kwargs): + super(RS485, self).__init__(*args, **kwargs) + self._alternate_rs485_settings = None + + def write(self, b): + """Write to port, controlling RTS before and after transmitting.""" + if self._alternate_rs485_settings is not None: + # apply level for TX and optional delay + self.setRTS(self._alternate_rs485_settings.rts_level_for_tx) + if self._alternate_rs485_settings.delay_before_tx is not None: + time.sleep(self._alternate_rs485_settings.delay_before_tx) + # write and wait for data to be written + super(RS485, self).write(b) + super(RS485, self).flush() + # optional delay and apply level for RX + if self._alternate_rs485_settings.delay_before_rx is not None: + time.sleep(self._alternate_rs485_settings.delay_before_rx) + self.setRTS(self._alternate_rs485_settings.rts_level_for_rx) + else: + super(RS485, self).write(b) + + # redirect where the property stores the settings so that underlying Serial + # instance does not see them + @property + def rs485_mode(self): + """\ + Enable RS485 mode and apply new settings, set to None to disable. + See serial.rs485.RS485Settings for more info about the value. + """ + return self._alternate_rs485_settings + + @rs485_mode.setter + def rs485_mode(self, rs485_settings): + self._alternate_rs485_settings = rs485_settings diff --git a/software/tools/pymcuprog/libs/serial/serialcli.py b/software/tools/pymcuprog/libs/serial/serialcli.py new file mode 100644 index 0000000..0727a52 --- /dev/null +++ b/software/tools/pymcuprog/libs/serial/serialcli.py @@ -0,0 +1,251 @@ +#! python +# +# Backend for .NET/Mono (IronPython), .NET >= 2 +# +# This file is part of pySerial. https://github.com/pyserial/pyserial +# (C) 2008-2015 Chris Liechti +# +# SPDX-License-Identifier: BSD-3-Clause + +import System +import System.IO.Ports +from serial.serialutil import * + +# must invoke function with byte array, make a helper to convert strings +# to byte arrays +sab = System.Array[System.Byte] + + +def as_byte_array(string): + return sab([ord(x) for x in string]) # XXX will require adaption when run with a 3.x compatible IronPython + + +class Serial(SerialBase): + """Serial port implementation for .NET/Mono.""" + + BAUDRATES = (50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, 4800, + 9600, 19200, 38400, 57600, 115200) + + def open(self): + """\ + Open port with current settings. This may throw a SerialException + if the port cannot be opened. + """ + if self._port is None: + raise SerialException("Port must be configured before it can be used.") + if self.is_open: + raise SerialException("Port is already open.") + try: + self._port_handle = System.IO.Ports.SerialPort(self.portstr) + except Exception as msg: + self._port_handle = None + raise SerialException("could not open port %s: %s" % (self.portstr, msg)) + + # if RTS and/or DTR are not set before open, they default to True + if self._rts_state is None: + self._rts_state = True + if self._dtr_state is None: + self._dtr_state = True + + self._reconfigure_port() + self._port_handle.Open() + self.is_open = True + if not self._dsrdtr: + self._update_dtr_state() + if not self._rtscts: + self._update_rts_state() + self.reset_input_buffer() + + def _reconfigure_port(self): + """Set communication parameters on opened port.""" + if not self._port_handle: + raise SerialException("Can only operate on a valid port handle") + + #~ self._port_handle.ReceivedBytesThreshold = 1 + + if self._timeout is None: + self._port_handle.ReadTimeout = System.IO.Ports.SerialPort.InfiniteTimeout + else: + self._port_handle.ReadTimeout = int(self._timeout * 1000) + + # if self._timeout != 0 and self._interCharTimeout is not None: + # timeouts = (int(self._interCharTimeout * 1000),) + timeouts[1:] + + if self._write_timeout is None: + self._port_handle.WriteTimeout = System.IO.Ports.SerialPort.InfiniteTimeout + else: + self._port_handle.WriteTimeout = int(self._write_timeout * 1000) + + # Setup the connection info. + try: + self._port_handle.BaudRate = self._baudrate + except IOError as e: + # catch errors from illegal baudrate settings + raise ValueError(str(e)) + + if self._bytesize == FIVEBITS: + self._port_handle.DataBits = 5 + elif self._bytesize == SIXBITS: + self._port_handle.DataBits = 6 + elif self._bytesize == SEVENBITS: + self._port_handle.DataBits = 7 + elif self._bytesize == EIGHTBITS: + self._port_handle.DataBits = 8 + else: + raise ValueError("Unsupported number of data bits: %r" % self._bytesize) + + if self._parity == PARITY_NONE: + self._port_handle.Parity = getattr(System.IO.Ports.Parity, 'None') # reserved keyword in Py3k + elif self._parity == PARITY_EVEN: + self._port_handle.Parity = System.IO.Ports.Parity.Even + elif self._parity == PARITY_ODD: + self._port_handle.Parity = System.IO.Ports.Parity.Odd + elif self._parity == PARITY_MARK: + self._port_handle.Parity = System.IO.Ports.Parity.Mark + elif self._parity == PARITY_SPACE: + self._port_handle.Parity = System.IO.Ports.Parity.Space + else: + raise ValueError("Unsupported parity mode: %r" % self._parity) + + if self._stopbits == STOPBITS_ONE: + self._port_handle.StopBits = System.IO.Ports.StopBits.One + elif self._stopbits == STOPBITS_ONE_POINT_FIVE: + self._port_handle.StopBits = System.IO.Ports.StopBits.OnePointFive + elif self._stopbits == STOPBITS_TWO: + self._port_handle.StopBits = System.IO.Ports.StopBits.Two + else: + raise ValueError("Unsupported number of stop bits: %r" % self._stopbits) + + if self._rtscts and self._xonxoff: + self._port_handle.Handshake = System.IO.Ports.Handshake.RequestToSendXOnXOff + elif self._rtscts: + self._port_handle.Handshake = System.IO.Ports.Handshake.RequestToSend + elif self._xonxoff: + self._port_handle.Handshake = System.IO.Ports.Handshake.XOnXOff + else: + self._port_handle.Handshake = getattr(System.IO.Ports.Handshake, 'None') # reserved keyword in Py3k + + #~ def __del__(self): + #~ self.close() + + def close(self): + """Close port""" + if self.is_open: + if self._port_handle: + try: + self._port_handle.Close() + except System.IO.Ports.InvalidOperationException: + # ignore errors. can happen for unplugged USB serial devices + pass + self._port_handle = None + self.is_open = False + + # - - - - - - - - - - - - - - - - - - - - - - - - + + @property + def in_waiting(self): + """Return the number of characters currently in the input buffer.""" + if not self.is_open: + raise portNotOpenError + return self._port_handle.BytesToRead + + def read(self, size=1): + """\ + Read size bytes from the serial port. If a timeout is set it may + return less characters as requested. With no timeout it will block + until the requested number of bytes is read. + """ + if not self.is_open: + raise portNotOpenError + # must use single byte reads as this is the only way to read + # without applying encodings + data = bytearray() + while size: + try: + data.append(self._port_handle.ReadByte()) + except System.TimeoutException: + break + else: + size -= 1 + return bytes(data) + + def write(self, data): + """Output the given string over the serial port.""" + if not self.is_open: + raise portNotOpenError + #~ if not isinstance(data, (bytes, bytearray)): + #~ raise TypeError('expected %s or bytearray, got %s' % (bytes, type(data))) + try: + # must call overloaded method with byte array argument + # as this is the only one not applying encodings + self._port_handle.Write(as_byte_array(data), 0, len(data)) + except System.TimeoutException: + raise writeTimeoutError + return len(data) + + def reset_input_buffer(self): + """Clear input buffer, discarding all that is in the buffer.""" + if not self.is_open: + raise portNotOpenError + self._port_handle.DiscardInBuffer() + + def reset_output_buffer(self): + """\ + Clear output buffer, aborting the current output and + discarding all that is in the buffer. + """ + if not self.is_open: + raise portNotOpenError + self._port_handle.DiscardOutBuffer() + + def _update_break_state(self): + """ + Set break: Controls TXD. When active, to transmitting is possible. + """ + if not self.is_open: + raise portNotOpenError + self._port_handle.BreakState = bool(self._break_state) + + def _update_rts_state(self): + """Set terminal status line: Request To Send""" + if not self.is_open: + raise portNotOpenError + self._port_handle.RtsEnable = bool(self._rts_state) + + def _update_dtr_state(self): + """Set terminal status line: Data Terminal Ready""" + if not self.is_open: + raise portNotOpenError + self._port_handle.DtrEnable = bool(self._dtr_state) + + @property + def cts(self): + """Read terminal status line: Clear To Send""" + if not self.is_open: + raise portNotOpenError + return self._port_handle.CtsHolding + + @property + def dsr(self): + """Read terminal status line: Data Set Ready""" + if not self.is_open: + raise portNotOpenError + return self._port_handle.DsrHolding + + @property + def ri(self): + """Read terminal status line: Ring Indicator""" + if not self.is_open: + raise portNotOpenError + #~ return self._port_handle.XXX + return False # XXX an error would be better + + @property + def cd(self): + """Read terminal status line: Carrier Detect""" + if not self.is_open: + raise portNotOpenError + return self._port_handle.CDHolding + + # - - platform specific - - - - + # none diff --git a/software/tools/pymcuprog/libs/serial/serialjava.py b/software/tools/pymcuprog/libs/serial/serialjava.py new file mode 100644 index 0000000..7bd5b3e --- /dev/null +++ b/software/tools/pymcuprog/libs/serial/serialjava.py @@ -0,0 +1,249 @@ +#!jython +# +# Backend Jython with JavaComm +# +# This file is part of pySerial. https://github.com/pyserial/pyserial +# (C) 2002-2015 Chris Liechti +# +# SPDX-License-Identifier: BSD-3-Clause + +from serial.serialutil import * + + +def my_import(name): + mod = __import__(name) + components = name.split('.') + for comp in components[1:]: + mod = getattr(mod, comp) + return mod + + +def detect_java_comm(names): + """try given list of modules and return that imports""" + for name in names: + try: + mod = my_import(name) + mod.SerialPort + return mod + except (ImportError, AttributeError): + pass + raise ImportError("No Java Communications API implementation found") + + +# Java Communications API implementations +# http://mho.republika.pl/java/comm/ + +comm = detect_java_comm([ + 'javax.comm', # Sun/IBM + 'gnu.io', # RXTX +]) + + +def device(portnumber): + """Turn a port number into a device name""" + enum = comm.CommPortIdentifier.getPortIdentifiers() + ports = [] + while enum.hasMoreElements(): + el = enum.nextElement() + if el.getPortType() == comm.CommPortIdentifier.PORT_SERIAL: + ports.append(el) + return ports[portnumber].getName() + + +class Serial(SerialBase): + """\ + Serial port class, implemented with Java Communications API and + thus usable with jython and the appropriate java extension. + """ + + def open(self): + """\ + Open port with current settings. This may throw a SerialException + if the port cannot be opened. + """ + if self._port is None: + raise SerialException("Port must be configured before it can be used.") + if self.is_open: + raise SerialException("Port is already open.") + if type(self._port) == type(''): # strings are taken directly + portId = comm.CommPortIdentifier.getPortIdentifier(self._port) + else: + portId = comm.CommPortIdentifier.getPortIdentifier(device(self._port)) # numbers are transformed to a comport id obj + try: + self.sPort = portId.open("python serial module", 10) + except Exception as msg: + self.sPort = None + raise SerialException("Could not open port: %s" % msg) + self._reconfigurePort() + self._instream = self.sPort.getInputStream() + self._outstream = self.sPort.getOutputStream() + self.is_open = True + + def _reconfigurePort(self): + """Set communication parameters on opened port.""" + if not self.sPort: + raise SerialException("Can only operate on a valid port handle") + + self.sPort.enableReceiveTimeout(30) + if self._bytesize == FIVEBITS: + jdatabits = comm.SerialPort.DATABITS_5 + elif self._bytesize == SIXBITS: + jdatabits = comm.SerialPort.DATABITS_6 + elif self._bytesize == SEVENBITS: + jdatabits = comm.SerialPort.DATABITS_7 + elif self._bytesize == EIGHTBITS: + jdatabits = comm.SerialPort.DATABITS_8 + else: + raise ValueError("unsupported bytesize: %r" % self._bytesize) + + if self._stopbits == STOPBITS_ONE: + jstopbits = comm.SerialPort.STOPBITS_1 + elif self._stopbits == STOPBITS_ONE_POINT_FIVE: + jstopbits = comm.SerialPort.STOPBITS_1_5 + elif self._stopbits == STOPBITS_TWO: + jstopbits = comm.SerialPort.STOPBITS_2 + else: + raise ValueError("unsupported number of stopbits: %r" % self._stopbits) + + if self._parity == PARITY_NONE: + jparity = comm.SerialPort.PARITY_NONE + elif self._parity == PARITY_EVEN: + jparity = comm.SerialPort.PARITY_EVEN + elif self._parity == PARITY_ODD: + jparity = comm.SerialPort.PARITY_ODD + elif self._parity == PARITY_MARK: + jparity = comm.SerialPort.PARITY_MARK + elif self._parity == PARITY_SPACE: + jparity = comm.SerialPort.PARITY_SPACE + else: + raise ValueError("unsupported parity type: %r" % self._parity) + + jflowin = jflowout = 0 + if self._rtscts: + jflowin |= comm.SerialPort.FLOWCONTROL_RTSCTS_IN + jflowout |= comm.SerialPort.FLOWCONTROL_RTSCTS_OUT + if self._xonxoff: + jflowin |= comm.SerialPort.FLOWCONTROL_XONXOFF_IN + jflowout |= comm.SerialPort.FLOWCONTROL_XONXOFF_OUT + + self.sPort.setSerialPortParams(self._baudrate, jdatabits, jstopbits, jparity) + self.sPort.setFlowControlMode(jflowin | jflowout) + + if self._timeout >= 0: + self.sPort.enableReceiveTimeout(int(self._timeout*1000)) + else: + self.sPort.disableReceiveTimeout() + + def close(self): + """Close port""" + if self.is_open: + if self.sPort: + self._instream.close() + self._outstream.close() + self.sPort.close() + self.sPort = None + self.is_open = False + + # - - - - - - - - - - - - - - - - - - - - - - - - + + @property + def in_waiting(self): + """Return the number of characters currently in the input buffer.""" + if not self.sPort: + raise portNotOpenError + return self._instream.available() + + def read(self, size=1): + """\ + Read size bytes from the serial port. If a timeout is set it may + return less characters as requested. With no timeout it will block + until the requested number of bytes is read. + """ + if not self.sPort: + raise portNotOpenError + read = bytearray() + if size > 0: + while len(read) < size: + x = self._instream.read() + if x == -1: + if self.timeout >= 0: + break + else: + read.append(x) + return bytes(read) + + def write(self, data): + """Output the given string over the serial port.""" + if not self.sPort: + raise portNotOpenError + if not isinstance(data, (bytes, bytearray)): + raise TypeError('expected %s or bytearray, got %s' % (bytes, type(data))) + self._outstream.write(data) + return len(data) + + def reset_input_buffer(self): + """Clear input buffer, discarding all that is in the buffer.""" + if not self.sPort: + raise portNotOpenError + self._instream.skip(self._instream.available()) + + def reset_output_buffer(self): + """\ + Clear output buffer, aborting the current output and + discarding all that is in the buffer. + """ + if not self.sPort: + raise portNotOpenError + self._outstream.flush() + + def send_break(self, duration=0.25): + """Send break condition. Timed, returns to idle state after given duration.""" + if not self.sPort: + raise portNotOpenError + self.sPort.sendBreak(duration*1000.0) + + def _update_break_state(self): + """Set break: Controls TXD. When active, to transmitting is possible.""" + if self.fd is None: + raise portNotOpenError + raise SerialException("The _update_break_state function is not implemented in java.") + + def _update_rts_state(self): + """Set terminal status line: Request To Send""" + if not self.sPort: + raise portNotOpenError + self.sPort.setRTS(self._rts_state) + + def _update_dtr_state(self): + """Set terminal status line: Data Terminal Ready""" + if not self.sPort: + raise portNotOpenError + self.sPort.setDTR(self._dtr_state) + + @property + def cts(self): + """Read terminal status line: Clear To Send""" + if not self.sPort: + raise portNotOpenError + self.sPort.isCTS() + + @property + def dsr(self): + """Read terminal status line: Data Set Ready""" + if not self.sPort: + raise portNotOpenError + self.sPort.isDSR() + + @property + def ri(self): + """Read terminal status line: Ring Indicator""" + if not self.sPort: + raise portNotOpenError + self.sPort.isRI() + + @property + def cd(self): + """Read terminal status line: Carrier Detect""" + if not self.sPort: + raise portNotOpenError + self.sPort.isCD() diff --git a/software/tools/pymcuprog/libs/serial/serialposix.py b/software/tools/pymcuprog/libs/serial/serialposix.py new file mode 100644 index 0000000..afe5062 --- /dev/null +++ b/software/tools/pymcuprog/libs/serial/serialposix.py @@ -0,0 +1,811 @@ +#!/usr/bin/env python +# +# backend for serial IO for POSIX compatible systems, like Linux, OSX +# +# This file is part of pySerial. https://github.com/pyserial/pyserial +# (C) 2001-2016 Chris Liechti +# +# SPDX-License-Identifier: BSD-3-Clause +# +# parts based on code from Grant B. Edwards : +# ftp://ftp.visi.com/users/grante/python/PosixSerial.py +# +# references: http://www.easysw.com/~mike/serial/serial.html + +# Collection of port names (was previously used by number_to_device which was +# removed. +# - Linux /dev/ttyS%d (confirmed) +# - cygwin/win32 /dev/com%d (confirmed) +# - openbsd (OpenBSD) /dev/cua%02d +# - bsd*, freebsd* /dev/cuad%d +# - darwin (OS X) /dev/cuad%d +# - netbsd /dev/dty%02d (NetBSD 1.6 testing by Erk) +# - irix (IRIX) /dev/ttyf%d (partially tested) names depending on flow control +# - hp (HP-UX) /dev/tty%dp0 (not tested) +# - sunos (Solaris/SunOS) /dev/tty%c (letters, 'a'..'z') (confirmed) +# - aix (AIX) /dev/tty%d + + +# pylint: disable=abstract-method +import errno +import fcntl +import os +import select +import struct +import sys +import termios + +import serial +from serial.serialutil import SerialBase, SerialException, to_bytes, \ + portNotOpenError, writeTimeoutError, Timeout + + +class PlatformSpecificBase(object): + BAUDRATE_CONSTANTS = {} + + def _set_special_baudrate(self, baudrate): + raise NotImplementedError('non-standard baudrates are not supported on this platform') + + def _set_rs485_mode(self, rs485_settings): + raise NotImplementedError('RS485 not supported on this platform') + + +# some systems support an extra flag to enable the two in POSIX unsupported +# paritiy settings for MARK and SPACE +CMSPAR = 0 # default, for unsupported platforms, override below + +# try to detect the OS so that a device can be selected... +# this code block should supply a device() and set_special_baudrate() function +# for the platform +plat = sys.platform.lower() + +if plat[:5] == 'linux': # Linux (confirmed) # noqa + import array + + # extra termios flags + CMSPAR = 0o10000000000 # Use "stick" (mark/space) parity + + # baudrate ioctls + TCGETS2 = 0x802C542A + TCSETS2 = 0x402C542B + BOTHER = 0o010000 + + # RS485 ioctls + TIOCGRS485 = 0x542E + TIOCSRS485 = 0x542F + SER_RS485_ENABLED = 0b00000001 + SER_RS485_RTS_ON_SEND = 0b00000010 + SER_RS485_RTS_AFTER_SEND = 0b00000100 + SER_RS485_RX_DURING_TX = 0b00010000 + + class PlatformSpecific(PlatformSpecificBase): + BAUDRATE_CONSTANTS = { + 0: 0o000000, # hang up + 50: 0o000001, + 75: 0o000002, + 110: 0o000003, + 134: 0o000004, + 150: 0o000005, + 200: 0o000006, + 300: 0o000007, + 600: 0o000010, + 1200: 0o000011, + 1800: 0o000012, + 2400: 0o000013, + 4800: 0o000014, + 9600: 0o000015, + 19200: 0o000016, + 38400: 0o000017, + 57600: 0o010001, + 115200: 0o010002, + 230400: 0o010003, + 460800: 0o010004, + 500000: 0o010005, + 576000: 0o010006, + 921600: 0o010007, + 1000000: 0o010010, + 1152000: 0o010011, + 1500000: 0o010012, + 2000000: 0o010013, + 2500000: 0o010014, + 3000000: 0o010015, + 3500000: 0o010016, + 4000000: 0o010017 + } + + def _set_special_baudrate(self, baudrate): + # right size is 44 on x86_64, allow for some growth + buf = array.array('i', [0] * 64) + try: + # get serial_struct + fcntl.ioctl(self.fd, TCGETS2, buf) + # set custom speed + buf[2] &= ~termios.CBAUD + buf[2] |= BOTHER + buf[9] = buf[10] = baudrate + + # set serial_struct + fcntl.ioctl(self.fd, TCSETS2, buf) + except IOError as e: + raise ValueError('Failed to set custom baud rate ({}): {}'.format(baudrate, e)) + + def _set_rs485_mode(self, rs485_settings): + buf = array.array('i', [0] * 8) # flags, delaytx, delayrx, padding + try: + fcntl.ioctl(self.fd, TIOCGRS485, buf) + buf[0] |= SER_RS485_ENABLED + if rs485_settings is not None: + if rs485_settings.loopback: + buf[0] |= SER_RS485_RX_DURING_TX + else: + buf[0] &= ~SER_RS485_RX_DURING_TX + if rs485_settings.rts_level_for_tx: + buf[0] |= SER_RS485_RTS_ON_SEND + else: + buf[0] &= ~SER_RS485_RTS_ON_SEND + if rs485_settings.rts_level_for_rx: + buf[0] |= SER_RS485_RTS_AFTER_SEND + else: + buf[0] &= ~SER_RS485_RTS_AFTER_SEND + if rs485_settings.delay_before_tx is not None: + buf[1] = int(rs485_settings.delay_before_tx * 1000) + if rs485_settings.delay_before_rx is not None: + buf[2] = int(rs485_settings.delay_before_rx * 1000) + else: + buf[0] = 0 # clear SER_RS485_ENABLED + fcntl.ioctl(self.fd, TIOCSRS485, buf) + except IOError as e: + raise ValueError('Failed to set RS485 mode: {}'.format(e)) + + +elif plat == 'cygwin': # cygwin/win32 (confirmed) + + class PlatformSpecific(PlatformSpecificBase): + BAUDRATE_CONSTANTS = { + 128000: 0x01003, + 256000: 0x01005, + 500000: 0x01007, + 576000: 0x01008, + 921600: 0x01009, + 1000000: 0x0100a, + 1152000: 0x0100b, + 1500000: 0x0100c, + 2000000: 0x0100d, + 2500000: 0x0100e, + 3000000: 0x0100f + } + + +elif plat[:6] == 'darwin': # OS X + import array + IOSSIOSPEED = 0x80045402 # _IOW('T', 2, speed_t) + + class PlatformSpecific(PlatformSpecificBase): + osx_version = os.uname()[2].split('.') + # Tiger or above can support arbitrary serial speeds + if int(osx_version[0]) >= 8: + def _set_special_baudrate(self, baudrate): + # use IOKit-specific call to set up high speeds + buf = array.array('i', [baudrate]) + fcntl.ioctl(self.fd, IOSSIOSPEED, buf, 1) + +elif plat[:3] == 'bsd' or \ + plat[:7] == 'freebsd' or \ + plat[:6] == 'netbsd' or \ + plat[:7] == 'openbsd': + + class ReturnBaudrate(object): + def __getitem__(self, key): + return key + + class PlatformSpecific(PlatformSpecificBase): + # Only tested on FreeBSD: + # The baud rate may be passed in as + # a literal value. + BAUDRATE_CONSTANTS = ReturnBaudrate() + +else: + class PlatformSpecific(PlatformSpecificBase): + pass + + +# load some constants for later use. +# try to use values from termios, use defaults from linux otherwise +TIOCMGET = getattr(termios, 'TIOCMGET', 0x5415) +TIOCMBIS = getattr(termios, 'TIOCMBIS', 0x5416) +TIOCMBIC = getattr(termios, 'TIOCMBIC', 0x5417) +TIOCMSET = getattr(termios, 'TIOCMSET', 0x5418) + +# TIOCM_LE = getattr(termios, 'TIOCM_LE', 0x001) +TIOCM_DTR = getattr(termios, 'TIOCM_DTR', 0x002) +TIOCM_RTS = getattr(termios, 'TIOCM_RTS', 0x004) +# TIOCM_ST = getattr(termios, 'TIOCM_ST', 0x008) +# TIOCM_SR = getattr(termios, 'TIOCM_SR', 0x010) + +TIOCM_CTS = getattr(termios, 'TIOCM_CTS', 0x020) +TIOCM_CAR = getattr(termios, 'TIOCM_CAR', 0x040) +TIOCM_RNG = getattr(termios, 'TIOCM_RNG', 0x080) +TIOCM_DSR = getattr(termios, 'TIOCM_DSR', 0x100) +TIOCM_CD = getattr(termios, 'TIOCM_CD', TIOCM_CAR) +TIOCM_RI = getattr(termios, 'TIOCM_RI', TIOCM_RNG) +# TIOCM_OUT1 = getattr(termios, 'TIOCM_OUT1', 0x2000) +# TIOCM_OUT2 = getattr(termios, 'TIOCM_OUT2', 0x4000) +if hasattr(termios, 'TIOCINQ'): + TIOCINQ = termios.TIOCINQ +else: + TIOCINQ = getattr(termios, 'FIONREAD', 0x541B) +TIOCOUTQ = getattr(termios, 'TIOCOUTQ', 0x5411) + +TIOCM_zero_str = struct.pack('I', 0) +TIOCM_RTS_str = struct.pack('I', TIOCM_RTS) +TIOCM_DTR_str = struct.pack('I', TIOCM_DTR) + +TIOCSBRK = getattr(termios, 'TIOCSBRK', 0x5427) +TIOCCBRK = getattr(termios, 'TIOCCBRK', 0x5428) + + +class Serial(SerialBase, PlatformSpecific): + """\ + Serial port class POSIX implementation. Serial port configuration is + done with termios and fcntl. Runs on Linux and many other Un*x like + systems. + """ + + def open(self): + """\ + Open port with current settings. This may throw a SerialException + if the port cannot be opened.""" + if self._port is None: + raise SerialException("Port must be configured before it can be used.") + if self.is_open: + raise SerialException("Port is already open.") + self.fd = None + # open + try: + self.fd = os.open(self.portstr, os.O_RDWR | os.O_NOCTTY | os.O_NONBLOCK) + except OSError as msg: + self.fd = None + raise SerialException(msg.errno, "could not open port {}: {}".format(self._port, msg)) + #~ fcntl.fcntl(self.fd, fcntl.F_SETFL, 0) # set blocking + + try: + self._reconfigure_port(force_update=True) + except: + try: + os.close(self.fd) + except: + # ignore any exception when closing the port + # also to keep original exception that happened when setting up + pass + self.fd = None + raise + else: + self.is_open = True + try: + if not self._dsrdtr: + self._update_dtr_state() + if not self._rtscts: + self._update_rts_state() + except IOError as e: + if e.errno in (errno.EINVAL, errno.ENOTTY): + # ignore Invalid argument and Inappropriate ioctl + pass + else: + raise + self.reset_input_buffer() + self.pipe_abort_read_r, self.pipe_abort_read_w = os.pipe() + self.pipe_abort_write_r, self.pipe_abort_write_w = os.pipe() + fcntl.fcntl(self.pipe_abort_read_r, fcntl.F_SETFL, os.O_NONBLOCK) + fcntl.fcntl(self.pipe_abort_write_r, fcntl.F_SETFL, os.O_NONBLOCK) + + def _reconfigure_port(self, force_update=False): + """Set communication parameters on opened port.""" + if self.fd is None: + raise SerialException("Can only operate on a valid file descriptor") + + # if exclusive lock is requested, create it before we modify anything else + if self._exclusive is not None: + if self._exclusive: + try: + fcntl.flock(self.fd, fcntl.LOCK_EX | fcntl.LOCK_NB) + except IOError as msg: + raise SerialException(msg.errno, "Could not exclusively lock port {}: {}".format(self._port, msg)) + else: + fcntl.flock(self.fd, fcntl.LOCK_UN) + + custom_baud = None + + vmin = vtime = 0 # timeout is done via select + if self._inter_byte_timeout is not None: + vmin = 1 + vtime = int(self._inter_byte_timeout * 10) + try: + orig_attr = termios.tcgetattr(self.fd) + iflag, oflag, cflag, lflag, ispeed, ospeed, cc = orig_attr + except termios.error as msg: # if a port is nonexistent but has a /dev file, it'll fail here + raise SerialException("Could not configure port: {}".format(msg)) + # set up raw mode / no echo / binary + cflag |= (termios.CLOCAL | termios.CREAD) + lflag &= ~(termios.ICANON | termios.ECHO | termios.ECHOE | + termios.ECHOK | termios.ECHONL | + termios.ISIG | termios.IEXTEN) # |termios.ECHOPRT + for flag in ('ECHOCTL', 'ECHOKE'): # netbsd workaround for Erk + if hasattr(termios, flag): + lflag &= ~getattr(termios, flag) + + oflag &= ~(termios.OPOST | termios.ONLCR | termios.OCRNL) + iflag &= ~(termios.INLCR | termios.IGNCR | termios.ICRNL | termios.IGNBRK) + if hasattr(termios, 'IUCLC'): + iflag &= ~termios.IUCLC + if hasattr(termios, 'PARMRK'): + iflag &= ~termios.PARMRK + + # setup baud rate + try: + ispeed = ospeed = getattr(termios, 'B{}'.format(self._baudrate)) + except AttributeError: + try: + ispeed = ospeed = self.BAUDRATE_CONSTANTS[self._baudrate] + except KeyError: + #~ raise ValueError('Invalid baud rate: %r' % self._baudrate) + # may need custom baud rate, it isn't in our list. + ispeed = ospeed = getattr(termios, 'B38400') + try: + custom_baud = int(self._baudrate) # store for later + except ValueError: + raise ValueError('Invalid baud rate: {!r}'.format(self._baudrate)) + else: + if custom_baud < 0: + raise ValueError('Invalid baud rate: {!r}'.format(self._baudrate)) + + # setup char len + cflag &= ~termios.CSIZE + if self._bytesize == 8: + cflag |= termios.CS8 + elif self._bytesize == 7: + cflag |= termios.CS7 + elif self._bytesize == 6: + cflag |= termios.CS6 + elif self._bytesize == 5: + cflag |= termios.CS5 + else: + raise ValueError('Invalid char len: {!r}'.format(self._bytesize)) + # setup stop bits + if self._stopbits == serial.STOPBITS_ONE: + cflag &= ~(termios.CSTOPB) + elif self._stopbits == serial.STOPBITS_ONE_POINT_FIVE: + cflag |= (termios.CSTOPB) # XXX same as TWO.. there is no POSIX support for 1.5 + elif self._stopbits == serial.STOPBITS_TWO: + cflag |= (termios.CSTOPB) + else: + raise ValueError('Invalid stop bit specification: {!r}'.format(self._stopbits)) + # setup parity + iflag &= ~(termios.INPCK | termios.ISTRIP) + if self._parity == serial.PARITY_NONE: + cflag &= ~(termios.PARENB | termios.PARODD | CMSPAR) + elif self._parity == serial.PARITY_EVEN: + cflag &= ~(termios.PARODD | CMSPAR) + cflag |= (termios.PARENB) + elif self._parity == serial.PARITY_ODD: + cflag &= ~CMSPAR + cflag |= (termios.PARENB | termios.PARODD) + elif self._parity == serial.PARITY_MARK and CMSPAR: + cflag |= (termios.PARENB | CMSPAR | termios.PARODD) + elif self._parity == serial.PARITY_SPACE and CMSPAR: + cflag |= (termios.PARENB | CMSPAR) + cflag &= ~(termios.PARODD) + else: + raise ValueError('Invalid parity: {!r}'.format(self._parity)) + # setup flow control + # xonxoff + if hasattr(termios, 'IXANY'): + if self._xonxoff: + iflag |= (termios.IXON | termios.IXOFF) # |termios.IXANY) + else: + iflag &= ~(termios.IXON | termios.IXOFF | termios.IXANY) + else: + if self._xonxoff: + iflag |= (termios.IXON | termios.IXOFF) + else: + iflag &= ~(termios.IXON | termios.IXOFF) + # rtscts + if hasattr(termios, 'CRTSCTS'): + if self._rtscts: + cflag |= (termios.CRTSCTS) + else: + cflag &= ~(termios.CRTSCTS) + elif hasattr(termios, 'CNEW_RTSCTS'): # try it with alternate constant name + if self._rtscts: + cflag |= (termios.CNEW_RTSCTS) + else: + cflag &= ~(termios.CNEW_RTSCTS) + # XXX should there be a warning if setting up rtscts (and xonxoff etc) fails?? + + # buffer + # vmin "minimal number of characters to be read. 0 for non blocking" + if vmin < 0 or vmin > 255: + raise ValueError('Invalid vmin: {!r}'.format(vmin)) + cc[termios.VMIN] = vmin + # vtime + if vtime < 0 or vtime > 255: + raise ValueError('Invalid vtime: {!r}'.format(vtime)) + cc[termios.VTIME] = vtime + # activate settings + if force_update or [iflag, oflag, cflag, lflag, ispeed, ospeed, cc] != orig_attr: + termios.tcsetattr( + self.fd, + termios.TCSANOW, + [iflag, oflag, cflag, lflag, ispeed, ospeed, cc]) + + # apply custom baud rate, if any + if custom_baud is not None: + self._set_special_baudrate(custom_baud) + + if self._rs485_mode is not None: + self._set_rs485_mode(self._rs485_mode) + + def close(self): + """Close port""" + if self.is_open: + if self.fd is not None: + os.close(self.fd) + self.fd = None + os.close(self.pipe_abort_read_w) + os.close(self.pipe_abort_read_r) + os.close(self.pipe_abort_write_w) + os.close(self.pipe_abort_write_r) + self.pipe_abort_read_r, self.pipe_abort_read_w = None, None + self.pipe_abort_write_r, self.pipe_abort_write_w = None, None + self.is_open = False + + # - - - - - - - - - - - - - - - - - - - - - - - - + + @property + def in_waiting(self): + """Return the number of bytes currently in the input buffer.""" + #~ s = fcntl.ioctl(self.fd, termios.FIONREAD, TIOCM_zero_str) + s = fcntl.ioctl(self.fd, TIOCINQ, TIOCM_zero_str) + return struct.unpack('I', s)[0] + + # select based implementation, proved to work on many systems + def read(self, size=1): + """\ + Read size bytes from the serial port. If a timeout is set it may + return less characters as requested. With no timeout it will block + until the requested number of bytes is read. + """ + if not self.is_open: + raise portNotOpenError + read = bytearray() + timeout = Timeout(self._timeout) + while len(read) < size: + try: + ready, _, _ = select.select([self.fd, self.pipe_abort_read_r], [], [], timeout.time_left()) + if self.pipe_abort_read_r in ready: + os.read(self.pipe_abort_read_r, 1000) + break + # If select was used with a timeout, and the timeout occurs, it + # returns with empty lists -> thus abort read operation. + # For timeout == 0 (non-blocking operation) also abort when + # there is nothing to read. + if not ready: + break # timeout + buf = os.read(self.fd, size - len(read)) + # read should always return some data as select reported it was + # ready to read when we get to this point. + if not buf: + # Disconnected devices, at least on Linux, show the + # behavior that they are always ready to read immediately + # but reading returns nothing. + raise SerialException( + 'device reports readiness to read but returned no data ' + '(device disconnected or multiple access on port?)') + read.extend(buf) + except OSError as e: + # this is for Python 3.x where select.error is a subclass of + # OSError ignore BlockingIOErrors and EINTR. other errors are shown + # https://www.python.org/dev/peps/pep-0475. + if e.errno not in (errno.EAGAIN, errno.EALREADY, errno.EWOULDBLOCK, errno.EINPROGRESS, errno.EINTR): + raise SerialException('read failed: {}'.format(e)) + except select.error as e: + # this is for Python 2.x + # ignore BlockingIOErrors and EINTR. all errors are shown + # see also http://www.python.org/dev/peps/pep-3151/#select + if e[0] not in (errno.EAGAIN, errno.EALREADY, errno.EWOULDBLOCK, errno.EINPROGRESS, errno.EINTR): + raise SerialException('read failed: {}'.format(e)) + if timeout.expired(): + break + return bytes(read) + + def cancel_read(self): + if self.is_open: + os.write(self.pipe_abort_read_w, b"x") + + def cancel_write(self): + if self.is_open: + os.write(self.pipe_abort_write_w, b"x") + + def write(self, data): + """Output the given byte string over the serial port.""" + if not self.is_open: + raise portNotOpenError + d = to_bytes(data) + tx_len = length = len(d) + timeout = Timeout(self._write_timeout) + while tx_len > 0: + try: + n = os.write(self.fd, d) + if timeout.is_non_blocking: + # Zero timeout indicates non-blocking - simply return the + # number of bytes of data actually written + return n + elif not timeout.is_infinite: + # when timeout is set, use select to wait for being ready + # with the time left as timeout + if timeout.expired(): + raise writeTimeoutError + abort, ready, _ = select.select([self.pipe_abort_write_r], [self.fd], [], timeout.time_left()) + if abort: + os.read(self.pipe_abort_write_r, 1000) + break + if not ready: + raise writeTimeoutError + else: + assert timeout.time_left() is None + # wait for write operation + abort, ready, _ = select.select([self.pipe_abort_write_r], [self.fd], [], None) + if abort: + os.read(self.pipe_abort_write_r, 1) + break + if not ready: + raise SerialException('write failed (select)') + d = d[n:] + tx_len -= n + except SerialException: + raise + except OSError as e: + # this is for Python 3.x where select.error is a subclass of + # OSError ignore BlockingIOErrors and EINTR. other errors are shown + # https://www.python.org/dev/peps/pep-0475. + if e.errno not in (errno.EAGAIN, errno.EALREADY, errno.EWOULDBLOCK, errno.EINPROGRESS, errno.EINTR): + raise SerialException('write failed: {}'.format(e)) + except select.error as e: + # this is for Python 2.x + # ignore BlockingIOErrors and EINTR. all errors are shown + # see also http://www.python.org/dev/peps/pep-3151/#select + if e[0] not in (errno.EAGAIN, errno.EALREADY, errno.EWOULDBLOCK, errno.EINPROGRESS, errno.EINTR): + raise SerialException('write failed: {}'.format(e)) + if not timeout.is_non_blocking and timeout.expired(): + raise writeTimeoutError + return length - len(d) + + def flush(self): + """\ + Flush of file like objects. In this case, wait until all data + is written. + """ + if not self.is_open: + raise portNotOpenError + termios.tcdrain(self.fd) + + def reset_input_buffer(self): + """Clear input buffer, discarding all that is in the buffer.""" + if not self.is_open: + raise portNotOpenError + termios.tcflush(self.fd, termios.TCIFLUSH) + + def reset_output_buffer(self): + """\ + Clear output buffer, aborting the current output and discarding all + that is in the buffer. + """ + if not self.is_open: + raise portNotOpenError + termios.tcflush(self.fd, termios.TCOFLUSH) + + def send_break(self, duration=0.25): + """\ + Send break condition. Timed, returns to idle state after given + duration. + """ + if not self.is_open: + raise portNotOpenError + termios.tcsendbreak(self.fd, int(duration / 0.25)) + + def _update_break_state(self): + """\ + Set break: Controls TXD. When active, no transmitting is possible. + """ + if self._break_state: + fcntl.ioctl(self.fd, TIOCSBRK) + else: + fcntl.ioctl(self.fd, TIOCCBRK) + + def _update_rts_state(self): + """Set terminal status line: Request To Send""" + if self._rts_state: + fcntl.ioctl(self.fd, TIOCMBIS, TIOCM_RTS_str) + else: + fcntl.ioctl(self.fd, TIOCMBIC, TIOCM_RTS_str) + + def _update_dtr_state(self): + """Set terminal status line: Data Terminal Ready""" + if self._dtr_state: + fcntl.ioctl(self.fd, TIOCMBIS, TIOCM_DTR_str) + else: + fcntl.ioctl(self.fd, TIOCMBIC, TIOCM_DTR_str) + + @property + def cts(self): + """Read terminal status line: Clear To Send""" + if not self.is_open: + raise portNotOpenError + s = fcntl.ioctl(self.fd, TIOCMGET, TIOCM_zero_str) + return struct.unpack('I', s)[0] & TIOCM_CTS != 0 + + @property + def dsr(self): + """Read terminal status line: Data Set Ready""" + if not self.is_open: + raise portNotOpenError + s = fcntl.ioctl(self.fd, TIOCMGET, TIOCM_zero_str) + return struct.unpack('I', s)[0] & TIOCM_DSR != 0 + + @property + def ri(self): + """Read terminal status line: Ring Indicator""" + if not self.is_open: + raise portNotOpenError + s = fcntl.ioctl(self.fd, TIOCMGET, TIOCM_zero_str) + return struct.unpack('I', s)[0] & TIOCM_RI != 0 + + @property + def cd(self): + """Read terminal status line: Carrier Detect""" + if not self.is_open: + raise portNotOpenError + s = fcntl.ioctl(self.fd, TIOCMGET, TIOCM_zero_str) + return struct.unpack('I', s)[0] & TIOCM_CD != 0 + + # - - platform specific - - - - + + @property + def out_waiting(self): + """Return the number of bytes currently in the output buffer.""" + #~ s = fcntl.ioctl(self.fd, termios.FIONREAD, TIOCM_zero_str) + s = fcntl.ioctl(self.fd, TIOCOUTQ, TIOCM_zero_str) + return struct.unpack('I', s)[0] + + def fileno(self): + """\ + For easier use of the serial port instance with select. + WARNING: this function is not portable to different platforms! + """ + if not self.is_open: + raise portNotOpenError + return self.fd + + def set_input_flow_control(self, enable=True): + """\ + Manually control flow - when software flow control is enabled. + This will send XON (true) or XOFF (false) to the other device. + WARNING: this function is not portable to different platforms! + """ + if not self.is_open: + raise portNotOpenError + if enable: + termios.tcflow(self.fd, termios.TCION) + else: + termios.tcflow(self.fd, termios.TCIOFF) + + def set_output_flow_control(self, enable=True): + """\ + Manually control flow of outgoing data - when hardware or software flow + control is enabled. + WARNING: this function is not portable to different platforms! + """ + if not self.is_open: + raise portNotOpenError + if enable: + termios.tcflow(self.fd, termios.TCOON) + else: + termios.tcflow(self.fd, termios.TCOOFF) + + def nonblocking(self): + """DEPRECATED - has no use""" + import warnings + warnings.warn("nonblocking() has no effect, already nonblocking", DeprecationWarning) + + +class PosixPollSerial(Serial): + """\ + Poll based read implementation. Not all systems support poll properly. + However this one has better handling of errors, such as a device + disconnecting while it's in use (e.g. USB-serial unplugged). + """ + + def read(self, size=1): + """\ + Read size bytes from the serial port. If a timeout is set it may + return less characters as requested. With no timeout it will block + until the requested number of bytes is read. + """ + if not self.is_open: + raise portNotOpenError + read = bytearray() + poll = select.poll() + poll.register(self.fd, select.POLLIN | select.POLLERR | select.POLLHUP | select.POLLNVAL) + if size > 0: + while len(read) < size: + # print "\tread(): size",size, "have", len(read) #debug + # wait until device becomes ready to read (or something fails) + for fd, event in poll.poll(self._timeout * 1000): + if event & (select.POLLERR | select.POLLHUP | select.POLLNVAL): + raise SerialException('device reports error (poll)') + # we don't care if it is select.POLLIN or timeout, that's + # handled below + buf = os.read(self.fd, size - len(read)) + read.extend(buf) + if ((self._timeout is not None and self._timeout >= 0) or + (self._inter_byte_timeout is not None and self._inter_byte_timeout > 0)) and not buf: + break # early abort on timeout + return bytes(read) + + +class VTIMESerial(Serial): + """\ + Implement timeout using vtime of tty device instead of using select. + This means that no inter character timeout can be specified and that + the error handling is degraded. + + Overall timeout is disabled when inter-character timeout is used. + """ + + def _reconfigure_port(self, force_update=True): + """Set communication parameters on opened port.""" + super(VTIMESerial, self)._reconfigure_port() + fcntl.fcntl(self.fd, fcntl.F_SETFL, 0) # clear O_NONBLOCK + + if self._inter_byte_timeout is not None: + vmin = 1 + vtime = int(self._inter_byte_timeout * 10) + elif self._timeout is None: + vmin = 1 + vtime = 0 + else: + vmin = 0 + vtime = int(self._timeout * 10) + try: + orig_attr = termios.tcgetattr(self.fd) + iflag, oflag, cflag, lflag, ispeed, ospeed, cc = orig_attr + except termios.error as msg: # if a port is nonexistent but has a /dev file, it'll fail here + raise serial.SerialException("Could not configure port: {}".format(msg)) + + if vtime < 0 or vtime > 255: + raise ValueError('Invalid vtime: {!r}'.format(vtime)) + cc[termios.VTIME] = vtime + cc[termios.VMIN] = vmin + + termios.tcsetattr( + self.fd, + termios.TCSANOW, + [iflag, oflag, cflag, lflag, ispeed, ospeed, cc]) + + def read(self, size=1): + """\ + Read size bytes from the serial port. If a timeout is set it may + return less characters as requested. With no timeout it will block + until the requested number of bytes is read. + """ + if not self.is_open: + raise portNotOpenError + read = bytearray() + while len(read) < size: + buf = os.read(self.fd, size - len(read)) + if not buf: + break + read.extend(buf) + return bytes(read) + + # hack to make hasattr return false + cancel_read = property() diff --git a/software/tools/pymcuprog/libs/serial/serialutil.py b/software/tools/pymcuprog/libs/serial/serialutil.py new file mode 100644 index 0000000..7d51752 --- /dev/null +++ b/software/tools/pymcuprog/libs/serial/serialutil.py @@ -0,0 +1,693 @@ +#! python +# +# Base class and support functions used by various backends. +# +# This file is part of pySerial. https://github.com/pyserial/pyserial +# (C) 2001-2016 Chris Liechti +# +# SPDX-License-Identifier: BSD-3-Clause + +import io +import time + +# ``memoryview`` was introduced in Python 2.7 and ``bytes(some_memoryview)`` +# isn't returning the contents (very unfortunate). Therefore we need special +# cases and test for it. Ensure that there is a ``memoryview`` object for older +# Python versions. This is easier than making every test dependent on its +# existence. +try: + memoryview +except (NameError, AttributeError): + # implementation does not matter as we do not really use it. + # it just must not inherit from something else we might care for. + class memoryview(object): # pylint: disable=redefined-builtin,invalid-name + pass + +try: + unicode +except (NameError, AttributeError): + unicode = str # for Python 3, pylint: disable=redefined-builtin,invalid-name + +try: + basestring +except (NameError, AttributeError): + basestring = (str,) # for Python 3, pylint: disable=redefined-builtin,invalid-name + + +# "for byte in data" fails for python3 as it returns ints instead of bytes +def iterbytes(b): + """Iterate over bytes, returning bytes instead of ints (python3)""" + if isinstance(b, memoryview): + b = b.tobytes() + i = 0 + while True: + a = b[i:i + 1] + i += 1 + if a: + yield a + else: + break + + +# all Python versions prior 3.x convert ``str([17])`` to '[17]' instead of '\x11' +# so a simple ``bytes(sequence)`` doesn't work for all versions +def to_bytes(seq): + """convert a sequence to a bytes type""" + if isinstance(seq, bytes): + return seq + elif isinstance(seq, bytearray): + return bytes(seq) + elif isinstance(seq, memoryview): + return seq.tobytes() + elif isinstance(seq, unicode): + raise TypeError('unicode strings are not supported, please encode to bytes: {!r}'.format(seq)) + else: + # handle list of integers and bytes (one or more items) for Python 2 and 3 + return bytes(bytearray(seq)) + + +# create control bytes +XON = to_bytes([17]) +XOFF = to_bytes([19]) + +CR = to_bytes([13]) +LF = to_bytes([10]) + + +PARITY_NONE, PARITY_EVEN, PARITY_ODD, PARITY_MARK, PARITY_SPACE = 'N', 'E', 'O', 'M', 'S' +STOPBITS_ONE, STOPBITS_ONE_POINT_FIVE, STOPBITS_TWO = (1, 1.5, 2) +FIVEBITS, SIXBITS, SEVENBITS, EIGHTBITS = (5, 6, 7, 8) + +PARITY_NAMES = { + PARITY_NONE: 'None', + PARITY_EVEN: 'Even', + PARITY_ODD: 'Odd', + PARITY_MARK: 'Mark', + PARITY_SPACE: 'Space', +} + + +class SerialException(IOError): + """Base class for serial port related exceptions.""" + + +class SerialTimeoutException(SerialException): + """Write timeouts give an exception""" + + +writeTimeoutError = SerialTimeoutException('Write timeout') +portNotOpenError = SerialException('Attempting to use a port that is not open') + + +class Timeout(object): + """\ + Abstraction for timeout operations. Using time.monotonic() if available + or time.time() in all other cases. + + The class can also be initialized with 0 or None, in order to support + non-blocking and fully blocking I/O operations. The attributes + is_non_blocking and is_infinite are set accordingly. + """ + if hasattr(time, 'monotonic'): + # Timeout implementation with time.monotonic(). This function is only + # supported by Python 3.3 and above. It returns a time in seconds + # (float) just as time.time(), but is not affected by system clock + # adjustments. + TIME = time.monotonic + else: + # Timeout implementation with time.time(). This is compatible with all + # Python versions but has issues if the clock is adjusted while the + # timeout is running. + TIME = time.time + + def __init__(self, duration): + """Initialize a timeout with given duration""" + self.is_infinite = (duration is None) + self.is_non_blocking = (duration == 0) + self.duration = duration + if duration is not None: + self.target_time = self.TIME() + duration + else: + self.target_time = None + + def expired(self): + """Return a boolean, telling if the timeout has expired""" + return self.target_time is not None and self.time_left() <= 0 + + def time_left(self): + """Return how many seconds are left until the timeout expires""" + if self.is_non_blocking: + return 0 + elif self.is_infinite: + return None + else: + delta = self.target_time - self.TIME() + if delta > self.duration: + # clock jumped, recalculate + self.target_time = self.TIME() + self.duration + return self.duration + else: + return max(0, delta) + + def restart(self, duration): + """\ + Restart a timeout, only supported if a timeout was already set up + before. + """ + self.duration = duration + self.target_time = self.TIME() + duration + + +class SerialBase(io.RawIOBase): + """\ + Serial port base class. Provides __init__ function and properties to + get/set port settings. + """ + + # default values, may be overridden in subclasses that do not support all values + BAUDRATES = (50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, 4800, + 9600, 19200, 38400, 57600, 115200, 230400, 460800, 500000, + 576000, 921600, 1000000, 1152000, 1500000, 2000000, 2500000, + 3000000, 3500000, 4000000) + BYTESIZES = (FIVEBITS, SIXBITS, SEVENBITS, EIGHTBITS) + PARITIES = (PARITY_NONE, PARITY_EVEN, PARITY_ODD, PARITY_MARK, PARITY_SPACE) + STOPBITS = (STOPBITS_ONE, STOPBITS_ONE_POINT_FIVE, STOPBITS_TWO) + + def __init__(self, + port=None, + baudrate=9600, + bytesize=EIGHTBITS, + parity=PARITY_NONE, + stopbits=STOPBITS_ONE, + timeout=None, + xonxoff=False, + rtscts=False, + write_timeout=None, + dsrdtr=False, + inter_byte_timeout=None, + exclusive=None, + **kwargs): + """\ + Initialize comm port object. If a "port" is given, then the port will be + opened immediately. Otherwise a Serial port object in closed state + is returned. + """ + + self.is_open = False + self.portstr = None + self.name = None + # correct values are assigned below through properties + self._port = None + self._baudrate = None + self._bytesize = None + self._parity = None + self._stopbits = None + self._timeout = None + self._write_timeout = None + self._xonxoff = None + self._rtscts = None + self._dsrdtr = None + self._inter_byte_timeout = None + self._rs485_mode = None # disabled by default + self._rts_state = True + self._dtr_state = True + self._break_state = False + self._exclusive = None + + # assign values using get/set methods using the properties feature + self.port = port + self.baudrate = baudrate + self.bytesize = bytesize + self.parity = parity + self.stopbits = stopbits + self.timeout = timeout + self.write_timeout = write_timeout + self.xonxoff = xonxoff + self.rtscts = rtscts + self.dsrdtr = dsrdtr + self.inter_byte_timeout = inter_byte_timeout + self.exclusive = exclusive + + # watch for backward compatible kwargs + if 'writeTimeout' in kwargs: + self.write_timeout = kwargs.pop('writeTimeout') + if 'interCharTimeout' in kwargs: + self.inter_byte_timeout = kwargs.pop('interCharTimeout') + if kwargs: + raise ValueError('unexpected keyword arguments: {!r}'.format(kwargs)) + + if port is not None: + self.open() + + # - - - - - - - - - - - - - - - - - - - - - - - - + + # to be implemented by subclasses: + # def open(self): + # def close(self): + + # - - - - - - - - - - - - - - - - - - - - - - - - + + @property + def port(self): + """\ + Get the current port setting. The value that was passed on init or using + setPort() is passed back. + """ + return self._port + + @port.setter + def port(self, port): + """\ + Change the port. + """ + if port is not None and not isinstance(port, basestring): + raise ValueError('"port" must be None or a string, not {}'.format(type(port))) + was_open = self.is_open + if was_open: + self.close() + self.portstr = port + self._port = port + self.name = self.portstr + if was_open: + self.open() + + @property + def baudrate(self): + """Get the current baud rate setting.""" + return self._baudrate + + @baudrate.setter + def baudrate(self, baudrate): + """\ + Change baud rate. It raises a ValueError if the port is open and the + baud rate is not possible. If the port is closed, then the value is + accepted and the exception is raised when the port is opened. + """ + try: + b = int(baudrate) + except TypeError: + raise ValueError("Not a valid baudrate: {!r}".format(baudrate)) + else: + if b < 0: + raise ValueError("Not a valid baudrate: {!r}".format(baudrate)) + self._baudrate = b + if self.is_open: + self._reconfigure_port() + + @property + def bytesize(self): + """Get the current byte size setting.""" + return self._bytesize + + @bytesize.setter + def bytesize(self, bytesize): + """Change byte size.""" + if bytesize not in self.BYTESIZES: + raise ValueError("Not a valid byte size: {!r}".format(bytesize)) + self._bytesize = bytesize + if self.is_open: + self._reconfigure_port() + + @property + def exclusive(self): + """Get the current exclusive access setting.""" + return self._exclusive + + @exclusive.setter + def exclusive(self, exclusive): + """Change the exclusive access setting.""" + self._exclusive = exclusive + if self.is_open: + self._reconfigure_port() + + @property + def parity(self): + """Get the current parity setting.""" + return self._parity + + @parity.setter + def parity(self, parity): + """Change parity setting.""" + if parity not in self.PARITIES: + raise ValueError("Not a valid parity: {!r}".format(parity)) + self._parity = parity + if self.is_open: + self._reconfigure_port() + + @property + def stopbits(self): + """Get the current stop bits setting.""" + return self._stopbits + + @stopbits.setter + def stopbits(self, stopbits): + """Change stop bits size.""" + if stopbits not in self.STOPBITS: + raise ValueError("Not a valid stop bit size: {!r}".format(stopbits)) + self._stopbits = stopbits + if self.is_open: + self._reconfigure_port() + + @property + def timeout(self): + """Get the current timeout setting.""" + return self._timeout + + @timeout.setter + def timeout(self, timeout): + """Change timeout setting.""" + if timeout is not None: + try: + timeout + 1 # test if it's a number, will throw a TypeError if not... + except TypeError: + raise ValueError("Not a valid timeout: {!r}".format(timeout)) + if timeout < 0: + raise ValueError("Not a valid timeout: {!r}".format(timeout)) + self._timeout = timeout + if self.is_open: + self._reconfigure_port() + + @property + def write_timeout(self): + """Get the current timeout setting.""" + return self._write_timeout + + @write_timeout.setter + def write_timeout(self, timeout): + """Change timeout setting.""" + if timeout is not None: + if timeout < 0: + raise ValueError("Not a valid timeout: {!r}".format(timeout)) + try: + timeout + 1 # test if it's a number, will throw a TypeError if not... + except TypeError: + raise ValueError("Not a valid timeout: {!r}".format(timeout)) + + self._write_timeout = timeout + if self.is_open: + self._reconfigure_port() + + @property + def inter_byte_timeout(self): + """Get the current inter-character timeout setting.""" + return self._inter_byte_timeout + + @inter_byte_timeout.setter + def inter_byte_timeout(self, ic_timeout): + """Change inter-byte timeout setting.""" + if ic_timeout is not None: + if ic_timeout < 0: + raise ValueError("Not a valid timeout: {!r}".format(ic_timeout)) + try: + ic_timeout + 1 # test if it's a number, will throw a TypeError if not... + except TypeError: + raise ValueError("Not a valid timeout: {!r}".format(ic_timeout)) + + self._inter_byte_timeout = ic_timeout + if self.is_open: + self._reconfigure_port() + + @property + def xonxoff(self): + """Get the current XON/XOFF setting.""" + return self._xonxoff + + @xonxoff.setter + def xonxoff(self, xonxoff): + """Change XON/XOFF setting.""" + self._xonxoff = xonxoff + if self.is_open: + self._reconfigure_port() + + @property + def rtscts(self): + """Get the current RTS/CTS flow control setting.""" + return self._rtscts + + @rtscts.setter + def rtscts(self, rtscts): + """Change RTS/CTS flow control setting.""" + self._rtscts = rtscts + if self.is_open: + self._reconfigure_port() + + @property + def dsrdtr(self): + """Get the current DSR/DTR flow control setting.""" + return self._dsrdtr + + @dsrdtr.setter + def dsrdtr(self, dsrdtr=None): + """Change DsrDtr flow control setting.""" + if dsrdtr is None: + # if not set, keep backwards compatibility and follow rtscts setting + self._dsrdtr = self._rtscts + else: + # if defined independently, follow its value + self._dsrdtr = dsrdtr + if self.is_open: + self._reconfigure_port() + + @property + def rts(self): + return self._rts_state + + @rts.setter + def rts(self, value): + self._rts_state = value + if self.is_open: + self._update_rts_state() + + @property + def dtr(self): + return self._dtr_state + + @dtr.setter + def dtr(self, value): + self._dtr_state = value + if self.is_open: + self._update_dtr_state() + + @property + def break_condition(self): + return self._break_state + + @break_condition.setter + def break_condition(self, value): + self._break_state = value + if self.is_open: + self._update_break_state() + + # - - - - - - - - - - - - - - - - - - - - - - - - + # functions useful for RS-485 adapters + + @property + def rs485_mode(self): + """\ + Enable RS485 mode and apply new settings, set to None to disable. + See serial.rs485.RS485Settings for more info about the value. + """ + return self._rs485_mode + + @rs485_mode.setter + def rs485_mode(self, rs485_settings): + self._rs485_mode = rs485_settings + if self.is_open: + self._reconfigure_port() + + # - - - - - - - - - - - - - - - - - - - - - - - - + + _SAVED_SETTINGS = ('baudrate', 'bytesize', 'parity', 'stopbits', 'xonxoff', + 'dsrdtr', 'rtscts', 'timeout', 'write_timeout', + 'inter_byte_timeout') + + def get_settings(self): + """\ + Get current port settings as a dictionary. For use with + apply_settings(). + """ + return dict([(key, getattr(self, '_' + key)) for key in self._SAVED_SETTINGS]) + + def apply_settings(self, d): + """\ + Apply stored settings from a dictionary returned from + get_settings(). It's allowed to delete keys from the dictionary. These + values will simply left unchanged. + """ + for key in self._SAVED_SETTINGS: + if key in d and d[key] != getattr(self, '_' + key): # check against internal "_" value + setattr(self, key, d[key]) # set non "_" value to use properties write function + + # - - - - - - - - - - - - - - - - - - - - - - - - + + def __repr__(self): + """String representation of the current port settings and its state.""" + return '{name}(port={p.portstr!r}, ' \ + 'baudrate={p.baudrate!r}, bytesize={p.bytesize!r}, parity={p.parity!r}, ' \ + 'stopbits={p.stopbits!r}, timeout={p.timeout!r}, xonxoff={p.xonxoff!r}, ' \ + 'rtscts={p.rtscts!r}, dsrdtr={p.dsrdtr!r})'.format( + name=self.__class__.__name__, id=id(self), p=self) + + # - - - - - - - - - - - - - - - - - - - - - - - - + # compatibility with io library + # pylint: disable=invalid-name,missing-docstring + + def readable(self): + return True + + def writable(self): + return True + + def seekable(self): + return False + + def readinto(self, b): + data = self.read(len(b)) + n = len(data) + try: + b[:n] = data + except TypeError as err: + import array + if not isinstance(b, array.array): + raise err + b[:n] = array.array('b', data) + return n + + # - - - - - - - - - - - - - - - - - - - - - - - - + # context manager + + def __enter__(self): + if not self.is_open: + self.open() + return self + + def __exit__(self, *args, **kwargs): + self.close() + + # - - - - - - - - - - - - - - - - - - - - - - - - + + def send_break(self, duration=0.25): + """\ + Send break condition. Timed, returns to idle state after given + duration. + """ + if not self.is_open: + raise portNotOpenError + self.break_condition = True + time.sleep(duration) + self.break_condition = False + + # - - - - - - - - - - - - - - - - - - - - - - - - + # backwards compatibility / deprecated functions + + def flushInput(self): + self.reset_input_buffer() + + def flushOutput(self): + self.reset_output_buffer() + + def inWaiting(self): + return self.in_waiting + + def sendBreak(self, duration=0.25): + self.send_break(duration) + + def setRTS(self, value=1): + self.rts = value + + def setDTR(self, value=1): + self.dtr = value + + def getCTS(self): + return self.cts + + def getDSR(self): + return self.dsr + + def getRI(self): + return self.ri + + def getCD(self): + return self.cd + + def setPort(self, port): + self.port = port + + @property + def writeTimeout(self): + return self.write_timeout + + @writeTimeout.setter + def writeTimeout(self, timeout): + self.write_timeout = timeout + + @property + def interCharTimeout(self): + return self.inter_byte_timeout + + @interCharTimeout.setter + def interCharTimeout(self, interCharTimeout): + self.inter_byte_timeout = interCharTimeout + + def getSettingsDict(self): + return self.get_settings() + + def applySettingsDict(self, d): + self.apply_settings(d) + + def isOpen(self): + return self.is_open + + # - - - - - - - - - - - - - - - - - - - - - - - - + # additional functionality + + def read_all(self): + """\ + Read all bytes currently available in the buffer of the OS. + """ + return self.read(self.in_waiting) + + def read_until(self, terminator=LF, size=None): + """\ + Read until a termination sequence is found ('\n' by default), the size + is exceeded or until timeout occurs. + """ + lenterm = len(terminator) + line = bytearray() + timeout = Timeout(self._timeout) + while True: + c = self.read(1) + if c: + line += c + if line[-lenterm:] == terminator: + break + if size is not None and len(line) >= size: + break + else: + break + if timeout.expired(): + break + return bytes(line) + + def iread_until(self, *args, **kwargs): + """\ + Read lines, implemented as generator. It will raise StopIteration on + timeout (empty read). + """ + while True: + line = self.read_until(*args, **kwargs) + if not line: + break + yield line + + +# - - - - - - - - - - - - - - - - - - - - - - - - - +if __name__ == '__main__': + import sys + s = SerialBase() + sys.stdout.write('port name: {}\n'.format(s.name)) + sys.stdout.write('baud rates: {}\n'.format(s.BAUDRATES)) + sys.stdout.write('byte sizes: {}\n'.format(s.BYTESIZES)) + sys.stdout.write('parities: {}\n'.format(s.PARITIES)) + sys.stdout.write('stop bits: {}\n'.format(s.STOPBITS)) + sys.stdout.write('{}\n'.format(s)) diff --git a/software/tools/pymcuprog/libs/serial/serialwin32.py b/software/tools/pymcuprog/libs/serial/serialwin32.py new file mode 100644 index 0000000..7b88999 --- /dev/null +++ b/software/tools/pymcuprog/libs/serial/serialwin32.py @@ -0,0 +1,475 @@ +#! python +# +# backend for Windows ("win32" incl. 32/64 bit support) +# +# (C) 2001-2015 Chris Liechti +# +# This file is part of pySerial. https://github.com/pyserial/pyserial +# SPDX-License-Identifier: BSD-3-Clause +# +# Initial patch to use ctypes by Giovanni Bajo + +# pylint: disable=invalid-name,too-few-public-methods +import ctypes +import time +from serial import win32 + +import serial +from serial.serialutil import SerialBase, SerialException, to_bytes, portNotOpenError, writeTimeoutError + + +class Serial(SerialBase): + """Serial port implementation for Win32 based on ctypes.""" + + BAUDRATES = (50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, 4800, + 9600, 19200, 38400, 57600, 115200) + + def __init__(self, *args, **kwargs): + self._port_handle = None + self._overlapped_read = None + self._overlapped_write = None + super(Serial, self).__init__(*args, **kwargs) + + def open(self): + """\ + Open port with current settings. This may throw a SerialException + if the port cannot be opened. + """ + if self._port is None: + raise SerialException("Port must be configured before it can be used.") + if self.is_open: + raise SerialException("Port is already open.") + # the "\\.\COMx" format is required for devices other than COM1-COM8 + # not all versions of windows seem to support this properly + # so that the first few ports are used with the DOS device name + port = self.name + try: + if port.upper().startswith('COM') and int(port[3:]) > 8: + port = '\\\\.\\' + port + except ValueError: + # for like COMnotanumber + pass + self._port_handle = win32.CreateFile( + port, + win32.GENERIC_READ | win32.GENERIC_WRITE, + 0, # exclusive access + None, # no security + win32.OPEN_EXISTING, + win32.FILE_ATTRIBUTE_NORMAL | win32.FILE_FLAG_OVERLAPPED, + 0) + if self._port_handle == win32.INVALID_HANDLE_VALUE: + self._port_handle = None # 'cause __del__ is called anyway + raise SerialException("could not open port {!r}: {!r}".format(self.portstr, ctypes.WinError())) + + try: + self._overlapped_read = win32.OVERLAPPED() + self._overlapped_read.hEvent = win32.CreateEvent(None, 1, 0, None) + self._overlapped_write = win32.OVERLAPPED() + #~ self._overlapped_write.hEvent = win32.CreateEvent(None, 1, 0, None) + self._overlapped_write.hEvent = win32.CreateEvent(None, 0, 0, None) + + # Setup a 4k buffer + win32.SetupComm(self._port_handle, 4096, 4096) + + # Save original timeout values: + self._orgTimeouts = win32.COMMTIMEOUTS() + win32.GetCommTimeouts(self._port_handle, ctypes.byref(self._orgTimeouts)) + + self._reconfigure_port() + + # Clear buffers: + # Remove anything that was there + win32.PurgeComm( + self._port_handle, + win32.PURGE_TXCLEAR | win32.PURGE_TXABORT | + win32.PURGE_RXCLEAR | win32.PURGE_RXABORT) + except: + try: + self._close() + except: + # ignore any exception when closing the port + # also to keep original exception that happened when setting up + pass + self._port_handle = None + raise + else: + self.is_open = True + + def _reconfigure_port(self): + """Set communication parameters on opened port.""" + if not self._port_handle: + raise SerialException("Can only operate on a valid port handle") + + # Set Windows timeout values + # timeouts is a tuple with the following items: + # (ReadIntervalTimeout,ReadTotalTimeoutMultiplier, + # ReadTotalTimeoutConstant,WriteTotalTimeoutMultiplier, + # WriteTotalTimeoutConstant) + timeouts = win32.COMMTIMEOUTS() + if self._timeout is None: + pass # default of all zeros is OK + elif self._timeout == 0: + timeouts.ReadIntervalTimeout = win32.MAXDWORD + else: + timeouts.ReadTotalTimeoutConstant = max(int(self._timeout * 1000), 1) + if self._timeout != 0 and self._inter_byte_timeout is not None: + timeouts.ReadIntervalTimeout = max(int(self._inter_byte_timeout * 1000), 1) + + if self._write_timeout is None: + pass + elif self._write_timeout == 0: + timeouts.WriteTotalTimeoutConstant = win32.MAXDWORD + else: + timeouts.WriteTotalTimeoutConstant = max(int(self._write_timeout * 1000), 1) + win32.SetCommTimeouts(self._port_handle, ctypes.byref(timeouts)) + + win32.SetCommMask(self._port_handle, win32.EV_ERR) + + # Setup the connection info. + # Get state and modify it: + comDCB = win32.DCB() + win32.GetCommState(self._port_handle, ctypes.byref(comDCB)) + comDCB.BaudRate = self._baudrate + + if self._bytesize == serial.FIVEBITS: + comDCB.ByteSize = 5 + elif self._bytesize == serial.SIXBITS: + comDCB.ByteSize = 6 + elif self._bytesize == serial.SEVENBITS: + comDCB.ByteSize = 7 + elif self._bytesize == serial.EIGHTBITS: + comDCB.ByteSize = 8 + else: + raise ValueError("Unsupported number of data bits: {!r}".format(self._bytesize)) + + if self._parity == serial.PARITY_NONE: + comDCB.Parity = win32.NOPARITY + comDCB.fParity = 0 # Disable Parity Check + elif self._parity == serial.PARITY_EVEN: + comDCB.Parity = win32.EVENPARITY + comDCB.fParity = 1 # Enable Parity Check + elif self._parity == serial.PARITY_ODD: + comDCB.Parity = win32.ODDPARITY + comDCB.fParity = 1 # Enable Parity Check + elif self._parity == serial.PARITY_MARK: + comDCB.Parity = win32.MARKPARITY + comDCB.fParity = 1 # Enable Parity Check + elif self._parity == serial.PARITY_SPACE: + comDCB.Parity = win32.SPACEPARITY + comDCB.fParity = 1 # Enable Parity Check + else: + raise ValueError("Unsupported parity mode: {!r}".format(self._parity)) + + if self._stopbits == serial.STOPBITS_ONE: + comDCB.StopBits = win32.ONESTOPBIT + elif self._stopbits == serial.STOPBITS_ONE_POINT_FIVE: + comDCB.StopBits = win32.ONE5STOPBITS + elif self._stopbits == serial.STOPBITS_TWO: + comDCB.StopBits = win32.TWOSTOPBITS + else: + raise ValueError("Unsupported number of stop bits: {!r}".format(self._stopbits)) + + comDCB.fBinary = 1 # Enable Binary Transmission + # Char. w/ Parity-Err are replaced with 0xff (if fErrorChar is set to TRUE) + if self._rs485_mode is None: + if self._rtscts: + comDCB.fRtsControl = win32.RTS_CONTROL_HANDSHAKE + else: + comDCB.fRtsControl = win32.RTS_CONTROL_ENABLE if self._rts_state else win32.RTS_CONTROL_DISABLE + comDCB.fOutxCtsFlow = self._rtscts + else: + # checks for unsupported settings + # XXX verify if platform really does not have a setting for those + if not self._rs485_mode.rts_level_for_tx: + raise ValueError( + 'Unsupported value for RS485Settings.rts_level_for_tx: {!r}'.format( + self._rs485_mode.rts_level_for_tx,)) + if self._rs485_mode.rts_level_for_rx: + raise ValueError( + 'Unsupported value for RS485Settings.rts_level_for_rx: {!r}'.format( + self._rs485_mode.rts_level_for_rx,)) + if self._rs485_mode.delay_before_tx is not None: + raise ValueError( + 'Unsupported value for RS485Settings.delay_before_tx: {!r}'.format( + self._rs485_mode.delay_before_tx,)) + if self._rs485_mode.delay_before_rx is not None: + raise ValueError( + 'Unsupported value for RS485Settings.delay_before_rx: {!r}'.format( + self._rs485_mode.delay_before_rx,)) + if self._rs485_mode.loopback: + raise ValueError( + 'Unsupported value for RS485Settings.loopback: {!r}'.format( + self._rs485_mode.loopback,)) + comDCB.fRtsControl = win32.RTS_CONTROL_TOGGLE + comDCB.fOutxCtsFlow = 0 + + if self._dsrdtr: + comDCB.fDtrControl = win32.DTR_CONTROL_HANDSHAKE + else: + comDCB.fDtrControl = win32.DTR_CONTROL_ENABLE if self._dtr_state else win32.DTR_CONTROL_DISABLE + comDCB.fOutxDsrFlow = self._dsrdtr + comDCB.fOutX = self._xonxoff + comDCB.fInX = self._xonxoff + comDCB.fNull = 0 + comDCB.fErrorChar = 0 + comDCB.fAbortOnError = 0 + comDCB.XonChar = serial.XON + comDCB.XoffChar = serial.XOFF + + if not win32.SetCommState(self._port_handle, ctypes.byref(comDCB)): + raise SerialException( + 'Cannot configure port, something went wrong. ' + 'Original message: {!r}'.format(ctypes.WinError())) + + #~ def __del__(self): + #~ self.close() + + def _close(self): + """internal close port helper""" + if self._port_handle is not None: + # Restore original timeout values: + win32.SetCommTimeouts(self._port_handle, self._orgTimeouts) + if self._overlapped_read is not None: + self.cancel_read() + win32.CloseHandle(self._overlapped_read.hEvent) + self._overlapped_read = None + if self._overlapped_write is not None: + self.cancel_write() + win32.CloseHandle(self._overlapped_write.hEvent) + self._overlapped_write = None + win32.CloseHandle(self._port_handle) + self._port_handle = None + + def close(self): + """Close port""" + if self.is_open: + self._close() + self.is_open = False + + # - - - - - - - - - - - - - - - - - - - - - - - - + + @property + def in_waiting(self): + """Return the number of bytes currently in the input buffer.""" + flags = win32.DWORD() + comstat = win32.COMSTAT() + if not win32.ClearCommError(self._port_handle, ctypes.byref(flags), ctypes.byref(comstat)): + raise SerialException("ClearCommError failed ({!r})".format(ctypes.WinError())) + return comstat.cbInQue + + def read(self, size=1): + """\ + Read size bytes from the serial port. If a timeout is set it may + return less characters as requested. With no timeout it will block + until the requested number of bytes is read. + """ + if not self.is_open: + raise portNotOpenError + if size > 0: + win32.ResetEvent(self._overlapped_read.hEvent) + flags = win32.DWORD() + comstat = win32.COMSTAT() + if not win32.ClearCommError(self._port_handle, ctypes.byref(flags), ctypes.byref(comstat)): + raise SerialException("ClearCommError failed ({!r})".format(ctypes.WinError())) + n = min(comstat.cbInQue, size) if self.timeout == 0 else size + if n > 0: + buf = ctypes.create_string_buffer(n) + rc = win32.DWORD() + read_ok = win32.ReadFile( + self._port_handle, + buf, + n, + ctypes.byref(rc), + ctypes.byref(self._overlapped_read)) + if not read_ok and win32.GetLastError() not in (win32.ERROR_SUCCESS, win32.ERROR_IO_PENDING): + raise SerialException("ReadFile failed ({!r})".format(ctypes.WinError())) + result_ok = win32.GetOverlappedResult( + self._port_handle, + ctypes.byref(self._overlapped_read), + ctypes.byref(rc), + True) + if not result_ok: + if win32.GetLastError() != win32.ERROR_OPERATION_ABORTED: + raise SerialException("GetOverlappedResult failed ({!r})".format(ctypes.WinError())) + read = buf.raw[:rc.value] + else: + read = bytes() + else: + read = bytes() + return bytes(read) + + def write(self, data): + """Output the given byte string over the serial port.""" + if not self.is_open: + raise portNotOpenError + #~ if not isinstance(data, (bytes, bytearray)): + #~ raise TypeError('expected %s or bytearray, got %s' % (bytes, type(data))) + # convert data (needed in case of memoryview instance: Py 3.1 io lib), ctypes doesn't like memoryview + data = to_bytes(data) + if data: + #~ win32event.ResetEvent(self._overlapped_write.hEvent) + n = win32.DWORD() + success = win32.WriteFile(self._port_handle, data, len(data), ctypes.byref(n), self._overlapped_write) + if self._write_timeout != 0: # if blocking (None) or w/ write timeout (>0) + if not success and win32.GetLastError() not in (win32.ERROR_SUCCESS, win32.ERROR_IO_PENDING): + raise SerialException("WriteFile failed ({!r})".format(ctypes.WinError())) + + # Wait for the write to complete. + #~ win32.WaitForSingleObject(self._overlapped_write.hEvent, win32.INFINITE) + win32.GetOverlappedResult(self._port_handle, self._overlapped_write, ctypes.byref(n), True) + if win32.GetLastError() == win32.ERROR_OPERATION_ABORTED: + return n.value # canceled IO is no error + if n.value != len(data): + raise writeTimeoutError + return n.value + else: + errorcode = win32.ERROR_SUCCESS if success else win32.GetLastError() + if errorcode in (win32.ERROR_INVALID_USER_BUFFER, win32.ERROR_NOT_ENOUGH_MEMORY, + win32.ERROR_OPERATION_ABORTED): + return 0 + elif errorcode in (win32.ERROR_SUCCESS, win32.ERROR_IO_PENDING): + # no info on true length provided by OS function in async mode + return len(data) + else: + raise SerialException("WriteFile failed ({!r})".format(ctypes.WinError())) + else: + return 0 + + def flush(self): + """\ + Flush of file like objects. In this case, wait until all data + is written. + """ + while self.out_waiting: + time.sleep(0.05) + # XXX could also use WaitCommEvent with mask EV_TXEMPTY, but it would + # require overlapped IO and it's also only possible to set a single mask + # on the port--- + + def reset_input_buffer(self): + """Clear input buffer, discarding all that is in the buffer.""" + if not self.is_open: + raise portNotOpenError + win32.PurgeComm(self._port_handle, win32.PURGE_RXCLEAR | win32.PURGE_RXABORT) + + def reset_output_buffer(self): + """\ + Clear output buffer, aborting the current output and discarding all + that is in the buffer. + """ + if not self.is_open: + raise portNotOpenError + win32.PurgeComm(self._port_handle, win32.PURGE_TXCLEAR | win32.PURGE_TXABORT) + + def _update_break_state(self): + """Set break: Controls TXD. When active, to transmitting is possible.""" + if not self.is_open: + raise portNotOpenError + if self._break_state: + win32.SetCommBreak(self._port_handle) + else: + win32.ClearCommBreak(self._port_handle) + + def _update_rts_state(self): + """Set terminal status line: Request To Send""" + if self._rts_state: + win32.EscapeCommFunction(self._port_handle, win32.SETRTS) + else: + win32.EscapeCommFunction(self._port_handle, win32.CLRRTS) + + def _update_dtr_state(self): + """Set terminal status line: Data Terminal Ready""" + if self._dtr_state: + win32.EscapeCommFunction(self._port_handle, win32.SETDTR) + else: + win32.EscapeCommFunction(self._port_handle, win32.CLRDTR) + + def _GetCommModemStatus(self): + if not self.is_open: + raise portNotOpenError + stat = win32.DWORD() + win32.GetCommModemStatus(self._port_handle, ctypes.byref(stat)) + return stat.value + + @property + def cts(self): + """Read terminal status line: Clear To Send""" + return win32.MS_CTS_ON & self._GetCommModemStatus() != 0 + + @property + def dsr(self): + """Read terminal status line: Data Set Ready""" + return win32.MS_DSR_ON & self._GetCommModemStatus() != 0 + + @property + def ri(self): + """Read terminal status line: Ring Indicator""" + return win32.MS_RING_ON & self._GetCommModemStatus() != 0 + + @property + def cd(self): + """Read terminal status line: Carrier Detect""" + return win32.MS_RLSD_ON & self._GetCommModemStatus() != 0 + + # - - platform specific - - - - + + def set_buffer_size(self, rx_size=4096, tx_size=None): + """\ + Recommend a buffer size to the driver (device driver can ignore this + value). Must be called before the port is opened. + """ + if tx_size is None: + tx_size = rx_size + win32.SetupComm(self._port_handle, rx_size, tx_size) + + def set_output_flow_control(self, enable=True): + """\ + Manually control flow - when software flow control is enabled. + This will do the same as if XON (true) or XOFF (false) are received + from the other device and control the transmission accordingly. + WARNING: this function is not portable to different platforms! + """ + if not self.is_open: + raise portNotOpenError + if enable: + win32.EscapeCommFunction(self._port_handle, win32.SETXON) + else: + win32.EscapeCommFunction(self._port_handle, win32.SETXOFF) + + @property + def out_waiting(self): + """Return how many bytes the in the outgoing buffer""" + flags = win32.DWORD() + comstat = win32.COMSTAT() + if not win32.ClearCommError(self._port_handle, ctypes.byref(flags), ctypes.byref(comstat)): + raise SerialException("ClearCommError failed ({!r})".format(ctypes.WinError())) + return comstat.cbOutQue + + def _cancel_overlapped_io(self, overlapped): + """Cancel a blocking read operation, may be called from other thread""" + # check if read operation is pending + rc = win32.DWORD() + err = win32.GetOverlappedResult( + self._port_handle, + ctypes.byref(overlapped), + ctypes.byref(rc), + False) + if not err and win32.GetLastError() in (win32.ERROR_IO_PENDING, win32.ERROR_IO_INCOMPLETE): + # cancel, ignoring any errors (e.g. it may just have finished on its own) + win32.CancelIoEx(self._port_handle, overlapped) + + def cancel_read(self): + """Cancel a blocking read operation, may be called from other thread""" + self._cancel_overlapped_io(self._overlapped_read) + + def cancel_write(self): + """Cancel a blocking write operation, may be called from other thread""" + self._cancel_overlapped_io(self._overlapped_write) + + @SerialBase.exclusive.setter + def exclusive(self, exclusive): + """Change the exclusive access setting.""" + if exclusive is not None and not exclusive: + raise ValueError('win32 only supports exclusive access (not: {})'.format(exclusive)) + else: + serial.SerialBase.exclusive.__set__(self, exclusive) diff --git a/software/tools/pymcuprog/libs/serial/win32.py b/software/tools/pymcuprog/libs/serial/win32.py new file mode 100644 index 0000000..905ce0f --- /dev/null +++ b/software/tools/pymcuprog/libs/serial/win32.py @@ -0,0 +1,354 @@ +#! python +# +# Constants and types for use with Windows API, used by serialwin32.py +# +# This file is part of pySerial. https://github.com/pyserial/pyserial +# (C) 2001-2015 Chris Liechti +# +# SPDX-License-Identifier: BSD-3-Clause + +# pylint: disable=invalid-name,too-few-public-methods,protected-access,too-many-instance-attributes + +from ctypes import c_ulong, c_void_p, c_int64, c_char, \ + WinDLL, sizeof, Structure, Union, POINTER +from ctypes.wintypes import HANDLE +from ctypes.wintypes import BOOL +from ctypes.wintypes import LPCWSTR +from ctypes.wintypes import DWORD +from ctypes.wintypes import WORD +from ctypes.wintypes import BYTE +_stdcall_libraries = {} +_stdcall_libraries['kernel32'] = WinDLL('kernel32') + +INVALID_HANDLE_VALUE = HANDLE(-1).value + + +# some details of the windows API differ between 32 and 64 bit systems.. +def is_64bit(): + """Returns true when running on a 64 bit system""" + return sizeof(c_ulong) != sizeof(c_void_p) + +# ULONG_PTR is a an ordinary number, not a pointer and contrary to the name it +# is either 32 or 64 bits, depending on the type of windows... +# so test if this a 32 bit windows... +if is_64bit(): + ULONG_PTR = c_int64 +else: + ULONG_PTR = c_ulong + + +class _SECURITY_ATTRIBUTES(Structure): + pass +LPSECURITY_ATTRIBUTES = POINTER(_SECURITY_ATTRIBUTES) + + +try: + CreateEventW = _stdcall_libraries['kernel32'].CreateEventW +except AttributeError: + # Fallback to non wide char version for old OS... + from ctypes.wintypes import LPCSTR + CreateEventA = _stdcall_libraries['kernel32'].CreateEventA + CreateEventA.restype = HANDLE + CreateEventA.argtypes = [LPSECURITY_ATTRIBUTES, BOOL, BOOL, LPCSTR] + CreateEvent = CreateEventA + + CreateFileA = _stdcall_libraries['kernel32'].CreateFileA + CreateFileA.restype = HANDLE + CreateFileA.argtypes = [LPCSTR, DWORD, DWORD, LPSECURITY_ATTRIBUTES, DWORD, DWORD, HANDLE] + CreateFile = CreateFileA +else: + CreateEventW.restype = HANDLE + CreateEventW.argtypes = [LPSECURITY_ATTRIBUTES, BOOL, BOOL, LPCWSTR] + CreateEvent = CreateEventW # alias + + CreateFileW = _stdcall_libraries['kernel32'].CreateFileW + CreateFileW.restype = HANDLE + CreateFileW.argtypes = [LPCWSTR, DWORD, DWORD, LPSECURITY_ATTRIBUTES, DWORD, DWORD, HANDLE] + CreateFile = CreateFileW # alias + + +class _OVERLAPPED(Structure): + pass + +OVERLAPPED = _OVERLAPPED + + +class _COMSTAT(Structure): + pass + +COMSTAT = _COMSTAT + + +class _DCB(Structure): + pass + +DCB = _DCB + + +class _COMMTIMEOUTS(Structure): + pass + +COMMTIMEOUTS = _COMMTIMEOUTS + +GetLastError = _stdcall_libraries['kernel32'].GetLastError +GetLastError.restype = DWORD +GetLastError.argtypes = [] + +LPOVERLAPPED = POINTER(_OVERLAPPED) +LPDWORD = POINTER(DWORD) + +GetOverlappedResult = _stdcall_libraries['kernel32'].GetOverlappedResult +GetOverlappedResult.restype = BOOL +GetOverlappedResult.argtypes = [HANDLE, LPOVERLAPPED, LPDWORD, BOOL] + +ResetEvent = _stdcall_libraries['kernel32'].ResetEvent +ResetEvent.restype = BOOL +ResetEvent.argtypes = [HANDLE] + +LPCVOID = c_void_p + +WriteFile = _stdcall_libraries['kernel32'].WriteFile +WriteFile.restype = BOOL +WriteFile.argtypes = [HANDLE, LPCVOID, DWORD, LPDWORD, LPOVERLAPPED] + +LPVOID = c_void_p + +ReadFile = _stdcall_libraries['kernel32'].ReadFile +ReadFile.restype = BOOL +ReadFile.argtypes = [HANDLE, LPVOID, DWORD, LPDWORD, LPOVERLAPPED] + +CloseHandle = _stdcall_libraries['kernel32'].CloseHandle +CloseHandle.restype = BOOL +CloseHandle.argtypes = [HANDLE] + +ClearCommBreak = _stdcall_libraries['kernel32'].ClearCommBreak +ClearCommBreak.restype = BOOL +ClearCommBreak.argtypes = [HANDLE] + +LPCOMSTAT = POINTER(_COMSTAT) + +ClearCommError = _stdcall_libraries['kernel32'].ClearCommError +ClearCommError.restype = BOOL +ClearCommError.argtypes = [HANDLE, LPDWORD, LPCOMSTAT] + +SetupComm = _stdcall_libraries['kernel32'].SetupComm +SetupComm.restype = BOOL +SetupComm.argtypes = [HANDLE, DWORD, DWORD] + +EscapeCommFunction = _stdcall_libraries['kernel32'].EscapeCommFunction +EscapeCommFunction.restype = BOOL +EscapeCommFunction.argtypes = [HANDLE, DWORD] + +GetCommModemStatus = _stdcall_libraries['kernel32'].GetCommModemStatus +GetCommModemStatus.restype = BOOL +GetCommModemStatus.argtypes = [HANDLE, LPDWORD] + +LPDCB = POINTER(_DCB) + +GetCommState = _stdcall_libraries['kernel32'].GetCommState +GetCommState.restype = BOOL +GetCommState.argtypes = [HANDLE, LPDCB] + +LPCOMMTIMEOUTS = POINTER(_COMMTIMEOUTS) + +GetCommTimeouts = _stdcall_libraries['kernel32'].GetCommTimeouts +GetCommTimeouts.restype = BOOL +GetCommTimeouts.argtypes = [HANDLE, LPCOMMTIMEOUTS] + +PurgeComm = _stdcall_libraries['kernel32'].PurgeComm +PurgeComm.restype = BOOL +PurgeComm.argtypes = [HANDLE, DWORD] + +SetCommBreak = _stdcall_libraries['kernel32'].SetCommBreak +SetCommBreak.restype = BOOL +SetCommBreak.argtypes = [HANDLE] + +SetCommMask = _stdcall_libraries['kernel32'].SetCommMask +SetCommMask.restype = BOOL +SetCommMask.argtypes = [HANDLE, DWORD] + +SetCommState = _stdcall_libraries['kernel32'].SetCommState +SetCommState.restype = BOOL +SetCommState.argtypes = [HANDLE, LPDCB] + +SetCommTimeouts = _stdcall_libraries['kernel32'].SetCommTimeouts +SetCommTimeouts.restype = BOOL +SetCommTimeouts.argtypes = [HANDLE, LPCOMMTIMEOUTS] + +WaitForSingleObject = _stdcall_libraries['kernel32'].WaitForSingleObject +WaitForSingleObject.restype = DWORD +WaitForSingleObject.argtypes = [HANDLE, DWORD] + +CancelIoEx = _stdcall_libraries['kernel32'].CancelIoEx +CancelIoEx.restype = BOOL +CancelIoEx.argtypes = [HANDLE, LPOVERLAPPED] + +ONESTOPBIT = 0 # Variable c_int +TWOSTOPBITS = 2 # Variable c_int +ONE5STOPBITS = 1 + +NOPARITY = 0 # Variable c_int +ODDPARITY = 1 # Variable c_int +EVENPARITY = 2 # Variable c_int +MARKPARITY = 3 +SPACEPARITY = 4 + +RTS_CONTROL_HANDSHAKE = 2 # Variable c_int +RTS_CONTROL_DISABLE = 0 # Variable c_int +RTS_CONTROL_ENABLE = 1 # Variable c_int +RTS_CONTROL_TOGGLE = 3 # Variable c_int +SETRTS = 3 +CLRRTS = 4 + +DTR_CONTROL_HANDSHAKE = 2 # Variable c_int +DTR_CONTROL_DISABLE = 0 # Variable c_int +DTR_CONTROL_ENABLE = 1 # Variable c_int +SETDTR = 5 +CLRDTR = 6 + +MS_DSR_ON = 32 # Variable c_ulong +EV_RING = 256 # Variable c_int +EV_PERR = 512 # Variable c_int +EV_ERR = 128 # Variable c_int +SETXOFF = 1 # Variable c_int +EV_RXCHAR = 1 # Variable c_int +GENERIC_WRITE = 1073741824 # Variable c_long +PURGE_TXCLEAR = 4 # Variable c_int +FILE_FLAG_OVERLAPPED = 1073741824 # Variable c_int +EV_DSR = 16 # Variable c_int +MAXDWORD = 4294967295 # Variable c_uint +EV_RLSD = 32 # Variable c_int + +ERROR_SUCCESS = 0 +ERROR_NOT_ENOUGH_MEMORY = 8 +ERROR_OPERATION_ABORTED = 995 +ERROR_IO_INCOMPLETE = 996 +ERROR_IO_PENDING = 997 # Variable c_long +ERROR_INVALID_USER_BUFFER = 1784 + +MS_CTS_ON = 16 # Variable c_ulong +EV_EVENT1 = 2048 # Variable c_int +EV_RX80FULL = 1024 # Variable c_int +PURGE_RXABORT = 2 # Variable c_int +FILE_ATTRIBUTE_NORMAL = 128 # Variable c_int +PURGE_TXABORT = 1 # Variable c_int +SETXON = 2 # Variable c_int +OPEN_EXISTING = 3 # Variable c_int +MS_RING_ON = 64 # Variable c_ulong +EV_TXEMPTY = 4 # Variable c_int +EV_RXFLAG = 2 # Variable c_int +MS_RLSD_ON = 128 # Variable c_ulong +GENERIC_READ = 2147483648 # Variable c_ulong +EV_EVENT2 = 4096 # Variable c_int +EV_CTS = 8 # Variable c_int +EV_BREAK = 64 # Variable c_int +PURGE_RXCLEAR = 8 # Variable c_int +INFINITE = 0xFFFFFFFF + + +class N11_OVERLAPPED4DOLLAR_48E(Union): + pass + + +class N11_OVERLAPPED4DOLLAR_484DOLLAR_49E(Structure): + pass + + +N11_OVERLAPPED4DOLLAR_484DOLLAR_49E._fields_ = [ + ('Offset', DWORD), + ('OffsetHigh', DWORD), +] + +PVOID = c_void_p + +N11_OVERLAPPED4DOLLAR_48E._anonymous_ = ['_0'] +N11_OVERLAPPED4DOLLAR_48E._fields_ = [ + ('_0', N11_OVERLAPPED4DOLLAR_484DOLLAR_49E), + ('Pointer', PVOID), +] +_OVERLAPPED._anonymous_ = ['_0'] +_OVERLAPPED._fields_ = [ + ('Internal', ULONG_PTR), + ('InternalHigh', ULONG_PTR), + ('_0', N11_OVERLAPPED4DOLLAR_48E), + ('hEvent', HANDLE), +] +_SECURITY_ATTRIBUTES._fields_ = [ + ('nLength', DWORD), + ('lpSecurityDescriptor', LPVOID), + ('bInheritHandle', BOOL), +] +_COMSTAT._fields_ = [ + ('fCtsHold', DWORD, 1), + ('fDsrHold', DWORD, 1), + ('fRlsdHold', DWORD, 1), + ('fXoffHold', DWORD, 1), + ('fXoffSent', DWORD, 1), + ('fEof', DWORD, 1), + ('fTxim', DWORD, 1), + ('fReserved', DWORD, 25), + ('cbInQue', DWORD), + ('cbOutQue', DWORD), +] +_DCB._fields_ = [ + ('DCBlength', DWORD), + ('BaudRate', DWORD), + ('fBinary', DWORD, 1), + ('fParity', DWORD, 1), + ('fOutxCtsFlow', DWORD, 1), + ('fOutxDsrFlow', DWORD, 1), + ('fDtrControl', DWORD, 2), + ('fDsrSensitivity', DWORD, 1), + ('fTXContinueOnXoff', DWORD, 1), + ('fOutX', DWORD, 1), + ('fInX', DWORD, 1), + ('fErrorChar', DWORD, 1), + ('fNull', DWORD, 1), + ('fRtsControl', DWORD, 2), + ('fAbortOnError', DWORD, 1), + ('fDummy2', DWORD, 17), + ('wReserved', WORD), + ('XonLim', WORD), + ('XoffLim', WORD), + ('ByteSize', BYTE), + ('Parity', BYTE), + ('StopBits', BYTE), + ('XonChar', c_char), + ('XoffChar', c_char), + ('ErrorChar', c_char), + ('EofChar', c_char), + ('EvtChar', c_char), + ('wReserved1', WORD), +] +_COMMTIMEOUTS._fields_ = [ + ('ReadIntervalTimeout', DWORD), + ('ReadTotalTimeoutMultiplier', DWORD), + ('ReadTotalTimeoutConstant', DWORD), + ('WriteTotalTimeoutMultiplier', DWORD), + ('WriteTotalTimeoutConstant', DWORD), +] +__all__ = ['GetLastError', 'MS_CTS_ON', 'FILE_ATTRIBUTE_NORMAL', + 'DTR_CONTROL_ENABLE', '_COMSTAT', 'MS_RLSD_ON', + 'GetOverlappedResult', 'SETXON', 'PURGE_TXABORT', + 'PurgeComm', 'N11_OVERLAPPED4DOLLAR_48E', 'EV_RING', + 'ONESTOPBIT', 'SETXOFF', 'PURGE_RXABORT', 'GetCommState', + 'RTS_CONTROL_ENABLE', '_DCB', 'CreateEvent', + '_COMMTIMEOUTS', '_SECURITY_ATTRIBUTES', 'EV_DSR', + 'EV_PERR', 'EV_RXFLAG', 'OPEN_EXISTING', 'DCB', + 'FILE_FLAG_OVERLAPPED', 'EV_CTS', 'SetupComm', + 'LPOVERLAPPED', 'EV_TXEMPTY', 'ClearCommBreak', + 'LPSECURITY_ATTRIBUTES', 'SetCommBreak', 'SetCommTimeouts', + 'COMMTIMEOUTS', 'ODDPARITY', 'EV_RLSD', + 'GetCommModemStatus', 'EV_EVENT2', 'PURGE_TXCLEAR', + 'EV_BREAK', 'EVENPARITY', 'LPCVOID', 'COMSTAT', 'ReadFile', + 'PVOID', '_OVERLAPPED', 'WriteFile', 'GetCommTimeouts', + 'ResetEvent', 'EV_RXCHAR', 'LPCOMSTAT', 'ClearCommError', + 'ERROR_IO_PENDING', 'EscapeCommFunction', 'GENERIC_READ', + 'RTS_CONTROL_HANDSHAKE', 'OVERLAPPED', + 'DTR_CONTROL_HANDSHAKE', 'PURGE_RXCLEAR', 'GENERIC_WRITE', + 'LPDCB', 'CreateEventW', 'SetCommMask', 'EV_EVENT1', + 'SetCommState', 'LPVOID', 'CreateFileW', 'LPDWORD', + 'EV_RX80FULL', 'TWOSTOPBITS', 'LPCOMMTIMEOUTS', 'MAXDWORD', + 'MS_DSR_ON', 'MS_RING_ON', + 'N11_OVERLAPPED4DOLLAR_484DOLLAR_49E', 'EV_ERR', + 'ULONG_PTR', 'CreateFile', 'NOPARITY', 'CloseHandle'] diff --git a/software/tools/pymcuprog/libs/yaml/__init__.py b/software/tools/pymcuprog/libs/yaml/__init__.py new file mode 100644 index 0000000..9e35fe2 --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/__init__.py @@ -0,0 +1,312 @@ + +from .error import * + +from .tokens import * +from .events import * +from .nodes import * + +from .loader import * +from .dumper import * + +__version__ = '3.13' +try: + from .cyaml import * + __with_libyaml__ = True +except ImportError: + __with_libyaml__ = False + +import io + +def scan(stream, Loader=Loader): + """ + Scan a YAML stream and produce scanning tokens. + """ + loader = Loader(stream) + try: + while loader.check_token(): + yield loader.get_token() + finally: + loader.dispose() + +def parse(stream, Loader=Loader): + """ + Parse a YAML stream and produce parsing events. + """ + loader = Loader(stream) + try: + while loader.check_event(): + yield loader.get_event() + finally: + loader.dispose() + +def compose(stream, Loader=Loader): + """ + Parse the first YAML document in a stream + and produce the corresponding representation tree. + """ + loader = Loader(stream) + try: + return loader.get_single_node() + finally: + loader.dispose() + +def compose_all(stream, Loader=Loader): + """ + Parse all YAML documents in a stream + and produce corresponding representation trees. + """ + loader = Loader(stream) + try: + while loader.check_node(): + yield loader.get_node() + finally: + loader.dispose() + +def load(stream, Loader=Loader): + """ + Parse the first YAML document in a stream + and produce the corresponding Python object. + """ + loader = Loader(stream) + try: + return loader.get_single_data() + finally: + loader.dispose() + +def load_all(stream, Loader=Loader): + """ + Parse all YAML documents in a stream + and produce corresponding Python objects. + """ + loader = Loader(stream) + try: + while loader.check_data(): + yield loader.get_data() + finally: + loader.dispose() + +def safe_load(stream): + """ + Parse the first YAML document in a stream + and produce the corresponding Python object. + Resolve only basic YAML tags. + """ + return load(stream, SafeLoader) + +def safe_load_all(stream): + """ + Parse all YAML documents in a stream + and produce corresponding Python objects. + Resolve only basic YAML tags. + """ + return load_all(stream, SafeLoader) + +def emit(events, stream=None, Dumper=Dumper, + canonical=None, indent=None, width=None, + allow_unicode=None, line_break=None): + """ + Emit YAML parsing events into a stream. + If stream is None, return the produced string instead. + """ + getvalue = None + if stream is None: + stream = io.StringIO() + getvalue = stream.getvalue + dumper = Dumper(stream, canonical=canonical, indent=indent, width=width, + allow_unicode=allow_unicode, line_break=line_break) + try: + for event in events: + dumper.emit(event) + finally: + dumper.dispose() + if getvalue: + return getvalue() + +def serialize_all(nodes, stream=None, Dumper=Dumper, + canonical=None, indent=None, width=None, + allow_unicode=None, line_break=None, + encoding=None, explicit_start=None, explicit_end=None, + version=None, tags=None): + """ + Serialize a sequence of representation trees into a YAML stream. + If stream is None, return the produced string instead. + """ + getvalue = None + if stream is None: + if encoding is None: + stream = io.StringIO() + else: + stream = io.BytesIO() + getvalue = stream.getvalue + dumper = Dumper(stream, canonical=canonical, indent=indent, width=width, + allow_unicode=allow_unicode, line_break=line_break, + encoding=encoding, version=version, tags=tags, + explicit_start=explicit_start, explicit_end=explicit_end) + try: + dumper.open() + for node in nodes: + dumper.serialize(node) + dumper.close() + finally: + dumper.dispose() + if getvalue: + return getvalue() + +def serialize(node, stream=None, Dumper=Dumper, **kwds): + """ + Serialize a representation tree into a YAML stream. + If stream is None, return the produced string instead. + """ + return serialize_all([node], stream, Dumper=Dumper, **kwds) + +def dump_all(documents, stream=None, Dumper=Dumper, + default_style=None, default_flow_style=None, + canonical=None, indent=None, width=None, + allow_unicode=None, line_break=None, + encoding=None, explicit_start=None, explicit_end=None, + version=None, tags=None): + """ + Serialize a sequence of Python objects into a YAML stream. + If stream is None, return the produced string instead. + """ + getvalue = None + if stream is None: + if encoding is None: + stream = io.StringIO() + else: + stream = io.BytesIO() + getvalue = stream.getvalue + dumper = Dumper(stream, default_style=default_style, + default_flow_style=default_flow_style, + canonical=canonical, indent=indent, width=width, + allow_unicode=allow_unicode, line_break=line_break, + encoding=encoding, version=version, tags=tags, + explicit_start=explicit_start, explicit_end=explicit_end) + try: + dumper.open() + for data in documents: + dumper.represent(data) + dumper.close() + finally: + dumper.dispose() + if getvalue: + return getvalue() + +def dump(data, stream=None, Dumper=Dumper, **kwds): + """ + Serialize a Python object into a YAML stream. + If stream is None, return the produced string instead. + """ + return dump_all([data], stream, Dumper=Dumper, **kwds) + +def safe_dump_all(documents, stream=None, **kwds): + """ + Serialize a sequence of Python objects into a YAML stream. + Produce only basic YAML tags. + If stream is None, return the produced string instead. + """ + return dump_all(documents, stream, Dumper=SafeDumper, **kwds) + +def safe_dump(data, stream=None, **kwds): + """ + Serialize a Python object into a YAML stream. + Produce only basic YAML tags. + If stream is None, return the produced string instead. + """ + return dump_all([data], stream, Dumper=SafeDumper, **kwds) + +def add_implicit_resolver(tag, regexp, first=None, + Loader=Loader, Dumper=Dumper): + """ + Add an implicit scalar detector. + If an implicit scalar value matches the given regexp, + the corresponding tag is assigned to the scalar. + first is a sequence of possible initial characters or None. + """ + Loader.add_implicit_resolver(tag, regexp, first) + Dumper.add_implicit_resolver(tag, regexp, first) + +def add_path_resolver(tag, path, kind=None, Loader=Loader, Dumper=Dumper): + """ + Add a path based resolver for the given tag. + A path is a list of keys that forms a path + to a node in the representation tree. + Keys can be string values, integers, or None. + """ + Loader.add_path_resolver(tag, path, kind) + Dumper.add_path_resolver(tag, path, kind) + +def add_constructor(tag, constructor, Loader=Loader): + """ + Add a constructor for the given tag. + Constructor is a function that accepts a Loader instance + and a node object and produces the corresponding Python object. + """ + Loader.add_constructor(tag, constructor) + +def add_multi_constructor(tag_prefix, multi_constructor, Loader=Loader): + """ + Add a multi-constructor for the given tag prefix. + Multi-constructor is called for a node if its tag starts with tag_prefix. + Multi-constructor accepts a Loader instance, a tag suffix, + and a node object and produces the corresponding Python object. + """ + Loader.add_multi_constructor(tag_prefix, multi_constructor) + +def add_representer(data_type, representer, Dumper=Dumper): + """ + Add a representer for the given type. + Representer is a function accepting a Dumper instance + and an instance of the given data type + and producing the corresponding representation node. + """ + Dumper.add_representer(data_type, representer) + +def add_multi_representer(data_type, multi_representer, Dumper=Dumper): + """ + Add a representer for the given type. + Multi-representer is a function accepting a Dumper instance + and an instance of the given data type or subtype + and producing the corresponding representation node. + """ + Dumper.add_multi_representer(data_type, multi_representer) + +class YAMLObjectMetaclass(type): + """ + The metaclass for YAMLObject. + """ + def __init__(cls, name, bases, kwds): + super(YAMLObjectMetaclass, cls).__init__(name, bases, kwds) + if 'yaml_tag' in kwds and kwds['yaml_tag'] is not None: + cls.yaml_loader.add_constructor(cls.yaml_tag, cls.from_yaml) + cls.yaml_dumper.add_representer(cls, cls.to_yaml) + +class YAMLObject(metaclass=YAMLObjectMetaclass): + """ + An object that can dump itself to a YAML stream + and load itself from a YAML stream. + """ + + __slots__ = () # no direct instantiation, so allow immutable subclasses + + yaml_loader = Loader + yaml_dumper = Dumper + + yaml_tag = None + yaml_flow_style = None + + @classmethod + def from_yaml(cls, loader, node): + """ + Convert a representation node to a Python object. + """ + return loader.construct_yaml_object(node, cls) + + @classmethod + def to_yaml(cls, dumper, data): + """ + Convert a Python object to a representation node. + """ + return dumper.represent_yaml_object(cls.yaml_tag, data, cls, + flow_style=cls.yaml_flow_style) + diff --git a/software/tools/pymcuprog/libs/yaml/composer.py b/software/tools/pymcuprog/libs/yaml/composer.py new file mode 100644 index 0000000..d5c6a7a --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/composer.py @@ -0,0 +1,139 @@ + +__all__ = ['Composer', 'ComposerError'] + +from .error import MarkedYAMLError +from .events import * +from .nodes import * + +class ComposerError(MarkedYAMLError): + pass + +class Composer: + + def __init__(self): + self.anchors = {} + + def check_node(self): + # Drop the STREAM-START event. + if self.check_event(StreamStartEvent): + self.get_event() + + # If there are more documents available? + return not self.check_event(StreamEndEvent) + + def get_node(self): + # Get the root node of the next document. + if not self.check_event(StreamEndEvent): + return self.compose_document() + + def get_single_node(self): + # Drop the STREAM-START event. + self.get_event() + + # Compose a document if the stream is not empty. + document = None + if not self.check_event(StreamEndEvent): + document = self.compose_document() + + # Ensure that the stream contains no more documents. + if not self.check_event(StreamEndEvent): + event = self.get_event() + raise ComposerError("expected a single document in the stream", + document.start_mark, "but found another document", + event.start_mark) + + # Drop the STREAM-END event. + self.get_event() + + return document + + def compose_document(self): + # Drop the DOCUMENT-START event. + self.get_event() + + # Compose the root node. + node = self.compose_node(None, None) + + # Drop the DOCUMENT-END event. + self.get_event() + + self.anchors = {} + return node + + def compose_node(self, parent, index): + if self.check_event(AliasEvent): + event = self.get_event() + anchor = event.anchor + if anchor not in self.anchors: + raise ComposerError(None, None, "found undefined alias %r" + % anchor, event.start_mark) + return self.anchors[anchor] + event = self.peek_event() + anchor = event.anchor + if anchor is not None: + if anchor in self.anchors: + raise ComposerError("found duplicate anchor %r; first occurence" + % anchor, self.anchors[anchor].start_mark, + "second occurence", event.start_mark) + self.descend_resolver(parent, index) + if self.check_event(ScalarEvent): + node = self.compose_scalar_node(anchor) + elif self.check_event(SequenceStartEvent): + node = self.compose_sequence_node(anchor) + elif self.check_event(MappingStartEvent): + node = self.compose_mapping_node(anchor) + self.ascend_resolver() + return node + + def compose_scalar_node(self, anchor): + event = self.get_event() + tag = event.tag + if tag is None or tag == '!': + tag = self.resolve(ScalarNode, event.value, event.implicit) + node = ScalarNode(tag, event.value, + event.start_mark, event.end_mark, style=event.style) + if anchor is not None: + self.anchors[anchor] = node + return node + + def compose_sequence_node(self, anchor): + start_event = self.get_event() + tag = start_event.tag + if tag is None or tag == '!': + tag = self.resolve(SequenceNode, None, start_event.implicit) + node = SequenceNode(tag, [], + start_event.start_mark, None, + flow_style=start_event.flow_style) + if anchor is not None: + self.anchors[anchor] = node + index = 0 + while not self.check_event(SequenceEndEvent): + node.value.append(self.compose_node(node, index)) + index += 1 + end_event = self.get_event() + node.end_mark = end_event.end_mark + return node + + def compose_mapping_node(self, anchor): + start_event = self.get_event() + tag = start_event.tag + if tag is None or tag == '!': + tag = self.resolve(MappingNode, None, start_event.implicit) + node = MappingNode(tag, [], + start_event.start_mark, None, + flow_style=start_event.flow_style) + if anchor is not None: + self.anchors[anchor] = node + while not self.check_event(MappingEndEvent): + #key_event = self.peek_event() + item_key = self.compose_node(node, None) + #if item_key in node.value: + # raise ComposerError("while composing a mapping", start_event.start_mark, + # "found duplicate key", key_event.start_mark) + item_value = self.compose_node(node, item_key) + #node.value[item_key] = item_value + node.value.append((item_key, item_value)) + end_event = self.get_event() + node.end_mark = end_event.end_mark + return node + diff --git a/software/tools/pymcuprog/libs/yaml/constructor.py b/software/tools/pymcuprog/libs/yaml/constructor.py new file mode 100644 index 0000000..981543a --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/constructor.py @@ -0,0 +1,686 @@ + +__all__ = ['BaseConstructor', 'SafeConstructor', 'Constructor', + 'ConstructorError'] + +from .error import * +from .nodes import * + +import collections, datetime, base64, binascii, re, sys, types + +class ConstructorError(MarkedYAMLError): + pass + +class BaseConstructor: + + yaml_constructors = {} + yaml_multi_constructors = {} + + def __init__(self): + self.constructed_objects = {} + self.recursive_objects = {} + self.state_generators = [] + self.deep_construct = False + + def check_data(self): + # If there are more documents available? + return self.check_node() + + def get_data(self): + # Construct and return the next document. + if self.check_node(): + return self.construct_document(self.get_node()) + + def get_single_data(self): + # Ensure that the stream contains a single document and construct it. + node = self.get_single_node() + if node is not None: + return self.construct_document(node) + return None + + def construct_document(self, node): + data = self.construct_object(node) + while self.state_generators: + state_generators = self.state_generators + self.state_generators = [] + for generator in state_generators: + for dummy in generator: + pass + self.constructed_objects = {} + self.recursive_objects = {} + self.deep_construct = False + return data + + def construct_object(self, node, deep=False): + if node in self.constructed_objects: + return self.constructed_objects[node] + if deep: + old_deep = self.deep_construct + self.deep_construct = True + if node in self.recursive_objects: + raise ConstructorError(None, None, + "found unconstructable recursive node", node.start_mark) + self.recursive_objects[node] = None + constructor = None + tag_suffix = None + if node.tag in self.yaml_constructors: + constructor = self.yaml_constructors[node.tag] + else: + for tag_prefix in self.yaml_multi_constructors: + if node.tag.startswith(tag_prefix): + tag_suffix = node.tag[len(tag_prefix):] + constructor = self.yaml_multi_constructors[tag_prefix] + break + else: + if None in self.yaml_multi_constructors: + tag_suffix = node.tag + constructor = self.yaml_multi_constructors[None] + elif None in self.yaml_constructors: + constructor = self.yaml_constructors[None] + elif isinstance(node, ScalarNode): + constructor = self.__class__.construct_scalar + elif isinstance(node, SequenceNode): + constructor = self.__class__.construct_sequence + elif isinstance(node, MappingNode): + constructor = self.__class__.construct_mapping + if tag_suffix is None: + data = constructor(self, node) + else: + data = constructor(self, tag_suffix, node) + if isinstance(data, types.GeneratorType): + generator = data + data = next(generator) + if self.deep_construct: + for dummy in generator: + pass + else: + self.state_generators.append(generator) + self.constructed_objects[node] = data + del self.recursive_objects[node] + if deep: + self.deep_construct = old_deep + return data + + def construct_scalar(self, node): + if not isinstance(node, ScalarNode): + raise ConstructorError(None, None, + "expected a scalar node, but found %s" % node.id, + node.start_mark) + return node.value + + def construct_sequence(self, node, deep=False): + if not isinstance(node, SequenceNode): + raise ConstructorError(None, None, + "expected a sequence node, but found %s" % node.id, + node.start_mark) + return [self.construct_object(child, deep=deep) + for child in node.value] + + def construct_mapping(self, node, deep=False): + if not isinstance(node, MappingNode): + raise ConstructorError(None, None, + "expected a mapping node, but found %s" % node.id, + node.start_mark) + mapping = {} + for key_node, value_node in node.value: + key = self.construct_object(key_node, deep=deep) + if not isinstance(key, collections.Hashable): + raise ConstructorError("while constructing a mapping", node.start_mark, + "found unhashable key", key_node.start_mark) + value = self.construct_object(value_node, deep=deep) + mapping[key] = value + return mapping + + def construct_pairs(self, node, deep=False): + if not isinstance(node, MappingNode): + raise ConstructorError(None, None, + "expected a mapping node, but found %s" % node.id, + node.start_mark) + pairs = [] + for key_node, value_node in node.value: + key = self.construct_object(key_node, deep=deep) + value = self.construct_object(value_node, deep=deep) + pairs.append((key, value)) + return pairs + + @classmethod + def add_constructor(cls, tag, constructor): + if not 'yaml_constructors' in cls.__dict__: + cls.yaml_constructors = cls.yaml_constructors.copy() + cls.yaml_constructors[tag] = constructor + + @classmethod + def add_multi_constructor(cls, tag_prefix, multi_constructor): + if not 'yaml_multi_constructors' in cls.__dict__: + cls.yaml_multi_constructors = cls.yaml_multi_constructors.copy() + cls.yaml_multi_constructors[tag_prefix] = multi_constructor + +class SafeConstructor(BaseConstructor): + + def construct_scalar(self, node): + if isinstance(node, MappingNode): + for key_node, value_node in node.value: + if key_node.tag == 'tag:yaml.org,2002:value': + return self.construct_scalar(value_node) + return super().construct_scalar(node) + + def flatten_mapping(self, node): + merge = [] + index = 0 + while index < len(node.value): + key_node, value_node = node.value[index] + if key_node.tag == 'tag:yaml.org,2002:merge': + del node.value[index] + if isinstance(value_node, MappingNode): + self.flatten_mapping(value_node) + merge.extend(value_node.value) + elif isinstance(value_node, SequenceNode): + submerge = [] + for subnode in value_node.value: + if not isinstance(subnode, MappingNode): + raise ConstructorError("while constructing a mapping", + node.start_mark, + "expected a mapping for merging, but found %s" + % subnode.id, subnode.start_mark) + self.flatten_mapping(subnode) + submerge.append(subnode.value) + submerge.reverse() + for value in submerge: + merge.extend(value) + else: + raise ConstructorError("while constructing a mapping", node.start_mark, + "expected a mapping or list of mappings for merging, but found %s" + % value_node.id, value_node.start_mark) + elif key_node.tag == 'tag:yaml.org,2002:value': + key_node.tag = 'tag:yaml.org,2002:str' + index += 1 + else: + index += 1 + if merge: + node.value = merge + node.value + + def construct_mapping(self, node, deep=False): + if isinstance(node, MappingNode): + self.flatten_mapping(node) + return super().construct_mapping(node, deep=deep) + + def construct_yaml_null(self, node): + self.construct_scalar(node) + return None + + bool_values = { + 'yes': True, + 'no': False, + 'true': True, + 'false': False, + 'on': True, + 'off': False, + } + + def construct_yaml_bool(self, node): + value = self.construct_scalar(node) + return self.bool_values[value.lower()] + + def construct_yaml_int(self, node): + value = self.construct_scalar(node) + value = value.replace('_', '') + sign = +1 + if value[0] == '-': + sign = -1 + if value[0] in '+-': + value = value[1:] + if value == '0': + return 0 + elif value.startswith('0b'): + return sign*int(value[2:], 2) + elif value.startswith('0x'): + return sign*int(value[2:], 16) + elif value[0] == '0': + return sign*int(value, 8) + elif ':' in value: + digits = [int(part) for part in value.split(':')] + digits.reverse() + base = 1 + value = 0 + for digit in digits: + value += digit*base + base *= 60 + return sign*value + else: + return sign*int(value) + + inf_value = 1e300 + while inf_value != inf_value*inf_value: + inf_value *= inf_value + nan_value = -inf_value/inf_value # Trying to make a quiet NaN (like C99). + + def construct_yaml_float(self, node): + value = self.construct_scalar(node) + value = value.replace('_', '').lower() + sign = +1 + if value[0] == '-': + sign = -1 + if value[0] in '+-': + value = value[1:] + if value == '.inf': + return sign*self.inf_value + elif value == '.nan': + return self.nan_value + elif ':' in value: + digits = [float(part) for part in value.split(':')] + digits.reverse() + base = 1 + value = 0.0 + for digit in digits: + value += digit*base + base *= 60 + return sign*value + else: + return sign*float(value) + + def construct_yaml_binary(self, node): + try: + value = self.construct_scalar(node).encode('ascii') + except UnicodeEncodeError as exc: + raise ConstructorError(None, None, + "failed to convert base64 data into ascii: %s" % exc, + node.start_mark) + try: + if hasattr(base64, 'decodebytes'): + return base64.decodebytes(value) + else: + return base64.decodestring(value) + except binascii.Error as exc: + raise ConstructorError(None, None, + "failed to decode base64 data: %s" % exc, node.start_mark) + + timestamp_regexp = re.compile( + r'''^(?P[0-9][0-9][0-9][0-9]) + -(?P[0-9][0-9]?) + -(?P[0-9][0-9]?) + (?:(?:[Tt]|[ \t]+) + (?P[0-9][0-9]?) + :(?P[0-9][0-9]) + :(?P[0-9][0-9]) + (?:\.(?P[0-9]*))? + (?:[ \t]*(?PZ|(?P[-+])(?P[0-9][0-9]?) + (?::(?P[0-9][0-9]))?))?)?$''', re.X) + + def construct_yaml_timestamp(self, node): + value = self.construct_scalar(node) + match = self.timestamp_regexp.match(node.value) + values = match.groupdict() + year = int(values['year']) + month = int(values['month']) + day = int(values['day']) + if not values['hour']: + return datetime.date(year, month, day) + hour = int(values['hour']) + minute = int(values['minute']) + second = int(values['second']) + fraction = 0 + if values['fraction']: + fraction = values['fraction'][:6] + while len(fraction) < 6: + fraction += '0' + fraction = int(fraction) + delta = None + if values['tz_sign']: + tz_hour = int(values['tz_hour']) + tz_minute = int(values['tz_minute'] or 0) + delta = datetime.timedelta(hours=tz_hour, minutes=tz_minute) + if values['tz_sign'] == '-': + delta = -delta + data = datetime.datetime(year, month, day, hour, minute, second, fraction) + if delta: + data -= delta + return data + + def construct_yaml_omap(self, node): + # Note: we do not check for duplicate keys, because it's too + # CPU-expensive. + omap = [] + yield omap + if not isinstance(node, SequenceNode): + raise ConstructorError("while constructing an ordered map", node.start_mark, + "expected a sequence, but found %s" % node.id, node.start_mark) + for subnode in node.value: + if not isinstance(subnode, MappingNode): + raise ConstructorError("while constructing an ordered map", node.start_mark, + "expected a mapping of length 1, but found %s" % subnode.id, + subnode.start_mark) + if len(subnode.value) != 1: + raise ConstructorError("while constructing an ordered map", node.start_mark, + "expected a single mapping item, but found %d items" % len(subnode.value), + subnode.start_mark) + key_node, value_node = subnode.value[0] + key = self.construct_object(key_node) + value = self.construct_object(value_node) + omap.append((key, value)) + + def construct_yaml_pairs(self, node): + # Note: the same code as `construct_yaml_omap`. + pairs = [] + yield pairs + if not isinstance(node, SequenceNode): + raise ConstructorError("while constructing pairs", node.start_mark, + "expected a sequence, but found %s" % node.id, node.start_mark) + for subnode in node.value: + if not isinstance(subnode, MappingNode): + raise ConstructorError("while constructing pairs", node.start_mark, + "expected a mapping of length 1, but found %s" % subnode.id, + subnode.start_mark) + if len(subnode.value) != 1: + raise ConstructorError("while constructing pairs", node.start_mark, + "expected a single mapping item, but found %d items" % len(subnode.value), + subnode.start_mark) + key_node, value_node = subnode.value[0] + key = self.construct_object(key_node) + value = self.construct_object(value_node) + pairs.append((key, value)) + + def construct_yaml_set(self, node): + data = set() + yield data + value = self.construct_mapping(node) + data.update(value) + + def construct_yaml_str(self, node): + return self.construct_scalar(node) + + def construct_yaml_seq(self, node): + data = [] + yield data + data.extend(self.construct_sequence(node)) + + def construct_yaml_map(self, node): + data = {} + yield data + value = self.construct_mapping(node) + data.update(value) + + def construct_yaml_object(self, node, cls): + data = cls.__new__(cls) + yield data + if hasattr(data, '__setstate__'): + state = self.construct_mapping(node, deep=True) + data.__setstate__(state) + else: + state = self.construct_mapping(node) + data.__dict__.update(state) + + def construct_undefined(self, node): + raise ConstructorError(None, None, + "could not determine a constructor for the tag %r" % node.tag, + node.start_mark) + +SafeConstructor.add_constructor( + 'tag:yaml.org,2002:null', + SafeConstructor.construct_yaml_null) + +SafeConstructor.add_constructor( + 'tag:yaml.org,2002:bool', + SafeConstructor.construct_yaml_bool) + +SafeConstructor.add_constructor( + 'tag:yaml.org,2002:int', + SafeConstructor.construct_yaml_int) + +SafeConstructor.add_constructor( + 'tag:yaml.org,2002:float', + SafeConstructor.construct_yaml_float) + +SafeConstructor.add_constructor( + 'tag:yaml.org,2002:binary', + SafeConstructor.construct_yaml_binary) + +SafeConstructor.add_constructor( + 'tag:yaml.org,2002:timestamp', + SafeConstructor.construct_yaml_timestamp) + +SafeConstructor.add_constructor( + 'tag:yaml.org,2002:omap', + SafeConstructor.construct_yaml_omap) + +SafeConstructor.add_constructor( + 'tag:yaml.org,2002:pairs', + SafeConstructor.construct_yaml_pairs) + +SafeConstructor.add_constructor( + 'tag:yaml.org,2002:set', + SafeConstructor.construct_yaml_set) + +SafeConstructor.add_constructor( + 'tag:yaml.org,2002:str', + SafeConstructor.construct_yaml_str) + +SafeConstructor.add_constructor( + 'tag:yaml.org,2002:seq', + SafeConstructor.construct_yaml_seq) + +SafeConstructor.add_constructor( + 'tag:yaml.org,2002:map', + SafeConstructor.construct_yaml_map) + +SafeConstructor.add_constructor(None, + SafeConstructor.construct_undefined) + +class Constructor(SafeConstructor): + + def construct_python_str(self, node): + return self.construct_scalar(node) + + def construct_python_unicode(self, node): + return self.construct_scalar(node) + + def construct_python_bytes(self, node): + try: + value = self.construct_scalar(node).encode('ascii') + except UnicodeEncodeError as exc: + raise ConstructorError(None, None, + "failed to convert base64 data into ascii: %s" % exc, + node.start_mark) + try: + if hasattr(base64, 'decodebytes'): + return base64.decodebytes(value) + else: + return base64.decodestring(value) + except binascii.Error as exc: + raise ConstructorError(None, None, + "failed to decode base64 data: %s" % exc, node.start_mark) + + def construct_python_long(self, node): + return self.construct_yaml_int(node) + + def construct_python_complex(self, node): + return complex(self.construct_scalar(node)) + + def construct_python_tuple(self, node): + return tuple(self.construct_sequence(node)) + + def find_python_module(self, name, mark): + if not name: + raise ConstructorError("while constructing a Python module", mark, + "expected non-empty name appended to the tag", mark) + try: + __import__(name) + except ImportError as exc: + raise ConstructorError("while constructing a Python module", mark, + "cannot find module %r (%s)" % (name, exc), mark) + return sys.modules[name] + + def find_python_name(self, name, mark): + if not name: + raise ConstructorError("while constructing a Python object", mark, + "expected non-empty name appended to the tag", mark) + if '.' in name: + module_name, object_name = name.rsplit('.', 1) + else: + module_name = 'builtins' + object_name = name + try: + __import__(module_name) + except ImportError as exc: + raise ConstructorError("while constructing a Python object", mark, + "cannot find module %r (%s)" % (module_name, exc), mark) + module = sys.modules[module_name] + if not hasattr(module, object_name): + raise ConstructorError("while constructing a Python object", mark, + "cannot find %r in the module %r" + % (object_name, module.__name__), mark) + return getattr(module, object_name) + + def construct_python_name(self, suffix, node): + value = self.construct_scalar(node) + if value: + raise ConstructorError("while constructing a Python name", node.start_mark, + "expected the empty value, but found %r" % value, node.start_mark) + return self.find_python_name(suffix, node.start_mark) + + def construct_python_module(self, suffix, node): + value = self.construct_scalar(node) + if value: + raise ConstructorError("while constructing a Python module", node.start_mark, + "expected the empty value, but found %r" % value, node.start_mark) + return self.find_python_module(suffix, node.start_mark) + + def make_python_instance(self, suffix, node, + args=None, kwds=None, newobj=False): + if not args: + args = [] + if not kwds: + kwds = {} + cls = self.find_python_name(suffix, node.start_mark) + if newobj and isinstance(cls, type): + return cls.__new__(cls, *args, **kwds) + else: + return cls(*args, **kwds) + + def set_python_instance_state(self, instance, state): + if hasattr(instance, '__setstate__'): + instance.__setstate__(state) + else: + slotstate = {} + if isinstance(state, tuple) and len(state) == 2: + state, slotstate = state + if hasattr(instance, '__dict__'): + instance.__dict__.update(state) + elif state: + slotstate.update(state) + for key, value in slotstate.items(): + setattr(object, key, value) + + def construct_python_object(self, suffix, node): + # Format: + # !!python/object:module.name { ... state ... } + instance = self.make_python_instance(suffix, node, newobj=True) + yield instance + deep = hasattr(instance, '__setstate__') + state = self.construct_mapping(node, deep=deep) + self.set_python_instance_state(instance, state) + + def construct_python_object_apply(self, suffix, node, newobj=False): + # Format: + # !!python/object/apply # (or !!python/object/new) + # args: [ ... arguments ... ] + # kwds: { ... keywords ... } + # state: ... state ... + # listitems: [ ... listitems ... ] + # dictitems: { ... dictitems ... } + # or short format: + # !!python/object/apply [ ... arguments ... ] + # The difference between !!python/object/apply and !!python/object/new + # is how an object is created, check make_python_instance for details. + if isinstance(node, SequenceNode): + args = self.construct_sequence(node, deep=True) + kwds = {} + state = {} + listitems = [] + dictitems = {} + else: + value = self.construct_mapping(node, deep=True) + args = value.get('args', []) + kwds = value.get('kwds', {}) + state = value.get('state', {}) + listitems = value.get('listitems', []) + dictitems = value.get('dictitems', {}) + instance = self.make_python_instance(suffix, node, args, kwds, newobj) + if state: + self.set_python_instance_state(instance, state) + if listitems: + instance.extend(listitems) + if dictitems: + for key in dictitems: + instance[key] = dictitems[key] + return instance + + def construct_python_object_new(self, suffix, node): + return self.construct_python_object_apply(suffix, node, newobj=True) + +Constructor.add_constructor( + 'tag:yaml.org,2002:python/none', + Constructor.construct_yaml_null) + +Constructor.add_constructor( + 'tag:yaml.org,2002:python/bool', + Constructor.construct_yaml_bool) + +Constructor.add_constructor( + 'tag:yaml.org,2002:python/str', + Constructor.construct_python_str) + +Constructor.add_constructor( + 'tag:yaml.org,2002:python/unicode', + Constructor.construct_python_unicode) + +Constructor.add_constructor( + 'tag:yaml.org,2002:python/bytes', + Constructor.construct_python_bytes) + +Constructor.add_constructor( + 'tag:yaml.org,2002:python/int', + Constructor.construct_yaml_int) + +Constructor.add_constructor( + 'tag:yaml.org,2002:python/long', + Constructor.construct_python_long) + +Constructor.add_constructor( + 'tag:yaml.org,2002:python/float', + Constructor.construct_yaml_float) + +Constructor.add_constructor( + 'tag:yaml.org,2002:python/complex', + Constructor.construct_python_complex) + +Constructor.add_constructor( + 'tag:yaml.org,2002:python/list', + Constructor.construct_yaml_seq) + +Constructor.add_constructor( + 'tag:yaml.org,2002:python/tuple', + Constructor.construct_python_tuple) + +Constructor.add_constructor( + 'tag:yaml.org,2002:python/dict', + Constructor.construct_yaml_map) + +Constructor.add_multi_constructor( + 'tag:yaml.org,2002:python/name:', + Constructor.construct_python_name) + +Constructor.add_multi_constructor( + 'tag:yaml.org,2002:python/module:', + Constructor.construct_python_module) + +Constructor.add_multi_constructor( + 'tag:yaml.org,2002:python/object:', + Constructor.construct_python_object) + +Constructor.add_multi_constructor( + 'tag:yaml.org,2002:python/object/apply:', + Constructor.construct_python_object_apply) + +Constructor.add_multi_constructor( + 'tag:yaml.org,2002:python/object/new:', + Constructor.construct_python_object_new) + diff --git a/software/tools/pymcuprog/libs/yaml/cyaml.py b/software/tools/pymcuprog/libs/yaml/cyaml.py new file mode 100644 index 0000000..d5cb87e --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/cyaml.py @@ -0,0 +1,85 @@ + +__all__ = ['CBaseLoader', 'CSafeLoader', 'CLoader', + 'CBaseDumper', 'CSafeDumper', 'CDumper'] + +from _yaml import CParser, CEmitter + +from .constructor import * + +from .serializer import * +from .representer import * + +from .resolver import * + +class CBaseLoader(CParser, BaseConstructor, BaseResolver): + + def __init__(self, stream): + CParser.__init__(self, stream) + BaseConstructor.__init__(self) + BaseResolver.__init__(self) + +class CSafeLoader(CParser, SafeConstructor, Resolver): + + def __init__(self, stream): + CParser.__init__(self, stream) + SafeConstructor.__init__(self) + Resolver.__init__(self) + +class CLoader(CParser, Constructor, Resolver): + + def __init__(self, stream): + CParser.__init__(self, stream) + Constructor.__init__(self) + Resolver.__init__(self) + +class CBaseDumper(CEmitter, BaseRepresenter, BaseResolver): + + def __init__(self, stream, + default_style=None, default_flow_style=None, + canonical=None, indent=None, width=None, + allow_unicode=None, line_break=None, + encoding=None, explicit_start=None, explicit_end=None, + version=None, tags=None): + CEmitter.__init__(self, stream, canonical=canonical, + indent=indent, width=width, encoding=encoding, + allow_unicode=allow_unicode, line_break=line_break, + explicit_start=explicit_start, explicit_end=explicit_end, + version=version, tags=tags) + Representer.__init__(self, default_style=default_style, + default_flow_style=default_flow_style) + Resolver.__init__(self) + +class CSafeDumper(CEmitter, SafeRepresenter, Resolver): + + def __init__(self, stream, + default_style=None, default_flow_style=None, + canonical=None, indent=None, width=None, + allow_unicode=None, line_break=None, + encoding=None, explicit_start=None, explicit_end=None, + version=None, tags=None): + CEmitter.__init__(self, stream, canonical=canonical, + indent=indent, width=width, encoding=encoding, + allow_unicode=allow_unicode, line_break=line_break, + explicit_start=explicit_start, explicit_end=explicit_end, + version=version, tags=tags) + SafeRepresenter.__init__(self, default_style=default_style, + default_flow_style=default_flow_style) + Resolver.__init__(self) + +class CDumper(CEmitter, Serializer, Representer, Resolver): + + def __init__(self, stream, + default_style=None, default_flow_style=None, + canonical=None, indent=None, width=None, + allow_unicode=None, line_break=None, + encoding=None, explicit_start=None, explicit_end=None, + version=None, tags=None): + CEmitter.__init__(self, stream, canonical=canonical, + indent=indent, width=width, encoding=encoding, + allow_unicode=allow_unicode, line_break=line_break, + explicit_start=explicit_start, explicit_end=explicit_end, + version=version, tags=tags) + Representer.__init__(self, default_style=default_style, + default_flow_style=default_flow_style) + Resolver.__init__(self) + diff --git a/software/tools/pymcuprog/libs/yaml/dumper.py b/software/tools/pymcuprog/libs/yaml/dumper.py new file mode 100644 index 0000000..0b69128 --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/dumper.py @@ -0,0 +1,62 @@ + +__all__ = ['BaseDumper', 'SafeDumper', 'Dumper'] + +from .emitter import * +from .serializer import * +from .representer import * +from .resolver import * + +class BaseDumper(Emitter, Serializer, BaseRepresenter, BaseResolver): + + def __init__(self, stream, + default_style=None, default_flow_style=None, + canonical=None, indent=None, width=None, + allow_unicode=None, line_break=None, + encoding=None, explicit_start=None, explicit_end=None, + version=None, tags=None): + Emitter.__init__(self, stream, canonical=canonical, + indent=indent, width=width, + allow_unicode=allow_unicode, line_break=line_break) + Serializer.__init__(self, encoding=encoding, + explicit_start=explicit_start, explicit_end=explicit_end, + version=version, tags=tags) + Representer.__init__(self, default_style=default_style, + default_flow_style=default_flow_style) + Resolver.__init__(self) + +class SafeDumper(Emitter, Serializer, SafeRepresenter, Resolver): + + def __init__(self, stream, + default_style=None, default_flow_style=None, + canonical=None, indent=None, width=None, + allow_unicode=None, line_break=None, + encoding=None, explicit_start=None, explicit_end=None, + version=None, tags=None): + Emitter.__init__(self, stream, canonical=canonical, + indent=indent, width=width, + allow_unicode=allow_unicode, line_break=line_break) + Serializer.__init__(self, encoding=encoding, + explicit_start=explicit_start, explicit_end=explicit_end, + version=version, tags=tags) + SafeRepresenter.__init__(self, default_style=default_style, + default_flow_style=default_flow_style) + Resolver.__init__(self) + +class Dumper(Emitter, Serializer, Representer, Resolver): + + def __init__(self, stream, + default_style=None, default_flow_style=None, + canonical=None, indent=None, width=None, + allow_unicode=None, line_break=None, + encoding=None, explicit_start=None, explicit_end=None, + version=None, tags=None): + Emitter.__init__(self, stream, canonical=canonical, + indent=indent, width=width, + allow_unicode=allow_unicode, line_break=line_break) + Serializer.__init__(self, encoding=encoding, + explicit_start=explicit_start, explicit_end=explicit_end, + version=version, tags=tags) + Representer.__init__(self, default_style=default_style, + default_flow_style=default_flow_style) + Resolver.__init__(self) + diff --git a/software/tools/pymcuprog/libs/yaml/emitter.py b/software/tools/pymcuprog/libs/yaml/emitter.py new file mode 100644 index 0000000..34cb145 --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/emitter.py @@ -0,0 +1,1137 @@ + +# Emitter expects events obeying the following grammar: +# stream ::= STREAM-START document* STREAM-END +# document ::= DOCUMENT-START node DOCUMENT-END +# node ::= SCALAR | sequence | mapping +# sequence ::= SEQUENCE-START node* SEQUENCE-END +# mapping ::= MAPPING-START (node node)* MAPPING-END + +__all__ = ['Emitter', 'EmitterError'] + +from .error import YAMLError +from .events import * + +class EmitterError(YAMLError): + pass + +class ScalarAnalysis: + def __init__(self, scalar, empty, multiline, + allow_flow_plain, allow_block_plain, + allow_single_quoted, allow_double_quoted, + allow_block): + self.scalar = scalar + self.empty = empty + self.multiline = multiline + self.allow_flow_plain = allow_flow_plain + self.allow_block_plain = allow_block_plain + self.allow_single_quoted = allow_single_quoted + self.allow_double_quoted = allow_double_quoted + self.allow_block = allow_block + +class Emitter: + + DEFAULT_TAG_PREFIXES = { + '!' : '!', + 'tag:yaml.org,2002:' : '!!', + } + + def __init__(self, stream, canonical=None, indent=None, width=None, + allow_unicode=None, line_break=None): + + # The stream should have the methods `write` and possibly `flush`. + self.stream = stream + + # Encoding can be overriden by STREAM-START. + self.encoding = None + + # Emitter is a state machine with a stack of states to handle nested + # structures. + self.states = [] + self.state = self.expect_stream_start + + # Current event and the event queue. + self.events = [] + self.event = None + + # The current indentation level and the stack of previous indents. + self.indents = [] + self.indent = None + + # Flow level. + self.flow_level = 0 + + # Contexts. + self.root_context = False + self.sequence_context = False + self.mapping_context = False + self.simple_key_context = False + + # Characteristics of the last emitted character: + # - current position. + # - is it a whitespace? + # - is it an indention character + # (indentation space, '-', '?', or ':')? + self.line = 0 + self.column = 0 + self.whitespace = True + self.indention = True + + # Whether the document requires an explicit document indicator + self.open_ended = False + + # Formatting details. + self.canonical = canonical + self.allow_unicode = allow_unicode + self.best_indent = 2 + if indent and 1 < indent < 10: + self.best_indent = indent + self.best_width = 80 + if width and width > self.best_indent*2: + self.best_width = width + self.best_line_break = '\n' + if line_break in ['\r', '\n', '\r\n']: + self.best_line_break = line_break + + # Tag prefixes. + self.tag_prefixes = None + + # Prepared anchor and tag. + self.prepared_anchor = None + self.prepared_tag = None + + # Scalar analysis and style. + self.analysis = None + self.style = None + + def dispose(self): + # Reset the state attributes (to clear self-references) + self.states = [] + self.state = None + + def emit(self, event): + self.events.append(event) + while not self.need_more_events(): + self.event = self.events.pop(0) + self.state() + self.event = None + + # In some cases, we wait for a few next events before emitting. + + def need_more_events(self): + if not self.events: + return True + event = self.events[0] + if isinstance(event, DocumentStartEvent): + return self.need_events(1) + elif isinstance(event, SequenceStartEvent): + return self.need_events(2) + elif isinstance(event, MappingStartEvent): + return self.need_events(3) + else: + return False + + def need_events(self, count): + level = 0 + for event in self.events[1:]: + if isinstance(event, (DocumentStartEvent, CollectionStartEvent)): + level += 1 + elif isinstance(event, (DocumentEndEvent, CollectionEndEvent)): + level -= 1 + elif isinstance(event, StreamEndEvent): + level = -1 + if level < 0: + return False + return (len(self.events) < count+1) + + def increase_indent(self, flow=False, indentless=False): + self.indents.append(self.indent) + if self.indent is None: + if flow: + self.indent = self.best_indent + else: + self.indent = 0 + elif not indentless: + self.indent += self.best_indent + + # States. + + # Stream handlers. + + def expect_stream_start(self): + if isinstance(self.event, StreamStartEvent): + if self.event.encoding and not hasattr(self.stream, 'encoding'): + self.encoding = self.event.encoding + self.write_stream_start() + self.state = self.expect_first_document_start + else: + raise EmitterError("expected StreamStartEvent, but got %s" + % self.event) + + def expect_nothing(self): + raise EmitterError("expected nothing, but got %s" % self.event) + + # Document handlers. + + def expect_first_document_start(self): + return self.expect_document_start(first=True) + + def expect_document_start(self, first=False): + if isinstance(self.event, DocumentStartEvent): + if (self.event.version or self.event.tags) and self.open_ended: + self.write_indicator('...', True) + self.write_indent() + if self.event.version: + version_text = self.prepare_version(self.event.version) + self.write_version_directive(version_text) + self.tag_prefixes = self.DEFAULT_TAG_PREFIXES.copy() + if self.event.tags: + handles = sorted(self.event.tags.keys()) + for handle in handles: + prefix = self.event.tags[handle] + self.tag_prefixes[prefix] = handle + handle_text = self.prepare_tag_handle(handle) + prefix_text = self.prepare_tag_prefix(prefix) + self.write_tag_directive(handle_text, prefix_text) + implicit = (first and not self.event.explicit and not self.canonical + and not self.event.version and not self.event.tags + and not self.check_empty_document()) + if not implicit: + self.write_indent() + self.write_indicator('---', True) + if self.canonical: + self.write_indent() + self.state = self.expect_document_root + elif isinstance(self.event, StreamEndEvent): + if self.open_ended: + self.write_indicator('...', True) + self.write_indent() + self.write_stream_end() + self.state = self.expect_nothing + else: + raise EmitterError("expected DocumentStartEvent, but got %s" + % self.event) + + def expect_document_end(self): + if isinstance(self.event, DocumentEndEvent): + self.write_indent() + if self.event.explicit: + self.write_indicator('...', True) + self.write_indent() + self.flush_stream() + self.state = self.expect_document_start + else: + raise EmitterError("expected DocumentEndEvent, but got %s" + % self.event) + + def expect_document_root(self): + self.states.append(self.expect_document_end) + self.expect_node(root=True) + + # Node handlers. + + def expect_node(self, root=False, sequence=False, mapping=False, + simple_key=False): + self.root_context = root + self.sequence_context = sequence + self.mapping_context = mapping + self.simple_key_context = simple_key + if isinstance(self.event, AliasEvent): + self.expect_alias() + elif isinstance(self.event, (ScalarEvent, CollectionStartEvent)): + self.process_anchor('&') + self.process_tag() + if isinstance(self.event, ScalarEvent): + self.expect_scalar() + elif isinstance(self.event, SequenceStartEvent): + if self.flow_level or self.canonical or self.event.flow_style \ + or self.check_empty_sequence(): + self.expect_flow_sequence() + else: + self.expect_block_sequence() + elif isinstance(self.event, MappingStartEvent): + if self.flow_level or self.canonical or self.event.flow_style \ + or self.check_empty_mapping(): + self.expect_flow_mapping() + else: + self.expect_block_mapping() + else: + raise EmitterError("expected NodeEvent, but got %s" % self.event) + + def expect_alias(self): + if self.event.anchor is None: + raise EmitterError("anchor is not specified for alias") + self.process_anchor('*') + self.state = self.states.pop() + + def expect_scalar(self): + self.increase_indent(flow=True) + self.process_scalar() + self.indent = self.indents.pop() + self.state = self.states.pop() + + # Flow sequence handlers. + + def expect_flow_sequence(self): + self.write_indicator('[', True, whitespace=True) + self.flow_level += 1 + self.increase_indent(flow=True) + self.state = self.expect_first_flow_sequence_item + + def expect_first_flow_sequence_item(self): + if isinstance(self.event, SequenceEndEvent): + self.indent = self.indents.pop() + self.flow_level -= 1 + self.write_indicator(']', False) + self.state = self.states.pop() + else: + if self.canonical or self.column > self.best_width: + self.write_indent() + self.states.append(self.expect_flow_sequence_item) + self.expect_node(sequence=True) + + def expect_flow_sequence_item(self): + if isinstance(self.event, SequenceEndEvent): + self.indent = self.indents.pop() + self.flow_level -= 1 + if self.canonical: + self.write_indicator(',', False) + self.write_indent() + self.write_indicator(']', False) + self.state = self.states.pop() + else: + self.write_indicator(',', False) + if self.canonical or self.column > self.best_width: + self.write_indent() + self.states.append(self.expect_flow_sequence_item) + self.expect_node(sequence=True) + + # Flow mapping handlers. + + def expect_flow_mapping(self): + self.write_indicator('{', True, whitespace=True) + self.flow_level += 1 + self.increase_indent(flow=True) + self.state = self.expect_first_flow_mapping_key + + def expect_first_flow_mapping_key(self): + if isinstance(self.event, MappingEndEvent): + self.indent = self.indents.pop() + self.flow_level -= 1 + self.write_indicator('}', False) + self.state = self.states.pop() + else: + if self.canonical or self.column > self.best_width: + self.write_indent() + if not self.canonical and self.check_simple_key(): + self.states.append(self.expect_flow_mapping_simple_value) + self.expect_node(mapping=True, simple_key=True) + else: + self.write_indicator('?', True) + self.states.append(self.expect_flow_mapping_value) + self.expect_node(mapping=True) + + def expect_flow_mapping_key(self): + if isinstance(self.event, MappingEndEvent): + self.indent = self.indents.pop() + self.flow_level -= 1 + if self.canonical: + self.write_indicator(',', False) + self.write_indent() + self.write_indicator('}', False) + self.state = self.states.pop() + else: + self.write_indicator(',', False) + if self.canonical or self.column > self.best_width: + self.write_indent() + if not self.canonical and self.check_simple_key(): + self.states.append(self.expect_flow_mapping_simple_value) + self.expect_node(mapping=True, simple_key=True) + else: + self.write_indicator('?', True) + self.states.append(self.expect_flow_mapping_value) + self.expect_node(mapping=True) + + def expect_flow_mapping_simple_value(self): + self.write_indicator(':', False) + self.states.append(self.expect_flow_mapping_key) + self.expect_node(mapping=True) + + def expect_flow_mapping_value(self): + if self.canonical or self.column > self.best_width: + self.write_indent() + self.write_indicator(':', True) + self.states.append(self.expect_flow_mapping_key) + self.expect_node(mapping=True) + + # Block sequence handlers. + + def expect_block_sequence(self): + indentless = (self.mapping_context and not self.indention) + self.increase_indent(flow=False, indentless=indentless) + self.state = self.expect_first_block_sequence_item + + def expect_first_block_sequence_item(self): + return self.expect_block_sequence_item(first=True) + + def expect_block_sequence_item(self, first=False): + if not first and isinstance(self.event, SequenceEndEvent): + self.indent = self.indents.pop() + self.state = self.states.pop() + else: + self.write_indent() + self.write_indicator('-', True, indention=True) + self.states.append(self.expect_block_sequence_item) + self.expect_node(sequence=True) + + # Block mapping handlers. + + def expect_block_mapping(self): + self.increase_indent(flow=False) + self.state = self.expect_first_block_mapping_key + + def expect_first_block_mapping_key(self): + return self.expect_block_mapping_key(first=True) + + def expect_block_mapping_key(self, first=False): + if not first and isinstance(self.event, MappingEndEvent): + self.indent = self.indents.pop() + self.state = self.states.pop() + else: + self.write_indent() + if self.check_simple_key(): + self.states.append(self.expect_block_mapping_simple_value) + self.expect_node(mapping=True, simple_key=True) + else: + self.write_indicator('?', True, indention=True) + self.states.append(self.expect_block_mapping_value) + self.expect_node(mapping=True) + + def expect_block_mapping_simple_value(self): + self.write_indicator(':', False) + self.states.append(self.expect_block_mapping_key) + self.expect_node(mapping=True) + + def expect_block_mapping_value(self): + self.write_indent() + self.write_indicator(':', True, indention=True) + self.states.append(self.expect_block_mapping_key) + self.expect_node(mapping=True) + + # Checkers. + + def check_empty_sequence(self): + return (isinstance(self.event, SequenceStartEvent) and self.events + and isinstance(self.events[0], SequenceEndEvent)) + + def check_empty_mapping(self): + return (isinstance(self.event, MappingStartEvent) and self.events + and isinstance(self.events[0], MappingEndEvent)) + + def check_empty_document(self): + if not isinstance(self.event, DocumentStartEvent) or not self.events: + return False + event = self.events[0] + return (isinstance(event, ScalarEvent) and event.anchor is None + and event.tag is None and event.implicit and event.value == '') + + def check_simple_key(self): + length = 0 + if isinstance(self.event, NodeEvent) and self.event.anchor is not None: + if self.prepared_anchor is None: + self.prepared_anchor = self.prepare_anchor(self.event.anchor) + length += len(self.prepared_anchor) + if isinstance(self.event, (ScalarEvent, CollectionStartEvent)) \ + and self.event.tag is not None: + if self.prepared_tag is None: + self.prepared_tag = self.prepare_tag(self.event.tag) + length += len(self.prepared_tag) + if isinstance(self.event, ScalarEvent): + if self.analysis is None: + self.analysis = self.analyze_scalar(self.event.value) + length += len(self.analysis.scalar) + return (length < 128 and (isinstance(self.event, AliasEvent) + or (isinstance(self.event, ScalarEvent) + and not self.analysis.empty and not self.analysis.multiline) + or self.check_empty_sequence() or self.check_empty_mapping())) + + # Anchor, Tag, and Scalar processors. + + def process_anchor(self, indicator): + if self.event.anchor is None: + self.prepared_anchor = None + return + if self.prepared_anchor is None: + self.prepared_anchor = self.prepare_anchor(self.event.anchor) + if self.prepared_anchor: + self.write_indicator(indicator+self.prepared_anchor, True) + self.prepared_anchor = None + + def process_tag(self): + tag = self.event.tag + if isinstance(self.event, ScalarEvent): + if self.style is None: + self.style = self.choose_scalar_style() + if ((not self.canonical or tag is None) and + ((self.style == '' and self.event.implicit[0]) + or (self.style != '' and self.event.implicit[1]))): + self.prepared_tag = None + return + if self.event.implicit[0] and tag is None: + tag = '!' + self.prepared_tag = None + else: + if (not self.canonical or tag is None) and self.event.implicit: + self.prepared_tag = None + return + if tag is None: + raise EmitterError("tag is not specified") + if self.prepared_tag is None: + self.prepared_tag = self.prepare_tag(tag) + if self.prepared_tag: + self.write_indicator(self.prepared_tag, True) + self.prepared_tag = None + + def choose_scalar_style(self): + if self.analysis is None: + self.analysis = self.analyze_scalar(self.event.value) + if self.event.style == '"' or self.canonical: + return '"' + if not self.event.style and self.event.implicit[0]: + if (not (self.simple_key_context and + (self.analysis.empty or self.analysis.multiline)) + and (self.flow_level and self.analysis.allow_flow_plain + or (not self.flow_level and self.analysis.allow_block_plain))): + return '' + if self.event.style and self.event.style in '|>': + if (not self.flow_level and not self.simple_key_context + and self.analysis.allow_block): + return self.event.style + if not self.event.style or self.event.style == '\'': + if (self.analysis.allow_single_quoted and + not (self.simple_key_context and self.analysis.multiline)): + return '\'' + return '"' + + def process_scalar(self): + if self.analysis is None: + self.analysis = self.analyze_scalar(self.event.value) + if self.style is None: + self.style = self.choose_scalar_style() + split = (not self.simple_key_context) + #if self.analysis.multiline and split \ + # and (not self.style or self.style in '\'\"'): + # self.write_indent() + if self.style == '"': + self.write_double_quoted(self.analysis.scalar, split) + elif self.style == '\'': + self.write_single_quoted(self.analysis.scalar, split) + elif self.style == '>': + self.write_folded(self.analysis.scalar) + elif self.style == '|': + self.write_literal(self.analysis.scalar) + else: + self.write_plain(self.analysis.scalar, split) + self.analysis = None + self.style = None + + # Analyzers. + + def prepare_version(self, version): + major, minor = version + if major != 1: + raise EmitterError("unsupported YAML version: %d.%d" % (major, minor)) + return '%d.%d' % (major, minor) + + def prepare_tag_handle(self, handle): + if not handle: + raise EmitterError("tag handle must not be empty") + if handle[0] != '!' or handle[-1] != '!': + raise EmitterError("tag handle must start and end with '!': %r" % handle) + for ch in handle[1:-1]: + if not ('0' <= ch <= '9' or 'A' <= ch <= 'Z' or 'a' <= ch <= 'z' \ + or ch in '-_'): + raise EmitterError("invalid character %r in the tag handle: %r" + % (ch, handle)) + return handle + + def prepare_tag_prefix(self, prefix): + if not prefix: + raise EmitterError("tag prefix must not be empty") + chunks = [] + start = end = 0 + if prefix[0] == '!': + end = 1 + while end < len(prefix): + ch = prefix[end] + if '0' <= ch <= '9' or 'A' <= ch <= 'Z' or 'a' <= ch <= 'z' \ + or ch in '-;/?!:@&=+$,_.~*\'()[]': + end += 1 + else: + if start < end: + chunks.append(prefix[start:end]) + start = end = end+1 + data = ch.encode('utf-8') + for ch in data: + chunks.append('%%%02X' % ord(ch)) + if start < end: + chunks.append(prefix[start:end]) + return ''.join(chunks) + + def prepare_tag(self, tag): + if not tag: + raise EmitterError("tag must not be empty") + if tag == '!': + return tag + handle = None + suffix = tag + prefixes = sorted(self.tag_prefixes.keys()) + for prefix in prefixes: + if tag.startswith(prefix) \ + and (prefix == '!' or len(prefix) < len(tag)): + handle = self.tag_prefixes[prefix] + suffix = tag[len(prefix):] + chunks = [] + start = end = 0 + while end < len(suffix): + ch = suffix[end] + if '0' <= ch <= '9' or 'A' <= ch <= 'Z' or 'a' <= ch <= 'z' \ + or ch in '-;/?:@&=+$,_.~*\'()[]' \ + or (ch == '!' and handle != '!'): + end += 1 + else: + if start < end: + chunks.append(suffix[start:end]) + start = end = end+1 + data = ch.encode('utf-8') + for ch in data: + chunks.append('%%%02X' % ord(ch)) + if start < end: + chunks.append(suffix[start:end]) + suffix_text = ''.join(chunks) + if handle: + return '%s%s' % (handle, suffix_text) + else: + return '!<%s>' % suffix_text + + def prepare_anchor(self, anchor): + if not anchor: + raise EmitterError("anchor must not be empty") + for ch in anchor: + if not ('0' <= ch <= '9' or 'A' <= ch <= 'Z' or 'a' <= ch <= 'z' \ + or ch in '-_'): + raise EmitterError("invalid character %r in the anchor: %r" + % (ch, anchor)) + return anchor + + def analyze_scalar(self, scalar): + + # Empty scalar is a special case. + if not scalar: + return ScalarAnalysis(scalar=scalar, empty=True, multiline=False, + allow_flow_plain=False, allow_block_plain=True, + allow_single_quoted=True, allow_double_quoted=True, + allow_block=False) + + # Indicators and special characters. + block_indicators = False + flow_indicators = False + line_breaks = False + special_characters = False + + # Important whitespace combinations. + leading_space = False + leading_break = False + trailing_space = False + trailing_break = False + break_space = False + space_break = False + + # Check document indicators. + if scalar.startswith('---') or scalar.startswith('...'): + block_indicators = True + flow_indicators = True + + # First character or preceded by a whitespace. + preceeded_by_whitespace = True + + # Last character or followed by a whitespace. + followed_by_whitespace = (len(scalar) == 1 or + scalar[1] in '\0 \t\r\n\x85\u2028\u2029') + + # The previous character is a space. + previous_space = False + + # The previous character is a break. + previous_break = False + + index = 0 + while index < len(scalar): + ch = scalar[index] + + # Check for indicators. + if index == 0: + # Leading indicators are special characters. + if ch in '#,[]{}&*!|>\'\"%@`': + flow_indicators = True + block_indicators = True + if ch in '?:': + flow_indicators = True + if followed_by_whitespace: + block_indicators = True + if ch == '-' and followed_by_whitespace: + flow_indicators = True + block_indicators = True + else: + # Some indicators cannot appear within a scalar as well. + if ch in ',?[]{}': + flow_indicators = True + if ch == ':': + flow_indicators = True + if followed_by_whitespace: + block_indicators = True + if ch == '#' and preceeded_by_whitespace: + flow_indicators = True + block_indicators = True + + # Check for line breaks, special, and unicode characters. + if ch in '\n\x85\u2028\u2029': + line_breaks = True + if not (ch == '\n' or '\x20' <= ch <= '\x7E'): + if (ch == '\x85' or '\xA0' <= ch <= '\uD7FF' + or '\uE000' <= ch <= '\uFFFD') and ch != '\uFEFF': + unicode_characters = True + if not self.allow_unicode: + special_characters = True + else: + special_characters = True + + # Detect important whitespace combinations. + if ch == ' ': + if index == 0: + leading_space = True + if index == len(scalar)-1: + trailing_space = True + if previous_break: + break_space = True + previous_space = True + previous_break = False + elif ch in '\n\x85\u2028\u2029': + if index == 0: + leading_break = True + if index == len(scalar)-1: + trailing_break = True + if previous_space: + space_break = True + previous_space = False + previous_break = True + else: + previous_space = False + previous_break = False + + # Prepare for the next character. + index += 1 + preceeded_by_whitespace = (ch in '\0 \t\r\n\x85\u2028\u2029') + followed_by_whitespace = (index+1 >= len(scalar) or + scalar[index+1] in '\0 \t\r\n\x85\u2028\u2029') + + # Let's decide what styles are allowed. + allow_flow_plain = True + allow_block_plain = True + allow_single_quoted = True + allow_double_quoted = True + allow_block = True + + # Leading and trailing whitespaces are bad for plain scalars. + if (leading_space or leading_break + or trailing_space or trailing_break): + allow_flow_plain = allow_block_plain = False + + # We do not permit trailing spaces for block scalars. + if trailing_space: + allow_block = False + + # Spaces at the beginning of a new line are only acceptable for block + # scalars. + if break_space: + allow_flow_plain = allow_block_plain = allow_single_quoted = False + + # Spaces followed by breaks, as well as special character are only + # allowed for double quoted scalars. + if space_break or special_characters: + allow_flow_plain = allow_block_plain = \ + allow_single_quoted = allow_block = False + + # Although the plain scalar writer supports breaks, we never emit + # multiline plain scalars. + if line_breaks: + allow_flow_plain = allow_block_plain = False + + # Flow indicators are forbidden for flow plain scalars. + if flow_indicators: + allow_flow_plain = False + + # Block indicators are forbidden for block plain scalars. + if block_indicators: + allow_block_plain = False + + return ScalarAnalysis(scalar=scalar, + empty=False, multiline=line_breaks, + allow_flow_plain=allow_flow_plain, + allow_block_plain=allow_block_plain, + allow_single_quoted=allow_single_quoted, + allow_double_quoted=allow_double_quoted, + allow_block=allow_block) + + # Writers. + + def flush_stream(self): + if hasattr(self.stream, 'flush'): + self.stream.flush() + + def write_stream_start(self): + # Write BOM if needed. + if self.encoding and self.encoding.startswith('utf-16'): + self.stream.write('\uFEFF'.encode(self.encoding)) + + def write_stream_end(self): + self.flush_stream() + + def write_indicator(self, indicator, need_whitespace, + whitespace=False, indention=False): + if self.whitespace or not need_whitespace: + data = indicator + else: + data = ' '+indicator + self.whitespace = whitespace + self.indention = self.indention and indention + self.column += len(data) + self.open_ended = False + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + + def write_indent(self): + indent = self.indent or 0 + if not self.indention or self.column > indent \ + or (self.column == indent and not self.whitespace): + self.write_line_break() + if self.column < indent: + self.whitespace = True + data = ' '*(indent-self.column) + self.column = indent + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + + def write_line_break(self, data=None): + if data is None: + data = self.best_line_break + self.whitespace = True + self.indention = True + self.line += 1 + self.column = 0 + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + + def write_version_directive(self, version_text): + data = '%%YAML %s' % version_text + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + self.write_line_break() + + def write_tag_directive(self, handle_text, prefix_text): + data = '%%TAG %s %s' % (handle_text, prefix_text) + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + self.write_line_break() + + # Scalar streams. + + def write_single_quoted(self, text, split=True): + self.write_indicator('\'', True) + spaces = False + breaks = False + start = end = 0 + while end <= len(text): + ch = None + if end < len(text): + ch = text[end] + if spaces: + if ch is None or ch != ' ': + if start+1 == end and self.column > self.best_width and split \ + and start != 0 and end != len(text): + self.write_indent() + else: + data = text[start:end] + self.column += len(data) + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + start = end + elif breaks: + if ch is None or ch not in '\n\x85\u2028\u2029': + if text[start] == '\n': + self.write_line_break() + for br in text[start:end]: + if br == '\n': + self.write_line_break() + else: + self.write_line_break(br) + self.write_indent() + start = end + else: + if ch is None or ch in ' \n\x85\u2028\u2029' or ch == '\'': + if start < end: + data = text[start:end] + self.column += len(data) + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + start = end + if ch == '\'': + data = '\'\'' + self.column += 2 + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + start = end + 1 + if ch is not None: + spaces = (ch == ' ') + breaks = (ch in '\n\x85\u2028\u2029') + end += 1 + self.write_indicator('\'', False) + + ESCAPE_REPLACEMENTS = { + '\0': '0', + '\x07': 'a', + '\x08': 'b', + '\x09': 't', + '\x0A': 'n', + '\x0B': 'v', + '\x0C': 'f', + '\x0D': 'r', + '\x1B': 'e', + '\"': '\"', + '\\': '\\', + '\x85': 'N', + '\xA0': '_', + '\u2028': 'L', + '\u2029': 'P', + } + + def write_double_quoted(self, text, split=True): + self.write_indicator('"', True) + start = end = 0 + while end <= len(text): + ch = None + if end < len(text): + ch = text[end] + if ch is None or ch in '"\\\x85\u2028\u2029\uFEFF' \ + or not ('\x20' <= ch <= '\x7E' + or (self.allow_unicode + and ('\xA0' <= ch <= '\uD7FF' + or '\uE000' <= ch <= '\uFFFD'))): + if start < end: + data = text[start:end] + self.column += len(data) + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + start = end + if ch is not None: + if ch in self.ESCAPE_REPLACEMENTS: + data = '\\'+self.ESCAPE_REPLACEMENTS[ch] + elif ch <= '\xFF': + data = '\\x%02X' % ord(ch) + elif ch <= '\uFFFF': + data = '\\u%04X' % ord(ch) + else: + data = '\\U%08X' % ord(ch) + self.column += len(data) + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + start = end+1 + if 0 < end < len(text)-1 and (ch == ' ' or start >= end) \ + and self.column+(end-start) > self.best_width and split: + data = text[start:end]+'\\' + if start < end: + start = end + self.column += len(data) + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + self.write_indent() + self.whitespace = False + self.indention = False + if text[start] == ' ': + data = '\\' + self.column += len(data) + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + end += 1 + self.write_indicator('"', False) + + def determine_block_hints(self, text): + hints = '' + if text: + if text[0] in ' \n\x85\u2028\u2029': + hints += str(self.best_indent) + if text[-1] not in '\n\x85\u2028\u2029': + hints += '-' + elif len(text) == 1 or text[-2] in '\n\x85\u2028\u2029': + hints += '+' + return hints + + def write_folded(self, text): + hints = self.determine_block_hints(text) + self.write_indicator('>'+hints, True) + if hints[-1:] == '+': + self.open_ended = True + self.write_line_break() + leading_space = True + spaces = False + breaks = True + start = end = 0 + while end <= len(text): + ch = None + if end < len(text): + ch = text[end] + if breaks: + if ch is None or ch not in '\n\x85\u2028\u2029': + if not leading_space and ch is not None and ch != ' ' \ + and text[start] == '\n': + self.write_line_break() + leading_space = (ch == ' ') + for br in text[start:end]: + if br == '\n': + self.write_line_break() + else: + self.write_line_break(br) + if ch is not None: + self.write_indent() + start = end + elif spaces: + if ch != ' ': + if start+1 == end and self.column > self.best_width: + self.write_indent() + else: + data = text[start:end] + self.column += len(data) + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + start = end + else: + if ch is None or ch in ' \n\x85\u2028\u2029': + data = text[start:end] + self.column += len(data) + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + if ch is None: + self.write_line_break() + start = end + if ch is not None: + breaks = (ch in '\n\x85\u2028\u2029') + spaces = (ch == ' ') + end += 1 + + def write_literal(self, text): + hints = self.determine_block_hints(text) + self.write_indicator('|'+hints, True) + if hints[-1:] == '+': + self.open_ended = True + self.write_line_break() + breaks = True + start = end = 0 + while end <= len(text): + ch = None + if end < len(text): + ch = text[end] + if breaks: + if ch is None or ch not in '\n\x85\u2028\u2029': + for br in text[start:end]: + if br == '\n': + self.write_line_break() + else: + self.write_line_break(br) + if ch is not None: + self.write_indent() + start = end + else: + if ch is None or ch in '\n\x85\u2028\u2029': + data = text[start:end] + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + if ch is None: + self.write_line_break() + start = end + if ch is not None: + breaks = (ch in '\n\x85\u2028\u2029') + end += 1 + + def write_plain(self, text, split=True): + if self.root_context: + self.open_ended = True + if not text: + return + if not self.whitespace: + data = ' ' + self.column += len(data) + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + self.whitespace = False + self.indention = False + spaces = False + breaks = False + start = end = 0 + while end <= len(text): + ch = None + if end < len(text): + ch = text[end] + if spaces: + if ch != ' ': + if start+1 == end and self.column > self.best_width and split: + self.write_indent() + self.whitespace = False + self.indention = False + else: + data = text[start:end] + self.column += len(data) + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + start = end + elif breaks: + if ch not in '\n\x85\u2028\u2029': + if text[start] == '\n': + self.write_line_break() + for br in text[start:end]: + if br == '\n': + self.write_line_break() + else: + self.write_line_break(br) + self.write_indent() + self.whitespace = False + self.indention = False + start = end + else: + if ch is None or ch in ' \n\x85\u2028\u2029': + data = text[start:end] + self.column += len(data) + if self.encoding: + data = data.encode(self.encoding) + self.stream.write(data) + start = end + if ch is not None: + spaces = (ch == ' ') + breaks = (ch in '\n\x85\u2028\u2029') + end += 1 + diff --git a/software/tools/pymcuprog/libs/yaml/error.py b/software/tools/pymcuprog/libs/yaml/error.py new file mode 100644 index 0000000..b796b4d --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/error.py @@ -0,0 +1,75 @@ + +__all__ = ['Mark', 'YAMLError', 'MarkedYAMLError'] + +class Mark: + + def __init__(self, name, index, line, column, buffer, pointer): + self.name = name + self.index = index + self.line = line + self.column = column + self.buffer = buffer + self.pointer = pointer + + def get_snippet(self, indent=4, max_length=75): + if self.buffer is None: + return None + head = '' + start = self.pointer + while start > 0 and self.buffer[start-1] not in '\0\r\n\x85\u2028\u2029': + start -= 1 + if self.pointer-start > max_length/2-1: + head = ' ... ' + start += 5 + break + tail = '' + end = self.pointer + while end < len(self.buffer) and self.buffer[end] not in '\0\r\n\x85\u2028\u2029': + end += 1 + if end-self.pointer > max_length/2-1: + tail = ' ... ' + end -= 5 + break + snippet = self.buffer[start:end] + return ' '*indent + head + snippet + tail + '\n' \ + + ' '*(indent+self.pointer-start+len(head)) + '^' + + def __str__(self): + snippet = self.get_snippet() + where = " in \"%s\", line %d, column %d" \ + % (self.name, self.line+1, self.column+1) + if snippet is not None: + where += ":\n"+snippet + return where + +class YAMLError(Exception): + pass + +class MarkedYAMLError(YAMLError): + + def __init__(self, context=None, context_mark=None, + problem=None, problem_mark=None, note=None): + self.context = context + self.context_mark = context_mark + self.problem = problem + self.problem_mark = problem_mark + self.note = note + + def __str__(self): + lines = [] + if self.context is not None: + lines.append(self.context) + if self.context_mark is not None \ + and (self.problem is None or self.problem_mark is None + or self.context_mark.name != self.problem_mark.name + or self.context_mark.line != self.problem_mark.line + or self.context_mark.column != self.problem_mark.column): + lines.append(str(self.context_mark)) + if self.problem is not None: + lines.append(self.problem) + if self.problem_mark is not None: + lines.append(str(self.problem_mark)) + if self.note is not None: + lines.append(self.note) + return '\n'.join(lines) + diff --git a/software/tools/pymcuprog/libs/yaml/events.py b/software/tools/pymcuprog/libs/yaml/events.py new file mode 100644 index 0000000..f79ad38 --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/events.py @@ -0,0 +1,86 @@ + +# Abstract classes. + +class Event(object): + def __init__(self, start_mark=None, end_mark=None): + self.start_mark = start_mark + self.end_mark = end_mark + def __repr__(self): + attributes = [key for key in ['anchor', 'tag', 'implicit', 'value'] + if hasattr(self, key)] + arguments = ', '.join(['%s=%r' % (key, getattr(self, key)) + for key in attributes]) + return '%s(%s)' % (self.__class__.__name__, arguments) + +class NodeEvent(Event): + def __init__(self, anchor, start_mark=None, end_mark=None): + self.anchor = anchor + self.start_mark = start_mark + self.end_mark = end_mark + +class CollectionStartEvent(NodeEvent): + def __init__(self, anchor, tag, implicit, start_mark=None, end_mark=None, + flow_style=None): + self.anchor = anchor + self.tag = tag + self.implicit = implicit + self.start_mark = start_mark + self.end_mark = end_mark + self.flow_style = flow_style + +class CollectionEndEvent(Event): + pass + +# Implementations. + +class StreamStartEvent(Event): + def __init__(self, start_mark=None, end_mark=None, encoding=None): + self.start_mark = start_mark + self.end_mark = end_mark + self.encoding = encoding + +class StreamEndEvent(Event): + pass + +class DocumentStartEvent(Event): + def __init__(self, start_mark=None, end_mark=None, + explicit=None, version=None, tags=None): + self.start_mark = start_mark + self.end_mark = end_mark + self.explicit = explicit + self.version = version + self.tags = tags + +class DocumentEndEvent(Event): + def __init__(self, start_mark=None, end_mark=None, + explicit=None): + self.start_mark = start_mark + self.end_mark = end_mark + self.explicit = explicit + +class AliasEvent(NodeEvent): + pass + +class ScalarEvent(NodeEvent): + def __init__(self, anchor, tag, implicit, value, + start_mark=None, end_mark=None, style=None): + self.anchor = anchor + self.tag = tag + self.implicit = implicit + self.value = value + self.start_mark = start_mark + self.end_mark = end_mark + self.style = style + +class SequenceStartEvent(CollectionStartEvent): + pass + +class SequenceEndEvent(CollectionEndEvent): + pass + +class MappingStartEvent(CollectionStartEvent): + pass + +class MappingEndEvent(CollectionEndEvent): + pass + diff --git a/software/tools/pymcuprog/libs/yaml/loader.py b/software/tools/pymcuprog/libs/yaml/loader.py new file mode 100644 index 0000000..08c8f01 --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/loader.py @@ -0,0 +1,40 @@ + +__all__ = ['BaseLoader', 'SafeLoader', 'Loader'] + +from .reader import * +from .scanner import * +from .parser import * +from .composer import * +from .constructor import * +from .resolver import * + +class BaseLoader(Reader, Scanner, Parser, Composer, BaseConstructor, BaseResolver): + + def __init__(self, stream): + Reader.__init__(self, stream) + Scanner.__init__(self) + Parser.__init__(self) + Composer.__init__(self) + BaseConstructor.__init__(self) + BaseResolver.__init__(self) + +class SafeLoader(Reader, Scanner, Parser, Composer, SafeConstructor, Resolver): + + def __init__(self, stream): + Reader.__init__(self, stream) + Scanner.__init__(self) + Parser.__init__(self) + Composer.__init__(self) + SafeConstructor.__init__(self) + Resolver.__init__(self) + +class Loader(Reader, Scanner, Parser, Composer, Constructor, Resolver): + + def __init__(self, stream): + Reader.__init__(self, stream) + Scanner.__init__(self) + Parser.__init__(self) + Composer.__init__(self) + Constructor.__init__(self) + Resolver.__init__(self) + diff --git a/software/tools/pymcuprog/libs/yaml/nodes.py b/software/tools/pymcuprog/libs/yaml/nodes.py new file mode 100644 index 0000000..c4f070c --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/nodes.py @@ -0,0 +1,49 @@ + +class Node(object): + def __init__(self, tag, value, start_mark, end_mark): + self.tag = tag + self.value = value + self.start_mark = start_mark + self.end_mark = end_mark + def __repr__(self): + value = self.value + #if isinstance(value, list): + # if len(value) == 0: + # value = '' + # elif len(value) == 1: + # value = '<1 item>' + # else: + # value = '<%d items>' % len(value) + #else: + # if len(value) > 75: + # value = repr(value[:70]+u' ... ') + # else: + # value = repr(value) + value = repr(value) + return '%s(tag=%r, value=%s)' % (self.__class__.__name__, self.tag, value) + +class ScalarNode(Node): + id = 'scalar' + def __init__(self, tag, value, + start_mark=None, end_mark=None, style=None): + self.tag = tag + self.value = value + self.start_mark = start_mark + self.end_mark = end_mark + self.style = style + +class CollectionNode(Node): + def __init__(self, tag, value, + start_mark=None, end_mark=None, flow_style=None): + self.tag = tag + self.value = value + self.start_mark = start_mark + self.end_mark = end_mark + self.flow_style = flow_style + +class SequenceNode(CollectionNode): + id = 'sequence' + +class MappingNode(CollectionNode): + id = 'mapping' + diff --git a/software/tools/pymcuprog/libs/yaml/parser.py b/software/tools/pymcuprog/libs/yaml/parser.py new file mode 100644 index 0000000..13a5995 --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/parser.py @@ -0,0 +1,589 @@ + +# The following YAML grammar is LL(1) and is parsed by a recursive descent +# parser. +# +# stream ::= STREAM-START implicit_document? explicit_document* STREAM-END +# implicit_document ::= block_node DOCUMENT-END* +# explicit_document ::= DIRECTIVE* DOCUMENT-START block_node? DOCUMENT-END* +# block_node_or_indentless_sequence ::= +# ALIAS +# | properties (block_content | indentless_block_sequence)? +# | block_content +# | indentless_block_sequence +# block_node ::= ALIAS +# | properties block_content? +# | block_content +# flow_node ::= ALIAS +# | properties flow_content? +# | flow_content +# properties ::= TAG ANCHOR? | ANCHOR TAG? +# block_content ::= block_collection | flow_collection | SCALAR +# flow_content ::= flow_collection | SCALAR +# block_collection ::= block_sequence | block_mapping +# flow_collection ::= flow_sequence | flow_mapping +# block_sequence ::= BLOCK-SEQUENCE-START (BLOCK-ENTRY block_node?)* BLOCK-END +# indentless_sequence ::= (BLOCK-ENTRY block_node?)+ +# block_mapping ::= BLOCK-MAPPING_START +# ((KEY block_node_or_indentless_sequence?)? +# (VALUE block_node_or_indentless_sequence?)?)* +# BLOCK-END +# flow_sequence ::= FLOW-SEQUENCE-START +# (flow_sequence_entry FLOW-ENTRY)* +# flow_sequence_entry? +# FLOW-SEQUENCE-END +# flow_sequence_entry ::= flow_node | KEY flow_node? (VALUE flow_node?)? +# flow_mapping ::= FLOW-MAPPING-START +# (flow_mapping_entry FLOW-ENTRY)* +# flow_mapping_entry? +# FLOW-MAPPING-END +# flow_mapping_entry ::= flow_node | KEY flow_node? (VALUE flow_node?)? +# +# FIRST sets: +# +# stream: { STREAM-START } +# explicit_document: { DIRECTIVE DOCUMENT-START } +# implicit_document: FIRST(block_node) +# block_node: { ALIAS TAG ANCHOR SCALAR BLOCK-SEQUENCE-START BLOCK-MAPPING-START FLOW-SEQUENCE-START FLOW-MAPPING-START } +# flow_node: { ALIAS ANCHOR TAG SCALAR FLOW-SEQUENCE-START FLOW-MAPPING-START } +# block_content: { BLOCK-SEQUENCE-START BLOCK-MAPPING-START FLOW-SEQUENCE-START FLOW-MAPPING-START SCALAR } +# flow_content: { FLOW-SEQUENCE-START FLOW-MAPPING-START SCALAR } +# block_collection: { BLOCK-SEQUENCE-START BLOCK-MAPPING-START } +# flow_collection: { FLOW-SEQUENCE-START FLOW-MAPPING-START } +# block_sequence: { BLOCK-SEQUENCE-START } +# block_mapping: { BLOCK-MAPPING-START } +# block_node_or_indentless_sequence: { ALIAS ANCHOR TAG SCALAR BLOCK-SEQUENCE-START BLOCK-MAPPING-START FLOW-SEQUENCE-START FLOW-MAPPING-START BLOCK-ENTRY } +# indentless_sequence: { ENTRY } +# flow_collection: { FLOW-SEQUENCE-START FLOW-MAPPING-START } +# flow_sequence: { FLOW-SEQUENCE-START } +# flow_mapping: { FLOW-MAPPING-START } +# flow_sequence_entry: { ALIAS ANCHOR TAG SCALAR FLOW-SEQUENCE-START FLOW-MAPPING-START KEY } +# flow_mapping_entry: { ALIAS ANCHOR TAG SCALAR FLOW-SEQUENCE-START FLOW-MAPPING-START KEY } + +__all__ = ['Parser', 'ParserError'] + +from .error import MarkedYAMLError +from .tokens import * +from .events import * +from .scanner import * + +class ParserError(MarkedYAMLError): + pass + +class Parser: + # Since writing a recursive-descendant parser is a straightforward task, we + # do not give many comments here. + + DEFAULT_TAGS = { + '!': '!', + '!!': 'tag:yaml.org,2002:', + } + + def __init__(self): + self.current_event = None + self.yaml_version = None + self.tag_handles = {} + self.states = [] + self.marks = [] + self.state = self.parse_stream_start + + def dispose(self): + # Reset the state attributes (to clear self-references) + self.states = [] + self.state = None + + def check_event(self, *choices): + # Check the type of the next event. + if self.current_event is None: + if self.state: + self.current_event = self.state() + if self.current_event is not None: + if not choices: + return True + for choice in choices: + if isinstance(self.current_event, choice): + return True + return False + + def peek_event(self): + # Get the next event. + if self.current_event is None: + if self.state: + self.current_event = self.state() + return self.current_event + + def get_event(self): + # Get the next event and proceed further. + if self.current_event is None: + if self.state: + self.current_event = self.state() + value = self.current_event + self.current_event = None + return value + + # stream ::= STREAM-START implicit_document? explicit_document* STREAM-END + # implicit_document ::= block_node DOCUMENT-END* + # explicit_document ::= DIRECTIVE* DOCUMENT-START block_node? DOCUMENT-END* + + def parse_stream_start(self): + + # Parse the stream start. + token = self.get_token() + event = StreamStartEvent(token.start_mark, token.end_mark, + encoding=token.encoding) + + # Prepare the next state. + self.state = self.parse_implicit_document_start + + return event + + def parse_implicit_document_start(self): + + # Parse an implicit document. + if not self.check_token(DirectiveToken, DocumentStartToken, + StreamEndToken): + self.tag_handles = self.DEFAULT_TAGS + token = self.peek_token() + start_mark = end_mark = token.start_mark + event = DocumentStartEvent(start_mark, end_mark, + explicit=False) + + # Prepare the next state. + self.states.append(self.parse_document_end) + self.state = self.parse_block_node + + return event + + else: + return self.parse_document_start() + + def parse_document_start(self): + + # Parse any extra document end indicators. + while self.check_token(DocumentEndToken): + self.get_token() + + # Parse an explicit document. + if not self.check_token(StreamEndToken): + token = self.peek_token() + start_mark = token.start_mark + version, tags = self.process_directives() + if not self.check_token(DocumentStartToken): + raise ParserError(None, None, + "expected '', but found %r" + % self.peek_token().id, + self.peek_token().start_mark) + token = self.get_token() + end_mark = token.end_mark + event = DocumentStartEvent(start_mark, end_mark, + explicit=True, version=version, tags=tags) + self.states.append(self.parse_document_end) + self.state = self.parse_document_content + else: + # Parse the end of the stream. + token = self.get_token() + event = StreamEndEvent(token.start_mark, token.end_mark) + assert not self.states + assert not self.marks + self.state = None + return event + + def parse_document_end(self): + + # Parse the document end. + token = self.peek_token() + start_mark = end_mark = token.start_mark + explicit = False + if self.check_token(DocumentEndToken): + token = self.get_token() + end_mark = token.end_mark + explicit = True + event = DocumentEndEvent(start_mark, end_mark, + explicit=explicit) + + # Prepare the next state. + self.state = self.parse_document_start + + return event + + def parse_document_content(self): + if self.check_token(DirectiveToken, + DocumentStartToken, DocumentEndToken, StreamEndToken): + event = self.process_empty_scalar(self.peek_token().start_mark) + self.state = self.states.pop() + return event + else: + return self.parse_block_node() + + def process_directives(self): + self.yaml_version = None + self.tag_handles = {} + while self.check_token(DirectiveToken): + token = self.get_token() + if token.name == 'YAML': + if self.yaml_version is not None: + raise ParserError(None, None, + "found duplicate YAML directive", token.start_mark) + major, minor = token.value + if major != 1: + raise ParserError(None, None, + "found incompatible YAML document (version 1.* is required)", + token.start_mark) + self.yaml_version = token.value + elif token.name == 'TAG': + handle, prefix = token.value + if handle in self.tag_handles: + raise ParserError(None, None, + "duplicate tag handle %r" % handle, + token.start_mark) + self.tag_handles[handle] = prefix + if self.tag_handles: + value = self.yaml_version, self.tag_handles.copy() + else: + value = self.yaml_version, None + for key in self.DEFAULT_TAGS: + if key not in self.tag_handles: + self.tag_handles[key] = self.DEFAULT_TAGS[key] + return value + + # block_node_or_indentless_sequence ::= ALIAS + # | properties (block_content | indentless_block_sequence)? + # | block_content + # | indentless_block_sequence + # block_node ::= ALIAS + # | properties block_content? + # | block_content + # flow_node ::= ALIAS + # | properties flow_content? + # | flow_content + # properties ::= TAG ANCHOR? | ANCHOR TAG? + # block_content ::= block_collection | flow_collection | SCALAR + # flow_content ::= flow_collection | SCALAR + # block_collection ::= block_sequence | block_mapping + # flow_collection ::= flow_sequence | flow_mapping + + def parse_block_node(self): + return self.parse_node(block=True) + + def parse_flow_node(self): + return self.parse_node() + + def parse_block_node_or_indentless_sequence(self): + return self.parse_node(block=True, indentless_sequence=True) + + def parse_node(self, block=False, indentless_sequence=False): + if self.check_token(AliasToken): + token = self.get_token() + event = AliasEvent(token.value, token.start_mark, token.end_mark) + self.state = self.states.pop() + else: + anchor = None + tag = None + start_mark = end_mark = tag_mark = None + if self.check_token(AnchorToken): + token = self.get_token() + start_mark = token.start_mark + end_mark = token.end_mark + anchor = token.value + if self.check_token(TagToken): + token = self.get_token() + tag_mark = token.start_mark + end_mark = token.end_mark + tag = token.value + elif self.check_token(TagToken): + token = self.get_token() + start_mark = tag_mark = token.start_mark + end_mark = token.end_mark + tag = token.value + if self.check_token(AnchorToken): + token = self.get_token() + end_mark = token.end_mark + anchor = token.value + if tag is not None: + handle, suffix = tag + if handle is not None: + if handle not in self.tag_handles: + raise ParserError("while parsing a node", start_mark, + "found undefined tag handle %r" % handle, + tag_mark) + tag = self.tag_handles[handle]+suffix + else: + tag = suffix + #if tag == '!': + # raise ParserError("while parsing a node", start_mark, + # "found non-specific tag '!'", tag_mark, + # "Please check 'http://pyyaml.org/wiki/YAMLNonSpecificTag' and share your opinion.") + if start_mark is None: + start_mark = end_mark = self.peek_token().start_mark + event = None + implicit = (tag is None or tag == '!') + if indentless_sequence and self.check_token(BlockEntryToken): + end_mark = self.peek_token().end_mark + event = SequenceStartEvent(anchor, tag, implicit, + start_mark, end_mark) + self.state = self.parse_indentless_sequence_entry + else: + if self.check_token(ScalarToken): + token = self.get_token() + end_mark = token.end_mark + if (token.plain and tag is None) or tag == '!': + implicit = (True, False) + elif tag is None: + implicit = (False, True) + else: + implicit = (False, False) + event = ScalarEvent(anchor, tag, implicit, token.value, + start_mark, end_mark, style=token.style) + self.state = self.states.pop() + elif self.check_token(FlowSequenceStartToken): + end_mark = self.peek_token().end_mark + event = SequenceStartEvent(anchor, tag, implicit, + start_mark, end_mark, flow_style=True) + self.state = self.parse_flow_sequence_first_entry + elif self.check_token(FlowMappingStartToken): + end_mark = self.peek_token().end_mark + event = MappingStartEvent(anchor, tag, implicit, + start_mark, end_mark, flow_style=True) + self.state = self.parse_flow_mapping_first_key + elif block and self.check_token(BlockSequenceStartToken): + end_mark = self.peek_token().start_mark + event = SequenceStartEvent(anchor, tag, implicit, + start_mark, end_mark, flow_style=False) + self.state = self.parse_block_sequence_first_entry + elif block and self.check_token(BlockMappingStartToken): + end_mark = self.peek_token().start_mark + event = MappingStartEvent(anchor, tag, implicit, + start_mark, end_mark, flow_style=False) + self.state = self.parse_block_mapping_first_key + elif anchor is not None or tag is not None: + # Empty scalars are allowed even if a tag or an anchor is + # specified. + event = ScalarEvent(anchor, tag, (implicit, False), '', + start_mark, end_mark) + self.state = self.states.pop() + else: + if block: + node = 'block' + else: + node = 'flow' + token = self.peek_token() + raise ParserError("while parsing a %s node" % node, start_mark, + "expected the node content, but found %r" % token.id, + token.start_mark) + return event + + # block_sequence ::= BLOCK-SEQUENCE-START (BLOCK-ENTRY block_node?)* BLOCK-END + + def parse_block_sequence_first_entry(self): + token = self.get_token() + self.marks.append(token.start_mark) + return self.parse_block_sequence_entry() + + def parse_block_sequence_entry(self): + if self.check_token(BlockEntryToken): + token = self.get_token() + if not self.check_token(BlockEntryToken, BlockEndToken): + self.states.append(self.parse_block_sequence_entry) + return self.parse_block_node() + else: + self.state = self.parse_block_sequence_entry + return self.process_empty_scalar(token.end_mark) + if not self.check_token(BlockEndToken): + token = self.peek_token() + raise ParserError("while parsing a block collection", self.marks[-1], + "expected , but found %r" % token.id, token.start_mark) + token = self.get_token() + event = SequenceEndEvent(token.start_mark, token.end_mark) + self.state = self.states.pop() + self.marks.pop() + return event + + # indentless_sequence ::= (BLOCK-ENTRY block_node?)+ + + def parse_indentless_sequence_entry(self): + if self.check_token(BlockEntryToken): + token = self.get_token() + if not self.check_token(BlockEntryToken, + KeyToken, ValueToken, BlockEndToken): + self.states.append(self.parse_indentless_sequence_entry) + return self.parse_block_node() + else: + self.state = self.parse_indentless_sequence_entry + return self.process_empty_scalar(token.end_mark) + token = self.peek_token() + event = SequenceEndEvent(token.start_mark, token.start_mark) + self.state = self.states.pop() + return event + + # block_mapping ::= BLOCK-MAPPING_START + # ((KEY block_node_or_indentless_sequence?)? + # (VALUE block_node_or_indentless_sequence?)?)* + # BLOCK-END + + def parse_block_mapping_first_key(self): + token = self.get_token() + self.marks.append(token.start_mark) + return self.parse_block_mapping_key() + + def parse_block_mapping_key(self): + if self.check_token(KeyToken): + token = self.get_token() + if not self.check_token(KeyToken, ValueToken, BlockEndToken): + self.states.append(self.parse_block_mapping_value) + return self.parse_block_node_or_indentless_sequence() + else: + self.state = self.parse_block_mapping_value + return self.process_empty_scalar(token.end_mark) + if not self.check_token(BlockEndToken): + token = self.peek_token() + raise ParserError("while parsing a block mapping", self.marks[-1], + "expected , but found %r" % token.id, token.start_mark) + token = self.get_token() + event = MappingEndEvent(token.start_mark, token.end_mark) + self.state = self.states.pop() + self.marks.pop() + return event + + def parse_block_mapping_value(self): + if self.check_token(ValueToken): + token = self.get_token() + if not self.check_token(KeyToken, ValueToken, BlockEndToken): + self.states.append(self.parse_block_mapping_key) + return self.parse_block_node_or_indentless_sequence() + else: + self.state = self.parse_block_mapping_key + return self.process_empty_scalar(token.end_mark) + else: + self.state = self.parse_block_mapping_key + token = self.peek_token() + return self.process_empty_scalar(token.start_mark) + + # flow_sequence ::= FLOW-SEQUENCE-START + # (flow_sequence_entry FLOW-ENTRY)* + # flow_sequence_entry? + # FLOW-SEQUENCE-END + # flow_sequence_entry ::= flow_node | KEY flow_node? (VALUE flow_node?)? + # + # Note that while production rules for both flow_sequence_entry and + # flow_mapping_entry are equal, their interpretations are different. + # For `flow_sequence_entry`, the part `KEY flow_node? (VALUE flow_node?)?` + # generate an inline mapping (set syntax). + + def parse_flow_sequence_first_entry(self): + token = self.get_token() + self.marks.append(token.start_mark) + return self.parse_flow_sequence_entry(first=True) + + def parse_flow_sequence_entry(self, first=False): + if not self.check_token(FlowSequenceEndToken): + if not first: + if self.check_token(FlowEntryToken): + self.get_token() + else: + token = self.peek_token() + raise ParserError("while parsing a flow sequence", self.marks[-1], + "expected ',' or ']', but got %r" % token.id, token.start_mark) + + if self.check_token(KeyToken): + token = self.peek_token() + event = MappingStartEvent(None, None, True, + token.start_mark, token.end_mark, + flow_style=True) + self.state = self.parse_flow_sequence_entry_mapping_key + return event + elif not self.check_token(FlowSequenceEndToken): + self.states.append(self.parse_flow_sequence_entry) + return self.parse_flow_node() + token = self.get_token() + event = SequenceEndEvent(token.start_mark, token.end_mark) + self.state = self.states.pop() + self.marks.pop() + return event + + def parse_flow_sequence_entry_mapping_key(self): + token = self.get_token() + if not self.check_token(ValueToken, + FlowEntryToken, FlowSequenceEndToken): + self.states.append(self.parse_flow_sequence_entry_mapping_value) + return self.parse_flow_node() + else: + self.state = self.parse_flow_sequence_entry_mapping_value + return self.process_empty_scalar(token.end_mark) + + def parse_flow_sequence_entry_mapping_value(self): + if self.check_token(ValueToken): + token = self.get_token() + if not self.check_token(FlowEntryToken, FlowSequenceEndToken): + self.states.append(self.parse_flow_sequence_entry_mapping_end) + return self.parse_flow_node() + else: + self.state = self.parse_flow_sequence_entry_mapping_end + return self.process_empty_scalar(token.end_mark) + else: + self.state = self.parse_flow_sequence_entry_mapping_end + token = self.peek_token() + return self.process_empty_scalar(token.start_mark) + + def parse_flow_sequence_entry_mapping_end(self): + self.state = self.parse_flow_sequence_entry + token = self.peek_token() + return MappingEndEvent(token.start_mark, token.start_mark) + + # flow_mapping ::= FLOW-MAPPING-START + # (flow_mapping_entry FLOW-ENTRY)* + # flow_mapping_entry? + # FLOW-MAPPING-END + # flow_mapping_entry ::= flow_node | KEY flow_node? (VALUE flow_node?)? + + def parse_flow_mapping_first_key(self): + token = self.get_token() + self.marks.append(token.start_mark) + return self.parse_flow_mapping_key(first=True) + + def parse_flow_mapping_key(self, first=False): + if not self.check_token(FlowMappingEndToken): + if not first: + if self.check_token(FlowEntryToken): + self.get_token() + else: + token = self.peek_token() + raise ParserError("while parsing a flow mapping", self.marks[-1], + "expected ',' or '}', but got %r" % token.id, token.start_mark) + if self.check_token(KeyToken): + token = self.get_token() + if not self.check_token(ValueToken, + FlowEntryToken, FlowMappingEndToken): + self.states.append(self.parse_flow_mapping_value) + return self.parse_flow_node() + else: + self.state = self.parse_flow_mapping_value + return self.process_empty_scalar(token.end_mark) + elif not self.check_token(FlowMappingEndToken): + self.states.append(self.parse_flow_mapping_empty_value) + return self.parse_flow_node() + token = self.get_token() + event = MappingEndEvent(token.start_mark, token.end_mark) + self.state = self.states.pop() + self.marks.pop() + return event + + def parse_flow_mapping_value(self): + if self.check_token(ValueToken): + token = self.get_token() + if not self.check_token(FlowEntryToken, FlowMappingEndToken): + self.states.append(self.parse_flow_mapping_key) + return self.parse_flow_node() + else: + self.state = self.parse_flow_mapping_key + return self.process_empty_scalar(token.end_mark) + else: + self.state = self.parse_flow_mapping_key + token = self.peek_token() + return self.process_empty_scalar(token.start_mark) + + def parse_flow_mapping_empty_value(self): + self.state = self.parse_flow_mapping_key + return self.process_empty_scalar(self.peek_token().start_mark) + + def process_empty_scalar(self, mark): + return ScalarEvent(None, None, (True, False), '', mark, mark) + diff --git a/software/tools/pymcuprog/libs/yaml/reader.py b/software/tools/pymcuprog/libs/yaml/reader.py new file mode 100644 index 0000000..f70e920 --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/reader.py @@ -0,0 +1,192 @@ +# This module contains abstractions for the input stream. You don't have to +# looks further, there are no pretty code. +# +# We define two classes here. +# +# Mark(source, line, column) +# It's just a record and its only use is producing nice error messages. +# Parser does not use it for any other purposes. +# +# Reader(source, data) +# Reader determines the encoding of `data` and converts it to unicode. +# Reader provides the following methods and attributes: +# reader.peek(length=1) - return the next `length` characters +# reader.forward(length=1) - move the current position to `length` characters. +# reader.index - the number of the current character. +# reader.line, stream.column - the line and the column of the current character. + +__all__ = ['Reader', 'ReaderError'] + +from .error import YAMLError, Mark + +import codecs, re + +class ReaderError(YAMLError): + + def __init__(self, name, position, character, encoding, reason): + self.name = name + self.character = character + self.position = position + self.encoding = encoding + self.reason = reason + + def __str__(self): + if isinstance(self.character, bytes): + return "'%s' codec can't decode byte #x%02x: %s\n" \ + " in \"%s\", position %d" \ + % (self.encoding, ord(self.character), self.reason, + self.name, self.position) + else: + return "unacceptable character #x%04x: %s\n" \ + " in \"%s\", position %d" \ + % (self.character, self.reason, + self.name, self.position) + +class Reader(object): + # Reader: + # - determines the data encoding and converts it to a unicode string, + # - checks if characters are in allowed range, + # - adds '\0' to the end. + + # Reader accepts + # - a `bytes` object, + # - a `str` object, + # - a file-like object with its `read` method returning `str`, + # - a file-like object with its `read` method returning `unicode`. + + # Yeah, it's ugly and slow. + + def __init__(self, stream): + self.name = None + self.stream = None + self.stream_pointer = 0 + self.eof = True + self.buffer = '' + self.pointer = 0 + self.raw_buffer = None + self.raw_decode = None + self.encoding = None + self.index = 0 + self.line = 0 + self.column = 0 + if isinstance(stream, str): + self.name = "" + self.check_printable(stream) + self.buffer = stream+'\0' + elif isinstance(stream, bytes): + self.name = "" + self.raw_buffer = stream + self.determine_encoding() + else: + self.stream = stream + self.name = getattr(stream, 'name', "") + self.eof = False + self.raw_buffer = None + self.determine_encoding() + + def peek(self, index=0): + try: + return self.buffer[self.pointer+index] + except IndexError: + self.update(index+1) + return self.buffer[self.pointer+index] + + def prefix(self, length=1): + if self.pointer+length >= len(self.buffer): + self.update(length) + return self.buffer[self.pointer:self.pointer+length] + + def forward(self, length=1): + if self.pointer+length+1 >= len(self.buffer): + self.update(length+1) + while length: + ch = self.buffer[self.pointer] + self.pointer += 1 + self.index += 1 + if ch in '\n\x85\u2028\u2029' \ + or (ch == '\r' and self.buffer[self.pointer] != '\n'): + self.line += 1 + self.column = 0 + elif ch != '\uFEFF': + self.column += 1 + length -= 1 + + def get_mark(self): + if self.stream is None: + return Mark(self.name, self.index, self.line, self.column, + self.buffer, self.pointer) + else: + return Mark(self.name, self.index, self.line, self.column, + None, None) + + def determine_encoding(self): + while not self.eof and (self.raw_buffer is None or len(self.raw_buffer) < 2): + self.update_raw() + if isinstance(self.raw_buffer, bytes): + if self.raw_buffer.startswith(codecs.BOM_UTF16_LE): + self.raw_decode = codecs.utf_16_le_decode + self.encoding = 'utf-16-le' + elif self.raw_buffer.startswith(codecs.BOM_UTF16_BE): + self.raw_decode = codecs.utf_16_be_decode + self.encoding = 'utf-16-be' + else: + self.raw_decode = codecs.utf_8_decode + self.encoding = 'utf-8' + self.update(1) + + NON_PRINTABLE = re.compile('[^\x09\x0A\x0D\x20-\x7E\x85\xA0-\uD7FF\uE000-\uFFFD]') + def check_printable(self, data): + match = self.NON_PRINTABLE.search(data) + if match: + character = match.group() + position = self.index+(len(self.buffer)-self.pointer)+match.start() + raise ReaderError(self.name, position, ord(character), + 'unicode', "special characters are not allowed") + + def update(self, length): + if self.raw_buffer is None: + return + self.buffer = self.buffer[self.pointer:] + self.pointer = 0 + while len(self.buffer) < length: + if not self.eof: + self.update_raw() + if self.raw_decode is not None: + try: + data, converted = self.raw_decode(self.raw_buffer, + 'strict', self.eof) + except UnicodeDecodeError as exc: + character = self.raw_buffer[exc.start] + if self.stream is not None: + position = self.stream_pointer-len(self.raw_buffer)+exc.start + else: + position = exc.start + raise ReaderError(self.name, position, character, + exc.encoding, exc.reason) + else: + data = self.raw_buffer + converted = len(data) + self.check_printable(data) + self.buffer += data + self.raw_buffer = self.raw_buffer[converted:] + if self.eof: + self.buffer += '\0' + self.raw_buffer = None + break + + def update_raw(self, size=4096): + data = self.stream.read(size) + if self.raw_buffer is None: + self.raw_buffer = data + else: + self.raw_buffer += data + self.stream_pointer += len(data) + if not data: + self.eof = True + +#try: +# import psyco +# psyco.bind(Reader) +#except ImportError: +# pass + diff --git a/software/tools/pymcuprog/libs/yaml/representer.py b/software/tools/pymcuprog/libs/yaml/representer.py new file mode 100644 index 0000000..b9e65c5 --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/representer.py @@ -0,0 +1,387 @@ + +__all__ = ['BaseRepresenter', 'SafeRepresenter', 'Representer', + 'RepresenterError'] + +from .error import * +from .nodes import * + +import datetime, sys, copyreg, types, base64, collections + +class RepresenterError(YAMLError): + pass + +class BaseRepresenter: + + yaml_representers = {} + yaml_multi_representers = {} + + def __init__(self, default_style=None, default_flow_style=None): + self.default_style = default_style + self.default_flow_style = default_flow_style + self.represented_objects = {} + self.object_keeper = [] + self.alias_key = None + + def represent(self, data): + node = self.represent_data(data) + self.serialize(node) + self.represented_objects = {} + self.object_keeper = [] + self.alias_key = None + + def represent_data(self, data): + if self.ignore_aliases(data): + self.alias_key = None + else: + self.alias_key = id(data) + if self.alias_key is not None: + if self.alias_key in self.represented_objects: + node = self.represented_objects[self.alias_key] + #if node is None: + # raise RepresenterError("recursive objects are not allowed: %r" % data) + return node + #self.represented_objects[alias_key] = None + self.object_keeper.append(data) + data_types = type(data).__mro__ + if data_types[0] in self.yaml_representers: + node = self.yaml_representers[data_types[0]](self, data) + else: + for data_type in data_types: + if data_type in self.yaml_multi_representers: + node = self.yaml_multi_representers[data_type](self, data) + break + else: + if None in self.yaml_multi_representers: + node = self.yaml_multi_representers[None](self, data) + elif None in self.yaml_representers: + node = self.yaml_representers[None](self, data) + else: + node = ScalarNode(None, str(data)) + #if alias_key is not None: + # self.represented_objects[alias_key] = node + return node + + @classmethod + def add_representer(cls, data_type, representer): + if not 'yaml_representers' in cls.__dict__: + cls.yaml_representers = cls.yaml_representers.copy() + cls.yaml_representers[data_type] = representer + + @classmethod + def add_multi_representer(cls, data_type, representer): + if not 'yaml_multi_representers' in cls.__dict__: + cls.yaml_multi_representers = cls.yaml_multi_representers.copy() + cls.yaml_multi_representers[data_type] = representer + + def represent_scalar(self, tag, value, style=None): + if style is None: + style = self.default_style + node = ScalarNode(tag, value, style=style) + if self.alias_key is not None: + self.represented_objects[self.alias_key] = node + return node + + def represent_sequence(self, tag, sequence, flow_style=None): + value = [] + node = SequenceNode(tag, value, flow_style=flow_style) + if self.alias_key is not None: + self.represented_objects[self.alias_key] = node + best_style = True + for item in sequence: + node_item = self.represent_data(item) + if not (isinstance(node_item, ScalarNode) and not node_item.style): + best_style = False + value.append(node_item) + if flow_style is None: + if self.default_flow_style is not None: + node.flow_style = self.default_flow_style + else: + node.flow_style = best_style + return node + + def represent_mapping(self, tag, mapping, flow_style=None): + value = [] + node = MappingNode(tag, value, flow_style=flow_style) + if self.alias_key is not None: + self.represented_objects[self.alias_key] = node + best_style = True + if hasattr(mapping, 'items'): + mapping = list(mapping.items()) + try: + mapping = sorted(mapping) + except TypeError: + pass + for item_key, item_value in mapping: + node_key = self.represent_data(item_key) + node_value = self.represent_data(item_value) + if not (isinstance(node_key, ScalarNode) and not node_key.style): + best_style = False + if not (isinstance(node_value, ScalarNode) and not node_value.style): + best_style = False + value.append((node_key, node_value)) + if flow_style is None: + if self.default_flow_style is not None: + node.flow_style = self.default_flow_style + else: + node.flow_style = best_style + return node + + def ignore_aliases(self, data): + return False + +class SafeRepresenter(BaseRepresenter): + + def ignore_aliases(self, data): + if data is None: + return True + if isinstance(data, tuple) and data == (): + return True + if isinstance(data, (str, bytes, bool, int, float)): + return True + + def represent_none(self, data): + return self.represent_scalar('tag:yaml.org,2002:null', 'null') + + def represent_str(self, data): + return self.represent_scalar('tag:yaml.org,2002:str', data) + + def represent_binary(self, data): + if hasattr(base64, 'encodebytes'): + data = base64.encodebytes(data).decode('ascii') + else: + data = base64.encodestring(data).decode('ascii') + return self.represent_scalar('tag:yaml.org,2002:binary', data, style='|') + + def represent_bool(self, data): + if data: + value = 'true' + else: + value = 'false' + return self.represent_scalar('tag:yaml.org,2002:bool', value) + + def represent_int(self, data): + return self.represent_scalar('tag:yaml.org,2002:int', str(data)) + + inf_value = 1e300 + while repr(inf_value) != repr(inf_value*inf_value): + inf_value *= inf_value + + def represent_float(self, data): + if data != data or (data == 0.0 and data == 1.0): + value = '.nan' + elif data == self.inf_value: + value = '.inf' + elif data == -self.inf_value: + value = '-.inf' + else: + value = repr(data).lower() + # Note that in some cases `repr(data)` represents a float number + # without the decimal parts. For instance: + # >>> repr(1e17) + # '1e17' + # Unfortunately, this is not a valid float representation according + # to the definition of the `!!float` tag. We fix this by adding + # '.0' before the 'e' symbol. + if '.' not in value and 'e' in value: + value = value.replace('e', '.0e', 1) + return self.represent_scalar('tag:yaml.org,2002:float', value) + + def represent_list(self, data): + #pairs = (len(data) > 0 and isinstance(data, list)) + #if pairs: + # for item in data: + # if not isinstance(item, tuple) or len(item) != 2: + # pairs = False + # break + #if not pairs: + return self.represent_sequence('tag:yaml.org,2002:seq', data) + #value = [] + #for item_key, item_value in data: + # value.append(self.represent_mapping(u'tag:yaml.org,2002:map', + # [(item_key, item_value)])) + #return SequenceNode(u'tag:yaml.org,2002:pairs', value) + + def represent_dict(self, data): + return self.represent_mapping('tag:yaml.org,2002:map', data) + + def represent_set(self, data): + value = {} + for key in data: + value[key] = None + return self.represent_mapping('tag:yaml.org,2002:set', value) + + def represent_date(self, data): + value = data.isoformat() + return self.represent_scalar('tag:yaml.org,2002:timestamp', value) + + def represent_datetime(self, data): + value = data.isoformat(' ') + return self.represent_scalar('tag:yaml.org,2002:timestamp', value) + + def represent_yaml_object(self, tag, data, cls, flow_style=None): + if hasattr(data, '__getstate__'): + state = data.__getstate__() + else: + state = data.__dict__.copy() + return self.represent_mapping(tag, state, flow_style=flow_style) + + def represent_undefined(self, data): + raise RepresenterError("cannot represent an object: %s" % data) + +SafeRepresenter.add_representer(type(None), + SafeRepresenter.represent_none) + +SafeRepresenter.add_representer(str, + SafeRepresenter.represent_str) + +SafeRepresenter.add_representer(bytes, + SafeRepresenter.represent_binary) + +SafeRepresenter.add_representer(bool, + SafeRepresenter.represent_bool) + +SafeRepresenter.add_representer(int, + SafeRepresenter.represent_int) + +SafeRepresenter.add_representer(float, + SafeRepresenter.represent_float) + +SafeRepresenter.add_representer(list, + SafeRepresenter.represent_list) + +SafeRepresenter.add_representer(tuple, + SafeRepresenter.represent_list) + +SafeRepresenter.add_representer(dict, + SafeRepresenter.represent_dict) + +SafeRepresenter.add_representer(set, + SafeRepresenter.represent_set) + +SafeRepresenter.add_representer(datetime.date, + SafeRepresenter.represent_date) + +SafeRepresenter.add_representer(datetime.datetime, + SafeRepresenter.represent_datetime) + +SafeRepresenter.add_representer(None, + SafeRepresenter.represent_undefined) + +class Representer(SafeRepresenter): + + def represent_complex(self, data): + if data.imag == 0.0: + data = '%r' % data.real + elif data.real == 0.0: + data = '%rj' % data.imag + elif data.imag > 0: + data = '%r+%rj' % (data.real, data.imag) + else: + data = '%r%rj' % (data.real, data.imag) + return self.represent_scalar('tag:yaml.org,2002:python/complex', data) + + def represent_tuple(self, data): + return self.represent_sequence('tag:yaml.org,2002:python/tuple', data) + + def represent_name(self, data): + name = '%s.%s' % (data.__module__, data.__name__) + return self.represent_scalar('tag:yaml.org,2002:python/name:'+name, '') + + def represent_module(self, data): + return self.represent_scalar( + 'tag:yaml.org,2002:python/module:'+data.__name__, '') + + def represent_object(self, data): + # We use __reduce__ API to save the data. data.__reduce__ returns + # a tuple of length 2-5: + # (function, args, state, listitems, dictitems) + + # For reconstructing, we calls function(*args), then set its state, + # listitems, and dictitems if they are not None. + + # A special case is when function.__name__ == '__newobj__'. In this + # case we create the object with args[0].__new__(*args). + + # Another special case is when __reduce__ returns a string - we don't + # support it. + + # We produce a !!python/object, !!python/object/new or + # !!python/object/apply node. + + cls = type(data) + if cls in copyreg.dispatch_table: + reduce = copyreg.dispatch_table[cls](data) + elif hasattr(data, '__reduce_ex__'): + reduce = data.__reduce_ex__(2) + elif hasattr(data, '__reduce__'): + reduce = data.__reduce__() + else: + raise RepresenterError("cannot represent object: %r" % data) + reduce = (list(reduce)+[None]*5)[:5] + function, args, state, listitems, dictitems = reduce + args = list(args) + if state is None: + state = {} + if listitems is not None: + listitems = list(listitems) + if dictitems is not None: + dictitems = dict(dictitems) + if function.__name__ == '__newobj__': + function = args[0] + args = args[1:] + tag = 'tag:yaml.org,2002:python/object/new:' + newobj = True + else: + tag = 'tag:yaml.org,2002:python/object/apply:' + newobj = False + function_name = '%s.%s' % (function.__module__, function.__name__) + if not args and not listitems and not dictitems \ + and isinstance(state, dict) and newobj: + return self.represent_mapping( + 'tag:yaml.org,2002:python/object:'+function_name, state) + if not listitems and not dictitems \ + and isinstance(state, dict) and not state: + return self.represent_sequence(tag+function_name, args) + value = {} + if args: + value['args'] = args + if state or not isinstance(state, dict): + value['state'] = state + if listitems: + value['listitems'] = listitems + if dictitems: + value['dictitems'] = dictitems + return self.represent_mapping(tag+function_name, value) + + def represent_ordered_dict(self, data): + # Provide uniform representation across different Python versions. + data_type = type(data) + tag = 'tag:yaml.org,2002:python/object/apply:%s.%s' \ + % (data_type.__module__, data_type.__name__) + items = [[key, value] for key, value in data.items()] + return self.represent_sequence(tag, [items]) + +Representer.add_representer(complex, + Representer.represent_complex) + +Representer.add_representer(tuple, + Representer.represent_tuple) + +Representer.add_representer(type, + Representer.represent_name) + +Representer.add_representer(collections.OrderedDict, + Representer.represent_ordered_dict) + +Representer.add_representer(types.FunctionType, + Representer.represent_name) + +Representer.add_representer(types.BuiltinFunctionType, + Representer.represent_name) + +Representer.add_representer(types.ModuleType, + Representer.represent_module) + +Representer.add_multi_representer(object, + Representer.represent_object) + diff --git a/software/tools/pymcuprog/libs/yaml/resolver.py b/software/tools/pymcuprog/libs/yaml/resolver.py new file mode 100644 index 0000000..02b82e7 --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/resolver.py @@ -0,0 +1,227 @@ + +__all__ = ['BaseResolver', 'Resolver'] + +from .error import * +from .nodes import * + +import re + +class ResolverError(YAMLError): + pass + +class BaseResolver: + + DEFAULT_SCALAR_TAG = 'tag:yaml.org,2002:str' + DEFAULT_SEQUENCE_TAG = 'tag:yaml.org,2002:seq' + DEFAULT_MAPPING_TAG = 'tag:yaml.org,2002:map' + + yaml_implicit_resolvers = {} + yaml_path_resolvers = {} + + def __init__(self): + self.resolver_exact_paths = [] + self.resolver_prefix_paths = [] + + @classmethod + def add_implicit_resolver(cls, tag, regexp, first): + if not 'yaml_implicit_resolvers' in cls.__dict__: + implicit_resolvers = {} + for key in cls.yaml_implicit_resolvers: + implicit_resolvers[key] = cls.yaml_implicit_resolvers[key][:] + cls.yaml_implicit_resolvers = implicit_resolvers + if first is None: + first = [None] + for ch in first: + cls.yaml_implicit_resolvers.setdefault(ch, []).append((tag, regexp)) + + @classmethod + def add_path_resolver(cls, tag, path, kind=None): + # Note: `add_path_resolver` is experimental. The API could be changed. + # `new_path` is a pattern that is matched against the path from the + # root to the node that is being considered. `node_path` elements are + # tuples `(node_check, index_check)`. `node_check` is a node class: + # `ScalarNode`, `SequenceNode`, `MappingNode` or `None`. `None` + # matches any kind of a node. `index_check` could be `None`, a boolean + # value, a string value, or a number. `None` and `False` match against + # any _value_ of sequence and mapping nodes. `True` matches against + # any _key_ of a mapping node. A string `index_check` matches against + # a mapping value that corresponds to a scalar key which content is + # equal to the `index_check` value. An integer `index_check` matches + # against a sequence value with the index equal to `index_check`. + if not 'yaml_path_resolvers' in cls.__dict__: + cls.yaml_path_resolvers = cls.yaml_path_resolvers.copy() + new_path = [] + for element in path: + if isinstance(element, (list, tuple)): + if len(element) == 2: + node_check, index_check = element + elif len(element) == 1: + node_check = element[0] + index_check = True + else: + raise ResolverError("Invalid path element: %s" % element) + else: + node_check = None + index_check = element + if node_check is str: + node_check = ScalarNode + elif node_check is list: + node_check = SequenceNode + elif node_check is dict: + node_check = MappingNode + elif node_check not in [ScalarNode, SequenceNode, MappingNode] \ + and not isinstance(node_check, str) \ + and node_check is not None: + raise ResolverError("Invalid node checker: %s" % node_check) + if not isinstance(index_check, (str, int)) \ + and index_check is not None: + raise ResolverError("Invalid index checker: %s" % index_check) + new_path.append((node_check, index_check)) + if kind is str: + kind = ScalarNode + elif kind is list: + kind = SequenceNode + elif kind is dict: + kind = MappingNode + elif kind not in [ScalarNode, SequenceNode, MappingNode] \ + and kind is not None: + raise ResolverError("Invalid node kind: %s" % kind) + cls.yaml_path_resolvers[tuple(new_path), kind] = tag + + def descend_resolver(self, current_node, current_index): + if not self.yaml_path_resolvers: + return + exact_paths = {} + prefix_paths = [] + if current_node: + depth = len(self.resolver_prefix_paths) + for path, kind in self.resolver_prefix_paths[-1]: + if self.check_resolver_prefix(depth, path, kind, + current_node, current_index): + if len(path) > depth: + prefix_paths.append((path, kind)) + else: + exact_paths[kind] = self.yaml_path_resolvers[path, kind] + else: + for path, kind in self.yaml_path_resolvers: + if not path: + exact_paths[kind] = self.yaml_path_resolvers[path, kind] + else: + prefix_paths.append((path, kind)) + self.resolver_exact_paths.append(exact_paths) + self.resolver_prefix_paths.append(prefix_paths) + + def ascend_resolver(self): + if not self.yaml_path_resolvers: + return + self.resolver_exact_paths.pop() + self.resolver_prefix_paths.pop() + + def check_resolver_prefix(self, depth, path, kind, + current_node, current_index): + node_check, index_check = path[depth-1] + if isinstance(node_check, str): + if current_node.tag != node_check: + return + elif node_check is not None: + if not isinstance(current_node, node_check): + return + if index_check is True and current_index is not None: + return + if (index_check is False or index_check is None) \ + and current_index is None: + return + if isinstance(index_check, str): + if not (isinstance(current_index, ScalarNode) + and index_check == current_index.value): + return + elif isinstance(index_check, int) and not isinstance(index_check, bool): + if index_check != current_index: + return + return True + + def resolve(self, kind, value, implicit): + if kind is ScalarNode and implicit[0]: + if value == '': + resolvers = self.yaml_implicit_resolvers.get('', []) + else: + resolvers = self.yaml_implicit_resolvers.get(value[0], []) + resolvers += self.yaml_implicit_resolvers.get(None, []) + for tag, regexp in resolvers: + if regexp.match(value): + return tag + implicit = implicit[1] + if self.yaml_path_resolvers: + exact_paths = self.resolver_exact_paths[-1] + if kind in exact_paths: + return exact_paths[kind] + if None in exact_paths: + return exact_paths[None] + if kind is ScalarNode: + return self.DEFAULT_SCALAR_TAG + elif kind is SequenceNode: + return self.DEFAULT_SEQUENCE_TAG + elif kind is MappingNode: + return self.DEFAULT_MAPPING_TAG + +class Resolver(BaseResolver): + pass + +Resolver.add_implicit_resolver( + 'tag:yaml.org,2002:bool', + re.compile(r'''^(?:yes|Yes|YES|no|No|NO + |true|True|TRUE|false|False|FALSE + |on|On|ON|off|Off|OFF)$''', re.X), + list('yYnNtTfFoO')) + +Resolver.add_implicit_resolver( + 'tag:yaml.org,2002:float', + re.compile(r'''^(?:[-+]?(?:[0-9][0-9_]*)\.[0-9_]*(?:[eE][-+][0-9]+)? + |\.[0-9_]+(?:[eE][-+][0-9]+)? + |[-+]?[0-9][0-9_]*(?::[0-5]?[0-9])+\.[0-9_]* + |[-+]?\.(?:inf|Inf|INF) + |\.(?:nan|NaN|NAN))$''', re.X), + list('-+0123456789.')) + +Resolver.add_implicit_resolver( + 'tag:yaml.org,2002:int', + re.compile(r'''^(?:[-+]?0b[0-1_]+ + |[-+]?0[0-7_]+ + |[-+]?(?:0|[1-9][0-9_]*) + |[-+]?0x[0-9a-fA-F_]+ + |[-+]?[1-9][0-9_]*(?::[0-5]?[0-9])+)$''', re.X), + list('-+0123456789')) + +Resolver.add_implicit_resolver( + 'tag:yaml.org,2002:merge', + re.compile(r'^(?:<<)$'), + ['<']) + +Resolver.add_implicit_resolver( + 'tag:yaml.org,2002:null', + re.compile(r'''^(?: ~ + |null|Null|NULL + | )$''', re.X), + ['~', 'n', 'N', '']) + +Resolver.add_implicit_resolver( + 'tag:yaml.org,2002:timestamp', + re.compile(r'''^(?:[0-9][0-9][0-9][0-9]-[0-9][0-9]-[0-9][0-9] + |[0-9][0-9][0-9][0-9] -[0-9][0-9]? -[0-9][0-9]? + (?:[Tt]|[ \t]+)[0-9][0-9]? + :[0-9][0-9] :[0-9][0-9] (?:\.[0-9]*)? + (?:[ \t]*(?:Z|[-+][0-9][0-9]?(?::[0-9][0-9])?))?)$''', re.X), + list('0123456789')) + +Resolver.add_implicit_resolver( + 'tag:yaml.org,2002:value', + re.compile(r'^(?:=)$'), + ['=']) + +# The following resolver is only for documentation purposes. It cannot work +# because plain scalars cannot start with '!', '&', or '*'. +Resolver.add_implicit_resolver( + 'tag:yaml.org,2002:yaml', + re.compile(r'^(?:!|&|\*)$'), + list('!&*')) + diff --git a/software/tools/pymcuprog/libs/yaml/scanner.py b/software/tools/pymcuprog/libs/yaml/scanner.py new file mode 100644 index 0000000..c8d127b --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/scanner.py @@ -0,0 +1,1444 @@ + +# Scanner produces tokens of the following types: +# STREAM-START +# STREAM-END +# DIRECTIVE(name, value) +# DOCUMENT-START +# DOCUMENT-END +# BLOCK-SEQUENCE-START +# BLOCK-MAPPING-START +# BLOCK-END +# FLOW-SEQUENCE-START +# FLOW-MAPPING-START +# FLOW-SEQUENCE-END +# FLOW-MAPPING-END +# BLOCK-ENTRY +# FLOW-ENTRY +# KEY +# VALUE +# ALIAS(value) +# ANCHOR(value) +# TAG(value) +# SCALAR(value, plain, style) +# +# Read comments in the Scanner code for more details. +# + +__all__ = ['Scanner', 'ScannerError'] + +from .error import MarkedYAMLError +from .tokens import * + +class ScannerError(MarkedYAMLError): + pass + +class SimpleKey: + # See below simple keys treatment. + + def __init__(self, token_number, required, index, line, column, mark): + self.token_number = token_number + self.required = required + self.index = index + self.line = line + self.column = column + self.mark = mark + +class Scanner: + + def __init__(self): + """Initialize the scanner.""" + # It is assumed that Scanner and Reader will have a common descendant. + # Reader do the dirty work of checking for BOM and converting the + # input data to Unicode. It also adds NUL to the end. + # + # Reader supports the following methods + # self.peek(i=0) # peek the next i-th character + # self.prefix(l=1) # peek the next l characters + # self.forward(l=1) # read the next l characters and move the pointer. + + # Had we reached the end of the stream? + self.done = False + + # The number of unclosed '{' and '['. `flow_level == 0` means block + # context. + self.flow_level = 0 + + # List of processed tokens that are not yet emitted. + self.tokens = [] + + # Add the STREAM-START token. + self.fetch_stream_start() + + # Number of tokens that were emitted through the `get_token` method. + self.tokens_taken = 0 + + # The current indentation level. + self.indent = -1 + + # Past indentation levels. + self.indents = [] + + # Variables related to simple keys treatment. + + # A simple key is a key that is not denoted by the '?' indicator. + # Example of simple keys: + # --- + # block simple key: value + # ? not a simple key: + # : { flow simple key: value } + # We emit the KEY token before all keys, so when we find a potential + # simple key, we try to locate the corresponding ':' indicator. + # Simple keys should be limited to a single line and 1024 characters. + + # Can a simple key start at the current position? A simple key may + # start: + # - at the beginning of the line, not counting indentation spaces + # (in block context), + # - after '{', '[', ',' (in the flow context), + # - after '?', ':', '-' (in the block context). + # In the block context, this flag also signifies if a block collection + # may start at the current position. + self.allow_simple_key = True + + # Keep track of possible simple keys. This is a dictionary. The key + # is `flow_level`; there can be no more that one possible simple key + # for each level. The value is a SimpleKey record: + # (token_number, required, index, line, column, mark) + # A simple key may start with ALIAS, ANCHOR, TAG, SCALAR(flow), + # '[', or '{' tokens. + self.possible_simple_keys = {} + + # Public methods. + + def check_token(self, *choices): + # Check if the next token is one of the given types. + while self.need_more_tokens(): + self.fetch_more_tokens() + if self.tokens: + if not choices: + return True + for choice in choices: + if isinstance(self.tokens[0], choice): + return True + return False + + def peek_token(self): + # Return the next token, but do not delete if from the queue. + while self.need_more_tokens(): + self.fetch_more_tokens() + if self.tokens: + return self.tokens[0] + + def get_token(self): + # Return the next token. + while self.need_more_tokens(): + self.fetch_more_tokens() + if self.tokens: + self.tokens_taken += 1 + return self.tokens.pop(0) + + # Private methods. + + def need_more_tokens(self): + if self.done: + return False + if not self.tokens: + return True + # The current token may be a potential simple key, so we + # need to look further. + self.stale_possible_simple_keys() + if self.next_possible_simple_key() == self.tokens_taken: + return True + + def fetch_more_tokens(self): + + # Eat whitespaces and comments until we reach the next token. + self.scan_to_next_token() + + # Remove obsolete possible simple keys. + self.stale_possible_simple_keys() + + # Compare the current indentation and column. It may add some tokens + # and decrease the current indentation level. + self.unwind_indent(self.column) + + # Peek the next character. + ch = self.peek() + + # Is it the end of stream? + if ch == '\0': + return self.fetch_stream_end() + + # Is it a directive? + if ch == '%' and self.check_directive(): + return self.fetch_directive() + + # Is it the document start? + if ch == '-' and self.check_document_start(): + return self.fetch_document_start() + + # Is it the document end? + if ch == '.' and self.check_document_end(): + return self.fetch_document_end() + + # TODO: support for BOM within a stream. + #if ch == '\uFEFF': + # return self.fetch_bom() <-- issue BOMToken + + # Note: the order of the following checks is NOT significant. + + # Is it the flow sequence start indicator? + if ch == '[': + return self.fetch_flow_sequence_start() + + # Is it the flow mapping start indicator? + if ch == '{': + return self.fetch_flow_mapping_start() + + # Is it the flow sequence end indicator? + if ch == ']': + return self.fetch_flow_sequence_end() + + # Is it the flow mapping end indicator? + if ch == '}': + return self.fetch_flow_mapping_end() + + # Is it the flow entry indicator? + if ch == ',': + return self.fetch_flow_entry() + + # Is it the block entry indicator? + if ch == '-' and self.check_block_entry(): + return self.fetch_block_entry() + + # Is it the key indicator? + if ch == '?' and self.check_key(): + return self.fetch_key() + + # Is it the value indicator? + if ch == ':' and self.check_value(): + return self.fetch_value() + + # Is it an alias? + if ch == '*': + return self.fetch_alias() + + # Is it an anchor? + if ch == '&': + return self.fetch_anchor() + + # Is it a tag? + if ch == '!': + return self.fetch_tag() + + # Is it a literal scalar? + if ch == '|' and not self.flow_level: + return self.fetch_literal() + + # Is it a folded scalar? + if ch == '>' and not self.flow_level: + return self.fetch_folded() + + # Is it a single quoted scalar? + if ch == '\'': + return self.fetch_single() + + # Is it a double quoted scalar? + if ch == '\"': + return self.fetch_double() + + # It must be a plain scalar then. + if self.check_plain(): + return self.fetch_plain() + + # No? It's an error. Let's produce a nice error message. + raise ScannerError("while scanning for the next token", None, + "found character %r that cannot start any token" % ch, + self.get_mark()) + + # Simple keys treatment. + + def next_possible_simple_key(self): + # Return the number of the nearest possible simple key. Actually we + # don't need to loop through the whole dictionary. We may replace it + # with the following code: + # if not self.possible_simple_keys: + # return None + # return self.possible_simple_keys[ + # min(self.possible_simple_keys.keys())].token_number + min_token_number = None + for level in self.possible_simple_keys: + key = self.possible_simple_keys[level] + if min_token_number is None or key.token_number < min_token_number: + min_token_number = key.token_number + return min_token_number + + def stale_possible_simple_keys(self): + # Remove entries that are no longer possible simple keys. According to + # the YAML specification, simple keys + # - should be limited to a single line, + # - should be no longer than 1024 characters. + # Disabling this procedure will allow simple keys of any length and + # height (may cause problems if indentation is broken though). + for level in list(self.possible_simple_keys): + key = self.possible_simple_keys[level] + if key.line != self.line \ + or self.index-key.index > 1024: + if key.required: + raise ScannerError("while scanning a simple key", key.mark, + "could not find expected ':'", self.get_mark()) + del self.possible_simple_keys[level] + + def save_possible_simple_key(self): + # The next token may start a simple key. We check if it's possible + # and save its position. This function is called for + # ALIAS, ANCHOR, TAG, SCALAR(flow), '[', and '{'. + + # Check if a simple key is required at the current position. + required = not self.flow_level and self.indent == self.column + + # The next token might be a simple key. Let's save it's number and + # position. + if self.allow_simple_key: + self.remove_possible_simple_key() + token_number = self.tokens_taken+len(self.tokens) + key = SimpleKey(token_number, required, + self.index, self.line, self.column, self.get_mark()) + self.possible_simple_keys[self.flow_level] = key + + def remove_possible_simple_key(self): + # Remove the saved possible key position at the current flow level. + if self.flow_level in self.possible_simple_keys: + key = self.possible_simple_keys[self.flow_level] + + if key.required: + raise ScannerError("while scanning a simple key", key.mark, + "could not find expected ':'", self.get_mark()) + + del self.possible_simple_keys[self.flow_level] + + # Indentation functions. + + def unwind_indent(self, column): + + ## In flow context, tokens should respect indentation. + ## Actually the condition should be `self.indent >= column` according to + ## the spec. But this condition will prohibit intuitively correct + ## constructions such as + ## key : { + ## } + #if self.flow_level and self.indent > column: + # raise ScannerError(None, None, + # "invalid intendation or unclosed '[' or '{'", + # self.get_mark()) + + # In the flow context, indentation is ignored. We make the scanner less + # restrictive then specification requires. + if self.flow_level: + return + + # In block context, we may need to issue the BLOCK-END tokens. + while self.indent > column: + mark = self.get_mark() + self.indent = self.indents.pop() + self.tokens.append(BlockEndToken(mark, mark)) + + def add_indent(self, column): + # Check if we need to increase indentation. + if self.indent < column: + self.indents.append(self.indent) + self.indent = column + return True + return False + + # Fetchers. + + def fetch_stream_start(self): + # We always add STREAM-START as the first token and STREAM-END as the + # last token. + + # Read the token. + mark = self.get_mark() + + # Add STREAM-START. + self.tokens.append(StreamStartToken(mark, mark, + encoding=self.encoding)) + + + def fetch_stream_end(self): + + # Set the current intendation to -1. + self.unwind_indent(-1) + + # Reset simple keys. + self.remove_possible_simple_key() + self.allow_simple_key = False + self.possible_simple_keys = {} + + # Read the token. + mark = self.get_mark() + + # Add STREAM-END. + self.tokens.append(StreamEndToken(mark, mark)) + + # The steam is finished. + self.done = True + + def fetch_directive(self): + + # Set the current intendation to -1. + self.unwind_indent(-1) + + # Reset simple keys. + self.remove_possible_simple_key() + self.allow_simple_key = False + + # Scan and add DIRECTIVE. + self.tokens.append(self.scan_directive()) + + def fetch_document_start(self): + self.fetch_document_indicator(DocumentStartToken) + + def fetch_document_end(self): + self.fetch_document_indicator(DocumentEndToken) + + def fetch_document_indicator(self, TokenClass): + + # Set the current intendation to -1. + self.unwind_indent(-1) + + # Reset simple keys. Note that there could not be a block collection + # after '---'. + self.remove_possible_simple_key() + self.allow_simple_key = False + + # Add DOCUMENT-START or DOCUMENT-END. + start_mark = self.get_mark() + self.forward(3) + end_mark = self.get_mark() + self.tokens.append(TokenClass(start_mark, end_mark)) + + def fetch_flow_sequence_start(self): + self.fetch_flow_collection_start(FlowSequenceStartToken) + + def fetch_flow_mapping_start(self): + self.fetch_flow_collection_start(FlowMappingStartToken) + + def fetch_flow_collection_start(self, TokenClass): + + # '[' and '{' may start a simple key. + self.save_possible_simple_key() + + # Increase the flow level. + self.flow_level += 1 + + # Simple keys are allowed after '[' and '{'. + self.allow_simple_key = True + + # Add FLOW-SEQUENCE-START or FLOW-MAPPING-START. + start_mark = self.get_mark() + self.forward() + end_mark = self.get_mark() + self.tokens.append(TokenClass(start_mark, end_mark)) + + def fetch_flow_sequence_end(self): + self.fetch_flow_collection_end(FlowSequenceEndToken) + + def fetch_flow_mapping_end(self): + self.fetch_flow_collection_end(FlowMappingEndToken) + + def fetch_flow_collection_end(self, TokenClass): + + # Reset possible simple key on the current level. + self.remove_possible_simple_key() + + # Decrease the flow level. + self.flow_level -= 1 + + # No simple keys after ']' or '}'. + self.allow_simple_key = False + + # Add FLOW-SEQUENCE-END or FLOW-MAPPING-END. + start_mark = self.get_mark() + self.forward() + end_mark = self.get_mark() + self.tokens.append(TokenClass(start_mark, end_mark)) + + def fetch_flow_entry(self): + + # Simple keys are allowed after ','. + self.allow_simple_key = True + + # Reset possible simple key on the current level. + self.remove_possible_simple_key() + + # Add FLOW-ENTRY. + start_mark = self.get_mark() + self.forward() + end_mark = self.get_mark() + self.tokens.append(FlowEntryToken(start_mark, end_mark)) + + def fetch_block_entry(self): + + # Block context needs additional checks. + if not self.flow_level: + + # Are we allowed to start a new entry? + if not self.allow_simple_key: + raise ScannerError(None, None, + "sequence entries are not allowed here", + self.get_mark()) + + # We may need to add BLOCK-SEQUENCE-START. + if self.add_indent(self.column): + mark = self.get_mark() + self.tokens.append(BlockSequenceStartToken(mark, mark)) + + # It's an error for the block entry to occur in the flow context, + # but we let the parser detect this. + else: + pass + + # Simple keys are allowed after '-'. + self.allow_simple_key = True + + # Reset possible simple key on the current level. + self.remove_possible_simple_key() + + # Add BLOCK-ENTRY. + start_mark = self.get_mark() + self.forward() + end_mark = self.get_mark() + self.tokens.append(BlockEntryToken(start_mark, end_mark)) + + def fetch_key(self): + + # Block context needs additional checks. + if not self.flow_level: + + # Are we allowed to start a key (not nessesary a simple)? + if not self.allow_simple_key: + raise ScannerError(None, None, + "mapping keys are not allowed here", + self.get_mark()) + + # We may need to add BLOCK-MAPPING-START. + if self.add_indent(self.column): + mark = self.get_mark() + self.tokens.append(BlockMappingStartToken(mark, mark)) + + # Simple keys are allowed after '?' in the block context. + self.allow_simple_key = not self.flow_level + + # Reset possible simple key on the current level. + self.remove_possible_simple_key() + + # Add KEY. + start_mark = self.get_mark() + self.forward() + end_mark = self.get_mark() + self.tokens.append(KeyToken(start_mark, end_mark)) + + def fetch_value(self): + + # Do we determine a simple key? + if self.flow_level in self.possible_simple_keys: + + # Add KEY. + key = self.possible_simple_keys[self.flow_level] + del self.possible_simple_keys[self.flow_level] + self.tokens.insert(key.token_number-self.tokens_taken, + KeyToken(key.mark, key.mark)) + + # If this key starts a new block mapping, we need to add + # BLOCK-MAPPING-START. + if not self.flow_level: + if self.add_indent(key.column): + self.tokens.insert(key.token_number-self.tokens_taken, + BlockMappingStartToken(key.mark, key.mark)) + + # There cannot be two simple keys one after another. + self.allow_simple_key = False + + # It must be a part of a complex key. + else: + + # Block context needs additional checks. + # (Do we really need them? They will be catched by the parser + # anyway.) + if not self.flow_level: + + # We are allowed to start a complex value if and only if + # we can start a simple key. + if not self.allow_simple_key: + raise ScannerError(None, None, + "mapping values are not allowed here", + self.get_mark()) + + # If this value starts a new block mapping, we need to add + # BLOCK-MAPPING-START. It will be detected as an error later by + # the parser. + if not self.flow_level: + if self.add_indent(self.column): + mark = self.get_mark() + self.tokens.append(BlockMappingStartToken(mark, mark)) + + # Simple keys are allowed after ':' in the block context. + self.allow_simple_key = not self.flow_level + + # Reset possible simple key on the current level. + self.remove_possible_simple_key() + + # Add VALUE. + start_mark = self.get_mark() + self.forward() + end_mark = self.get_mark() + self.tokens.append(ValueToken(start_mark, end_mark)) + + def fetch_alias(self): + + # ALIAS could be a simple key. + self.save_possible_simple_key() + + # No simple keys after ALIAS. + self.allow_simple_key = False + + # Scan and add ALIAS. + self.tokens.append(self.scan_anchor(AliasToken)) + + def fetch_anchor(self): + + # ANCHOR could start a simple key. + self.save_possible_simple_key() + + # No simple keys after ANCHOR. + self.allow_simple_key = False + + # Scan and add ANCHOR. + self.tokens.append(self.scan_anchor(AnchorToken)) + + def fetch_tag(self): + + # TAG could start a simple key. + self.save_possible_simple_key() + + # No simple keys after TAG. + self.allow_simple_key = False + + # Scan and add TAG. + self.tokens.append(self.scan_tag()) + + def fetch_literal(self): + self.fetch_block_scalar(style='|') + + def fetch_folded(self): + self.fetch_block_scalar(style='>') + + def fetch_block_scalar(self, style): + + # A simple key may follow a block scalar. + self.allow_simple_key = True + + # Reset possible simple key on the current level. + self.remove_possible_simple_key() + + # Scan and add SCALAR. + self.tokens.append(self.scan_block_scalar(style)) + + def fetch_single(self): + self.fetch_flow_scalar(style='\'') + + def fetch_double(self): + self.fetch_flow_scalar(style='"') + + def fetch_flow_scalar(self, style): + + # A flow scalar could be a simple key. + self.save_possible_simple_key() + + # No simple keys after flow scalars. + self.allow_simple_key = False + + # Scan and add SCALAR. + self.tokens.append(self.scan_flow_scalar(style)) + + def fetch_plain(self): + + # A plain scalar could be a simple key. + self.save_possible_simple_key() + + # No simple keys after plain scalars. But note that `scan_plain` will + # change this flag if the scan is finished at the beginning of the + # line. + self.allow_simple_key = False + + # Scan and add SCALAR. May change `allow_simple_key`. + self.tokens.append(self.scan_plain()) + + # Checkers. + + def check_directive(self): + + # DIRECTIVE: ^ '%' ... + # The '%' indicator is already checked. + if self.column == 0: + return True + + def check_document_start(self): + + # DOCUMENT-START: ^ '---' (' '|'\n') + if self.column == 0: + if self.prefix(3) == '---' \ + and self.peek(3) in '\0 \t\r\n\x85\u2028\u2029': + return True + + def check_document_end(self): + + # DOCUMENT-END: ^ '...' (' '|'\n') + if self.column == 0: + if self.prefix(3) == '...' \ + and self.peek(3) in '\0 \t\r\n\x85\u2028\u2029': + return True + + def check_block_entry(self): + + # BLOCK-ENTRY: '-' (' '|'\n') + return self.peek(1) in '\0 \t\r\n\x85\u2028\u2029' + + def check_key(self): + + # KEY(flow context): '?' + if self.flow_level: + return True + + # KEY(block context): '?' (' '|'\n') + else: + return self.peek(1) in '\0 \t\r\n\x85\u2028\u2029' + + def check_value(self): + + # VALUE(flow context): ':' + if self.flow_level: + return True + + # VALUE(block context): ':' (' '|'\n') + else: + return self.peek(1) in '\0 \t\r\n\x85\u2028\u2029' + + def check_plain(self): + + # A plain scalar may start with any non-space character except: + # '-', '?', ':', ',', '[', ']', '{', '}', + # '#', '&', '*', '!', '|', '>', '\'', '\"', + # '%', '@', '`'. + # + # It may also start with + # '-', '?', ':' + # if it is followed by a non-space character. + # + # Note that we limit the last rule to the block context (except the + # '-' character) because we want the flow context to be space + # independent. + ch = self.peek() + return ch not in '\0 \t\r\n\x85\u2028\u2029-?:,[]{}#&*!|>\'\"%@`' \ + or (self.peek(1) not in '\0 \t\r\n\x85\u2028\u2029' + and (ch == '-' or (not self.flow_level and ch in '?:'))) + + # Scanners. + + def scan_to_next_token(self): + # We ignore spaces, line breaks and comments. + # If we find a line break in the block context, we set the flag + # `allow_simple_key` on. + # The byte order mark is stripped if it's the first character in the + # stream. We do not yet support BOM inside the stream as the + # specification requires. Any such mark will be considered as a part + # of the document. + # + # TODO: We need to make tab handling rules more sane. A good rule is + # Tabs cannot precede tokens + # BLOCK-SEQUENCE-START, BLOCK-MAPPING-START, BLOCK-END, + # KEY(block), VALUE(block), BLOCK-ENTRY + # So the checking code is + # if : + # self.allow_simple_keys = False + # We also need to add the check for `allow_simple_keys == True` to + # `unwind_indent` before issuing BLOCK-END. + # Scanners for block, flow, and plain scalars need to be modified. + + if self.index == 0 and self.peek() == '\uFEFF': + self.forward() + found = False + while not found: + while self.peek() == ' ': + self.forward() + if self.peek() == '#': + while self.peek() not in '\0\r\n\x85\u2028\u2029': + self.forward() + if self.scan_line_break(): + if not self.flow_level: + self.allow_simple_key = True + else: + found = True + + def scan_directive(self): + # See the specification for details. + start_mark = self.get_mark() + self.forward() + name = self.scan_directive_name(start_mark) + value = None + if name == 'YAML': + value = self.scan_yaml_directive_value(start_mark) + end_mark = self.get_mark() + elif name == 'TAG': + value = self.scan_tag_directive_value(start_mark) + end_mark = self.get_mark() + else: + end_mark = self.get_mark() + while self.peek() not in '\0\r\n\x85\u2028\u2029': + self.forward() + self.scan_directive_ignored_line(start_mark) + return DirectiveToken(name, value, start_mark, end_mark) + + def scan_directive_name(self, start_mark): + # See the specification for details. + length = 0 + ch = self.peek(length) + while '0' <= ch <= '9' or 'A' <= ch <= 'Z' or 'a' <= ch <= 'z' \ + or ch in '-_': + length += 1 + ch = self.peek(length) + if not length: + raise ScannerError("while scanning a directive", start_mark, + "expected alphabetic or numeric character, but found %r" + % ch, self.get_mark()) + value = self.prefix(length) + self.forward(length) + ch = self.peek() + if ch not in '\0 \r\n\x85\u2028\u2029': + raise ScannerError("while scanning a directive", start_mark, + "expected alphabetic or numeric character, but found %r" + % ch, self.get_mark()) + return value + + def scan_yaml_directive_value(self, start_mark): + # See the specification for details. + while self.peek() == ' ': + self.forward() + major = self.scan_yaml_directive_number(start_mark) + if self.peek() != '.': + raise ScannerError("while scanning a directive", start_mark, + "expected a digit or '.', but found %r" % self.peek(), + self.get_mark()) + self.forward() + minor = self.scan_yaml_directive_number(start_mark) + if self.peek() not in '\0 \r\n\x85\u2028\u2029': + raise ScannerError("while scanning a directive", start_mark, + "expected a digit or ' ', but found %r" % self.peek(), + self.get_mark()) + return (major, minor) + + def scan_yaml_directive_number(self, start_mark): + # See the specification for details. + ch = self.peek() + if not ('0' <= ch <= '9'): + raise ScannerError("while scanning a directive", start_mark, + "expected a digit, but found %r" % ch, self.get_mark()) + length = 0 + while '0' <= self.peek(length) <= '9': + length += 1 + value = int(self.prefix(length)) + self.forward(length) + return value + + def scan_tag_directive_value(self, start_mark): + # See the specification for details. + while self.peek() == ' ': + self.forward() + handle = self.scan_tag_directive_handle(start_mark) + while self.peek() == ' ': + self.forward() + prefix = self.scan_tag_directive_prefix(start_mark) + return (handle, prefix) + + def scan_tag_directive_handle(self, start_mark): + # See the specification for details. + value = self.scan_tag_handle('directive', start_mark) + ch = self.peek() + if ch != ' ': + raise ScannerError("while scanning a directive", start_mark, + "expected ' ', but found %r" % ch, self.get_mark()) + return value + + def scan_tag_directive_prefix(self, start_mark): + # See the specification for details. + value = self.scan_tag_uri('directive', start_mark) + ch = self.peek() + if ch not in '\0 \r\n\x85\u2028\u2029': + raise ScannerError("while scanning a directive", start_mark, + "expected ' ', but found %r" % ch, self.get_mark()) + return value + + def scan_directive_ignored_line(self, start_mark): + # See the specification for details. + while self.peek() == ' ': + self.forward() + if self.peek() == '#': + while self.peek() not in '\0\r\n\x85\u2028\u2029': + self.forward() + ch = self.peek() + if ch not in '\0\r\n\x85\u2028\u2029': + raise ScannerError("while scanning a directive", start_mark, + "expected a comment or a line break, but found %r" + % ch, self.get_mark()) + self.scan_line_break() + + def scan_anchor(self, TokenClass): + # The specification does not restrict characters for anchors and + # aliases. This may lead to problems, for instance, the document: + # [ *alias, value ] + # can be interpteted in two ways, as + # [ "value" ] + # and + # [ *alias , "value" ] + # Therefore we restrict aliases to numbers and ASCII letters. + start_mark = self.get_mark() + indicator = self.peek() + if indicator == '*': + name = 'alias' + else: + name = 'anchor' + self.forward() + length = 0 + ch = self.peek(length) + while '0' <= ch <= '9' or 'A' <= ch <= 'Z' or 'a' <= ch <= 'z' \ + or ch in '-_': + length += 1 + ch = self.peek(length) + if not length: + raise ScannerError("while scanning an %s" % name, start_mark, + "expected alphabetic or numeric character, but found %r" + % ch, self.get_mark()) + value = self.prefix(length) + self.forward(length) + ch = self.peek() + if ch not in '\0 \t\r\n\x85\u2028\u2029?:,]}%@`': + raise ScannerError("while scanning an %s" % name, start_mark, + "expected alphabetic or numeric character, but found %r" + % ch, self.get_mark()) + end_mark = self.get_mark() + return TokenClass(value, start_mark, end_mark) + + def scan_tag(self): + # See the specification for details. + start_mark = self.get_mark() + ch = self.peek(1) + if ch == '<': + handle = None + self.forward(2) + suffix = self.scan_tag_uri('tag', start_mark) + if self.peek() != '>': + raise ScannerError("while parsing a tag", start_mark, + "expected '>', but found %r" % self.peek(), + self.get_mark()) + self.forward() + elif ch in '\0 \t\r\n\x85\u2028\u2029': + handle = None + suffix = '!' + self.forward() + else: + length = 1 + use_handle = False + while ch not in '\0 \r\n\x85\u2028\u2029': + if ch == '!': + use_handle = True + break + length += 1 + ch = self.peek(length) + handle = '!' + if use_handle: + handle = self.scan_tag_handle('tag', start_mark) + else: + handle = '!' + self.forward() + suffix = self.scan_tag_uri('tag', start_mark) + ch = self.peek() + if ch not in '\0 \r\n\x85\u2028\u2029': + raise ScannerError("while scanning a tag", start_mark, + "expected ' ', but found %r" % ch, self.get_mark()) + value = (handle, suffix) + end_mark = self.get_mark() + return TagToken(value, start_mark, end_mark) + + def scan_block_scalar(self, style): + # See the specification for details. + + if style == '>': + folded = True + else: + folded = False + + chunks = [] + start_mark = self.get_mark() + + # Scan the header. + self.forward() + chomping, increment = self.scan_block_scalar_indicators(start_mark) + self.scan_block_scalar_ignored_line(start_mark) + + # Determine the indentation level and go to the first non-empty line. + min_indent = self.indent+1 + if min_indent < 1: + min_indent = 1 + if increment is None: + breaks, max_indent, end_mark = self.scan_block_scalar_indentation() + indent = max(min_indent, max_indent) + else: + indent = min_indent+increment-1 + breaks, end_mark = self.scan_block_scalar_breaks(indent) + line_break = '' + + # Scan the inner part of the block scalar. + while self.column == indent and self.peek() != '\0': + chunks.extend(breaks) + leading_non_space = self.peek() not in ' \t' + length = 0 + while self.peek(length) not in '\0\r\n\x85\u2028\u2029': + length += 1 + chunks.append(self.prefix(length)) + self.forward(length) + line_break = self.scan_line_break() + breaks, end_mark = self.scan_block_scalar_breaks(indent) + if self.column == indent and self.peek() != '\0': + + # Unfortunately, folding rules are ambiguous. + # + # This is the folding according to the specification: + + if folded and line_break == '\n' \ + and leading_non_space and self.peek() not in ' \t': + if not breaks: + chunks.append(' ') + else: + chunks.append(line_break) + + # This is Clark Evans's interpretation (also in the spec + # examples): + # + #if folded and line_break == '\n': + # if not breaks: + # if self.peek() not in ' \t': + # chunks.append(' ') + # else: + # chunks.append(line_break) + #else: + # chunks.append(line_break) + else: + break + + # Chomp the tail. + if chomping is not False: + chunks.append(line_break) + if chomping is True: + chunks.extend(breaks) + + # We are done. + return ScalarToken(''.join(chunks), False, start_mark, end_mark, + style) + + def scan_block_scalar_indicators(self, start_mark): + # See the specification for details. + chomping = None + increment = None + ch = self.peek() + if ch in '+-': + if ch == '+': + chomping = True + else: + chomping = False + self.forward() + ch = self.peek() + if ch in '0123456789': + increment = int(ch) + if increment == 0: + raise ScannerError("while scanning a block scalar", start_mark, + "expected indentation indicator in the range 1-9, but found 0", + self.get_mark()) + self.forward() + elif ch in '0123456789': + increment = int(ch) + if increment == 0: + raise ScannerError("while scanning a block scalar", start_mark, + "expected indentation indicator in the range 1-9, but found 0", + self.get_mark()) + self.forward() + ch = self.peek() + if ch in '+-': + if ch == '+': + chomping = True + else: + chomping = False + self.forward() + ch = self.peek() + if ch not in '\0 \r\n\x85\u2028\u2029': + raise ScannerError("while scanning a block scalar", start_mark, + "expected chomping or indentation indicators, but found %r" + % ch, self.get_mark()) + return chomping, increment + + def scan_block_scalar_ignored_line(self, start_mark): + # See the specification for details. + while self.peek() == ' ': + self.forward() + if self.peek() == '#': + while self.peek() not in '\0\r\n\x85\u2028\u2029': + self.forward() + ch = self.peek() + if ch not in '\0\r\n\x85\u2028\u2029': + raise ScannerError("while scanning a block scalar", start_mark, + "expected a comment or a line break, but found %r" % ch, + self.get_mark()) + self.scan_line_break() + + def scan_block_scalar_indentation(self): + # See the specification for details. + chunks = [] + max_indent = 0 + end_mark = self.get_mark() + while self.peek() in ' \r\n\x85\u2028\u2029': + if self.peek() != ' ': + chunks.append(self.scan_line_break()) + end_mark = self.get_mark() + else: + self.forward() + if self.column > max_indent: + max_indent = self.column + return chunks, max_indent, end_mark + + def scan_block_scalar_breaks(self, indent): + # See the specification for details. + chunks = [] + end_mark = self.get_mark() + while self.column < indent and self.peek() == ' ': + self.forward() + while self.peek() in '\r\n\x85\u2028\u2029': + chunks.append(self.scan_line_break()) + end_mark = self.get_mark() + while self.column < indent and self.peek() == ' ': + self.forward() + return chunks, end_mark + + def scan_flow_scalar(self, style): + # See the specification for details. + # Note that we loose indentation rules for quoted scalars. Quoted + # scalars don't need to adhere indentation because " and ' clearly + # mark the beginning and the end of them. Therefore we are less + # restrictive then the specification requires. We only need to check + # that document separators are not included in scalars. + if style == '"': + double = True + else: + double = False + chunks = [] + start_mark = self.get_mark() + quote = self.peek() + self.forward() + chunks.extend(self.scan_flow_scalar_non_spaces(double, start_mark)) + while self.peek() != quote: + chunks.extend(self.scan_flow_scalar_spaces(double, start_mark)) + chunks.extend(self.scan_flow_scalar_non_spaces(double, start_mark)) + self.forward() + end_mark = self.get_mark() + return ScalarToken(''.join(chunks), False, start_mark, end_mark, + style) + + ESCAPE_REPLACEMENTS = { + '0': '\0', + 'a': '\x07', + 'b': '\x08', + 't': '\x09', + '\t': '\x09', + 'n': '\x0A', + 'v': '\x0B', + 'f': '\x0C', + 'r': '\x0D', + 'e': '\x1B', + ' ': '\x20', + '\"': '\"', + '\\': '\\', + 'N': '\x85', + '_': '\xA0', + 'L': '\u2028', + 'P': '\u2029', + } + + ESCAPE_CODES = { + 'x': 2, + 'u': 4, + 'U': 8, + } + + def scan_flow_scalar_non_spaces(self, double, start_mark): + # See the specification for details. + chunks = [] + while True: + length = 0 + while self.peek(length) not in '\'\"\\\0 \t\r\n\x85\u2028\u2029': + length += 1 + if length: + chunks.append(self.prefix(length)) + self.forward(length) + ch = self.peek() + if not double and ch == '\'' and self.peek(1) == '\'': + chunks.append('\'') + self.forward(2) + elif (double and ch == '\'') or (not double and ch in '\"\\'): + chunks.append(ch) + self.forward() + elif double and ch == '\\': + self.forward() + ch = self.peek() + if ch in self.ESCAPE_REPLACEMENTS: + chunks.append(self.ESCAPE_REPLACEMENTS[ch]) + self.forward() + elif ch in self.ESCAPE_CODES: + length = self.ESCAPE_CODES[ch] + self.forward() + for k in range(length): + if self.peek(k) not in '0123456789ABCDEFabcdef': + raise ScannerError("while scanning a double-quoted scalar", start_mark, + "expected escape sequence of %d hexdecimal numbers, but found %r" % + (length, self.peek(k)), self.get_mark()) + code = int(self.prefix(length), 16) + chunks.append(chr(code)) + self.forward(length) + elif ch in '\r\n\x85\u2028\u2029': + self.scan_line_break() + chunks.extend(self.scan_flow_scalar_breaks(double, start_mark)) + else: + raise ScannerError("while scanning a double-quoted scalar", start_mark, + "found unknown escape character %r" % ch, self.get_mark()) + else: + return chunks + + def scan_flow_scalar_spaces(self, double, start_mark): + # See the specification for details. + chunks = [] + length = 0 + while self.peek(length) in ' \t': + length += 1 + whitespaces = self.prefix(length) + self.forward(length) + ch = self.peek() + if ch == '\0': + raise ScannerError("while scanning a quoted scalar", start_mark, + "found unexpected end of stream", self.get_mark()) + elif ch in '\r\n\x85\u2028\u2029': + line_break = self.scan_line_break() + breaks = self.scan_flow_scalar_breaks(double, start_mark) + if line_break != '\n': + chunks.append(line_break) + elif not breaks: + chunks.append(' ') + chunks.extend(breaks) + else: + chunks.append(whitespaces) + return chunks + + def scan_flow_scalar_breaks(self, double, start_mark): + # See the specification for details. + chunks = [] + while True: + # Instead of checking indentation, we check for document + # separators. + prefix = self.prefix(3) + if (prefix == '---' or prefix == '...') \ + and self.peek(3) in '\0 \t\r\n\x85\u2028\u2029': + raise ScannerError("while scanning a quoted scalar", start_mark, + "found unexpected document separator", self.get_mark()) + while self.peek() in ' \t': + self.forward() + if self.peek() in '\r\n\x85\u2028\u2029': + chunks.append(self.scan_line_break()) + else: + return chunks + + def scan_plain(self): + # See the specification for details. + # We add an additional restriction for the flow context: + # plain scalars in the flow context cannot contain ',', ':' and '?'. + # We also keep track of the `allow_simple_key` flag here. + # Indentation rules are loosed for the flow context. + chunks = [] + start_mark = self.get_mark() + end_mark = start_mark + indent = self.indent+1 + # We allow zero indentation for scalars, but then we need to check for + # document separators at the beginning of the line. + #if indent == 0: + # indent = 1 + spaces = [] + while True: + length = 0 + if self.peek() == '#': + break + while True: + ch = self.peek(length) + if ch in '\0 \t\r\n\x85\u2028\u2029' \ + or (not self.flow_level and ch == ':' and + self.peek(length+1) in '\0 \t\r\n\x85\u2028\u2029') \ + or (self.flow_level and ch in ',:?[]{}'): + break + length += 1 + # It's not clear what we should do with ':' in the flow context. + if (self.flow_level and ch == ':' + and self.peek(length+1) not in '\0 \t\r\n\x85\u2028\u2029,[]{}'): + self.forward(length) + raise ScannerError("while scanning a plain scalar", start_mark, + "found unexpected ':'", self.get_mark(), + "Please check http://pyyaml.org/wiki/YAMLColonInFlowContext for details.") + if length == 0: + break + self.allow_simple_key = False + chunks.extend(spaces) + chunks.append(self.prefix(length)) + self.forward(length) + end_mark = self.get_mark() + spaces = self.scan_plain_spaces(indent, start_mark) + if not spaces or self.peek() == '#' \ + or (not self.flow_level and self.column < indent): + break + return ScalarToken(''.join(chunks), True, start_mark, end_mark) + + def scan_plain_spaces(self, indent, start_mark): + # See the specification for details. + # The specification is really confusing about tabs in plain scalars. + # We just forbid them completely. Do not use tabs in YAML! + chunks = [] + length = 0 + while self.peek(length) in ' ': + length += 1 + whitespaces = self.prefix(length) + self.forward(length) + ch = self.peek() + if ch in '\r\n\x85\u2028\u2029': + line_break = self.scan_line_break() + self.allow_simple_key = True + prefix = self.prefix(3) + if (prefix == '---' or prefix == '...') \ + and self.peek(3) in '\0 \t\r\n\x85\u2028\u2029': + return + breaks = [] + while self.peek() in ' \r\n\x85\u2028\u2029': + if self.peek() == ' ': + self.forward() + else: + breaks.append(self.scan_line_break()) + prefix = self.prefix(3) + if (prefix == '---' or prefix == '...') \ + and self.peek(3) in '\0 \t\r\n\x85\u2028\u2029': + return + if line_break != '\n': + chunks.append(line_break) + elif not breaks: + chunks.append(' ') + chunks.extend(breaks) + elif whitespaces: + chunks.append(whitespaces) + return chunks + + def scan_tag_handle(self, name, start_mark): + # See the specification for details. + # For some strange reasons, the specification does not allow '_' in + # tag handles. I have allowed it anyway. + ch = self.peek() + if ch != '!': + raise ScannerError("while scanning a %s" % name, start_mark, + "expected '!', but found %r" % ch, self.get_mark()) + length = 1 + ch = self.peek(length) + if ch != ' ': + while '0' <= ch <= '9' or 'A' <= ch <= 'Z' or 'a' <= ch <= 'z' \ + or ch in '-_': + length += 1 + ch = self.peek(length) + if ch != '!': + self.forward(length) + raise ScannerError("while scanning a %s" % name, start_mark, + "expected '!', but found %r" % ch, self.get_mark()) + length += 1 + value = self.prefix(length) + self.forward(length) + return value + + def scan_tag_uri(self, name, start_mark): + # See the specification for details. + # Note: we do not check if URI is well-formed. + chunks = [] + length = 0 + ch = self.peek(length) + while '0' <= ch <= '9' or 'A' <= ch <= 'Z' or 'a' <= ch <= 'z' \ + or ch in '-;/?:@&=+$,_.!~*\'()[]%': + if ch == '%': + chunks.append(self.prefix(length)) + self.forward(length) + length = 0 + chunks.append(self.scan_uri_escapes(name, start_mark)) + else: + length += 1 + ch = self.peek(length) + if length: + chunks.append(self.prefix(length)) + self.forward(length) + length = 0 + if not chunks: + raise ScannerError("while parsing a %s" % name, start_mark, + "expected URI, but found %r" % ch, self.get_mark()) + return ''.join(chunks) + + def scan_uri_escapes(self, name, start_mark): + # See the specification for details. + codes = [] + mark = self.get_mark() + while self.peek() == '%': + self.forward() + for k in range(2): + if self.peek(k) not in '0123456789ABCDEFabcdef': + raise ScannerError("while scanning a %s" % name, start_mark, + "expected URI escape sequence of 2 hexdecimal numbers, but found %r" + % self.peek(k), self.get_mark()) + codes.append(int(self.prefix(2), 16)) + self.forward(2) + try: + value = bytes(codes).decode('utf-8') + except UnicodeDecodeError as exc: + raise ScannerError("while scanning a %s" % name, start_mark, str(exc), mark) + return value + + def scan_line_break(self): + # Transforms: + # '\r\n' : '\n' + # '\r' : '\n' + # '\n' : '\n' + # '\x85' : '\n' + # '\u2028' : '\u2028' + # '\u2029 : '\u2029' + # default : '' + ch = self.peek() + if ch in '\r\n\x85': + if self.prefix(2) == '\r\n': + self.forward(2) + else: + self.forward() + return '\n' + elif ch in '\u2028\u2029': + self.forward() + return ch + return '' + +#try: +# import psyco +# psyco.bind(Scanner) +#except ImportError: +# pass + diff --git a/software/tools/pymcuprog/libs/yaml/serializer.py b/software/tools/pymcuprog/libs/yaml/serializer.py new file mode 100644 index 0000000..fe911e6 --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/serializer.py @@ -0,0 +1,111 @@ + +__all__ = ['Serializer', 'SerializerError'] + +from .error import YAMLError +from .events import * +from .nodes import * + +class SerializerError(YAMLError): + pass + +class Serializer: + + ANCHOR_TEMPLATE = 'id%03d' + + def __init__(self, encoding=None, + explicit_start=None, explicit_end=None, version=None, tags=None): + self.use_encoding = encoding + self.use_explicit_start = explicit_start + self.use_explicit_end = explicit_end + self.use_version = version + self.use_tags = tags + self.serialized_nodes = {} + self.anchors = {} + self.last_anchor_id = 0 + self.closed = None + + def open(self): + if self.closed is None: + self.emit(StreamStartEvent(encoding=self.use_encoding)) + self.closed = False + elif self.closed: + raise SerializerError("serializer is closed") + else: + raise SerializerError("serializer is already opened") + + def close(self): + if self.closed is None: + raise SerializerError("serializer is not opened") + elif not self.closed: + self.emit(StreamEndEvent()) + self.closed = True + + #def __del__(self): + # self.close() + + def serialize(self, node): + if self.closed is None: + raise SerializerError("serializer is not opened") + elif self.closed: + raise SerializerError("serializer is closed") + self.emit(DocumentStartEvent(explicit=self.use_explicit_start, + version=self.use_version, tags=self.use_tags)) + self.anchor_node(node) + self.serialize_node(node, None, None) + self.emit(DocumentEndEvent(explicit=self.use_explicit_end)) + self.serialized_nodes = {} + self.anchors = {} + self.last_anchor_id = 0 + + def anchor_node(self, node): + if node in self.anchors: + if self.anchors[node] is None: + self.anchors[node] = self.generate_anchor(node) + else: + self.anchors[node] = None + if isinstance(node, SequenceNode): + for item in node.value: + self.anchor_node(item) + elif isinstance(node, MappingNode): + for key, value in node.value: + self.anchor_node(key) + self.anchor_node(value) + + def generate_anchor(self, node): + self.last_anchor_id += 1 + return self.ANCHOR_TEMPLATE % self.last_anchor_id + + def serialize_node(self, node, parent, index): + alias = self.anchors[node] + if node in self.serialized_nodes: + self.emit(AliasEvent(alias)) + else: + self.serialized_nodes[node] = True + self.descend_resolver(parent, index) + if isinstance(node, ScalarNode): + detected_tag = self.resolve(ScalarNode, node.value, (True, False)) + default_tag = self.resolve(ScalarNode, node.value, (False, True)) + implicit = (node.tag == detected_tag), (node.tag == default_tag) + self.emit(ScalarEvent(alias, node.tag, implicit, node.value, + style=node.style)) + elif isinstance(node, SequenceNode): + implicit = (node.tag + == self.resolve(SequenceNode, node.value, True)) + self.emit(SequenceStartEvent(alias, node.tag, implicit, + flow_style=node.flow_style)) + index = 0 + for item in node.value: + self.serialize_node(item, node, index) + index += 1 + self.emit(SequenceEndEvent()) + elif isinstance(node, MappingNode): + implicit = (node.tag + == self.resolve(MappingNode, node.value, True)) + self.emit(MappingStartEvent(alias, node.tag, implicit, + flow_style=node.flow_style)) + for key, value in node.value: + self.serialize_node(key, node, None) + self.serialize_node(value, node, key) + self.emit(MappingEndEvent()) + self.ascend_resolver() + diff --git a/software/tools/pymcuprog/libs/yaml/tokens.py b/software/tools/pymcuprog/libs/yaml/tokens.py new file mode 100644 index 0000000..4d0b48a --- /dev/null +++ b/software/tools/pymcuprog/libs/yaml/tokens.py @@ -0,0 +1,104 @@ + +class Token(object): + def __init__(self, start_mark, end_mark): + self.start_mark = start_mark + self.end_mark = end_mark + def __repr__(self): + attributes = [key for key in self.__dict__ + if not key.endswith('_mark')] + attributes.sort() + arguments = ', '.join(['%s=%r' % (key, getattr(self, key)) + for key in attributes]) + return '%s(%s)' % (self.__class__.__name__, arguments) + +#class BOMToken(Token): +# id = '' + +class DirectiveToken(Token): + id = '' + def __init__(self, name, value, start_mark, end_mark): + self.name = name + self.value = value + self.start_mark = start_mark + self.end_mark = end_mark + +class DocumentStartToken(Token): + id = '' + +class DocumentEndToken(Token): + id = '' + +class StreamStartToken(Token): + id = '' + def __init__(self, start_mark=None, end_mark=None, + encoding=None): + self.start_mark = start_mark + self.end_mark = end_mark + self.encoding = encoding + +class StreamEndToken(Token): + id = '' + +class BlockSequenceStartToken(Token): + id = '' + +class BlockMappingStartToken(Token): + id = '' + +class BlockEndToken(Token): + id = '' + +class FlowSequenceStartToken(Token): + id = '[' + +class FlowMappingStartToken(Token): + id = '{' + +class FlowSequenceEndToken(Token): + id = ']' + +class FlowMappingEndToken(Token): + id = '}' + +class KeyToken(Token): + id = '?' + +class ValueToken(Token): + id = ':' + +class BlockEntryToken(Token): + id = '-' + +class FlowEntryToken(Token): + id = ',' + +class AliasToken(Token): + id = '' + def __init__(self, value, start_mark, end_mark): + self.value = value + self.start_mark = start_mark + self.end_mark = end_mark + +class AnchorToken(Token): + id = '' + def __init__(self, value, start_mark, end_mark): + self.value = value + self.start_mark = start_mark + self.end_mark = end_mark + +class TagToken(Token): + id = '' + def __init__(self, value, start_mark, end_mark): + self.value = value + self.start_mark = start_mark + self.end_mark = end_mark + +class ScalarToken(Token): + id = '' + def __init__(self, value, plain, start_mark, end_mark, style=None): + self.value = value + self.plain = plain + self.start_mark = start_mark + self.end_mark = end_mark + self.style = style + diff --git a/software/tools/pymcuprog/prog.py b/software/tools/pymcuprog/prog.py new file mode 100644 index 0000000..f96cefe --- /dev/null +++ b/software/tools/pymcuprog/prog.py @@ -0,0 +1,282 @@ +#!/usr/bin/python3 + +# -*- coding: utf-8 -*- +import sys +import os +import argparse + +# dependencies +toolspath = os.path.dirname(os.path.realpath(__file__)) +sys.path.insert(0, os.path.join(toolspath, "libs")) + +import pymcuprog.pymcuprog_main as pymcu +from pymcuprog.pymcuprog import setup_logging + +import logging + +import datetime + + +class PyMcuException(Exception): + pass + + +def main(): + parser = argparse.ArgumentParser() + + parser.add_argument("-a", "--action", + type=str, + default="", + help="Action to perform {write, read, erase}.") + + parser.add_argument("-b", "--baudrate", + type=str, + default="115200", + help="Serial baud rate, if applicable, (default: 115200).") + + parser.add_argument("-wc", "--write_chunk", + type=int, + default=-1, + help="Max number of bytes of serial data to write per usb packet. -1 (whole page) is recommended. (Default: -1 (no write chunking)) Intended as workaround for specific serial adapters. ") + + parser.add_argument("-rc", "--read_chunk", + type=int, + default=-1, + help="Max number of bytes to request from the device at a time when reading or verifying. (Default: -1 (maximum - usually 512b)) Intended as a workaround for specific serial adapters.") + + parser.add_argument("-d", "--device", + type=str, + help="Part number, lowercase (e.g. attiny412, ...).") + + parser.add_argument("--fuses", + nargs='+', + type=str, + default="", + help="List of offset:value (0x, 0b or decimal).") + + parser.add_argument("--fuses_print", + action="store_true", + help="Print fuse values.") + + parser.add_argument("-f", "--filename", + type=str, + default="", + help="Hex file to read/write.") + + parser.add_argument("-wd", "--writedelay", + type=float, + default=0, + help="Page write delay [ms] for tinyAVR and megaAVR. USB latency is usually sufficient without this. (Default: 0 - this severely impacts write performance)") + + parser.add_argument("-t", "--tool", + type=str, + default="uart", + help="Tool name, defaults to 'uart' (SerialUPDI) mode. The other options are neither tested nor maintained.") + + parser.add_argument("-u", "--uart", + type=str, + default="", + help="Serial port to use if tool is uart.") + + parser.add_argument("-s", "--serialnumber", + type=str, + default="", + help="Tool USB serial (optional, for non-Serial UPDI programmers only. This feature is neither tested nor maintained.).") + + parser.add_argument("-v", "--verbose", + action="count", + default=0, + help="Display more info (can be repeated).") + + # Parse args + args = parser.parse_args() + + if args.action == "" and args.fuses == "" and not args.fuses_print: + parser.print_help() + sys.exit(0) + + if args.action != "" and args.action not in ("read", "write", "erase"): + print("Error: unknown action '{}'".format(args.action)) + sys.exit(1) + + if args.action not in ("read", "write") and args.filename != "": + print("Error: action '{}' takes no filename".format(args.action)) + sys.exit(1) + + if args.action in ("read", "write") and args.filename == "": + print("Error: no filename provided") + sys.exit(1) + + fuses_dict = {} + for fuse_str in args.fuses: + fuse_offset, fuse_val = fuse_str.split(":") + try: + fuse_offset = int(fuse_offset, 0) + fuse_val = int(fuse_val, 0) + fuses_dict[fuse_offset] = fuse_val + except ValueError as e: + print("Error: cannot parse fuse, '{}'".format(e)) + sys.exit(1) + + print_report(args) + + logging_level = logging.ERROR + if args.verbose == 1: + logging_level = logging.INFO + elif args.verbose > 1: + logging_level = logging.DEBUG + + try: + setup_logging(user_requested_level=logging_level) + return_code = pymcuprog_basic(args, fuses_dict) + sys.exit(return_code) + except PyMcuException as e: + print("Error: ".format(e)) + sys.exit(1) + + +def run_pymcu_action(func, backend, *args, **kwargs): + args_pymcu = argparse.Namespace(**kwargs) + time_start = datetime.datetime.now() + status = func(backend, *args, args_pymcu) + time_stop = datetime.datetime.now() + print("Action took {:.2f}s".format((time_stop - time_start).total_seconds())) + if status != pymcu.STATUS_SUCCESS: + backend.end_session() + backend.disconnect_from_tool() + raise PyMcuException("Call to {} failed".format(func.__name__)) + + +def print_report(args): + print("SerialUPDI") + print("UPDI programming for Arduino using a serial adapter") + print("Based on pymcuprog, with significant modifications") + print("By Quentin Bolsee and Spence Konde") + print("Version 1.2.0 - June 2021") + print("Using serial port {} at {} baud.".format(args.uart, args.baudrate)) + print("Target: {}".format(args.device)) + if args.fuses != "": + print("Set fuses: {}".format(args.fuses)) + print("Action: {}".format(args.action)) + if args.filename != "": + print("File: {}".format(args.filename)) + + +def pymcuprog_basic(args, fuses_dict): + """ + Main program + """ + backend = pymcu.Backend() + + # connect to tool + toolconnection = pymcu._setup_tool_connection(argparse.Namespace(tool=args.tool, + uart=args.uart, + serialnumber=args.serialnumber)) + try: + backend.connect_to_tool(toolconnection) + except pymcu.PymcuprogToolConnectionError as error: + print("Error: Cannot connect, '{}'".format(error)) + return 1 + + # select device + device_selected = pymcu._select_target_device(backend, argparse.Namespace(device=args.device, tool=args.tool)) + if device_selected is None: + backend.disconnect_from_tool() + print("Error: device selection failed") + return 1 + + # start session + args_start = argparse.Namespace(interface="updi", + clk=args.baudrate, + high_voltage=False, + user_row_locked_device=False, + chip_erase_locked_device=False, + packpath=False) + + status = pymcu._start_session(backend, + device_selected, + args_start) + + if status != pymcu.STATUS_SUCCESS: + if status == pymcu.STATUS_FAILURE_LOCKED and args.action in ("write", "erase"): + print("Locked state detected, performing chip erase") + args_start.chip_erase_locked_device = True + status = pymcu._start_session(backend, + device_selected, + args_start) + if status != pymcu.STATUS_SUCCESS: + raise PyMcuException("Failed to unlock!") + else: + raise PyMcuException("Cannot start session!") + + try: + pymcu._action_ping(backend) + except ValueError: + print("Device ID mismatch! Stopping.") + backend.end_session() + backend.disconnect_from_tool() + return 1 + + # write fuses + if fuses_dict is not None and len(fuses_dict) > 0: + for fuse_offset in sorted(fuses_dict.keys()): + fuse_value = fuses_dict[fuse_offset] + print("Setting fuse {}={}".format(hex(fuse_offset), hex(fuse_value))) + run_pymcu_action(pymcu._action_write, backend, + offset=fuse_offset, + literal=[fuse_value], + memory=pymcu.MemoryNames.FUSES, + verify=True, + filename=None) + print("Finished writing fuses.") + + # print fuses + if args.fuses_print: + run_pymcu_action(pymcu._action_read, backend, + memory=pymcu.MemoryNames.FUSES, + offset=0, + bytes=0, + filename=None) + + # actions + if args.action == "write": + run_pymcu_action(pymcu._action_erase, backend, + memory=pymcu.MemoryNameAliases.ALL, + offset=0) + + run_pymcu_action(pymcu._action_write, backend, + memory=pymcu.MemoryNameAliases.ALL, + offset=0, + literal=None, + verify=False, + filename=args.filename, + blocksize=None if args.write_chunk <= 0 else args.write_chunk, + pagewrite_delay=args.writedelay) + + run_pymcu_action(pymcu._action_verify, backend, + memory=pymcu.MemoryNameAliases.ALL, + offset=0, + literal=None, + filename=args.filename, + max_read_chunk=None if args.read_chunk <= 0 else args.read_chunk) + + elif args.action == "read": + run_pymcu_action(pymcu._action_read, backend, + memory=pymcu.MemoryNames.FLASH, + offset=0, + bytes=0, + filename=args.filename, + max_read_chunk=None if args.read_chunk <= 0 else args.read_chunk) + elif args.action == "erase": + run_pymcu_action(pymcu._action_erase, backend, + memory=pymcu.MemoryNameAliases.ALL, + offset=0) + + # close session + backend.end_session() + backend.disconnect_from_tool() + return 0 + + +if __name__ == '__main__': + main() diff --git a/software/tools/pymcuprog/readme.txt b/software/tools/pymcuprog/readme.txt new file mode 100644 index 0000000..6d8fc72 --- /dev/null +++ b/software/tools/pymcuprog/readme.txt @@ -0,0 +1,4 @@ +Description: pymcuprog - python-based serial-updi programmer, modified by Spence Konde and Quentin Bolsee +Source: https://pypi.org/project/pymcuprog/ + https://github.com/SpenceKonde/DxCore +License: MIT License diff --git a/software/usb_pd_adapter.hex b/software/usb_pd_adapter.hex new file mode 100644 index 0000000..b90d856 --- /dev/null +++ b/software/usb_pd_adapter.hex @@ -0,0 +1,130 @@ +:1000000019C028C027C026C025C024C023C022C0D4 +:1000100021C020C01FC01EC01DC0FBC01BC01AC015 +:1000200019C018C017C016C015C014C013C012C024 +:1000300011C010C011241FBECFEFCDBFDFE3DEBF64 +:100040002FE3A0E8BFE301C01D92A538B207E1F796 +:1000500008D145C3D5CF809318088091150886FF35 +:10006000FCCF08951F93CF93DF93E82FEE0F880FF7 +:10007000880F880FCE2FC80F80E0EDDF80E0EBDF28 +:1000800080E0E9DF80E0E7DFDAE0DC0F11E01C0F61 +:10009000EC2FF0E0EE51F9478081DDDFC12F1D1319 +:1000A000F5CFDF91CF911F9108958093170880912C +:1000B0001508807CE1F30895CF93C82F88E7F5DF1A +:1000C00080E0C9DF82E2C7DF8C2FC5DF81E08C0FC3 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