mirror of
https://gitea.ecohim.ru:3000/RS485_Relay/RS485_Relay2_fw.git
synced 2025-08-11 01:47:35 +03:00
Migrated to a new HAL version
This commit is contained in:
Anton Mukhin
@@ -7,7 +7,7 @@
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
@@ -37,16 +37,12 @@ extern "C" {
|
||||
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
|
||||
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
|
||||
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
|
||||
#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
|
||||
#if defined(STM32H7) || defined(STM32MP1)
|
||||
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
|
||||
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
|
||||
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
|
||||
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
|
||||
#if defined(STM32U5)
|
||||
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
|
||||
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
|
||||
#endif /* STM32U5 */
|
||||
#endif /* STM32U5 || STM32H7 || STM32MP1 */
|
||||
#endif /* STM32H7 || STM32MP1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -279,7 +275,7 @@ extern "C" {
|
||||
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
|
||||
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
|
||||
|
||||
#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
|
||||
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
|
||||
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
|
||||
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
|
||||
#endif
|
||||
@@ -552,6 +548,16 @@ extern "C" {
|
||||
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
|
||||
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
|
||||
#endif /* STM32U5 */
|
||||
#if defined(STM32U0)
|
||||
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
|
||||
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
|
||||
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
|
||||
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
|
||||
#define OB_USER_nBOOT0 OB_USER_NBOOT0
|
||||
#define OB_USER_nBOOT1 OB_USER_NBOOT1
|
||||
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
|
||||
#define OB_nBOOT0_SET OB_NBOOT0_SET
|
||||
#endif /* STM32U0 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -1243,10 +1249,10 @@ extern "C" {
|
||||
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
|
||||
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
|
||||
|
||||
#if defined(STM32H5)
|
||||
#if defined(STM32H5) || defined(STM32H7RS)
|
||||
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
|
||||
#endif /* STM32H5 */
|
||||
#endif /* STM32H5 || STM32H7RS */
|
||||
|
||||
#if defined(STM32WBA)
|
||||
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
@@ -1258,10 +1264,10 @@ extern "C" {
|
||||
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
|
||||
#endif /* STM32WBA */
|
||||
|
||||
#if defined(STM32H5) || defined(STM32WBA)
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
|
||||
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
|
||||
#endif /* STM32H5 || STM32WBA */
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS */
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
|
||||
@@ -1599,6 +1605,8 @@ extern "C" {
|
||||
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
|
||||
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
|
||||
|
||||
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1991,12 +1999,12 @@ extern "C" {
|
||||
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32H5) || defined(STM32WBA)
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
|
||||
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
|
||||
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
|
||||
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
|
||||
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
|
||||
#endif /* STM32H5 || STM32WBA */
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -2311,8 +2319,8 @@ extern "C" {
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F302xE) || defined(STM32F302xC)
|
||||
#endif
|
||||
#if defined(STM32F302xE) || defined(STM32F302xC)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
@@ -2345,8 +2353,8 @@ extern "C" {
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
#endif
|
||||
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
|
||||
@@ -2403,8 +2411,8 @@ extern "C" {
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F373xC) ||defined(STM32F378xx)
|
||||
#endif
|
||||
#if defined(STM32F373xC) ||defined(STM32F378xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
@@ -2421,7 +2429,7 @@ extern "C" {
|
||||
__HAL_COMP_COMP2_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
#endif
|
||||
#else
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
@@ -2723,6 +2731,12 @@ extern "C" {
|
||||
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
|
||||
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
|
||||
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
|
||||
#if defined(STM32C0)
|
||||
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
|
||||
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
|
||||
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
|
||||
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
|
||||
#endif /* STM32C0 */
|
||||
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
|
||||
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
|
||||
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
|
||||
@@ -3646,8 +3660,12 @@ extern "C" {
|
||||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32U0)
|
||||
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
|
||||
defined(STM32WL) || defined(STM32C0)
|
||||
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
@@ -3749,8 +3767,10 @@ extern "C" {
|
||||
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
|
||||
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
|
||||
#if !defined(STM32U0)
|
||||
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
|
||||
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
|
||||
#endif
|
||||
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
|
||||
@@ -3896,7 +3916,8 @@ extern "C" {
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
|
||||
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
|
||||
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
|
||||
defined (STM32WBA) || defined (STM32H5) || \
|
||||
defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
@@ -3931,6 +3952,13 @@ extern "C" {
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
#endif /* STM32F1 */
|
||||
|
||||
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
|
||||
defined (STM32H7) || \
|
||||
defined (STM32L0) || defined (STM32L1) || \
|
||||
defined (STM32WB)
|
||||
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
|
||||
#endif
|
||||
|
||||
#define IS_ALARM IS_RTC_ALARM
|
||||
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
|
||||
#define IS_TAMPER IS_RTC_TAMPER
|
||||
@@ -4212,6 +4240,9 @@ extern "C" {
|
||||
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
|
||||
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
|
||||
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -236,8 +236,8 @@ typedef enum
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
|
||||
#define IS_GPIO_PIN(__PIN__) (((((uint32_t)__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
|
||||
((((uint32_t)__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
|
||||
#define IS_GPIO_PIN(__PIN__) (((((uint32_t)(__PIN__)) & GPIO_PIN_MASK) != 0x00U) &&\
|
||||
((((uint32_t)(__PIN__)) & ~GPIO_PIN_MASK) == 0x00U))
|
||||
|
||||
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
|
||||
@@ -118,8 +118,6 @@ typedef enum
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
|
||||
@@ -385,29 +385,28 @@ typedef struct
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
|
||||
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
|
||||
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
|
||||
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
|
||||
@@ -1656,8 +1655,9 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
|
||||
((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
|
||||
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
|
||||
(((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
|
||||
((__PERIOD__) > 0U))
|
||||
|
||||
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) || \
|
||||
@@ -1710,7 +1710,6 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
|
||||
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
|
||||
|
||||
|
||||
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
|
||||
((__STATE__) == TIM_BREAK_DISABLE))
|
||||
|
||||
@@ -2048,7 +2047,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength, uint32_t DataLength);
|
||||
|
||||
@@ -145,7 +145,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
|
||||
|
||||
|
||||
/**
|
||||
|
||||
@@ -559,10 +559,10 @@ typedef struct
|
||||
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
|
||||
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
|
||||
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
|
||||
/**
|
||||
* @}
|
||||
@@ -822,11 +822,11 @@ typedef struct
|
||||
#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
|
||||
@@ -1473,6 +1473,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
|
||||
CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
|
||||
* @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
|
||||
* @param TIMx Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
|
||||
{
|
||||
return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
|
||||
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
|
||||
|
||||
@@ -213,7 +213,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param Ticks Number of ticks
|
||||
* @param Ticks Frequency of Ticks (Hz)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
|
||||
Reference in New Issue
Block a user