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Update HAL version, board description, version number to 10.0

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This commit is contained in:
Anton Mukhin
2023-11-22 10:43:10 +03:00
parent 65ca64389e
commit 89ced0fc11
65 changed files with 21574 additions and 1608 deletions
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32
Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h
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@@ -9,22 +9,20 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral<EFBFBD>s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
@@ -70,7 +68,7 @@ typedef enum
/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
@@ -549,7 +547,7 @@ typedef struct
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
/* Note: No specific macro feature on this device */
@@ -637,7 +635,7 @@ typedef struct
#define ADC_CFGR1_ALIGN_Pos (5U)
#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR1_EXTSEL_Pos (6U)
#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
@@ -2731,7 +2729,7 @@ typedef struct
/* */
/*****************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
/******************** Bit definition for RCC_CR register *******************/
@@ -3290,7 +3288,7 @@ typedef struct
/* */
/*****************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -3750,7 +3748,7 @@ typedef struct
/*****************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
/* Note: No specific macro feature on this device */
@@ -5337,17 +5335,18 @@ typedef struct
#define ADC1_COMP_IRQn ADC1_IRQn
#define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
#define RCC_CRS_IRQn RCC_IRQn
#define SVC_IRQn SVCall_IRQn
/* Aliases for __IRQHandler */
#define ADC1_COMP_IRQHandler ADC1_IRQHandler
#define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
#define RCC_CRS_IRQHandler RCC_IRQHandler
@@ -5365,4 +5364,3 @@ typedef struct
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/